Interface ebe nchekwa mpụga Intel Stratix 10 FPGA IP Design Example

Imepụta Exampna Ntuziaka mmalite ngwa ngwa maka ntụgharị ebe nchekwa mpụga Intel® Stratix® 10 FPGA IP

Ọhụrụ interface na ndị ọzọ akpaaka imewe example eruba dị maka Intel® Stratix® 10 mpụga ebe nchekwa interfaces. The Example Designs tab na paramita nchịkọta akụkọ na-enye gị ohere ịkọwapụta ihe e kere eke nke njikọ na simulation file ntọala nke ị nwere ike iji kwado IP EMIF gị. Ị nwere ike ịmepụta example chepụta kpọmkwem maka ngwa mmepe Intel FPGA, ma ọ bụ maka IP EMIF ọ bụla ị na-emepụta.

Ọgụgụ 1. General Design Exampna usoro ọrụ

Ọgụgụ 2. Ịmepụta EMIF Example Kere ya na ihe Intel Stratix 10 Development Kit

Ịmepụta ọrụ EMIF

Maka ụdị sọftụwia Intel Quartus® Prime 17.1 na emesia, ị ga-emerịrị ọrụ Intel Quartus Prime tupu ịmepụta EMIF IP na imewe ex.ample.

1. Ẹkedori Intel Quartus Prime software wee họrọ File ➤ Ọkachamara Project ọhụrụ. Pịa Ọzọ.
2. Ezipụta akwụkwọ ndekọ aha na nme maka oru ngo nke ịchọrọ ịmepụta. Pịa Ọzọ.
3. Nyochaa na ahọpụtara Project efu. Pịa ugboro abụọ na-esote.
4. N'okpuru nzacha aha, pịnye nọmba akụkụ ngwaọrụ.
5. N'okpuru ngwaọrụ dị, họrọ ngwaọrụ kwesịrị ekwesị.
6. Pịa N'ikpeazụ.

Ịmepụta na ịhazi EMIF IP

Usoro ndị a na-egosi otu esi ewepụta na hazie IP EMIF. Nke a na-eme njem na-emepụta DDR4 interface, mana usoro ndị a yiri maka ụkpụrụ ndị ọzọ.

1. Na mpio katalọgụ IP, họrọ Intel Stratix 10 External Memory Interfaces. (Ọ bụrụ na ahụghị windo katalọgụ IP, họrọ View ➤ Utility Windows ➤ Katalọgụ IP.)
2. Na IP Parameter Editor, nye aha aha maka EMIF IP (aha ị nyere ebe a na-aghọ file aha maka IP) ma kọwaa ndekọ. Pịa Mepụta.
3. Onye nchịkọta akụkọ paramita nwere ọtụtụ taabụ ebe ị ga-ahazirịrị paramita iji gosipụta mmejuputa EMIF gị:

Ntuziaka nchịkọta akụkọ nke Intel Stratix 10 EMIF Parameter

Tebụl 1. EMIF Parameter Editor Guidelines

Parameter Editor Tab	Ntuziaka
Izugbe	Gbaa mbọ hụ na etinyere paramita ndị a nke ọma: • Ọsọ ọsọ maka ngwaọrụ. • Ugboro elekere ebe nchekwa. • Ugboro elekere ntụaka PLL.
Ebe nchekwa	• Rụtụ aka na mpempe data maka ngwaọrụ ebe nchekwa gị ka itinye paramita dị na Ebe nchekwa tab. • Ị ga-etinyekwa otu ebe maka ntụtụ ALART#. (Na-emetụta naanị DDR4 protocol ebe nchekwa.)
Mem I/O	• Maka nyocha ọrụ mbụ, ịnwere ike iji ntọala ndabara na Mem I/O tab. • Maka nkwado imewe dị elu, ịkwesịrị ịme simulation bọọdụ iji nweta ntọala nkwụsị kacha mma.
FPGA I/O	• Maka nyocha ọrụ mbụ, ịnwere ike iji ntọala ndabara na FPGA I/O tab. • Maka nkwado imewe dị elu, ị kwesịrị ịme simulation bọọdụ nwere ụdị IBIS metụtara iji họrọ ụkpụrụ I/O kwesịrị ekwesị.
Oge Mem	• Maka nyocha ọrụ mbụ, ịnwere ike iji ntọala ndabara na Oge Mem tab. • Maka nkwado imewe dị elu, ịkwesịrị itinye paramita dịka mpempe data ngwaọrụ ebe nchekwa gị siri dị.
bọọdụ	• Maka nyocha ọrụ mbụ, ịnwere ike iji ntọala ndabara na bọọdụ tab. • Maka nkwado imewe dị elu na mmechi oge ziri ezi, ịkwesịrị ịme simulation bọọdụ iji nweta nnyonye anya intersymbol ziri ezi (ISI)/ crosstalk na bọọdụ na ozi skew ngwugwu wee tinye ya na bọọdụ tab.
Onye njikwa	Tọọ paramita njikwa dịka nhazi na omume achọrọ maka njikwa ebe nchekwa gị.
Nchọpụta nchọpụta	Ị nwere ike iji paramita ndị dị na ya Nchọpụta nchọpụta tab iji nyere aka n'ịnwale na debugging interface ebe nchekwa gị.
Example Designs	Nke Example Designs tab na-ahapụ gị ịmepụta imewe examples maka synthesis na maka ịme anwansị. Ihe emepụtara example bụ usoro EMIF zuru oke nke nwere EMIF IP na onye ọkwọ ụgbọ ala na-emepụta okporo ụzọ na-enweghị usoro iji kwado interface ebe nchekwa.

Maka ozi zuru ezu na parampat onye ọ bụla, rụtụ aka na isiakwụkwọ dabara adaba maka usoro ebe nchekwa gị na ntuziaka onye ọrụ IP nke Intel Stratix 10 Mpụga ebe nchekwa.

Na-amụpụta EMIF Design Synthesizable Example

Maka ngwa mmepe Intel Stratix 10, o zuru ezu ịhapụ ọtụtụ ntọala Intel Stratix 10 EMIF na ụkpụrụ ndabara ha. Iji mepụta synthesizable imewe example, soro usoro ndị a:

1. Na taabụ Diagnostics, mee ka EMIF Debug Toolkit/On-Chip Debug Port na In-System-Sources-and-Probes iji nye ohere ịnweta atụmatụ nbipu dị.
2. Na Exampna Designs tab, hụ na enyochala igbe Synthesis.
3. Hazie EMIF IP wee pịa Mepụta Example Chepụta na elu-nri akuku nke window.
4. Ezipụta akwụkwọ ndekọ aha maka imewe EMIF example wee pịa OK. Ọgbọ na-aga nke ọma nke imewe EMIF example emepụta ihe ndị a filesetịpụrụ n'okpuru ndekọ qii.

Ọgụgụ 3. Emepụtara Synthesizable Design Example File Nhazi

Mara: Ọ bụrụ na ị họrọghị igbe nyocha Simulation ma ọ bụ Synthesis, ndekọ ebe ị ga-aga ga-enwe imewe Platform Designer. files, nke Intel Quartus Prime software anaghị achịkọta ozugbo, mana ọ nwere ike ịbụ viewed ma ọ bụ dezie n'okpuru Platform Designer. N'ọnọdụ a ị nwere ike ịme iwu ndị a ka ịmepụta njikọ na simulation file tent.

• Iji mepụta ọrụ anakọtara, ị ga-agbarịrị edemede quartus_sh -t make_qii_design.tcl na ndekọ ebe aga.
• Iji mepụta ọrụ ịme anwansị, ị ga-agbarịrị script quartus_sh -t make_sim_design.tcl n'ime ndekọ ebe aga.

Ozi metụtara

• Synthesis Example Kere na ibe 19
• Nkọwapụta Intel Stratix 10 EMIF IP Parameter maka DDR3
• Nkọwapụta Intel Stratix 10 EMIF IP Parameter maka DDR4
• Intel Stratix 10 EMIF IP Parameter Nkọwa maka QDRII/II+/Xtreme
• Intel Stratix 10 EMIF nkọwapụta Parameter IP maka QDR-IV
• Nkọwapụta Intel Stratix 10 EMIF IP Parameter maka RLDRAM 3

Na-emepụta EMIF Design Example maka Simulation
Maka ngwa mmepe Intel Stratix 10, o zuru ezu ịhapụ ọtụtụ ntọala Intel Stratix 10 EMIF na ụkpụrụ ndabara ha. Iji mepụta imewe example maka
ịme anwansị, soro usoro ndị a:

1. Na taabụ Diagnostics, ị nwere ike họrọ n'etiti ụdị nzizi abụọ: Mwụsa Calibration na Full Calibration. (Maka nkọwa gbasara ụdịdị ndị a, rụtụ aka na Simulation Versus Hardware Implementation, emechaa n'isiakwụkwọ a.) Iji belata oge ịme anwansị, họrọ Abstract PHY maka ịme anwansị ngwa ngwa.
2. Na Exampsite Designs tab, hụ na enyochala igbe Simulation. Họrọkwa usoro HDL Simulation achọrọ, ma ọ bụ Verilog ma ọ bụ VHDL.
3. Hazie EMIF IP wee pịa Mepụta Example Chepụta na elu-nri akuku nke window.
4. Ezipụta akwụkwọ ndekọ aha maka imewe EMIF example wee pịa OK.

Ọgbọ na-aga nke ọma nke imewe EMIF example emepụta otutu file setịpụrụ maka simulators dị iche iche na-akwado, n'okpuru ndekọ ndekọ sim/ed_sim.

Ọgụgụ 4. Emepụtara Simulation Design Example File Nhazi

Mara: Ọ bụrụ na ị họrọghị igbe nyocha Simulation ma ọ bụ Synthesis, ndekọ ebe ị ga-aga ga-enwe imewe Platform Designer. files, nke Intel Quartus Prime software anaghị achịkọta ozugbo, mana ọ nwere ike ịbụ viewed ma ọ bụ dezie n'okpuru Platform Designer. N'ọnọdụ a ị nwere ike ịme iwu ndị a ka ịmepụta njikọ na simulation file tent.

• Iji mepụta ọrụ anakọtara, ị ga-agbarịrị edemede quartus_sh -t make_qii_design.tcl na ndekọ ebe aga.
• Iji mepụta ọrụ ịme anwansị, ị ga-agbarịrị script quartus_sh -t make_sim_design.tcl n'ime ndekọ ebe aga.

Ozi metụtara
• Simulation Example Kere na
• Intel Stratix 10 EMIF IP - Ịmepụta ebe nchekwa IP
• Simulation Versus Ngwaike mmejuputa iwu na

Simulation Versus Ngwaike mmejuputa iwu
Maka ịme anwansị interface ebe nchekwa mpụga, ị nwere ike họrọ ma ịwụsa nhazi ma ọ bụ nhazi zuru oke na taabụ Diagnostics n'oge ọgbọ IP.
Ụdị Simulation EMIF
Tebụl a na-atụnyere njirimara nke nlegharị anya na-awụ elu na ụdị nhazi zuru oke.

Tebụl 2. Ụdị ịme anwansị EMIF: Kwụsịa calibration na nhazi zuru oke

Mafee nhazigharị	Nhazi zuru oke
Simulation ọkwa sistemụ na-elekwasị anya na mgbagha onye ọrụ.	Simulation interface ebe nchekwa na-elekwasị anya na nhazigharị.
Ededeghị nkọwapụta nke mmezi.	Na-ejide stages nke calibration.
Nwere ikike ịchekwa na weghachite data.	Na-agụnye nhazi ọkwa, kwa-bit deskew, wdg.
Na-anọchite anya arụmọrụ ziri ezi.
Ọ naghị echebara skew osisi.

RTL Simulation Versus Mmejuputa ngwaike

Tebụl a na-akọwapụta isi ihe dị iche n'etiti simulation EMIF na mmejuputa ngwaike.

Tebụl 3. EMIF RTL Simulation Versus Hardware Mmejuputa

RTL Simulation	Mmejuputa ngwaike
Nios® mmalite na koodu mmezi na-arụ n'otu oge.	Nios mbido na koodu mmezi na-eme n'usoro.
Interface na-ekwupụta mgbama cal_done n'otu oge na simulator.	Arụmọrụ fitter na-ekpebi usoro nhazigharị, na ihu adịghị ekwupụta cal_done n'otu oge.

Ịkwesịrị ịme ihe ngosi RTL dabere na usoro okporo ụzọ maka ngwa imewe gị. Rịba ama na ịme anwansị RTL anaghị egosipụta igbu oge nchọta PCB nke nwere ike ime ka enweghị nghọta dị n'etiti simulation RTL na mmejuputa ngwaike.

Iji ModelSim na-eme ka Interface ebe nchekwa dị na mpụga IP

Usoro a na-egosi otu esi eme ka EMIF chepụta example.

1. Ẹkedori Mentor Graphics* ModelSim software wee họrọ File ➤ Gbanwee ndekọ. Gaa na ndekọ ndekọ aha sim/ed_sim/ndụ n'ime ihe emepụtara example folda.
2. Nyochaa na egosipụtara mpio transcript n'okpuru ihuenyo ahụ. Ọ bụrụ na ahụghị windo transcript, gosi ya site na ịpị View ➤ transcript.
3. Na mpio transcript, mee isi iyi msim_setup.tcl.
4. Mgbe isi mmalite msim_setup.tcl gwụchara ọsọ, mee ld_debug na mpio transcript.
5. Mgbe ld_debug mechara ọsọ, chọpụta na egosipụtara mpio Ihe. Ọ bụrụ na ahụghị mpio ihe, gosi ya site na ịpị View ➤ Ihe.
6. Na mpio ihe, họrọ akara ngosi nke ịchọrọ ịme emume site na ịpị aka nri na họrọ Tinye Wave.
7. Mgbe ịmechara ịhọrọ akara maka ịme anwansị, mebie ọsọ - niile na windo VTranscript. Simulation na-agba ọsọ ruo mgbe emechara.
8. Ọ bụrụ na anaghị ahụ simulation ahụ, pịa View ➤ Wave.

Ozi metụtara
Intel Stratix 10 EMIF IP - Ebe nchekwa ebe nchekwa IP

Ntinye pin maka Intel Stratix 10 EMIF IP

Isiokwu a na-enye ntuziaka maka ntinye ntụtụ.

gafereview

Intel Stratix 10 FPGA nwere usoro ndị a:

• Ngwaọrụ ọ bụla nwere n'etiti kọlụm 2 na 3 I/O.
• Kọlụm I/O ọ bụla nwere ihe ruru ụlọ akụ I/O 12.
• Ụlọ akụ I/O ọ bụla nwere ụzọ anọ.
• Ụzọ nke ọ bụla nwere ntụtụ I/O (GPIO) iri na abụọ.

Ntuziaka Pin General
Isi ihe ndị a na-enye ụkpụrụ ntụzịaka n'ozuzu:

• Gbaa mbọ hụ na ntụtụ maka interface ebe nchekwa mpụga nyere dị n'ime otu kọlụm I/O.
• Interface nke gafere ọtụtụ ụlọ akụ ga-enwerịrị ihe ndị a chọrọ:
  • Ụlọ akụ ga-adị n'akụkụ ibe ha. Maka ozi gbasara ụlọ akụ dị n'akụkụ, rụtụ aka na ntuziaka onye ọrụ IP nke Intel Stratix 10 Mpụga ebe nchekwa.
  • Adreesị na ụlọ akụ iwu ga-ebirịrị n'ụlọ akụ etiti ka ibelata oge. Ọ bụrụ na interface ebe nchekwa na-eji ọbụna ọnụ ọgụgụ ụlọ akụ, adreesị na ụlọ akụ iwu nwere ike ibi na nke ọ bụla n'ime ụlọ akụ etiti abụọ ahụ.
• Enwere ike iji ntụtụ na-adịghị eji eme ihe dị ka ntụtụ I/O zuru oke.
• Adreesị na iwu yana ntụtụ ndị metụtara ga-ebirịrị n'ime otu ụlọ akụ.
• Adreesị na iwu na ntụtụ data nwere ike ịkekọrịta ụlọ akụ n'okpuru ọnọdụ ndị a:
  • Adreesị na iwu na ntụtụ data enweghị ike ịkekọrịta ụzọ I/O.
  • Naanị ụzọ I/O ejighi ya na adreesị na ụlọ akụ iwu ka enwere ike iji maka ntụtụ data.

Tebụl 4. Ihe mgbochi ntụtụ n'ozuzu

Ụdị mgbaàmà	Mmachi
Data Strobe	Mgbama niile nke otu DQ ga-ebirịrị n'otu ụzọ I/O.
Data	Ntụtụ DQ emetụtara ga-ebirịrị n'otu ụzọ I/O. Maka protocol na-akwadoghị ahịrị data bidirectional, ekwesịrị ịchịkọta akara agụ iche na akara ederede.
Adreesị na Iwu	Adreesị na ntụtụ iwu ga-ebirịrị na ọnọdụ akọwara n'ime ụlọ akụ I/O.

Ụlọ akụ dị n'akụkụ

Maka ụlọ akụ ga-ewere n'akụkụ, ha ga-ebi n'otu kọlụm I / O, Iji chọpụta ma ọ bụrụ na ụlọ akụ dị n'akụkụ, rụtụ aka na Modular I/O bank Location and Pin Counts in Stratix 10 Devices section dị na Stratix 10 General Purpose I. /O
Ntuziaka onye ọrụ.

Mgbe ị na-atụ aka na tebụl dị na ntuziaka onye ọrụ Stratix 10 General Purpose I/O, ọ dị mma iche na ụlọ akụ niile egosiri nọ n'akụkụ, ọ gwụla ma akara '-' dị; akara '-' na-egosi na ejikọtaghị ụlọ akụ maka ngwugwu ahụ.
Ihe Ntinye

Iji chọpụta ọnọdụ maka ntụtụ I/O EMIF niile, ị ga-edetụ aka na tebụl pin maka ngwaọrụ gị. Mgbe ị na-ezo aka na tebụl pin, a na-enye nọmba ụlọ akụ, indices ụlọ akụ I/O, na aha pin. Ị nwere ike ịchọta indices pin maka adreesị na ntụtụ iwu na Stratix 10 Scheme Table dị na Intel FPGA websaịtị. Ị nwere ike ịrụ ọrụ pin n'ụzọ dị iche iche. Usoro akwadoro bụ iji aka machie ụfọdụ akara interface ma hapụ Intel Quartus Prime Fitter aka ndị ọzọ. Usoro a gụnyere ileba anya na tebụl pin ka ịchọta ọnọdụ iwu maka ụfọdụ ntụtụ interface wee kenye ha site na .qsf. file nke emepụtara na EMIF design example. Maka usoro ntinye I/O a, ị ga-amachibido akara ndị a:

• CK0
• Otu ntụtụ DQS kwa otu
• Elekere ntụaka PLL
• RZQ

Dabere na mmachi ndị a dị n'elu, Intel Quartus Prime Fitter na-atụgharị pin n'ime ụzọ ọ bụla dị mkpa. Ọnụ ọgụgụ na-esonụ na-egosi onye bụbuample nke pin ọrụ maka DDR3 x72 interface nwere nhọrọ ndị a:

• A na-etinye adreesị na ntụtụ iwu na ụlọ akụ 2M ma chọọ ụzọ 3.
  • CK0 na-amachibido pin 8 na ụlọ akụ 2M.
  • A na-amachibido ntụtụ elekere PLL ka ọ bụrụ ntụtụ 24 na 25 na ụlọ akụ 2M.
  • Amachibidoro RZQ pin 26 na ụlọ akụ 2M.
• A na-etinye data na ụlọ akụ 2N, 2M, na 2L, ma chọọ ụzọ 9.
  • A na-etinye otu DQS 1-4 na ụlọ akụ 2N.
  • A na-etinye DQS otu 0 na ụlọ akụ 2M.
  • A na-etinye otu DQS 5-8 na ụlọ akụ 2L.

Ọgụgụ 5. Pin Ọrụ Ọpụample: DDR3 x73 Interface

Na nke a example, iji gbochie CK0 ka ọ pinye 8 na ụlọ akụ 2M, ị ga-agbakwunye ahịrị ndị a na .qsf file, dabere na tebụl pin kwesịrị ekwesị:

Enwere ike itinye usoro nke ọrụ ntụtụ dị n'elu na ntụtụ niile:

Ozi metụtara

• Ụlọ akụ I/O Modular na ngwaọrụ Intel Stratix 10
• Intel Stratix 10 EMIF IP DDR3
• Intel Stratix 10 EMIF IP maka DDR4
• Intel Stratix 10 EMIF IP maka QDRII/II+/Xtreme
• Intel Stratix 10 EMIF IP maka QDR-IV
• Intel Stratix 10 EMIF IP maka RLDRAM 3

Ịchịkọta na ịhazi Intel Stratix 10 EMIF Design Example

Mgbe ịmechara ọrụ ntụtụ dị mkpa na .qsf file, ị nwere ike chịkọta imewe exampna Intel Quartus Prime software.

1. Gaa na nchekwa Intel Quartus Prime nwere ihe ngosi example ndekọ.
2. Mepee ọrụ Intel Quartus Prime file, (.qpf).
3. Iji malite nchịkọta, pịa Nhazi ➤ Malite nchịkọta. Mmecha mkpokọta nke ọma na-ebute .sof file, nke na-enyere imewe aka na-agba ọsọ na ngwaike.
4. Iji hazie ngwaọrụ gị n'ụdị agbakọtara, mepee programmer site na ịpị Tools ➤ Programmer.
5. N'ime mmemme, pịa Chọpụta Nchekwa onwe ka ịchọpụta ngwaọrụ akwadoro.
6. Họrọ ngwaọrụ Intel Stratix 10 wee họrọ Gbanwee File.
7. Gaa na ed_synth.sof emepụtara file ma họrọ Mepee.
8. Pịa Malite ka ịmalite mmemme Intel Stratix 10 ngwaọrụ. Mgbe emebere ngwaọrụ ahụ nke ọma, ogwe ọganihu dị n'elu-nri nke mpio kwesịrị igosi 100% (Emere nke ọma).

Na-emezigharị Intel Stratix 10 EMIF Design Example
EMIF Debug Toolkit dị iji nyere aka n'ichepụta ihe nrụgharị ebe nchekwa mpụga. Ngwa ngwa na-enye gị ohere igosipụta oke ọgụgụ na ide ma mepụta eserese anya. Mgbe ịmechara ngwa mmepe Intel Stratix 10, ị nwere ike nyochaa ọrụ ya site na iji EMIF Debug Toolkit.

1. Iji malite EMIF Debug Toolkit, gaa na Ngwa Ngwaọrụ ➤ Ngwa Nrụpụta Sistemu ➤ Ngwa Ihe Nrụpụta Ebe Nchekwa Mpụga.
2. Pịa Malite njikọ.
3. Pịa Njikọ Project na ngwaọrụ. Window pụtara; nyochaa na ahọpụtara ngwaọrụ ziri ezi yana na .sof ziri ezi file ahọpụtara.
4. Pịa Mepụta njikọ interface ebe nchekwa. Nabata ntọala ndabara site na ịpị OK.

Emebere ngwa mmepe Intel Stratix 10 ka ọ rụọ ọrụ na EMIF Debug Toolkit, ị nwere ike iwepụta akụkọ ọ bụla na-esote site na ịpị ugboro abụọ na nhọrọ kwekọrọ:

• Malitegharịa mmezi. Na-ewepụta akụkọ mmezi nke na-achịkọta ọkwa nhazi n'otu DQ/DQS yana oke maka pin DQ/DQS ọ bụla.
• Ọkwọ ụgbọala Margining. Na-ewepụta akụkọ na-achịkọta ọnụ ọgụgụ ọgụgụ na dee n'otu ntụtụ I/O. Nke a dị iche na nhazi nhazi n'ihi na a na-ejide oke ọkwọ ụgbọala n'oge okporo ụzọ onye ọrụ kama n'oge nhazi
• Mepụta eserese anya. Na-emepụta agụ na dee eserese anya maka ntụtụ DQ ọ bụla dabere na ụkpụrụ data nhazigharị.
• Calibrate nkwụsị. Na-ekpochapụ ụkpụrụ nkwụsị dị iche iche ma na-akọ oke oke nke uru nkwụsị ọ bụla na-enye. Jiri atụmatụ a nyere aka họrọ njedebe kacha mma maka interface ebe nchekwa.

Ozi metụtara
Intel Stratix 10 EMIF IP Debugging

Imepụta ExampNkọwapụta maka Interfaces ebe nchekwa mpụga Intel Stratix 10 FPGA IP

Mgbe ị mebere ma mepụta IP EMIF gị, ị nwere ike ịkọwapụta na sistemụ ahụ na-emepụta akwụkwọ ndekọ aha maka ịme anwansị na njikọ. file setịpụ, ma mepụta ihe file na-esetịpụ na-akpaghị aka. Ọ bụrụ na ịhọrọ Simulation ma ọ bụ Synthesis n'okpuru Example Design Files na Exampna Designs tab, usoro na-emepụta a zuru ezu simulation file setịpụrụ ma ọ bụ njikọ zuru oke file setịpụ, dịka nhọrọ gị siri dị.

Synthesis Example Design

Ihe njikọ example imewe nwere isi blocks egosiri na foto dị n'okpuru.

• Onye na-emepụta okporo ụzọ, nke bụ Avalon®-MM example ọkwọ ụgbọ ala nke na-emejuputa atumatu pseudo-random nke na-agụ na-ede na a parameterized ọnụ ọgụgụ nke adreesị. Onye na-emepụta okporo ụzọ na-enyochakwa data a na-agụ site na ebe nchekwa iji hụ na ọ dabara na data edere wee kwupụta ọdịda ma ọ bụghị ya.
• Ihe atụ nke interface ebe nchekwa, nke gụnyere:
  • Ihe njikwa ebe nchekwa na-agafe n'etiti interface Avalon-MM na interface AFI.
  • PHY, nke na-arụ ọrụ dị ka interface n'etiti ihe njikwa ebe nchekwa na ngwaọrụ ebe nchekwa mpụga iji rụọ ọrụ ịgụ na ide.

Ọgụgụ 6. Synthesis Example Design

Ọ bụrụ na ị na-eji njirimara Ping Pong PHY, njikọ example imewe na-agụnye okporo ụzọ abụọ generators na-enye iwu na abụọ nọọrọ onwe ebe nchekwa ngwaọrụ site na abụọ nọọrọ onwe ha njikwa na a nkịtị PHY, dị ka e gosiri na-esonụ foto.

Ọgụgụ 7. Synthesis ExampNhazi maka Ping Pong PHY

Ọ bụrụ na ị na-eji RLDRAM 3, onye na-emepụta okporo ụzọ na njikọ example imewe na-ekwurịta okwu ozugbo na PHY site na iji AFI, dị ka egosiri na foto na-esonụ.

Ọgụgụ 8. Synthesis Example Kere maka RLDRAM 3 Interface

Rịba ama: Ọ bụrụ na otu ma ọ bụ karịa nke PLL Sharing Mode, DLL Sharing Mode, ma ọ bụ OCT Ịkekọrịta Mode ka edobere uru ọ bụla ọzọ karịa Enweghị Ịkekọrịta, njikọ ex.ample imewe ga-enwe okporo ụzọ generator/nchekwa interface ihe atụ. A na-ejikọta ihe atụ generator/ntụgharị ebe nchekwa okporo ụzọ abụọ ahụ naanị site na njikọ PLL/DLL/OCT kekọrịtara dịka ntọala oke akọwapụtara. Ihe atụ ihe na-emepụta okporo ụzọ/ihe ebe nchekwa na-egosi otu ị ga-esi mee njikọ dị otú ahụ n'ụdị nke gị.
Mara: Mgbasa njikọ nke ndị ọzọ dịka akọwara na ntuziaka onye ọrụ Intel Quartus Prime Standard Edition: Synthesis nke ndị ọzọ abụghị ihe nkwado maka EMIF IP.
Ozi metụtara
Na-amụpụta EMIF Design Synthesizable Example na

Simulation Example Design
Simulation example imewe nwere isi blocks egosiri na ndị a.

• Ihe atụ nke njikọ example imewe. Dị ka akọwara na ngalaba gara aga, njikọ example imewe nwere a okporo ụzọ generator na ihe atụ nke ebe nchekwa interface. Ndị a na-egbochi ndabara na ụdị ịme anwansị nkịtị ebe ọ dabara adaba maka ịme anwansị ngwa ngwa.
• Ụdị ebe nchekwa, nke na-arụ ọrụ dị ka ihe atụ nke na-agbaso nkọwa usoro ebe nchekwa. Ọtụtụ mgbe, ndị na-ere ebe nchekwa na-enye ụdị ịme anwansị maka akụrụngwa ebe nchekwa ha akọwapụtara nke ị nwere ike ibudata na ha websaịtị.
• Onye na-enyocha ọkwa, nke na-enyocha akara ọkwa site na interface ebe nchekwa IP na mpụta okporo ụzọ, iji gosi ọkwa ngafe ma ọ bụ ọnọdụ dara.

Ọgụgụ 9. Simulation Example Design

Ọ bụrụ na ị na-eji njirimara Ping Pong PHY, simulation example imewe na-agụnye okporo ụzọ abụọ generators na-enye iwu na abụọ nọọrọ onwe ebe nchekwa ngwaọrụ site na abụọ nọọrọ onwe ha njikwa na a nkịtị PHY, dị ka e gosiri na-esonụ foto.

Ọgụgụ 10. Simulation ExampNhazi maka Ping Pong PHY

Ọ bụrụ na ị na-eji RLDRAM 3, onye na-emepụta okporo ụzọ na simulation example imewe na-ekwurịta okwu ozugbo na PHY site na iji AFI, dị ka egosiri na foto na-esonụ.

Ọgụgụ 11. Simulation Example Kere maka RLDRAM 3 Interface

Ozi metụtara
Na-emepụta EMIF Design Example maka Simulation on

Exampma chepụta Interface Tab
Onye nchịkọta akụkọ parameter gụnyere Example Designs tab nke na-enye gị ohere ịmekọrịta na ịmepụta onye bụbu gịample atumatu.l
Dị Example Ngalaba Nhazi
The Select design pulldown na-enye gị ohere ịhọrọ ex chọrọ example imewe. Ugbu a, EMIF Example Design bụ naanị nhọrọ dị, ma ahọpụtara na ndabara.

Akụkọ ndozigharị akwụkwọ maka nrụnye ebe nchekwa mpụga Intel Stratix 10 FPGA IP Design Example ntuziaka onye ọrụ

Ụdị akwụkwọ	Intel Quartus Prime Version	Mgbanwe
2021.03.29	21.1	• N'ime Example Kere ngwa ngwa mmalite isi, wepụrụ ntụaka aka na simulator NCsim*.
2018.09.24	18.1	• Ọnụọgụ emelitere na Na-amụpụta EMIF Design Synthesizable Example na Na-emepụta EMIF Design Example maka Simulation isiokwu.
2018.05.07	18.0	• Gbanwee aha akwụkwọ site na Intel Stratix 10 Mpụga Ebe nchekwa Interface IP Design Example ntuziaka onye ọrụ ka Interface ebe nchekwa mpụga Intel Stratix 10 FPGA IP Design Example ntuziaka onye ọrụ. • ntụpọ mgbọ emeziri gafereview ngalaba nke Ntinye pin maka Intel Stratix 10 EMIF IP isiokwu.

Ụbọchị	Ụdị	Mgbanwe
Nọvemba 2017	2017.11.06	Ntọhapụ mbụ.

Ụlọ ọrụ Intel. Ikike niile echekwabara. Intel, akara Intel, na akara Intel ndị ọzọ bụ ụghalaahịa nke Intel Corporation ma ọ bụ ndị enyemaka ya. Intel nyere ikike ịrụ ọrụ nke FPGA na ngwaahịa semiconductor na nkọwapụta ugbu a dịka akwụkwọ ikike ọkọlọtọ Intel siri dị, mana nwere ikike ịme mgbanwe na ngwaahịa na ọrụ ọ bụla n'oge ọ bụla na-enweghị ọkwa. Intel anaghị ewere ọrụ ọ bụla ma ọ bụ ụgwọ sitere na ngwa ma ọ bụ iji ozi ọ bụla, ngwaahịa ma ọ bụ ọrụ akọwara n'ime ebe a belụsọ dị ka Intel kwetara na ederede. A dụrụ ndị ahịa Intel ọdụ ka ha nweta ụdị nkọwa ngwaọrụ kachasị ọhụrụ tupu ha adabere na ozi ọ bụla ebipụtara yana tupu ịnye iwu maka ngwaahịa ma ọ bụ ọrụ. * Enwere ike ịzọrọ aha na akara ndị ọzọ dị ka ihe onwunwe nke ndị ọzọ.

Akwụkwọ / akụrụngwa

Intel ebe nchekwa mpụga Intel Stratix 10 FPGA IP Design Example [pdf] Ntuziaka onye ọrụ Interface ebe nchekwa mpụga Intel Stratix 10 FPGA IP Design Example, Mpụga, Ebe nchekwa Interfaces Intel Stratix 10 FPGA IP Design Example, Intel Stratix 10 FPGA IP Design Example, 10 FPGA IP Design Example

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