UG-20219 Sab Nraud Memory Interfaces Intel Agilex FPGA IP Tsim Example

Txog Sab Nraud Memory Interfaces Intel® Agilexâ ¢ FPGA IP

Tshaj tawm cov ntaub ntawv

IP versions yog tib yam li Intel® Quartus® Prime Design Suite software versions mus txog v19.1. Los ntawm Intel Quartus Prime Design Suite software version 19.2 lossis tom qab ntawd, IP cores muaj cov txheej txheem tshiab IP versioning. Tus IP versioning scheme (XYZ) tus lej hloov ntawm ib qho software version mus rau lwm qhov. Kev hloov hauv:

• X qhia txog kev hloov kho loj ntawm IP. Yog tias koj hloov kho koj lub Intel Quartus Prime software, koj yuav tsum rov tsim dua tus IP.
• Y qhia tias tus IP suav nrog cov yam ntxwv tshiab. Rov tsim koj tus IP kom suav nrog cov yam ntxwv tshiab no.
• Z qhia tias IP suav nrog kev hloov pauv me me. Rov tsim koj tus IP kom suav nrog cov kev hloov pauv no.
  

  Yam khoom	Kev piav qhia
  IP Version	2.4.2
  Intel Quartus Prime	21.2
  Hnub tso tawm	2021.06.21

Tsim Example Phau Ntawv Qhia Pib Ceev rau Sab Nraud Memory Interfaces Intel Agilex™ FPGA IP

Ib qho automated tsim example flow muaj rau Intel Agilex™ sab nraud nco interfaces. Lub Generate Example Designs khawm ntawm Example Designs tab tso cai rau koj los qhia thiab tsim cov synthesis thiab simulation tsim example file teeb tsa uas koj tuaj yeem siv los txheeb xyuas koj tus EMIF IP. Koj tuaj yeem tsim tus qauv tsim example uas phim Intel FPGA cov khoom siv txhim kho, lossis rau ib qho EMIF IP uas koj tsim. Koj tuaj yeem siv tus qauv tsim example los pab koj qhov kev ntsuam xyuas, lossis ua qhov pib rau koj tus kheej qhov system.

General Design Example Workflows

Tsim ib qho EMIF Project

Rau nws Intel Quartus Prime software version 17.1 thiab tom qab ntawd, koj yuav tsum tsim ib qhov project Intel Quartus Prime ua ntej tsim EMIF IP thiab tsim example.

1. Tua tawm Intel Quartus Prime software thiab xaiv File ➤ New Project Wizard. Nyem Next. Tsim Example Phau Ntawv Qhia Pib Ceev rau Sab Nraud Memory Interfaces Intel Agilex™ FPGA IP
2. Qhia ib daim ntawv teev npe ( ), lub npe rau Intel Quartus Prime project ( ), thiab lub npe ntawm lub tuam txhab tsim sab saum toj ( ) uas koj xav tsim. Nyem Next.
3. Xyuas kom meej tias Empty Project raug xaiv. Nyem Next ob zaug.
4. Hauv Tsev Neeg, xaiv Intel Agilex.
5. Hauv lub npe lim, ntaus tus lej ntaus ntawv.
6. Hauv Cov Khoom Siv Muaj, xaiv lub cuab yeej tsim nyog.
7. Nyem Ua kom tiav.

Tsim thiab Configuring EMIF IP

Cov kauj ruam hauv qab no qhia txog yuav ua li cas tsim thiab teeb tsa EMIF IP. Qhov kev taug kev no tsim DDR4 interface, tab sis cov kauj ruam zoo sib xws rau lwm cov txheej txheem. (Cov kauj ruam no ua raws li IP Catalog (standalone) ntws; yog tias koj xaiv siv Platform Designer (system) ntws, cov kauj ruam zoo sib xws.)

1. Hauv qhov rai IP Catalog, xaiv Sab Nraud Memory Interfaces Intel Agilex FPGA IP. (Yog tias lub qhov rais IP Catalog tsis pom, xaiv View ➤ IP Catalog.)
2. Hauv IP Parameter Editor, muab lub npe chaw rau EMIF IP (lub npe uas koj muab ntawm no dhau los ua tus file npe rau tus IP) thiab qhia cov npe. Nyem Tsim.
3. Tus kws kho qhov ntsuas muaj ntau lub tab uas koj yuav tsum teeb tsa qhov ntsuas kom cuam tshuam koj qhov kev siv EMIF.

Intel Agilex EMIF Parameter Editor Cov Lus Qhia
Cov ncauj lus no muab cov lus qhia qib siab rau kev ntsuas cov tab hauv Intel Agilex EMIF IP parameter editor.

Table 1. EMIF Parameter Editor Cov Lus Qhia

Parameter Editor Tab	Cov lus qhia
General	Xyuas kom meej tias cov kev ntsuas hauv qab no tau nkag mus kom raug: • Qib ceev rau lub cuab yeej. • Lub cim xeeb moos zaus. • PLL siv moos zaus.
Nco	• Xa mus rau daim ntawv teev cov ntaub ntawv rau koj lub cim xeeb ntaus ntawv nkag mus rau cov tsis nyob rau hauv lub Nco tab. • Koj yuav tsum nkag mus rau qhov chaw tshwj xeeb rau ALERT# tus pin. (Siv rau DDR4 lub cim xeeb raws tu qauv nkaus xwb.)
Mem I/O	• Rau qhov kev tshawb nrhiav thawj zaug, koj tuaj yeem siv qhov chaw pib ntawm lub Mem I/O tab. • Rau kev tsim kho siab heev, koj yuav tsum ua lub rooj tsavxwm simulation kom tau txais qhov kev txiav txim siab zoo.
FPGA I/O	• Rau qhov kev tshawb nrhiav thawj zaug, koj tuaj yeem siv qhov chaw pib ntawm lub FPGA I/O tab. • Rau kev siv tau zoo tshaj plaws, koj yuav tsum ua lub rooj tsavxwm simulation nrog cov qauv IBIS los xaiv cov qauv tsim nyog I/O.
Mem sij hawm	• Rau qhov kev tshawb nrhiav thawj zaug, koj tuaj yeem siv qhov chaw pib ntawm lub Mem sij hawm tab. • Rau kev tsim kho siab heev, koj yuav tsum nkag mus rau qhov tsis raws li koj lub cim xeeb ntaus ntawv cov ntaub ntawv.
Tus tswj	Teem tus maub los tsis raws li qhov xav tau kev teeb tsa thiab tus cwj pwm rau koj lub cim xeeb tswj.
Kev kuaj mob	Koj tuaj yeem siv cov parameter ntawm lub Kev kuaj mob tab los pab hauv kev sim thiab debugging koj lub cim xeeb interface.
Example Designs	Cov Example Designs tab cia koj tsim tsim examples rau synthesis thiab simulation. Tus tsim tsim example yog ua tiav EMIF system uas muaj EMIF IP thiab tus tsav tsheb uas tsim cov tsheb khiav mus los kom siv tau lub cim xeeb interface.

Yog xav paub cov ntaub ntawv ntxaws ntxaws ntawm tus kheej tsis muaj, xa mus rau tshooj tsim nyog rau koj lub cim xeeb raws tu qauv hauv Sab Nraud Memory Interfaces Intel Agilex FPGA IP Tus Neeg Siv Qhia.

Tsim cov Synthesizable EMIF Tsim Example

Rau cov khoom siv txhim kho Intel Agilex, nws txaus los tawm feem ntau ntawm Intel Agilex EMIF IP chaw ntawm lawv qhov tseem ceeb. Txhawm rau tsim kom muaj cov qauv tsim ua ke example, ua raws li cov kauj ruam no:

1. Hauv Example Designs tab, xyuas kom meej tias lub thawv Synthesis raug kuaj xyuas.
   • Yog tias koj tab tom siv ib qho interface example tsim, configure EMIF IP thiab nias File➤ Txuag kom txuag tau qhov teeb tsa tam sim no rau hauv tus neeg siv IP hloov pauv file ( .ip).
     • Yog tias koj tab tom siv tus example tsim nrog ntau yam interfaces, qhia Tus lej ntawm IPs rau tus lej xav tau ntawm cov interfaces. Koj tuaj yeem pom tag nrho tus lej ntawm EMIF ID tib yam li tus naj npawb ntawm IPs xaiv. Ua raws li cov kauj ruam no los teeb tsa txhua qhov interface:
   •  Xaiv Cal-IP kom qhia meej qhov kev sib txuas ntawm lub interface mus rau Calibration IP.
   • Configure EMIF IP raws li nyob rau hauv tag nrho cov Parameter Editor Tab.
   • Rov qab mus rau Example Tsim tab thiab nyem Capture ntawm qhov xav tau EMIF ID.
   • Rov ua kauj ruam a mus rau c rau tag nrho EMIF ID.
   • Koj tuaj yeem nyem lub pob Clear kom tshem tawm cov tsis tau ntes thiab rov ua kauj ruam a mus rau c kom hloov pauv rau EMIF IP.
   • Nyem File➤ Txuag kom txuag tau qhov teeb tsa tam sim no rau hauv tus neeg siv IP hloov pauv file ( .ip).
2. Nyem Tsim Example Tsim nyob rau sab xis sab xis ntawm lub qhov rais.
3. Qhia kom meej ib daim ntawv teev npe rau EMIF tsim example thiab nias OK. Kev vam meej tiam ntawm EMIF tsim example tsim cov hauv qab no fileset under a qii directory.
4. Nyem File ➤ Tawm kom tawm ntawm IP Parameter Editor Pro qhov rai. Lub kaw lus ceeb toom, tsis ntev los no kev hloov pauv tsis tau tsim. Tsim tam sim no? Nyem Tsis yog mus txuas ntxiv nrog cov ntws tom ntej.
5. Qhib tus example design, click File ➤ Qhib Project, thiab mus rau qhov /ample_name>/qii/ed_synth.qpf thiab nyem Qhib.
   Nco tseg: Yog xav paub ntxiv txog kev suav sau thiab programming tus tsim example, refer
   Compiling thiab Programming Intel Agilex EMIF Tsim Example.

Daim duab 4. Generated Synthesizable Design Example File Qauv

Yog xav paub ntxiv txog kev tsim ib lub kaw lus nrog ob lossis ntau qhov chaw nco sab nraud, xa mus rau Tsim Tsim Example nrog Ntau EMIF Interfaces, hauv Sab Nraud Memory Interfaces Intel Agilex FPGA IP Tus Neeg Siv Qhia. Rau cov ntaub ntawv ntawm kev debugging ntau qhov sib cuam tshuam, xa mus rau Kev Ua Haujlwm EMIF Cov Khoom Siv Hauv Kev Tsim Nyog, hauv Sab Nraud Memory Interfaces Intel Agilex FPGA IP Tus Neeg Siv Qhia.

Nco tseg: Yog hais tias koj tsis xaiv lub Simulation los yog Synthesis checkbox, lub lo lus uas peb directory muaj tsuas yog Platform Designer tsim files, uas tsis suav nrog Intel Quartus Prime software ncaj qha, tab sis qhov koj tuaj yeem ua tau view lossis hloov kho hauv Platform Designer. Hauv qhov xwm txheej no koj tuaj yeem khiav cov lus txib hauv qab no los tsim cov synthesis thiab simulation file teeb.

• Txhawm rau tsim ib qhov project compilable, koj yuav tsum khiav lub quartus_sh -t make_qii_design.tclscript nyob rau hauv lo lus uas peb directory.
• Txhawm rau tsim qhov project simulation, koj yuav tsum khiav quartus_sh -t make_sim_design.tcl tsab ntawv nyob rau hauv lo lus uas peb directory.

Nco tseg: Yog hais tias koj tau tsim ib tug tsim example thiab tom qab ntawd hloov pauv rau nws hauv parameter editor, koj yuav tsum rov tsim dua tus qauv tsim example saib koj cov kev hloov pauv tau ua. Tus tshiab tsim tsim example tsis overwrite tus tsim uas twb muaj lawm example files.

Tsim cov EMIF Design Examprau Simulation

Rau cov khoom siv txhim kho Intel Agilex, nws txaus los tawm feem ntau ntawm Intel Agilex EMIF IP chaw ntawm lawv qhov tseem ceeb. Tsim kom muaj tus tsim example rau simulation, ua raws li cov kauj ruam no:

1. Hauv Example Designs tab, xyuas kom meej tias lub thawv Simulation raug kuaj xyuas. Kuj xaiv qhov yuav tsum tau Simulation HDL hom, xws li Verilog lossis VHDL.
2. Configure EMIF IP thiab nyem File ➤ Txuag kom txuag tau qhov teeb tsa tam sim no rau hauv tus neeg siv IP hloov pauv file ( .ip).
3. Nyem Tsim Example Tsim nyob rau sab xis sab xis ntawm lub qhov rais.
4. Qhia kom meej ib daim ntawv teev npe rau EMIF tsim example thiab nias OK. Kev vam meej tiam ntawm EMIF tsim example tsim ntau yam file teeb tsa rau ntau yam kev txhawb nqa simulators, nyob rau hauv daim ntawv qhia sim / ed_sim.
5. Nyem File ➤ Tawm kom tawm ntawm IP Parameter Editor Pro qhov rai. Lub kaw lus ceeb toom, tsis ntev los no kev hloov pauv tsis tau tsim. Tsim tam sim no? Nyem Tsis yog mus txuas ntxiv nrog cov ntws tom ntej.

Tsim Simulation Design Example File Qauv

Nco tseg: Sab Nraud Memory Interfaces Intel Agilex FPGA IP tam sim no txhawb nqa tsuas yog VCS, ModelSim/QuestaSim, thiab Xcelium simulators. Kev txhawb nqa simulator ntxiv yog npaj rau yav tom ntej tso tawm.

Nco tseg: Yog hais tias koj tsis xaiv lub Simulation los yog Synthesis checkbox, lub lo lus uas peb directory muaj tsuas yog Platform Designer tsim files, uas tsis suav nrog Intel Quartus Prime software ncaj qha, tab sis qhov koj tuaj yeem ua tau view lossis hloov kho hauv Platform Designer. Hauv qhov xwm txheej no koj tuaj yeem khiav cov lus txib hauv qab no los tsim cov synthesis thiab simulation file teeb.

• Txhawm rau tsim ib qhov project compilable, koj yuav tsum khiav quartus_sh -t make_qii_design.tcl tsab ntawv nyob rau hauv lo lus uas peb directory.
• Txhawm rau tsim qhov project simulation, koj yuav tsum khiav quartus_sh -t make_sim_design.tcl tsab ntawv nyob rau hauv lo lus uas peb directory.

Nco tseg: Yog hais tias koj tau tsim ib tug tsim example thiab tom qab ntawd hloov pauv rau nws hauv parameter editor, koj yuav tsum rov tsim dua tus qauv tsim example saib koj cov kev hloov pauv tau ua. Tus tshiab tsim tsim example tsis overwrite tus tsim uas twb muaj lawm example files.

Simulation Versus Hardware Implementation
Rau sab nraud nco interface simulation, koj tuaj yeem xaiv hla dhau calibration lossis tag nrho calibration ntawm Diagnostics tab thaum IP tiam.

EMIF Simulation Qauv
Cov lus no sib piv cov yam ntxwv ntawm hla calibration thiab tag nrho cov qauv calibration.

Table 2. EMIF Simulation Models: Hla Calibration piv rau Full Calibration

Hla Calibration	Calibration tag nrho
System-level simulation tsom rau cov neeg siv cov logic.	Memory interface simulation tsom rau calibration.
Cov ntsiab lus ntawm calibration tsis raug ntes.	Captures tag nrho stagyog calibration.
Nws muaj peev xwm khaws thiab khaws cov ntaub ntawv.	Xws li leveling, per-ntsis deskew, thiab lwm yam.
Sawv cev muaj tseeb efficiency.
Tsis xav txog board skew.

RTL Simulation Versus Hardware Implementation
Cov lus no qhia txog qhov sib txawv tseem ceeb ntawm EMIF simulation thiab kev siv kho vajtse.

Table 3. EMIF RTL Simulation Versus Hardware Implementation

RTL Simulation	Hardware Implementation
Nios® pib thiab calibration code ua nyob rau hauv parallel.	Nios pib thiab calibration code ua sequentially.
Interfaces lees paub cal_done teeb liab ib txhij hauv simulation.	Fitter kev khiav hauj lwm txiav txim qhov kev txiav txim ntawm calibration, thiab interfaces tsis lees tias cal_done ib txhij.

Koj yuav tsum khiav RTL simulations raws li cov qauv tsheb khiav rau koj tus tsim daim ntawv thov. Nco ntsoov tias RTL simulation tsis ua qauv PCB kab qeeb uas yuav ua rau muaj qhov sib txawv ntawm latency ntawm RTL simulation thiab kho vajtse siv.

 Simulating Sab Nraud Memory Interface IP Nrog ModelSim
Cov txheej txheem no qhia tau hais tias yuav ua li cas simulate EMIF tsim example.

1. Tua tawm Mentor Graphics* ModelSim software thiab xaiv File ➤ Hloov Daim Ntawv Teev Npe. Nkag mus rau sim / ed_sim / tus kws qhia ntawv hauv cov qauv tsim tawm example folder.
2. Xyuas kom tseeb tias lub qhov rais Transcript tshwm nyob rau hauv qab ntawm qhov screen. Yog tias lub qhov rais Transcript tsis pom, tso nws los ntawm txhaj View ➤ Cov ntawv sau tseg.
3. Nyob rau hauv lub qhov rais Transcript, khiav qhov chaw msim_setup.tcl.
4. Tom qab qhov chaw msim_setup.tcl ua tiav, khiav ld_debug nyob rau hauv lub qhov rais Transcript.
5. Tom qab ld_debug ua tiav khiav, xyuas kom meej tias cov khoom qhov rai tau tshwm sim. Yog hais tias cov khoom qhov rais tsis pom, tso saib nws los ntawm txhaj View ➤ Yam khoom.
6. Hauv Cov Khoom Qhov rai, xaiv cov cim uas koj xav simulate los ntawm txoj cai-nias thiab xaiv Ntxiv Wave.
7. Tom qab koj ua tiav kev xaiv cov cim rau kev simulation, ua haujlwm khiav -tag nrho hauv lub qhov rais Transcript. Lub simulation khiav mus txog thaum nws ua tiav.
8. Yog tias qhov kev simulation tsis pom, nyem View ➤ Wave.

Pin Placement rau Intel Agilex EMIF IP
Lub ncauj lus no muab cov lus qhia rau kev tso tus pin.

Tshajview
Intel Agilex FPGAs muaj cov qauv hauv qab no:

• Txhua lub cuab yeej muaj txog li 8 lub txhab nyiaj I/O.
• Txhua lub txhab nyiaj I/O muaj 2 lub txhab nyiaj sub-I/O.
• Txhua lub txhab nyiaj sub-I/O muaj 4 txoj kab.
• Txhua txoj kab muaj 12 lub hom phiaj dav dav I / O (GPIO) tus pins.

General Pin Guidelines
Cov hauv qab no yog cov lus qhia dav dav.

Nco tseg: Yog xav paub ntxiv tus pin cov ntaub ntawv, xa mus rau Intel Agilex FPGA EMIF IP Pin thiab Kev Npaj Pabcuam hauv tshooj lus tshwj xeeb rau koj cov txheej txheem nco sab nraud, nyob rau sab nraud Memory Interfaces Intel Agilex FPGA IP Tus Neeg Siv Qhia.

• Xyuas kom meej tias cov pins rau qhov muab kev nco sab nraud nyob hauv tib I / O kab.
• Interfaces uas hla ntau lub tsev txhab nyiaj yuav tsum ua raws li cov cai hauv qab no:
  •  Lub tsev txhab nyiaj yuav tsum nyob ib sab ntawm ib leeg. Yog xav paub ntaub ntawv ntawm cov tsev txhab nyiaj uas nyob ib sab, xa mus rau EMIF Architecture: I/O Bank cov ncauj lus nyob rau sab nraud Memory Interfaces Intel Agilex FPGA IP Tus Neeg Siv Qhia.
•  Txhua qhov chaw nyob thiab cov lus txib thiab cov pins cuam tshuam yuav tsum nyob hauv ib lub txhab nyiaj subbank.
• Chaw nyob thiab cov lus txib thiab cov ntaub ntawv tus pins tuaj yeem sib koom lub txhab nyiaj sub-bank raws li hauv qab no:
  • Chaw nyob thiab cov lus txib thiab cov ntaub ntawv tus pins tsis tuaj yeem sib koom ib txoj kab I/O.
  • Tsuas yog ib txoj kab uas tsis siv I/O nyob rau hauv qhov chaw nyob thiab hais kom ua lub txhab nyiaj tuaj yeem muaj cov ntaub ntawv pins.

Table 4. General Pin Constraints

Hom teeb liab	Kev txwv
Data Strobe	Tag nrho cov teeb liab uas yog pawg DQ yuav tsum nyob hauv tib txoj kab I/O.
Cov ntaub ntawv	Related DQ pins yuav tsum nyob hauv tib txoj kab I/O. Rau cov kev cai uas tsis txhawb nqa cov ntaub ntawv ob kab lus, nyeem cov cim yuav tsum tau muab cais los ntawm kev sau cov cim.
Chaw nyob thiab hais kom ua	Chaw nyob thiab Command pins yuav tsum nyob hauv qhov chaw uas tau teev tseg hauv lub txhab nyiaj I/O sub-bank.

Nco tseg: Yog xav paub ntxiv tus pin cov ntaub ntawv, xa mus rau Intel Agilex FPGA EMIF IP Pin thiab Kev Npaj Pabcuam hauv tshooj lus tshwj xeeb rau koj cov txheej txheem nco sab nraud, nyob rau sab nraud Memory Interfaces Intel Agilex FPGA IP Tus Neeg Siv Qhia.

• Xyuas kom meej tias cov pins rau qhov muab kev nco sab nraud nyob hauv tib I / O kab.
• Interfaces uas hla ntau lub tsev txhab nyiaj yuav tsum ua raws li cov cai hauv qab no:
  • Lub tsev txhab nyiaj yuav tsum nyob ib sab ntawm ib leeg. Yog xav paub ntaub ntawv ntawm cov tsev txhab nyiaj uas nyob ib sab, xa mus rau EMIF Architecture: I/O Bank cov ncauj lus nyob rau sab nraud Memory Interfaces Intel Agilex FPGA IP Tus Neeg Siv Qhia.
• Txhua qhov chaw nyob thiab cov lus txib thiab cov pins cuam tshuam yuav tsum nyob hauv ib lub txhab nyiaj subbank.
• Chaw nyob thiab cov lus txib thiab cov ntaub ntawv tus pins tuaj yeem sib koom lub txhab nyiaj sub-bank raws li hauv qab no:
  • Chaw nyob thiab cov lus txib thiab cov ntaub ntawv tus pins tsis tuaj yeem sib koom ib txoj kab I/O.
  • Tsuas yog ib txoj kab uas tsis siv I/O nyob rau hauv qhov chaw nyob thiab hais kom ua lub txhab nyiaj tuaj yeem muaj cov ntaub ntawv pins.

Tsim ib tug Design Example nrog TG Configuration Option

Tus tsim EMIF tsim example suav nrog lub tsheb tsim hluav taws xob thaiv (TG). Los ntawm lub neej ntawd, tus tsim example siv qhov yooj yim TG thaiv (altera_tg_avl) uas tsuas tuaj yeem rov pib dua thiaj li rov pib dua tus qauv tsheb khiav nyuaj. Yog tias tsim nyog, koj tuaj yeem xaiv los ua kom lub tshuab hluav taws xob teeb tsa (TG2) hloov. Nyob rau hauv lub configurable tsheb generator (TG2) (altera_tg_avl_2), koj muaj peev xwm configure lub tsheb qauv nyob rau hauv lub sij hawm los ntawm kev tswj registers - txhais tau hais tias koj tsis tas yuav recompile tus tsim los hloov los yog relaunch lub tsheb qauv. Lub tshuab hluav taws xob tsheb no muab kev tswj xyuas zoo ntawm hom tsheb uas nws xa mus rau EMIF tswj interface. Tsis tas li ntawd, nws muab cov xwm txheej sau npe uas muaj cov ncauj lus kom ntxaws txog kev ua tsis tiav.

Ua kom muaj tsheb khiav hauv lub tshuab hluav taws xob tsim Example

Koj tuaj yeem ua kom lub tshuab hluav taws xob teeb tsa tau los ntawm Diagnostics tab hauv EMIF parameter editor. Txhawm rau pab kom lub tshuab hluav taws xob teeb tsa tau teeb tsa, qhib Siv lub tshuab hluav taws xob Avalon teeb tsa 2.0 ntawm Diagnostics tab.

Daim duab 6.

• Koj tuaj yeem xaiv lov tes taw cov qauv tsheb khiav stage los yog userconfigured tsheb stage, tab sis koj yuav tsum muaj tsawg kawg ib stagua enabled. Rau cov ntaub ntawv ntawm cov stages, xa mus rau Default Traffic Pattern thiab User-configured Traffic Pattern in the External Memory Interfaces Intel Agilex FPGA IP User Guide.
• TG2 qhov ntsuas lub sijhawm ntsuas tsuas yog siv rau cov qauv kev tsav tsheb. Koj tuaj yeem xaiv lub sijhawm xeem luv luv, nruab nrab, lossis tsis kawg.
• Koj tuaj yeem xaiv ob qho ntawm ob qhov tseem ceeb rau TG2 Configuration Interface Mode parameter:
  • JTAG: Tso cai siv GUI hauv qhov system console. Yog xav paub ntxiv, xa mus rau Traffic Generator Configuration Interface nyob rau sab nraud Memory Interfaces Intel Agilex FPGA IP Tus Neeg Siv Qhia.
  • Export: Tso cai siv kev cai RTL logic los tswj cov qauv tsheb.

Siv tus Design Exampnrog rau EMIF Debug Toolkit

Ua ntej tshaj tawm EMIF Debug Toolkit, xyuas kom meej tias koj tau teeb tsa koj lub cuab yeej nrog lub programming file uas muaj EMIF Debug Toolkit enabled. Txhawm rau tso tawm EMIF Debug Toolkit, ua raws li cov kauj ruam no:

1. Hauv Intel Quartus Prime software, qhib qhov System Console los ntawm xaiv Cov Cuab Yeej ➤ System Debugging Tools ➤ System Console.
2. [Hloov cov kauj ruam no yog tias koj qhov project twb tau qhib hauv Intel Quartus Prime software.] Hauv System Console, thauj khoom SRAM file (.sof) uas koj tau teeb tsa lub rooj tsavxwm (raws li tau piav qhia hauv Cov Lus Qhia Ua Ntej rau Kev Siv EMIF Debug Toolkit, hauv Sab Nraud Memory Interfaces Intel Agilex FPGA IP Tus Neeg Siv Qhia).
3. Xaiv cov xwm txheej los daws qhov teeb meem.
4. Xaiv EMIF Calibration Debug Toolkit rau EMIF calibration debugging, raws li tau piav qhia hauv Kev Tsim Tus Qauv Exampnrog rau Calibration Debug Option. Xwb, xaiv EMIF TG Configuration Toolkit rau tsheb khiav generator debugging, raws li tau piav nyob rau hauv Tsim ib tug Tsim Example nrog TG Configuration Option.
5. Nyem Qhib Toolkit qhib lub ntsiab view ntawm EMIF Debug Toolkit.
6. Yog tias muaj ntau yam EMIF hauv qhov programmed tsim, xaiv kab (txoj kev mus rau JTAG master) thiab cim xeeb interface ID ntawm EMIF piv txwv uas yuav qhib lub cuab yeej.
7. Nyem Qhib Interface kom tso cai rau cov khoom siv los nyeem cov kev cuam tshuam cuam tshuam thiab ntsuas qhov xwm txheej.
8. Koj yuav tsum debug ib interface ntawm ib lub sij hawm; Yog li ntawd, txhawm rau txuas mus rau lwm qhov interface hauv qhov tsim, koj yuav tsum xub deactivate lub interface tam sim no.

Cov hauv qab no yog examples ntawm cov lus ceeb toom los ntawm EMIF Calibration Debug Toolkit thiab EMIF TG Configuration Toolkit:, feem.

Nco tseg: Rau cov ntsiab lus ntawm calibration debugging, xa mus rau Debugging nrog Sab Nraud Memory Interface Debug Toolkit, nyob rau sab nraud Memory Interfaces Intel Agilex FPGA IP Tus Neeg Siv Qhia.

Nco tseg: Yog xav paub meej txog lub tshuab hluav taws xob kev debugging, xa mus rau Traffic Generator Configuration User Interface, nyob rau sab nraud Memory Interfaces Intel Agilex FPGA IP Tus Neeg Siv Qhia.

Tsim Example Description for External Memory Interfaces Intel Agilex FPGA IP

Thaum koj parameterize thiab tsim koj tus IP EMIF, koj tuaj yeem qhia meej tias lub kaw lus tsim cov npe rau simulation thiab synthesis file sets, thiab generate cov file teem cia li. Yog tias koj xaiv Simulation lossis Synthesis hauv Examptsim Files pe Example Designs tab, lub kaw lus tsim kom tiav simulation file teeb los yog ua kom tiav synthesis file teem, raws li koj xaiv.

Synthesis Design Example
Synthesis tsim example muaj cov blocks loj qhia hauv daim duab hauv qab no.

• Lub tshuab hluav taws xob tsheb, uas yog ib qho kev sib xyaw ua ke Avalon®-MM example tus tsav tsheb uas siv cov qauv pseudo-random ntawm kev nyeem thiab sau rau tus lej ntawm qhov chaw nyob. Lub tshuab hluav taws xob tsheb kuj tseem saib xyuas cov ntaub ntawv nyeem los ntawm lub cim xeeb kom ntseeg tau tias nws phim cov ntaub ntawv sau thiab lees paub qhov ua tsis tiav.
• Ib qho piv txwv ntawm lub cim xeeb interface, uas suav nrog:
  • Lub cim xeeb tswj uas nruab nrab ntawm Avalon-MM interface thiab AFI interface.
  • Lub PHY, uas ua haujlwm los ntawm kev sib txuas ntawm lub cim xeeb tswj thiab lwm lub cim xeeb los ua haujlwm nyeem thiab sau ntawv.

Daim duab 7. Synthesis Design Example

Nco tseg: Yog tias ib qho lossis ntau dua ntawm PLL Sib Koom Hom, DLL Sib Koom Hom, lossis OCT Sib Koom Hom tsis raug teeb tsa rau ib qho txiaj ntsig uas tsis yog Kev Sib Koom, qhov sib koom tsim example yuav muaj ob lub tshuab hluav taws xob / lub cim xeeb interface. Ob lub tshuab hluav taws xob hluav taws xob / lub cim xeeb cuam tshuam tsuas yog cuam tshuam los ntawm kev sib koom PLL / DLL / OCTconnections raws li tau hais los ntawm qhov ntsuas qhov ntsuas. Lub tshuab hluav taws xob tsheb / lub cim xeeb interface piv txwv qhia tias koj tuaj yeem ua li cas sib txuas hauv koj tus kheej tsim.

Simulation Design Example
Lub simulation tsim example muaj cov blocks loj uas pom hauv daim duab hauv qab no.

• Ib qho piv txwv ntawm kev tsim qauv tsim example. Raws li tau piav nyob rau hauv nqe lus dhau los, lub synthesis tsim example muaj lub tshuab hluav taws xob tsheb, calibration tivthaiv, thiab ib qho piv txwv ntawm lub cim xeeb interface. Cov blocks default rau abstract simulation qauv uas tsim nyog rau ceev simulation.
• Lub cim xeeb qauv, uas ua raws li ib tug generic qauv uas ua raws li lub cim xeeb raws tu qauv specifications. Feem ntau, cov neeg muag khoom nco muab cov qauv simulation rau lawv cov cim xeeb tshwj xeeb uas koj tuaj yeem rub tawm los ntawm lawv webqhov chaw.
• Tus neeg saib xyuas xwm txheej, uas saib xyuas cov xwm txheej teeb liab los ntawm lub cim xeeb sab nraud interface IP thiab lub tshuab hluav taws xob tsheb, kom pom qhov kev hla dhau lossis tsis ua haujlwm.

Daim duab 10. Simulation Design Example

Example Designs Interface Tab
Cov parameter editor suav nrog Example Designs tab uas tso cai rau koj mus parameterize thiab tsim koj tus tsim examples.

Sab nraud Memory Interfaces Intel Agilex FPGA IP Tsim Example User Guide Archives

IP versions yog tib yam li Intel Quartus Prime Design Suite software versions mus txog v19.1. Los ntawm Intel Quartus Prime Design Suite software version 19.2 lossis tom qab ntawd, IPs muaj cov txheej txheem IP tshiab. Yog tias tus IP core version tsis tau teev tseg, cov lus qhia siv rau tus IP core version dhau los siv.

IP Core Version	Cov neeg siv phau ntawv qhia
2.4.0	Sab nraud Memory Interfaces Intel Agilex FPGA IP Tsim Example User Guide Archives
2.3.0	Sab nraud Memory Interfaces Intel Agilex FPGA IP Tsim Example User Guide Archives
2.3.0	Sab nraud Memory Interfaces Intel Agilex FPGA IP Tsim Example User Guide Archives
2.1.0	Sab nraud Memory Interfaces Intel Agilex FPGA IP Tsim Example User Guide Archives
19.3	Sab nraud Memory Interfaces Intel Agilex FPGA IP Tsim Example User Guide Archives

Cov ntaub ntawv kho dua tshiab rau Sab Nraud Memory Interfaces Intel Agilex FPGA IP Tsim Example User Guide

Cov ntaub ntawv Version	Intel Quartus Prime Version	IP Version	Hloov
2021.06.21	21.2	2.4.2	Hauv Tsim Example Quick Start tshooj: • Ntxiv ib daim ntawv rau lub Compiling thiab Programming Intel Agilex EMIF Tsim Example lub ntsiab lus. • Hloov lub npe ntawm tus Tsim ib tug Design Exampnrog rau Calibration Debug Option lub ntsiab lus. • Ntxiv rau Tsim ib tug Design Example nrog TG Configuration Option thiab Ua kom muaj tsheb khiav hauv lub tshuab hluav taws xob tsim Example cov ntsiab lus. • Hloov cov kauj ruam 2, 3, thiab 4, hloov kho ob peb daim duab, thiab ntxiv ib daim ntawv, nyob rau hauv Siv tus Design Exampnrog rau EMIF Debug Toolkit lub ntsiab lus.
2021.03.29	21.1	2.4.0	Hauv Tsim Example Quick Start tshooj: • Ntxiv ib daim ntawv rau lub Tsim cov Synthesizable EMIF Tsim Example thiab Tsim cov EMIF Design Examprau Simulation cov ntsiab lus. • Hloov kho cov File Structure diagram nyob rau hauv Tsim cov EMIF Design Examprau Simulation lub ntsiab lus.
2020.12.14	20.4	2.3.0	Hauv Tsim Example Quick Start tshooj, tau hloov pauv hauv qab no: • Hloov kho cov Tsim cov Synthesizable EMIF Tsim Example cov ncauj lus kom suav nrog ntau tus qauv EMIF. • Hloov kho daim duab rau kauj ruam 3, hauv Tsim cov EMIF Design Examprau Simulation lub ntsiab lus.
2020.10.05	20.3	2.3.0	Hauv Tsim Example Quick Start Guide tshooj, tau hloov pauv hauv qab no: • Hauv Tsim ib qho EMIF Project, kho cov duab hauv kauj ruam 6. • Hauv Tsim cov Synthesizable EMIF Tsim Example, hloov kho daim duab hauv kauj ruam 3. • Hauv Tsim cov EMIF Design Examprau Simulation, hloov kho daim duab hauv kauj ruam 3. • Hauv Simulation Versus Hardware Implementation, kho me ntsis typo nyob rau hauv lub rooj thib ob. • Hauv Siv tus Design Exampnrog rau EMIF Debug Toolkit, hloov kauj ruam 6, ntxiv cov kauj ruam 7 thiab 8.
txuas ntxiv…

Cov ntaub ntawv Version	Intel Quartus Prime Version	IP Version	Hloov
2020.04.13	20.1	2.1.0	• Hauv Txog tshooj, hloov lub rooj nyob rau hauv lub Tshaj tawm cov ntaub ntawv lub ntsiab lus. • Hauv Tsim Example Quick Start Guide tshooj: - Hloov kho cov kauj ruam 7 thiab cov duab cuam tshuam, hauv qhov Tsim cov Synthesizable EMIF Tsim Example lub ntsiab lus. - Hloov kho lub Tsim cov Design Example nrog Debug Option lub ntsiab lus. - Hloov kho lub Siv tus Design Exampnrog rau EMIF Debug Toolkit lub ntsiab lus.
2019.12.16	19.4	2.0.0	• Hauv Tsim Example Quick Start tshooj: - Hloov kho cov duab piv txwv hauv kauj ruam 6 ntawm lub Tsim ib qho EMIF Project lub ntsiab lus. - Hloov kho cov duab piv txwv hauv kauj ruam 4 ntawm lub Tsim cov Synthesizable EMIF Tsim Example lub ntsiab lus. - Hloov kho cov duab piv txwv hauv kauj ruam 4 ntawm lub Tsim cov EMIF Design Examprau Simulation lub ntsiab lus. - Hloov kho kauj ruam 5 hauv qhov Tsim cov EMIF Design Examprau Simulation lub ntsiab lus. - Hloov kho lub General Pin Guidelines thiab Cov tsev txhab nyiaj nyob ib sab seem ntawm lub Pin Placement rau Intel Agilex EMIF IP lub ntsiab lus.
2019.10.18	19.3		• Hauv Tsim ib qho EMIF Project lub ntsiab lus, kho cov duab nrog point 6. • Hauv Tsim thiab Configuring EMIF IP lub ntsiab lus, hloov kho daim duab nrog kauj ruam 1. • Nyob rau hauv lub rooj nyob rau hauv lub Intel Agilex EMIF Parameter Editor Cov Lus Qhia lub ncauj lus, hloov cov lus piav qhia rau lub Board tab. • Hauv Tsim cov Synthesizable EMIF Tsim Example thiab Tsim cov EMIF Design Examprau Simulation cov ncauj lus, kho cov duab hauv kauj ruam 3 ntawm txhua lub ncauj lus. • Hauv Tsim cov EMIF Design Examprau Simulation lub ntsiab lus, updated the Tsim Simulation Design Example File Qauv daim duab thiab hloov daim ntawv tom qab daim duab. • Hauv Tsim cov Synthesizable EMIF Tsim Example lub ntsiab lus, ntxiv ib kauj ruam thiab ib daim duab rau ntau yam interfaces.
2019.07.31	19.2	1.2.0	• Ntxiv Txog Sab Nraud Memory Interfaces Intel Agilex FPGA IP tshooj thiab Tshaj Tawm Cov Ntaub Ntawv. • Hloov tshiab hnub thiab tus lej version. • Txhim kho me me rau cov Synthesis Design Example fig hauv Synthesis Design Example lub ntsiab lus.
2019.04.02	19.1		• Kev tso tawm thawj zaug.

Cov ntaub ntawv kho dua tshiab rau Sab Nraud Memory Interfaces Intel Agilex FPGA IP Tsim Example User Guide

Cov ntaub ntawv / Cov ntaub ntawv

Intel UG-20219 Sab Nraud Memory Interfaces Intel Agilex FPGA IP Tsim Example [ua pdf] Cov neeg siv phau ntawv qhia UG-20219 Sab Nraud Memory Interfaces Intel Agilex FPGA IP Tsim Example, UG-20219, External Memory Interfaces Intel Agilex FPGA IP Design Example, Interfaces Intel Agilex FPGA IP Tsim Example, Agilex FPGA IP Design Example

Cov ntaub ntawv

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