Sab nraud Memory Interfaces Intel Stratix 10 FPGA IP Tsim Example

Tsim Example Quick Start Guide for External Memory Interfaces Intel® Stratix® 10 FPGA IP

Ib tug tshiab interface thiab ntau automated tsim example flow yog muaj rau Intel® Stratix® 10 sab nraud nco interfaces. Tus Example Designs tab nyob rau hauv parameter editor tso cai rau koj los qhia txog kev tsim cov synthesis thiab simulation file teeb tsa uas koj tuaj yeem siv los txheeb xyuas koj tus EMIF IP. Koj tuaj yeem tsim ib qho example tsim tshwj xeeb rau Intel FPGA cov khoom siv txhim kho, lossis rau ib qho EMIF IP uas koj tsim.

Daim duab 1. General Design Example Workflows

Daim duab 2. Tsim ib qho EMIF Example Tsim Nrog Intel Stratix 10 Development Kit

Tsim ib qho EMIF Project

Rau Intel Quartus® Prime software version 17.1 thiab tom qab ntawd, koj yuav tsum tsim ib qhov project Intel Quartus Prime ua ntej tsim EMIF IP thiab tsim example.

1. Tua tawm Intel Quartus Prime software thiab xaiv File ➤ New Project Wizard. Nyem Next.
2. Qhia cov npe thiab nme rau qhov project uas koj xav tsim. Nyem Next.
3. Xyuas kom meej tias Empty Project raug xaiv. Nyem Next ob zaug.
4. Hauv lub npe lim, ntaus tus lej ntaus ntawv.
5. Hauv Cov Khoom Siv Muaj, xaiv lub cuab yeej tsim nyog.
6. Nyem Ua kom tiav.

Tsim thiab Configuring EMIF IP

Cov kauj ruam hauv qab no qhia txog yuav ua li cas tsim thiab teeb tsa EMIF IP. Qhov kev taug kev no tsim DDR4 interface, tab sis cov kauj ruam zoo sib xws rau lwm cov txheej txheem.

1. Hauv qhov rai IP Catalog, xaiv Intel Stratix 10 Sab Nraud Memory Interfaces. (Yog tias lub qhov rais IP Catalog tsis pom, xaiv View ➤ Utility Windows ➤ IP Catalog.)
2. Hauv IP Parameter Editor, muab lub npe chaw rau EMIF IP (lub npe uas koj muab ntawm no dhau los ua tus file npe rau tus IP) thiab qhia cov npe. Nyem Tsim.
3. Tus kws kho qhov ntsuas muaj ntau lub tab uas koj yuav tsum teeb tsa qhov ntsuas kom cuam tshuam koj qhov kev siv EMIF:

Intel Stratix 10 EMIF Parameter Editor Cov Lus Qhia

Table 1. EMIF Parameter Editor Cov Lus Qhia

Parameter Editor Tab	Cov lus qhia
General	Xyuas kom meej tias cov kev ntsuas hauv qab no tau nkag mus kom raug: • Qib ceev rau lub cuab yeej. • Lub cim xeeb moos zaus. • PLL siv moos zaus.
Nco	• Xa mus rau daim ntawv teev cov ntaub ntawv rau koj lub cim xeeb ntaus ntawv nkag mus rau cov tsis nyob rau hauv lub Nco tab. • Koj yuav tsum nkag mus rau qhov chaw tshwj xeeb rau ALERT# tus pin. (Siv rau DDR4 lub cim xeeb raws tu qauv nkaus xwb.)
Mem I/O	• Rau qhov kev tshawb nrhiav thawj zaug, koj tuaj yeem siv qhov chaw pib ntawm lub Mem I/O tab. • Rau kev tsim kho siab heev, koj yuav tsum ua lub rooj tsavxwm simulation kom tau txais qhov kev txiav txim siab zoo.
FPGA I/O	• Rau qhov kev tshawb nrhiav thawj zaug, koj tuaj yeem siv qhov chaw pib ntawm lub FPGA I/O tab. • Rau kev siv tau zoo tshaj plaws, koj yuav tsum ua lub rooj tsavxwm simulation nrog cov qauv IBIS los xaiv cov qauv tsim nyog I/O.
Mem sij hawm	• Rau qhov kev tshawb nrhiav thawj zaug, koj tuaj yeem siv qhov chaw pib ntawm lub Mem sij hawm tab. • Rau kev tsim kho siab heev, koj yuav tsum nkag mus rau qhov tsis raws li koj lub cim xeeb ntaus ntawv cov ntaub ntawv.
Board	• Rau qhov kev tshawb nrhiav thawj zaug, koj tuaj yeem siv qhov chaw pib ntawm lub Board tab. • Rau kev tsim kho siab tshaj plaws thiab raug kaw lub sijhawm, koj yuav tsum ua lub rooj sib tham simulation kom tau txais qhov tseeb ntawm kev cuam tshuam kev cuam tshuam (ISI) / crosstalk thiab board thiab cov ntaub ntawv pob skew, thiab nkag mus rau hauv Board tab.
Tus tswj	Teem tus maub los tsis raws li qhov xav tau kev teeb tsa thiab tus cwj pwm rau koj lub cim xeeb tswj.
Kev kuaj mob	Koj tuaj yeem siv cov parameter ntawm lub Kev kuaj mob tab los pab hauv kev sim thiab debugging koj lub cim xeeb interface.
Example Designs	Cov Example Designs tab cia koj tsim tsim examples rau synthesis thiab simulation. Tus tsim tsim example yog ua tiav EMIF system uas muaj EMIF IP thiab tus tsav tsheb uas tsim cov tsheb khiav mus los kom siv tau lub cim xeeb interface.

Yog xav paub cov ntaub ntawv ntxaws ntxaws ntawm tus kheej tsis muaj, xa mus rau tshooj tsim nyog rau koj lub cim xeeb raws tu qauv hauv Intel Stratix 10 Sab Nrauv Memory Interfaces IP Tus Neeg Siv Qhia.

Tsim cov Synthesizable EMIF Tsim Example

Rau Intel Stratix 10 cov khoom siv txhim kho, nws txaus los tawm feem ntau ntawm Intel Stratix 10 EMIF IP chaw nyob ntawm lawv qhov tseem ceeb. Txhawm rau tsim kom muaj cov qauv tsim ua ke example, ua raws li cov kauj ruam no:

1. Ntawm Diagnostics tab, qhib lub EMIF Debug Toolkit / On-Chip Debug Chaw nres nkoj thiab Hauv-System-Sources-and-Probes los muab kev nkag mus rau cov yam ntxwv debugging muaj.
2. Hauv Example Designs tab, xyuas kom meej tias lub thawv Synthesis raug kuaj xyuas.
3. Configure EMIF IP thiab nyem Tsim Example Tsim nyob rau sab xis sab xis ntawm lub qhov rais.
4. Qhia kom meej ib daim ntawv teev npe rau EMIF tsim example thiab nias OK. Kev vam meej tiam ntawm EMIF tsim example tsim cov hauv qab no fileset under a qii directory.

Daim duab 3. Generated Synthesizable Design Example File Qauv

Nco tseg: Yog tias koj tsis xaiv lub Simulation lossis Synthesis checkbox, cov ntawv teev npe yuav muaj Platform Designer tsim files, uas tsis suav nrog Intel Quartus Prime software ncaj qha, tab sis tuaj yeem ua tau viewed los yog kho nyob rau hauv lub Platform Designer. Hauv qhov xwm txheej no koj tuaj yeem khiav cov lus txib hauv qab no los tsim cov synthesis thiab simulation file teeb.

• Txhawm rau tsim ib qhov project compilable, koj yuav tsum khiav quartus_sh -t make_qii_design.tcl tsab ntawv nyob rau hauv lo lus uas peb directory.
• Txhawm rau tsim qhov project simulation, koj yuav tsum khiav quartus_sh -t make_sim_design.tcl tsab ntawv nyob rau hauv lo lus uas peb directory.

Cov ntaub ntawv ntsig txog

• Synthesis Example Design ntawm nplooj 19
• Intel Stratix 10 EMIF IP Parameter Cov Lus Qhia rau DDR3
• Intel Stratix 10 EMIF IP Parameter Cov Lus Qhia rau DDR4
• Intel Stratix 10 EMIF IP Parameter Cov Lus Qhia rau QDRII / II + / Xtreme
• Intel Stratix 10 EMIF IP Parameter Descriptions rau QDR-IV
• Intel Stratix 10 EMIF IP Parameter Cov Lus Qhia rau RLDRAM 3

Tsim cov EMIF Design Examprau Simulation
Rau Intel Stratix 10 cov khoom siv txhim kho, nws txaus los tawm feem ntau ntawm Intel Stratix 10 EMIF IP chaw nyob ntawm lawv qhov tseem ceeb. Tsim kom muaj tus tsim example rau
simulation, ua raws li cov kauj ruam no:

1. Ntawm Diagnostics tab, koj tuaj yeem xaiv ntawm ob hom calibration: Hla Calibration thiab Full Calibration. (Rau cov ntsiab lus ntawm cov qauv no, xa mus rau Simulation Versus Hardware Implementation, tom qab hauv tshooj no.) Txhawm rau txo lub sijhawm simulation, xaiv Abstract PHY rau kev simulation ceev.
2. Hauv Example Designs tab, xyuas kom meej tias lub thawv Simulation raug kuaj xyuas. Kuj xaiv qhov yuav tsum tau Simulation HDL hom, xws li Verilog lossis VHDL.
3. Configure EMIF IP thiab nyem Tsim Example Tsim nyob rau sab xis sab xis ntawm lub qhov rais.
4. Qhia kom meej ib daim ntawv teev npe rau EMIF tsim example thiab nias OK.

Kev vam meej tiam ntawm EMIF tsim example tsim ntau yam file teeb tsa rau ntau yam kev txhawb nqa simulators, nyob rau hauv daim ntawv qhia sim / ed_sim.

Daim duab 4. Generated Simulation Design Example File Qauv

Nco tseg: Yog tias koj tsis xaiv qhov Simulation lossis Synthesis checkbox, cov ntawv teev npe yuav muaj Platform Designer tsim files, uas tsis suav nrog Intel Quartus Prime software ncaj qha, tab sis tuaj yeem ua tau viewed los yog kho nyob rau hauv lub Platform Designer. Hauv qhov xwm txheej no koj tuaj yeem khiav cov lus txib hauv qab no los tsim cov synthesis thiab simulation file teeb.

• Txhawm rau tsim ib qhov project compilable, koj yuav tsum khiav quartus_sh -t make_qii_design.tcl tsab ntawv nyob rau hauv lo lus uas peb directory.
• Txhawm rau tsim qhov project simulation, koj yuav tsum khiav quartus_sh -t make_sim_design.tcl tsab ntawv nyob rau hauv lo lus uas peb directory.

Cov ntaub ntawv ntsig txog
• Simulation Exampua Design on
• Intel Stratix 10 EMIF IP – Simulating Memory IP
• Simulation Versus Hardware Implementation on

Simulation Versus Hardware Implementation
Rau sab nraud nco interface simulation, koj tuaj yeem xaiv hla dhau calibration lossis tag nrho calibration ntawm Diagnostics tab thaum IP tiam.
EMIF Simulation Qauv
Cov lus no sib piv cov yam ntxwv ntawm hla calibration thiab tag nrho cov qauv calibration.

Table 2. EMIF Simulation Models: Hla Calibration piv rau Full Calibration

Hla Calibration	Calibration tag nrho
System-level simulation tsom rau cov neeg siv cov logic.	Memory interface simulation tsom rau calibration.
Cov ntsiab lus ntawm calibration tsis raug ntes.	Captures tag nrho stagyog calibration.
Nws muaj peev xwm khaws thiab khaws cov ntaub ntawv.	Xws li leveling, per-ntsis deskew, thiab lwm yam.
Sawv cev muaj tseeb efficiency.
Tsis xav txog board skew.

RTL Simulation Versus Hardware Implementation

Cov lus no qhia txog qhov sib txawv tseem ceeb ntawm EMIF simulation thiab kev siv kho vajtse.

Table 3. EMIF RTL Simulation Versus Hardware Implementation

RTL Simulation	Hardware Implementation
Nios® pib thiab calibration code ua nyob rau hauv parallel.	Nios pib thiab calibration code ua sequentially.
Interfaces lees paub cal_done teeb liab teeb liab ib txhij hauv simulation.	Fitter kev khiav hauj lwm txiav txim qhov kev txiav txim ntawm calibration, thiab interfaces tsis lees tias cal_done ib txhij.

Koj yuav tsum khiav RTL simulations raws li cov qauv tsheb khiav rau koj tus tsim daim ntawv thov. Nco ntsoov tias RTL simulation tsis ua qauv PCB kab qeeb uas yuav ua rau muaj qhov sib txawv ntawm latency ntawm RTL simulation thiab kho vajtse siv.

Simulating Sab Nraud Memory Interface IP Nrog ModelSim

Cov txheej txheem no qhia tau hais tias yuav ua li cas simulate EMIF tsim example.

1. Tua tawm Mentor Graphics* ModelSim software thiab xaiv File ➤ Hloov Daim Ntawv Teev Npe. Nkag mus rau sim / ed_sim / tus kws qhia ntawv hauv cov qauv tsim tawm example folder.
2. Xyuas kom tseeb tias lub qhov rais Transcript tshwm nyob rau hauv qab ntawm qhov screen. Yog tias lub qhov rais Transcript tsis pom, tso nws los ntawm txhaj View ➤ Cov ntawv sau tseg.
3. Nyob rau hauv lub qhov rais Transcript, khiav qhov chaw msim_setup.tcl.
4. Tom qab qhov chaw msim_setup.tcl ua tiav, khiav ld_debug nyob rau hauv lub qhov rais Transcript.
5. Tom qab ld_debug ua tiav khiav, xyuas kom meej tias cov khoom qhov rai tau tshwm sim. Yog hais tias cov khoom qhov rais tsis pom, tso saib nws los ntawm txhaj View ➤ Yam khoom.
6. Nyob rau hauv cov khoom qhov rais, xaiv cov teeb liab uas koj xav simulate los ntawm rightclicking thiab xaiv Ntxiv Wave.
7. Tom qab koj ua tiav xaiv cov cim rau kev simulation, ua haujlwm khiav -tag nrho hauv VTranscript window. Lub simulation khiav mus txog thaum nws ua tiav.
8. Yog tias qhov kev simulation tsis pom, nyem View ➤ Wave.

Cov ntaub ntawv ntsig txog
Intel Stratix 10 EMIF IP - Simulating Memory IP

Pin Placement rau Intel Stratix 10 EMIF IP

Lub ncauj lus no muab cov lus qhia rau kev tso tus pin.

Tshajview

Intel Stratix 10 FPGAs muaj cov qauv hauv qab no:

• Txhua lub cuab yeej muaj nruab nrab ntawm 2 thiab 3 I / O kab.
• Txhua kab I/O muaj txog li 12 lub txhab nyiaj I/O.
• Txhua lub txhab nyiaj I/O muaj 4 txoj kab.
• Txhua txoj kab muaj 12 lub hom phiaj dav dav I / O (GPIO) tus pins.

General Pin Guidelines
Cov ntsiab lus hauv qab no muab cov lus qhia dav dav rau tus pin:

• Xyuas kom meej tias cov pins rau qhov muab lub cim xeeb sab nraud nyob hauv ib kab I / O.
• Interfaces uas hla ntau lub tsev txhab nyiaj yuav tsum ua raws li cov cai hauv qab no:
  • Lub tsev txhab nyiaj yuav tsum nyob ib sab ntawm ib leeg. Yog xav paub ntaub ntawv ntawm cov tsev txhab nyiaj nyob ib sab, xa mus rau Intel Stratix 10 Sab Nraud Memory Interfaces IP Tus Neeg Siv Qhia.
  • Qhov chaw nyob thiab hais kom ua lub txhab nyiaj yuav tsum nyob hauv ib lub txhab nyiaj hauv nruab nrab kom txo qis latency. Yog tias lub cim xeeb interface siv ntau lub tsev txhab nyiaj, qhov chaw nyob thiab lub txhab nyiaj hais kom ua yuav nyob hauv ob lub tsev txhab nyiaj hauv nruab nrab.
• Cov pins tsis siv tau tuaj yeem siv los ua cov hom phiaj dav dav I / O tus pins.
• Txhua qhov chaw nyob thiab cov lus txib thiab cov pins cuam tshuam yuav tsum nyob hauv ib lub txhab nyiaj.
• Chaw nyob thiab cov lus txib thiab cov ntaub ntawv tus pins tuaj yeem sib koom lub txhab nyiaj raws li hauv qab no:
  • Chaw nyob thiab cov lus txib thiab cov ntaub ntawv tus pins tsis tuaj yeem sib koom ib txoj kab I/O.
  • Tsuas yog txoj kab I / O tsis siv nyob rau hauv qhov chaw nyob thiab lub txhab nyiaj hais kom siv tau rau cov ntaub ntawv pins.

Table 4. General Pin Constraints

Hom teeb liab	Kev txwv
Data Strobe	Tag nrho cov teeb liab uas yog pawg DQ yuav tsum nyob hauv tib txoj kab I/O.
Cov ntaub ntawv	Related DQ pins yuav tsum nyob hauv tib txoj kab I/O. Rau cov kev cai uas tsis txhawb nqa cov ntaub ntawv ob kab lus, nyeem cov cim yuav tsum tau muab cais los ntawm kev sau cov cim.
Chaw nyob thiab hais kom ua	Chaw nyob thiab tus pins hais kom ua yuav tsum nyob hauv qhov chaw tau teev tseg hauv lub txhab nyiaj I/O.

Cov tsev txhab nyiaj nyob ib sab

Rau cov tsev txhab nyiaj yuav tsum tau txiav txim siab nyob ib sab, lawv yuav tsum nyob hauv tib kab I / O, txhawm rau txiav txim siab tias cov tsev txhab nyiaj nyob ib sab, xa mus rau Modular I / O cov tsev txhab nyiaj Qhov Chaw thiab Pin Counts hauv Stratix 10 Devices seem nyob rau hauv Stratix 10 General Lub Hom Phiaj I /O
Cov neeg siv phau ntawv qhia.

Thaum xa mus rau cov ntxhuav hauv Stratix 10 General Purpose I/O User Guide, nws muaj kev nyab xeeb xav tias txhua lub tsev txhab nyiaj tau pom nyob ib sab, tshwj tsis yog muaj lub cim ' – ' tam sim no; ib lub cim ' – ' qhia tias lub txhab nyiaj tsis raug tso tawm rau pob.
Tus Pin Txoj Haujlwm

Txhawm rau txiav txim siab qhov chaw rau tag nrho EMIF I / O pins koj yuav tsum siv lub rooj pin rau koj lub cuab yeej. Thaum xa mus rau tus pin lub rooj, cov lej nyiaj hauv tuam txhab, I / O bank indices, thiab tus pin npe tau muab. Koj tuaj yeem nrhiav tus pin indices rau qhov chaw nyob thiab cov lus txib pins hauv Stratix 10 Scheme Table nyob ntawm Intel FPGA webqhov chaw. Koj tuaj yeem ua cov haujlwm pin hauv ntau txoj hauv kev. Txoj hauv kev pom zoo yog los tswj qee qhov kev cuam tshuam cuam tshuam thiab cia Intel Quartus Prime Fitter ua tus so. Txoj kev no muaj kev sab laj tus pin ntxhuav kom pom txoj haujlwm raug cai rau qee qhov ntawm tus pin interface thiab muab lawv los ntawm .qsf file uas yog generated nrog EMIF tsim example. Rau txoj kev no ntawm I / O kev tso kawm, koj yuav tsum txwv cov cim hauv qab no:

• TIAB SA 0
• Ib tug DQS tus pin rau ib pab pawg
• PLL siv moos
• RZQ

Raws li cov kev txwv saum toj no, Intel Quartus Prime Fitter tig pins hauv txhua txoj kab raws li qhov tsim nyog. Cov duab hauv qab no qhia txog tus example ntawm tus pin assignments rau DDR3 x72 interface nrog cov kev xaiv hauv qab no:

• Qhov chaw nyob thiab tus pin hais kom muab tso rau hauv txhab nyiaj 2M thiab yuav tsum muaj 3 txoj kab.
  • CK0 yog txwv rau tus pin 8 hauv txhab nyiaj 2M.
  • PLL siv moos pins raug txwv rau pins 24 thiab 25 hauv txhab nyiaj 2M.
  • RZQ yog txwv rau tus pin 26 hauv txhab nyiaj 2M.
• Cov ntaub ntawv muab tso rau hauv cov tsev txhab nyiaj 2N, 2M, thiab 2L, thiab xav tau 9 txoj kab.
  • DQS pawg 1-4 tau muab tso rau hauv txhab nyiaj 2N.
  • DQS pawg 0 muab tso rau hauv txhab nyiaj 2M.
  • DQS pawg 5-8 muab tso rau hauv txhab nyiaj 2L.

Daim duab 5. Pin Assignments Example: DDR3 x73 Interface

Hauv no example, kom txwv CK0 rau tus pin 8 hauv txhab nyiaj 2M, koj yuav ntxiv cov kab hauv qab no rau .qsf file, raws li qhov tsim nyog tus pin rooj:

Hom ntawv ntawm tus pin saum toj no tuaj yeem siv rau txhua tus pins:

Cov ntaub ntawv ntsig txog

• Modular I/O Banks hauv Intel Stratix 10 Devices
• Intel Stratix 10 EMIF IP DDR3
• Intel Stratix 10 EMIF IP rau DDR4
• Intel Stratix 10 EMIF IP rau QDRII / II + / Xtreme
• Intel Stratix 10 EMIF IP rau QDR-IV
• Intel Stratix 10 EMIF IP rau RLDRAM 3

Compiling thiab Programming Intel Stratix 10 EMIF Tsim Example

Tom qab koj tau ua qhov tsim nyog tus pin txoj haujlwm hauv .qsf file, koj tuaj yeem suav tus tsim exampnyob rau hauv Intel Quartus Prime software.

1. Nkag mus rau Intel Quartus Prime nplaub tshev uas muaj tus tsim exampua directory.
2. Qhib Intel Quartus Prime qhov project file, (.qpf).
3. Txhawm rau pib muab tso ua ke, nyem Ua Haujlwm ➤ Pib Sau. Kev ua tiav tiav ntawm kev muab tso ua ke tsim ib qho .sof file, uas enables tus tsim kom khiav ntawm hardware.
4. Txhawm rau program koj lub cuab yeej nrog tus qauv tsim, qhib tus programmer los ntawm nyem Cov Cuab Yeej ➤ Programmer.
5. Hauv qhov programmer, nyem Auto Detect txhawm rau txheeb xyuas cov khoom siv txhawb nqa.
6. Xaiv Intel Stratix 10 ntaus ntawv thiab tom qab ntawd xaiv Hloov File.
7. Nkag mus rau qhov generated ed_synth.sof file thiab xaiv Qhib.
8. Nyem Pib los pib lub programming Intel Stratix 10 ntaus ntawv. Thaum lub cuab yeej ua tiav programmed, qhov kev nce qib bar nyob rau sab xis ntawm lub qhov rais yuav tsum qhia 100% (Successful).

Debugging Intel Stratix 10 EMIF Tsim Example
EMIF Debug Toolkit muaj los pab hauv kev debugging sab nraud nco interface tsim. Cov cuab yeej tso cai rau koj los tso saib nyeem thiab sau cov npoo thiab tsim cov duab kos duab. Tom qab koj tau programmed Intel Stratix 10 cov khoom siv txhim kho, koj tuaj yeem txheeb xyuas nws txoj haujlwm siv EMIF Debug Toolkit.

1. Txhawm rau tso tawm EMIF Debug Toolkit, mus rau Cov Cuab Yeej ➤ System Debugging Tools ➤ Sab Nraud Memory Interface Toolkit.
2. Nyem Initialize Connections.
3. Nyem Link Project rau ntaus ntawv. Lub qhov rais tshwm; txheeb xyuas tias cov cuab yeej raug xaiv thiab qhov tseeb .sof file raug xaiv.
4. Nyem Tsim Memory Interface Txuas. Txais cov kev teeb tsa ua ntej los ntawm nias OK.

Intel Stratix 10 cov khoom siv txhim kho tam sim no tau teeb tsa los ua haujlwm nrog EMIF Debug Toolkit, thiab koj tuaj yeem tsim ib qho ntawm cov lus ceeb toom hauv qab no los ntawm ob-nias ntawm qhov kev xaiv sib xws:

• Rov qab calibration. Ua ib daim ntawv qhia calibration qhia txog cov xwm txheej calibration rau ib pawg DQ/DQS nrog rau cov npoo rau txhua tus DQ/DQS tus pin.
• Tsav tsheb Margining. Ua ib daim ntawv qhia txog kev nyeem thiab sau cov npoo ntawm I / O tus pin. Qhov no txawv ntawm calibration margining vim hais tias tus tsav tsheb margining yog ntes thaum lub sij hawm neeg siv hom tsheb es tsis yog thaum lub sij hawm calibration
• Tsim qhov muag daim duab. Tsim cov ntawv nyeem thiab sau daim duab qhov muag rau txhua tus DQ tus pin raws li cov qauv ntaub ntawv calibration.
• Calibrate Termination. Sweeps txawv qhov kev txiav txim siab thiab tshaj tawm cov npoo uas txhua tus nqi txiav tawm muab. Siv cov yam ntxwv no los pab xaiv qhov kev txiav txim siab zoo rau lub cim xeeb interface.

Cov ntaub ntawv ntsig txog
Intel Stratix 10 EMIF IP Debugging

Tsim Example Description for External Memory Interfaces Intel Stratix 10 FPGA IP

Thaum koj parameterize thiab tsim koj tus IP EMIF, koj tuaj yeem qhia meej tias lub kaw lus tsim cov npe rau simulation thiab synthesis file sets, thiab generate cov file teem cia li. Yog tias koj xaiv Simulation lossis Synthesis hauv Examptsim Files pe Example Designs tab, lub kaw lus tsim kom tiav simulation file teeb los yog ua kom tiav synthesis file teem, raws li koj xaiv.

Synthesis Examptsim

Cov synthesis example tsim muaj cov blocks loj qhia hauv daim duab hauv qab no.

• Lub tshuab hluav taws xob tsheb, uas yog ib qho kev sib xyaw ua ke Avalon®-MM example tus tsav tsheb uas siv cov qauv pseudo-random ntawm kev nyeem thiab sau rau tus lej ntawm qhov chaw nyob. Lub tshuab hluav taws xob tsheb kuj tseem saib xyuas cov ntaub ntawv nyeem los ntawm lub cim xeeb kom ntseeg tau tias nws phim cov ntaub ntawv sau thiab lees paub qhov ua tsis tiav.
• Ib qho piv txwv ntawm lub cim xeeb interface, uas suav nrog:
  • Lub cim xeeb tswj uas nruab nrab ntawm Avalon-MM interface thiab AFI interface.
  • Lub PHY, uas ua haujlwm los ntawm kev sib txuas ntawm lub cim xeeb tswj thiab lwm lub cim xeeb los ua haujlwm nyeem thiab sau ntawv.

Daim duab 6. Synthesis Examptsim

Yog tias koj siv Ping Pong PHY feature, cov synthesis example tsim suav nrog ob lub tshuab hluav taws xob tsim hluav taws xob tawm cov lus txib rau ob lub cim xeeb ywj pheej los ntawm ob tus tswj hwm ywj pheej thiab ib qho PHY, raws li qhia hauv daim duab hauv qab no.

Daim duab 7. Synthesis Example Design for Ping Pong PHY

Yog tias koj siv RLDRAM 3, lub tshuab hluav taws xob tsheb hauv kev sib txuas example tsim kev sib txuas lus ncaj qha nrog PHY siv AFI, raws li qhia hauv daim duab hauv qab no.

Daim duab 8. Synthesis Example Tsim rau RLDRAM 3 Interfaces

Nco tseg: Yog tias ib qho lossis ntau dua ntawm PLL Kev Sib Koom Hom, DLL Sib Koom Hom, lossis OCT Sib Koom Hom tsis raug teeb tsa rau lwm tus nqi uas tsis yog Tsis Sib Koom, qhov sib koom ua keample tsim yuav muaj ob lub tshuab hluav taws xob tsheb / lub cim xeeb interface. Ob lub tshuab hluav taws xob hluav taws xob / lub cim xeeb cuam tshuam tsuas yog cuam tshuam los ntawm kev sib koom PLL / DLL / OCT kev sib txuas raws li tau hais los ntawm qhov ntsuas qhov ntsuas. Lub tshuab hluav taws xob tsheb / lub cim xeeb interface piv txwv qhia tias koj tuaj yeem ua li cas sib txuas hauv koj tus kheej tsim.
Nco tseg: Thib peb-tog synthesis ntws raws li tau piav qhia hauv Intel Quartus Prime Standard Edition Tus Neeg Siv Qhia: Thib Peb Cov Kev Sib Koom Tes tsis yog kev txhawb nqa rau EMIF IP.
Cov ntaub ntawv ntsig txog
Tsim cov Synthesizable EMIF Tsim Exampua le

Simulation Examptsim
Lub simulation example tsim muaj cov blocks loj qhia hauv daim duab hauv qab no.

• Ib qho piv txwv ntawm cov synthesis example design. Raws li tau piav nyob rau hauv tshooj dhau los, lub synthesis example tsim muaj lub tshuab hluav taws xob tsheb thiab ib qho piv txwv ntawm lub cim xeeb interface. Cov blocks default rau abstract simulation qauv uas tsim nyog rau ceev simulation.
• Lub cim xeeb qauv, uas ua raws li ib tug generic qauv uas ua raws li lub cim xeeb raws tu qauv specifications. Feem ntau, cov neeg muag khoom nco muab cov qauv simulation rau lawv cov cim xeeb tshwj xeeb uas koj tuaj yeem rub tawm los ntawm lawv webqhov chaw.
• Tus neeg saib xyuas xwm txheej, uas saib xyuas cov xwm txheej teeb liab los ntawm lub cim xeeb sab nraud interface IP thiab lub tshuab hluav taws xob tsheb, kom pom qhov kev hla dhau lossis tsis ua haujlwm.

Daim duab 9. Simulation Examptsim

Yog tias koj siv Ping Pong PHY feature, simulation example tsim suav nrog ob lub tshuab hluav taws xob tsim hluav taws xob tawm cov lus txib rau ob lub cim xeeb ywj pheej los ntawm ob tus tswj hwm ywj pheej thiab ib qho PHY, raws li qhia hauv daim duab hauv qab no.

Daim duab 10. Simulation Example Design for Ping Pong PHY

Yog tias koj siv RLDRAM 3, lub tshuab hluav taws xob tsheb hauv kev simulation example tsim kev sib txuas lus ncaj qha nrog PHY siv AFI, raws li qhia hauv daim duab hauv qab no.

Daim duab 11. Simulation Example Tsim rau RLDRAM 3 Interfaces

Cov ntaub ntawv ntsig txog
Tsim cov EMIF Design Example for Simulation on

Example Designs Interface Tab
Cov parameter editor suav nrog Example Designs tab uas tso cai rau koj mus parameterize thiab tsim koj tus exampua designs.l
Muaj Example Designs Section
Qhov Xaiv tsim rub tawm tso cai rau koj xaiv qhov xav tau example design. Tam sim no, EMIF Example Tsim yog tib qho kev xaiv, thiab raug xaiv los ntawm lub neej ntawd.

Cov ntaub ntawv kho dua tshiab rau Sab Nraud Memory Interfaces Intel Stratix 10 FPGA IP Tsim Example User Guide

Cov ntaub ntawv Version	Intel Quartus Prime Version	Hloov
2021.03.29	21.1	• Hauv Example Design Quick Start tshooj, tshem tawm cov ntawv xa mus rau NCSim* simulator.
2018.09.24	18.1	• Hloov tshiab cov duab hauv Tsim cov Synthesizable EMIF Tsim Example thiab Tsim cov EMIF Design Examprau Simulation cov ntsiab lus.
2018.05.07	18.0	• Hloov cov ntaub ntawv npe los ntawm Intel Stratix 10 Sab Nraud Memory Interfaces IP Tsim Example User Guide rau Sab nraud Memory Interfaces Intel Stratix 10 FPGA IP Tsim Example User Guide. • Kho cov ntsiab lus mos txwv hauv Tshajview ntu ntawm cov Pin Placement rau Intel Stratix 10 EMIF IP lub ntsiab lus.

Hnub tim	Version	Hloov
Kaum Ib Hlis 2017	2017.11.06	Kev tso tawm thawj zaug.

Intel Corporation. Txhua txoj cai. Intel, Intel logo, thiab lwm yam Intel cov cim yog cov cim lag luam ntawm Intel Corporation lossis nws cov koom haum. Intel lav kev ua tau zoo ntawm nws cov FPGA thiab cov khoom lag luam semiconductor rau cov kev qhia tshwj xeeb tam sim no raws li Intel tus qauv kev lees paub, tab sis muaj txoj cai los hloov cov khoom thiab cov kev pabcuam txhua lub sijhawm yam tsis muaj ntawv ceeb toom. Intel xav tias tsis muaj lub luag haujlwm lossis kev lav phib xaub uas tshwm sim los ntawm daim ntawv thov lossis siv cov ntaub ntawv, cov khoom lag luam, lossis cov kev pabcuam uas tau piav qhia hauv no tshwj tsis yog raws li tau pom zoo hauv kev sau ntawv los ntawm Intel. Intel cov neeg siv khoom tau qhia kom tau txais qhov tseeb version ntawm cov cuab yeej tshwj xeeb ua ntej tso siab rau cov ntaub ntawv tshaj tawm thiab ua ntej muab xaj rau cov khoom lossis cov kev pabcuam. * Lwm lub npe thiab hom yuav raug lees paub raws li cov cuab yeej ntawm lwm tus.

Cov ntaub ntawv / Cov ntaub ntawv

Intel Sab Nraud Memory Interfaces Intel Stratix 10 FPGA IP Tsim Example [ua pdf] Cov neeg siv phau ntawv qhia Sab nraud Memory Interfaces Intel Stratix 10 FPGA IP Tsim Example, Sab nraud, Memory Interfaces Intel Stratix 10 FPGA IP Tsim Example, Intel Stratix 10 FPGA IP Design Example, 10 FPGA IP Design Example

Cov ntaub ntawv

• Cov neeg siv phau ntawv