UG-20219 External Memory Interfaces Intel Agilex FPGA IP Design Example

Mabapi le Memori ea Kantle ea Memori Intel® Agilexâ„¢ FPGA IP

Phatlalatso Boitsebiso

Liphetolelo tsa IP li tšoana le mefuta ea software ea Intel® Quartus® Prime Design Suite ho fihla ho v19.1. Ho tsoa ho Intel Quartus Prime Design Suite software version 19.2 kapa hamorao, li-cores tsa IP li na le morero o mocha oa phetolelo ea IP. Nomoro ea mofuta oa IP (XYZ) e fetoha ho tloha ho mofuta o mong oa software ho ea ho o mong. Phetoho ho:

• X e bontša phetoho e kholo ea IP. Haeba u nchafatsa software ea hau ea Intel Quartus Prime, u tlameha ho nchafatsa IP.
• Y e bonts'a IP e kenyelletsa likarolo tse ncha. Nchafatsa IP ea hau ho kenyelletsa likarolo tsena tse ncha.
• Z e bonts'a IP e kenyelletsa liphetoho tse nyane. Hlahisa IP ea hau bocha ho kenyelletsa liphetoho tsena.
  

  Ntho	Tlhaloso
  IP Version	2.4.2
  Intel Quartus Prime	21.2
  Letsatsi la ho nšoa	2021.06.21

Moqapi Example Tataiso ea ho Qala ka Potlako bakeng sa Litšebelisano tsa Memori ea Kantle Intel Agilex™ FPGA IP

Moqapi oa boiketsetso example flow e fumaneha bakeng sa likhokahano tsa memori tsa Intel Agilex ™. Hlahisa Example Designs konopo ho ExampLe Designs tab e o lumella ho hlakisa le ho hlahisa sebopeho le moralo oa papiso example file sete eo u ka e sebelisang ho netefatsa IP ea hau ea EMIF. O ka hlahisa ex designampe tšoanang le lisebelisoa tsa nts'etsopele tsa Intel FPGA, kapa bakeng sa EMIF IP efe kapa efe eo u e hlahisang. U ka sebelisa ex designample ho thusa tlhahlobo ea hau, kapa joalo ka qalo ea sistimi ea hau.

Moqapi o Akaretsang Example Workflows

Ho theha Morero oa EMIF

Bakeng sa eena Intel Quartus Prime software version 17.1 le hamorao, o tlameha ho theha morero oa Intel Quartus Prime pele o hlahisa EMIF IP le moqapi oa khale.ample.

1. Qala software ea Intel Quartus Prime ebe u khetha File ➤ Setsebi se Secha sa Morero. Tobetsa E latelang. Moqapi Example Tataiso ea ho Qala ka Potlako bakeng sa Litšebelisano tsa Memori ea Kantle Intel Agilex™ FPGA IP
2. Hlalosa directory ( ), lebitso la morero oa Intel Quartus Prime ( ), le lebitso la moetso oa boemo bo holimo ( ) tseo u batlang ho li etsa. Tobetsa E latelang.
3. Netefatsa hore Empty Project e khethiloe. Click Next makhetlo a mabeli.
4. Tlas'a Lelapa, khetha Intel Agilex.
5. Tlas'a Name filter, thaepa nomoro ea karolo ea sesebelisoa.
6. Tlas'a Lisebelisoa tse teng, khetha sesebelisoa se loketseng.
7. Tobetsa Qetella.

Ho hlahisa le ho lokisa EMIF IP

Mehato e latelang e bontša mokhoa oa ho hlahisa le ho hlophisa EMIF IP. Mokhoa ona oa ho tsamaea o theha sebopeho sa DDR4, empa mehato e tšoana le liprothokholo tse ling. (Mehato ena e latela phallo ea IP Catalog (standalone); haeba u khetha ho sebelisa Phallo ea Platform Designer (system) ho fapana le hoo, mehato ea tšoana.)

1. Ka fensetere ea IP Catalog, khetha External Memory Interfaces Intel Agilex FPGA IP. (Haeba fensetere ea IP Catalog e sa bonahale, khetha View ➤ Lenane la IP.)
2. Ho IP Parameter Editor, fana ka lebitso la setheo bakeng sa EMIF IP (lebitso leo u fanang ka lona mona le fetoha file lebitso la IP) 'me u hlalose directory. Tobetsa Create.
3. Mohlophisi oa paramethara o na le li-tab tse ngata moo o tlamehang ho hlophisa liparamente ho bonts'a ts'ebetsong ea EMIF ea hau.

Intel Agilex EMIF Parameter Editor Guidelines
Sehlooho sena se fana ka tataiso ea boemo bo holimo bakeng sa parameterizing li-tab ho Intel Agilex EMIF IP parameter editor.

Letlapa la 1. Tataiso ea Mohlophisi oa Parameter ea EMIF

Parameter Editor Tab	Tataiso
Kakaretso	Netefatsa hore li-parameter tse latelang li kentsoe ka nepo: • Kereiti ya lebelo la sesebediswa. • Leqhubu la oache ea memori. • Leqhubu la oache ea referense ea PLL.
Mohopolo	• Sheba leqephe la data bakeng sa sesebediswa sa hao sa memori ho kenya diparamente ho Mohopolo tab ya. • Hape o lokela ho kenya sebaka se itseng sa ALERT# phini. (E sebetsa ho DDR4 memori protocol feela.)
Mem I/O	• Bakeng sa lipatlisiso tsa pele tsa morero, u ka sebelisa litlhophiso tsa kamehla ho Mem I/O tab ya. • Bakeng sa netefatso e tsoetseng pele ea moralo, o lokela ho etsa papiso ea boto ho fumana litlhophiso tse nepahetseng tsa ho felisa.
FPGA I/O	• Bakeng sa lipatlisiso tsa pele tsa morero, u ka sebelisa litlhophiso tsa kamehla ho FPGA I/O tab ya. • Bakeng sa netefatso e tsoetseng pele ea moralo, o lokela ho etsa papiso ea boto le mefuta e amanang le IBIS ho khetha maemo a nepahetseng a I/O.
Mem Timing	• Bakeng sa lipatlisiso tsa pele tsa morero, u ka sebelisa litlhophiso tsa kamehla ho Mem Timing tab ya. • Bakeng sa netefatso e tsoetseng pele ea moralo, o lokela ho kenya liparamente ho latela leqephe la data la sesebelisoa sa hau sa memori.
Molaoli	Seta liparamente tsa taolo ho latela tlhophiso le boitšoaro bo lakatsehang bakeng sa taolo ea memori ea hau.
Diagnostics	U ka sebelisa li-parameter tse ka tlase Diagnostics tab ho thusa ho lekola le ho lokisa memori ea hau.
Example Designs	The Example Designs tab e o lumella ho hlahisa moralo oa examples bakeng sa kopanyo le bakeng sa ketsiso. Moetso o entsoeng example ke sistimi e felletseng ea EMIF e nang le EMIF IP le mokhanni ea hlahisang sephethephethe se sa reroang ho netefatsa segokanyimmediamentsi sa memori.

Bakeng sa tlhaiso-leseling e batsi ka liparamente ka bomong, sheba khaolo e nepahetseng bakeng sa protocol ea memori ea hau ho External Memory Interfaces Intel Agilex FPGA IP User Guide.

Ho Hlahisa Moralo oa Synthesizable EMIF Example

Bakeng sa lisebelisoa tsa nts'etsopele ea Intel Agilex, ho lekane ho tlohela boholo ba litlhophiso tsa Intel Agilex EMIF IP ka litekanyetso tsa bona tsa kamehla. Ho hlahisa moetso oa maiketsetso example, latela mehato ena:

1. Ho Example Designs tab, etsa bonnete ba hore lebokose la Synthesis le hlahlojoe.
   • Haeba o kenya ts'ebetsong ea single interface example moralo, lokisa EMIF IP ebe o tobetsa File➤ Boloka ho boloka maemo a hajoale molemong oa IP ea mosebelisi file ( .ip).
     • Haeba u sebelisa example moralo o nang le li-interfaces tse ngata, hlakisa Palo ea li-IP ho palo e lakatsehang ea li-interfaces. U ka bona palo eohle ea EMIF ID e ts'oanang le Nomoro e khethiloeng ea li-IP. Latela mehato ena ho hlophisa interface ka 'ngoe:
   •  Khetha Cal-IP ho hlakisa khokahano ea sehokelo ho Calibration IP.
   • Lokisa EMIF IP ka nepo ho Tab eohle ea Parameter Editor.
   • Khutlela ho Example Design tab ebe o tobetsa Capture ho EMIF ID eo u e batlang.
   • Pheta mohato oa pele ho ea ho c bakeng sa EMIF ID eohle.
   • U ka tobetsa konopo ea Hlakisa ho tlosa liparamente tse hapiloeng ebe u pheta mohato a ho ea ho c ho etsa liphetoho ho EMIF IP.
   • Tobetsa File➤ Boloka ho boloka maemo a hajoale molemong oa IP ea mosebelisi file ( .ip).
2. Tobetsa Hlahisa Example Moralo hukung e kaholimo ho le letona la fensetere.
3. Hlalosa bukana bakeng sa moralo oa EMIF exampebe o tobetsa OK. E atlehileng ho hlahisa moralo oa EMIF example bopa tse latelang filebeha tlas'a qii directory.
4. Tobetsa File ➤ Tsoa ho tsoa fensetereng ea IP Parameter Editor Pro. Sistimi e khothaletsa, Liphetoho tsa morao-rao ha li so hlahisoe. Hlahisa hona joale? Tobetsa Che ho tsoela pele ka phallo e latelang.
5. Ho bula example moralo, tobetsa File ➤ Open Project, ebe u ea ho /ample_name>/qii/ed_synth.qpf ebe o tobetsa Bula.
   Hlokomela: Ho fumana leseli mabapi le ho hlophisa le ho hlophisa moralo oa example, bua ka
   Ho hlophisa le ho hlophisa Intel Agilex EMIF Design Example.

Setšoantšo sa 4. Moqapi o Hlahisitsoeng oa Synthesizable Example File Sebopeho

Bakeng sa tlhahisoleseling mabapi le ho aha sistimi e nang le likhokahano tse peli kapa ho feta tsa memori ea kantle, sheba ho Ho etsa Design Example tse nang le li-interfaces tse ngata tsa EMIF, ka har'a Memory Interfaces ea Kantle ea Intel Agilex FPGA IP User Guide. Bakeng sa tlhahisoleseling mabapi le ho lokisa li-interfaces tse ngata, sheba ho Nobles EMIF Toolkit ka Moralo o Teng, ho External Memory Interfaces Intel Agilex FPGA IP User Guide.

Hlokomela: Haeba u sa khethe lebokose la tlhahlobo la Simulation kapa Synthesis, bukana ea moo u eang teng e na le moralo oa Platform Designer feela. files, tse sa kopanngoeng ke Intel Quartus Prime software ka kotloloho, empa tseo u ka li khonang view kapa edita ho Moqapi oa Platform. Boemong bona, o ka tsamaisa litaelo tse latelang ho hlahisa synthesis le ketsiso file lihlopha.

• Ho theha projeke e ka bopjoang, o tlameha ho tsamaisa quartus_sh -t make_qii_design.tclscript bukeng ea moo u eang.
• Ho theha morero oa papiso, o tlameha ho tsamaisa mongolo oa quartus_sh -t make_sim_design.tcl bukeng eo u eang ho eona.

Hlokomela: Haeba u hlahisitse moqapi oa example ebe o etsa liphetoho ho eona ho paramethara, o tlameha ho nchafatsa moralo oa example ho bona liphetoho tsa hau li kengoa tšebetsong. Moqapi o sa tsoa hlahisoa example ha e nyenyefatse moralo o teng example files.

Ho hlahisa EMIF Design Example bakeng sa Simulation

Bakeng sa lisebelisoa tsa nts'etsopele ea Intel Agilex, ho lekane ho tlohela boholo ba litlhophiso tsa Intel Agilex EMIF IP ka litekanyetso tsa bona tsa kamehla. Ho hlahisa moralo example bakeng sa papiso, latela mehato ena:

1. Ho Example Designs tab, etsa bonnete ba hore lebokose la Simulation le hlahlojoe. Hape khetha mofuta o hlokahalang oa Simulation HDL, ebang ke Verilog kapa VHDL.
2. Lokisa EMIF IP ebe o tobetsa File ➤ Boloka ho boloka maemo a hajoale molemong oa IP ea mosebelisi file ( .ip).
3. Tobetsa Hlahisa Example Moralo hukung e kaholimo ho le letona la fensetere.
4. Hlalosa bukana bakeng sa moralo oa EMIF exampebe o tobetsa OK. E atlehileng ho hlahisa moralo oa EMIF example bopa multiple file sete bakeng sa li-simulator tse fapaneng tse tšehelitsoeng, tlas'a buka ea sim/ed_sim.
5. Tobetsa File ➤ Tsoa ho tsoa fensetereng ea IP Parameter Editor Pro. Sistimi e khothaletsa, Liphetoho tsa morao-rao ha li so hlahisoe. Hlahisa hona joale? Tobetsa Che ho tsoela pele ka phallo e latelang.

Moqapi oa Ketsiso ea Hlahisitsoeng Example File Sebopeho

Hlokomela: The External Memory Interfaces Intel Agilex FPGA IP hajoale e tšehetsa feela li-simulator tsa VCS, ModelSim/QuestaSim, le Xcelium. Ts'ehetso e eketsehileng ea simulator e reriloe likhatisong tse tlang.

Hlokomela: Haeba u sa khethe lebokose la tlhahlobo la Simulation kapa Synthesis, bukana ea moo u eang teng e na le moralo oa Platform Designer feela. files, tse sa kopanngoeng ke Intel Quartus Prime software ka kotloloho, empa tseo u ka li khonang view kapa edita ho Moqapi oa Platform. Boemong bona, o ka tsamaisa litaelo tse latelang ho hlahisa synthesis le ketsiso file lihlopha.

• Ho theha projeke e ka bopjoang, o tlameha ho tsamaisa mongolo oa quartus_sh -t make_qii_design.tcl bukeng ea moo u eang.
• Ho theha morero oa papiso, o tlameha ho tsamaisa mongolo oa quartus_sh -t make_sim_design.tcl bukeng eo u eang ho eona.

Hlokomela: Haeba u hlahisitse moqapi oa example ebe o etsa liphetoho ho eona ho paramethara, o tlameha ho nchafatsa moralo oa example ho bona liphetoho tsa hau li kengoa tšebetsong. Moqapi o sa tsoa hlahisoa example ha e nyenyefatse moralo o teng example files.

Ketsiso khahlano le Ts'ebetso ea Hardware
Bakeng sa sebopeho sa memori sa kantle, o ka khetha ho qhekella kapa ho lekanya ka botlalo ho tabo ea Diagnostics nakong ea moloko oa IP.

EMIF Ketsiso Mehlala
Tafole ena e bapisa litšobotsi tsa skip calibration le mefuta e feletseng ea calibration.

Letlapa la 2. Meetso ea Ketsiso ea EMIF: Tlola Tekanyetso khahlano le Tekolo e Feletseng.

Tlola ho lekanya	Feletseng Calibration
Ketsiso ea boemo ba sistimi e shebaneng le mohopolo oa mosebelisi.	Ketsiso ea segokanyimmediamentsi sa memori e shebaneng le ho lekanya.
Lintlha tsa calibration ha li tšoaroe.	E hapa tsohle stages of calibration.
E na le bokhoni ba ho boloka le ho khutlisa data.	E kenyeletsa boemo, per-bit deskew, joalo-joalo.
E bontša bokhoni bo nepahetseng.
Ha e nahane ka board skew.

Ketsiso ea RTL Khahlanong le Ts'ebetso ea Hardware
Tafole ena e totobatsa liphapano tsa bohlokoa lipakeng tsa ketsiso ea EMIF le ts'ebetsong ea hardware.

Lethathamo la 3. Ketsiso ea EMIF RTL Ha e Bapisoa le Ts'ebetso ea Hardware

RTL Ketsiso	Lisebelisoa tsa Hardware
Kenyelletso ea Nios® le khoutu ea calibration e etsoa ka ho tsamaisana.	Qalo ea Nios le khoutu ea calibration e etsa ka tatellano.
Li-interfaces li tiisa lets'oao la cal_done ka nako e le 'ngoe ka papiso.	Lits'ebetso tsa Fitter li lekanya tatellano ea litekanyo, 'me likhokahano ha li bolele hore cal_done ka nako e le ngoe.

O lokela ho tsamaisa lipapiso tsa RTL ho ipapisitse le mekhoa ea sephethephethe bakeng sa ts'ebeliso ea moralo oa hau. Hlokomela hore ketsiso ea RTL ha e etse mohlala oa tieho ea morao-rao ea PCB e ka bakang phapang pakeng tsa ketsiso ea RTL le ts'ebetsong ea hardware.

 Ho etsisa Sebopeho sa Memori ea Kantle ea IP le ModelSim
Mokhoa ona o bonts'a mokhoa oa ho etsisa moralo oa EMIF example.

1. Qala software ea Mentor Graphics* ModelSim ebe u khetha File ➤ Fetola Bukana. Tsamaisa ho sim/ed_sim/mentor directory ka har'a moetso o entsoeng example foldara.
2. Netefatsa hore fensetere ea Transcript e hlaha ka tlase ho skrine. Haeba fensetere ea Transcript e sa bonahale, e hlahise ka ho tobetsa View ➤ Sengoliloeng.
3. Fesetereng ea Transcript, tsamaisa mohloli msim_setup.tcl.
4. Kamora hore mohloli oa msim_setup.tcl o qete ho sebetsa, tsamaisa ld_debug fensetereng ea Transcript.
5. Ka mor'a hore ld_debug e qete ho sebetsa, netefatsa hore fensetere ea Objects e hlaha. Haeba fensetere ea Lintho e sa bonahale, e hlahise ka ho tobetsa View ➤ Lintho.
6. Fesetereng ea Lintho, khetha matšoao ao u batlang ho a etsisa ka ho tobetsa ka ho le letona ebe u khetha Add Wave.
7. Ka mor'a hore u qete ho khetha matšoao a ho etsisa, etsa run -all ka fensetere ea Transcript. Ketsiso e sebetsa ho fihlela e phethiloe.
8. Haeba ketsiso e sa bonahale, tobetsa View ➤ Leqhubu.

Pin Placement bakeng sa Intel Agilex EMIF IP
Sehlooho sena se fana ka litataiso tsa ho beha li-pin.

Fetileview
Intel Agilex FPGAs e na le sebopeho se latelang:

• Sesebelisoa ka seng se na le libanka tse ka bang 8 tsa I/O.
• Banka e 'ngoe le e' ngoe ea I/O e na le libanka tse 2 tsa sub-I/O.
• Banka e 'ngoe le e' ngoe ea sub-I/O e na le litselana tse 4.
• Tsela e 'ngoe le e' ngoe e na le lithakhisa tse 12 tsa I/O (GPIO).

Kakaretso Pin Guidelines
Tse latelang ke litataiso tse akaretsang tsa phini.

Hlokomela: Bakeng sa tlhaiso-leseling e batsi ea phini, sheba karolo ea Intel Agilex FPGA EMIF IP Pin le Resource Planning khaolong e ikhethileng ea protocol bakeng sa protocol ea hau ea memori ea kantle, ho External Memory Interfaces Intel Agilex FPGA IP User Guide.

• Netefatsa hore lithakhisa tsa sebopeho sa memori sa kantle li lula ka har'a mola oa I/O.
• Li-interfaces tse sebetsanang le libanka tse ngata li tlameha ho fihlela litlhoko tse latelang:
  •  Libanka li tlameha ho ba haufi le tse ling. Bakeng sa tlhahisoleseling mabapi le libanka tse haufi, sheba sehlooho sa EMIF Architecture: I/O Bank ho External Memory Interfaces Intel Agilex FPGA IP User Guide.
•  Liaterese tsohle le litaelo le liphini tse amanang li tlameha ho lula ka har'a banka e le 'ngoe.
• Aterese le litaelo le li-pin tsa data li ka arolelana banka e nyane tlasa maemo a latelang:
  • Aterese le litaelo le liphini tsa data li ke ke tsa arolelana tsela ea I/O.
  • Ke tsela feela ea I/O e sa sebelisoeng atereseng le bankeng ea litaelo e ka bang le li-pins tsa data.

Lethathamo la 4. Litšitiso tsa Pin Kakaretso

Mofuta oa Letšoao	Tšitiso
Data Strobe	Lipontšo tsohle tsa sehlopha sa DQ li tlameha ho lula tseleng e tšoanang ea I/O.
Lintlha	Lithakhisa tsa DQ tse amanang li tlameha ho lula tseleng e tšoanang ea I/O. Bakeng sa liprothokholo tse sa tšehetseng mela ea data ea bobeli, matšoao a balang a lokela ho hlophisoa ka thoko ho matšoao a ho ngola.
Aterese le Taelo	Aterese le Lithakhisa tsa Taelo li tlameha ho lula libakeng tse boletsoeng esale pele ka har'a banka e nyane ea I/O.

Hlokomela: Bakeng sa tlhaiso-leseling e batsi ea phini, sheba karolo ea Intel Agilex FPGA EMIF IP Pin le Resource Planning khaolong e ikhethileng ea protocol bakeng sa protocol ea hau ea memori ea kantle, ho External Memory Interfaces Intel Agilex FPGA IP User Guide.

• Netefatsa hore lithakhisa tsa sebopeho sa memori sa kantle li lula ka har'a mola oa I/O.
• Li-interfaces tse sebetsanang le libanka tse ngata li tlameha ho fihlela litlhoko tse latelang:
  • Libanka li tlameha ho ba haufi le tse ling. Bakeng sa tlhahisoleseling mabapi le libanka tse haufi, sheba sehlooho sa EMIF Architecture: I/O Bank ho External Memory Interfaces Intel Agilex FPGA IP User Guide.
• Liaterese tsohle le litaelo le liphini tse amanang li tlameha ho lula ka har'a banka e le 'ngoe.
• Aterese le litaelo le li-pin tsa data li ka arolelana banka e nyane tlasa maemo a latelang:
  • Aterese le litaelo le liphini tsa data li ke ke tsa arolelana tsela ea I/O.
  • Ke tsela feela ea I/O e sa sebelisoeng atereseng le bankeng ea litaelo e ka bang le li-pins tsa data.

Ho Hlahisa Moqapi Example khetho ea TG Configuration

Moetso oa EMIF o entsoeng example kenyeletsa sephethephethe sa jenereithara (TG). Ka kamehla, moqapi exampLe e sebelisa TG block e bonolo (altera_tg_avl) e ka hlophisoang bocha molemong oa ho qala mokhoa oa sephethephethe o thata. Haeba ho hlokahala, o ka khetha ho nolofalletsa jenereithara ea sephethephethe e lokisehang (TG2) sebakeng sa eona. Ho jenereithara e lokisehang ea sephethephethe (TG2) (altera_tg_avl_2), o ka hlophisa mokhoa oa sephethephethe ka nako ea nnete ka lirekoto tsa taolo-ho bolelang hore ha ho hlokahale hore u boele u boele u boele u hlophise moralo ho fetola kapa ho qala mokhoa oa sephethephethe. Jenereithara ena ea sephethe-phethe e fana ka taolo e ntle holim'a mofuta oa sephethephethe seo e se romellang sebopeho sa taolo sa EMIF. Ho feta moo, e fana ka lirekoto tsa maemo tse nang le tlhaiso-leseling e felletseng ea ho hloleha.

Ho nolofalletsa Jenereithara ea Sephethephethe ho Moqapi oa Example

O ka nolofalletsa jenereithara ea sephethe-phethe e ka lokisoang ho tsoa ho "Diagnostics" ho mohlophisi oa paramethara ea EMIF. Ho nolofalletsa jenereithara ea sephethephethe, bulela Sebelisa jenereithara ea sephethephethe ea Avalon 2.0 e ka lokisoang ho tab ea Diagnostics.

Setšoantšo sa 6.

• U ka 'na ua khetha ho tima mokhoa oa kamehla oa sephethephethe stage kapa sephethephethe se hlophisitsoeng ke mosebelisi stage, empa o tlameha ho ba le bonyane stage nolofalitsoe. Bakeng sa tlhahisoleseding mabapi le tsena stages, e bua ka Paterone ea Sephethephethe e Tloaelehileng le Mohlala oa Sephethephethe o hlophisitsoeng ke Mosebelisi ka har'a Memory Interfaces ea Kantle ea Intel Agilex FPGA IP User Guide.
• Teko ea nako ea teko ea TG2 e sebetsa feela ho mohlala oa sephethephethe sa kamehla. U ka khetha nako ea teko ea nako e khuts'oane, e mahareng, kapa e sa feleng.
• o ka khetha e 'ngoe ea litekanyetso tse peli bakeng sa paramethara ea TG2 Configuration Interface Mode:
  • JTAG: E lumella ts'ebeliso ea GUI ho khomphutha ea sistimi. Bakeng sa tlhaiso-leseling e batsi, sheba Sehokelo sa Tlhophiso ea Sephethephethe sa Sephethephethe ho Memory Interfaces ea Kantle ea Intel Agilex FPGA IP User Guide.
  • Romela kantle: E lumella tšebeliso ea tloaelo ea RTL ho laola mokhoa oa sephethephethe.

Ho Sebelisa Moqapi Example EMIF Debug Toolkit

Pele o qala EMIF Debug Toolkit, etsa bonnete ba hore o lokiselitse sesebelisoa sa hau ka lenaneo. file e nang le EMIF Debug Toolkit e lumelletsoeng. Ho qala EMIF Debug Toolkit, latela mehato ena:

1. Ho Intel Quartus Prime software, bula System Console ka ho khetha Tools ➤ Lisebelisoa tsa ho lokisa tsamaiso ➤ System Console.
2. [Tlohela mohato ona haeba projeke ea hau e se e butsoe ho software ea Intel Quartus Prime.] Ho System Console, kenya ntho ea SRAM file (.sof) eo u hlophisitseng boto ka eona (joalokaha ho hlalositsoe ho Lintho Tse Hlokahalang Bakeng sa ho Sebelisa EMIF Debug Toolkit, ho External Memory Interfaces Intel Agilex FPGA IP User Guide).
3. Khetha maemo a ho lokisa liphoso.
4. Khetha EMIF Calibration Debug Toolkit bakeng sa EMIF calibration debugging, joalo ka ha ho hlalositsoe ho Hlahisa Design Ex.ample ka Khetho ea Calibration Debug. Ntle le moo, khetha EMIF TG Configuration Toolkit bakeng sa ho lokisa bothata ba jenereithara ea sephethephethe, joalo ka ha ho hlalositsoe ho Hlahisa Design Ex.ample khetho ea TG Configuration.
5. Tobetsa Open Toolkit ho bula sehlooho view ea EMIF Debug Toolkit.
6. Haeba ho na le maemo a mangata a EMIF moralong o hlophisitsoeng, khetha kholomo (tsela e eang ho JTAG master) le ID ea sebopeho sa memori sa mohlala oa EMIF oo u ka kenyang sesebelisoa sa lisebelisoa.
7. Tobetsa Activate Interface ho lumella sephutheloana sa lithulusi ho bala liparamente tsa sebopeho le boemo ba ho lekanya.
8. O tlameha ho lokisa sehokelo se le seng ka nako; kahoo, ho hokela ho segokanyimmediamentsi sa sebolokigolo e 'ngoe ka moralo, u lokela ho qala ka deactivate segokanyimmediamentsi sa sebolokigolo.

Tse latelang ke examplintlha tsa litlaleho tse tsoang ho EMIF Calibration Debug Toolkit le EMIF TG Configuration Toolkit:, ka ho latellana.

Hlokomela: Bakeng sa lintlha tse mabapi le ho lokisa liphoso, sheba ho Debugging ka External Memory Interface Debug Toolkit, ho External Memory Interfaces Intel Agilex FPGA IP User Guide.

Hlokomela: Bakeng sa lintlha tse mabapi le ho lokisa bothata ba jenereithara ea sephethephethe, sheba Sehokelo sa Mosebelisi sa Terene ea Sephethephethe, ho External Memory Interfaces Intel Agilex FPGA IP User Interface.

Moqapi Example Tlhaloso bakeng sa Litšebelisano tsa Memori ea Kantle Intel Agilex FPGA IP

Ha o etsa parameter mme o hlahisa EMIF IP ea hau, o ka hlakisa hore sistimi e theha li-directory bakeng sa papiso le ho kopanya. file sets, le ho hlahisa li- file seta ka tsela e iketsang. Haeba o kgetha Ketsiso kapa Synthesis tlasa Example Design Files ho Example Designs tab, sistimi e etsa papiso e felletseng file sete kapa tlhakanyo e felletseng file beha, ho latela khetho ea hau.

Moqapi oa Moqapi Example
Moqapi oa motsoako example na le li-blocks tse kholo tse bontšitsoeng setšoantšong se ka tlase.

• Jenereithara ea sephethe-phethe, e leng mofuta oa Avalon®-MM oa maiketsetsoample mokhanni ea sebelisang mokhoa oa pseudo-random oa ho bala le ho ngolla liaterese tse nang le parameterized. Jenereithara ea sephethephethe e boetse e lekola data e baloang ho tsoa mohopolong ho netefatsa hore e lumellana le data e ngotsoeng mme e bolela ho hloleha ho seng joalo.
• Mohlala oa sebopeho sa memori, se kenyelletsang:
  • Taolo ea memori e lekanyang pakeng tsa Avalon-MM interface le AFI interface.
  • PHY, e sebetsang e le sehokelo lipakeng tsa taolo ea memori le lisebelisoa tsa memori tsa kantle ho etsa ts'ebetso ea ho bala le ho ngola.

Setšoantšo sa 7. Moralo oa Synthesis Example

Hlokomela: Haeba e le 'ngoe kapa tse ngata tsa PLL Sharing Mode, DLL Sharing Mode, kapa OCT Sharing Mode parameter li behiloe boleng bofe kapa bofe ntle le No Sharing, moralo oa synthesis ex.ampLe tla ba le liketsahalo tse peli tsa jenereithara ea sephethephethe/memori. Maemo a mabeli a jenereithara / segokanyimmediamentsi sa memori se amana feela ka likhokahano tse arolelanoang tsa PLL/DLL/OCT joalo ka ha ho hlalosoa ke litlhophiso tsa paramethara. Mehlala ea jenereithara ea sephethephethe/memori e bonts'a hore na u ka etsa likhokahano tse joalo joang ka meralo ea hau.

Moqapi oa Ketsiso Example
Moqapi oa ketsiso example na le li-blocks tse kholo tse bontšitsoeng setšoantšong se latelang.

• Mohlala oa moralo oa motsoako example. Joalo ka ha ho hlalositsoe karolong e fetileng, moralo oa synthesis exampLe e na le jenereithara ea sephethephethe, karolo ea calibration, le mohlala oa sebopeho sa memori. Li-blocks tsena li lula li le teng ho mefuta ea papiso e sa bonahaleng moo ho loketseng bakeng sa papiso e potlakileng.
• Moetso oa memori, o sebetsang joalo ka mohlala o akaretsang o khomarelang lintlha tsa protocol ea memori. Khafetsa, barekisi ba memori ba fana ka mefuta ea papiso bakeng sa likarolo tsa bona tsa memori tseo u ka li khoasollang ho tsoa ho tsona weblibaka.
• Mohlahlobi oa maemo, o lekola matšoao a boemo ho tsoa ho sebopeho sa memori sa kantle sa IP le jenereithara ea sephethephethe, ho bonts'a boemo ba ho feta kapa ho hloleha ka kakaretso.

Setšoantšo sa 10. Moqapi oa Ketsiso Example

ExampLe Designs Interface Tab
Mohlophisi oa parameter o kenyelletsa Example Designs tab e u lumellang ho etsa parameter le ho hlahisa moralo oa hau oa khaleamples.

Memory Interfaces ea Kantle Intel Agilex FPGA IP Design Example User Guide Archives

Liphetolelo tsa IP li tšoana le mefuta ea software ea Intel Quartus Prime Design Suite ho fihla ho v19.1. Ho tsoa ho Intel Quartus Prime Design Suite software version 19.2 kapa hamorao, li-IP li na le morero o mocha oa phetolelo ea IP. Haeba mofuta oa IP core o sa thathamisoa, ho sebetsa tataiso ea mosebelisi bakeng sa mofuta o fetileng oa IP.

IP Core Version	Bukana ea Mosebelisi
2.4.0	Memory Interfaces ea Kantle Intel Agilex FPGA IP Design Example User Guide Archives
2.3.0	Memory Interfaces ea Kantle Intel Agilex FPGA IP Design Example User Guide Archives
2.3.0	Memory Interfaces ea Kantle Intel Agilex FPGA IP Design Example User Guide Archives
2.1.0	Memory Interfaces ea Kantle Intel Agilex FPGA IP Design Example User Guide Archives
19.3	Memory Interfaces ea Kantle Intel Agilex FPGA IP Design Example User Guide Archives

Nalane ea Phetoho ea Litokomane bakeng sa Litšebelisano tsa Memori ea Kantle Intel Agilex FPGA IP Design Example Bukana ea Mosebelisi

Tokomane Version	Intel Quartus Prime Version	IP Version	Liphetoho
2021.06.21	21.2	2.4.2	Ho Moqapi Example Quick Start khaolo: • E kentse molaetsa ho Ho hlophisa le ho hlophisa Intel Agilex EMIF Design Example sehlooho. • Fetotse sehlooho sa Ho Hlahisa Moqapi Example ka Khetho ea Calibration Debug sehlooho. • E kentse the Ho Hlahisa Moqapi Example khetho ea TG Configuration le Ho nolofalletsa Jenereithara ea Sephethephethe ho Moqapi oa Example lihlooho. • Mehato e fetotsoeng ea 2, 3, le 4, e nchafalitse lipalo tse 'maloa, le ho eketsa lintlha, ho Ho Sebelisa Moqapi Example EMIF Debug Toolkit sehlooho.
2021.03.29	21.1	2.4.0	Ho Moqapi Example Quick Start khaolo: • E kentse molaetsa ho Ho Hlahisa Moralo oa Synthesizable EMIF Example le Ho hlahisa EMIF Design Example bakeng sa Simulation lihlooho. • Ntjhafatswa File Setšoantšo sa sebopeho ho Ho hlahisa EMIF Design Example bakeng sa Simulation sehlooho.
2020.12.14	20.4	2.3.0	Ho Moqapi Example Quick Start Khaolong, e entse liphetoho tse latelang: • Ntjhafatswa Ho Hlahisa Moralo oa Synthesizable EMIF Example sehlooho ho kenyelletsa meralo ea EMIF e mengata. • E ntlafalitse setšoantšo sa mohato oa 3, ho Ho hlahisa EMIF Design Example bakeng sa Simulation sehlooho.
2020.10.05	20.3	2.3.0	Ho Moqapi Example Quick Start Guide Khaolong, e entse liphetoho tse latelang: • Ka hare Ho theha Morero oa EMIF, e ntlafalitse setšoantšo mohatong oa 6. • Ka hare Ho Hlahisa Moralo oa Synthesizable EMIF Example, e ntlafalitse setšoantšo mohatong oa 3. • Ka hare Ho hlahisa EMIF Design Example bakeng sa Simulation, e ntlafalitse setšoantšo mohatong oa 3. • Ka hare Ketsiso khahlano le Ts'ebetso ea Hardware, e lokisitse phoso e nyenyane ea ho ngola lethathamong la bobeli. • Ka hare Ho Sebelisa Moqapi Example EMIF Debug Toolkit, e fetotsoe mohato oa 6, e ekelitse mehato ea 7 le ea 8.
e tsoela pele…

Tokomane Version	Intel Quartus Prime Version	IP Version	Liphetoho
2020.04.13	20.1	2.1.0	• Ho About khaolo, e fetotsoeng tafole ka Phatlalatso Boitsebiso sehlooho. • Ho Moqapi Example Quick Start Guide khaolo: - E fetotsoe mohato oa 7 le setšoantšo se amanang le sona, ho Ho Hlahisa Moralo oa Synthesizable EMIF Example sehlooho. - E fetotsoe Ho Hlahisa Moqapi Example khetho ea Debug sehlooho. - E fetotsoe Ho Sebelisa Moqapi Example EMIF Debug Toolkit sehlooho.
2019.12.16	19.4	2.0.0	• Ho Moqapi Example Quick Start khaolo: - E ntlafalitse papiso mohatong oa 6 oa Ho theha Morero oa EMIF sehlooho. - E ntlafalitse papiso mohatong oa 4 oa Ho Hlahisa Moralo oa Synthesizable EMIF Example sehlooho. - E ntlafalitse papiso mohatong oa 4 oa Ho hlahisa EMIF Design Example bakeng sa Simulation sehlooho. - Fetotse mohato 5 ho Ho hlahisa EMIF Design Example bakeng sa Simulation sehlooho. - E fetotsoe Kakaretso Pin Guidelines le Libanka tse Haufi likarolo tsa Pin Placement bakeng sa Intel Agilex EMIF IP sehlooho.
2019.10.18	19.3		• Ho Ho theha Morero oa EMIF sehlooho, se ntlafalitse setšoantšo ka ntlha ea 6. • Ho Ho hlahisa le ho lokisa EMIF IP sehlooho, e ntlafalitse setšoantšo ka mohato oa 1. • Tafoleng ka har'a Intel Agilex EMIF Parameter Editor Guidelines sehlooho, fetola tlhaloso bakeng sa Boto tab ya. • Ho Ho Hlahisa Moralo oa Synthesizable EMIF Example le Ho hlahisa EMIF Design Example bakeng sa Simulation lihlooho, e nchafalitse setšoantšo mohatong oa 3 oa sehlooho ka seng. • Ho Ho hlahisa EMIF Design Example bakeng sa Simulation sehlooho se reng, ntjhafatswa the Moqapi oa Ketsiso ea Hlahisitsoeng Example File Sebopeho palo le ho fetola mongolo o latelang setšoantšo. • Ho Ho Hlahisa Moralo oa Synthesizable EMIF Example sehlooho, e ekelitse mohato le palo bakeng sa lihokelo tse ngata.
2019.07.31	19.2	1.2.0	• E kentsoe Mabapi le Memori ea Kantle ea Memori Intel Agilex FPGA IP khaolo le Boitsebiso ba Phatlalatso. • Matsatsi a ntlafalitsoeng le linomoro tsa mofuta. • Ntlafatso e nyane ho Moqapi oa Moqapi Example setšoantšo ho Moqapi oa Moqapi Example sehlooho.
2019.04.02	19.1		• Tokollo ea pele.

Nalane ea Phetoho ea Litokomane bakeng sa Litšebelisano tsa Memori ea Kantle Intel Agilex FPGA IP Design Example Bukana ea Mosebelisi

Litokomane / Lisebelisoa

Intel UG-20219 External Memory Interfaces Intel Agilex FPGA IP Design Example [pdf] Bukana ea Mosebelisi UG-20219 External Memory Interfaces Intel Agilex FPGA IP Design Example, UG-20219, Memory Interfaces ea Kantle Intel Agilex FPGA IP Design Example, Interfaces Intel Agilex FPGA IP Design Example, Agilex FPGA IP Design Example

Litšupiso

• Bukana ea Mosebelisi