UG-20219 Ƙwaƙwalwar Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwaƙwa tọn ne wanda aka kafa ) na Agilex FPGA na IP Example
Game da Interfaces na Ƙwaƙwalwar Ƙwaƙwalwar Waje na Intel® Agilexâ„¢ FPGA IP
Bayanin Saki
Sifofin IP iri ɗaya ne da nau'ikan software na Intel® Quartus® Prime Design Suite har zuwa v19.1. Daga Intel Quartus Prime Design Suite software version 19.2 ko kuma daga baya, IP cores suna da sabon tsarin sigar IP. Lambar sigar sigar IP (XYZ) tana canzawa daga sigar software zuwa wata. Canji a:
- X yana nuna babban bita na IP. Idan ka sabunta software na Quartus Prime na Intel, dole ne ka sabunta IP ɗin.
- Y yana nuna IP ɗin ya ƙunshi sabbin abubuwa. Sake haɓaka IP ɗin ku don haɗa waɗannan sabbin fasalolin.
- Z yana nuna IP ɗin ya ƙunshi ƙananan canje-canje. Sake haɓaka IP ɗin ku don haɗa waɗannan canje-canje.
Abu Bayani Sigar IP 2.4.2 Intel Quartus Prime 21.2 Ranar Saki 2021.06.21
Zane ExampJagoran Farawa Mai Sauri don Mutunan Ƙwaƙwalwar Waje na Intel Agilex™ FPGA IP
Zane mai sarrafa kansa example kwarara yana samuwa don haɗin ƙwaƙwalwar waje na Intel Agilex™. Generate Example Designs button a kan Example Designs shafin yana ba ka damar ƙididdigewa da samar da ƙira da ƙirar ƙiraample file saitin da za ku iya amfani da su don inganta EMIF IP ɗin ku. Za ka iya haifar da zane exampwanda ya dace da kayan haɓakawa na Intel FPGA, ko don kowane EMIF IP da kuka ƙirƙira. Za ka iya amfani da zane exampdon taimakawa kimantawar ku, ko azaman mafari don tsarin ku.
Babban Zane Exampda Ayyukan Aiki
Ƙirƙirar Aikin EMIF
Don shi Intel Quartus Prime software version 17.1 kuma daga baya, dole ne ku ƙirƙiri aikin Intel Quartus Prime kafin samar da EMIF IP da ƙirar ƙira.ample.
- Kaddamar da Intel Quartus Prime software kuma zaɓi File ➤ Sabon Mayen Aikin. Danna Gaba. Zane ExampJagoran Farawa Mai Sauri don Mutunan Ƙwaƙwalwar Waje na Intel Agilex™ FPGA IP
- Ƙayyade kundin adireshi ( ), suna ga Intel Quartus Prime project ( ), da sunan mahallin ƙira na babban matakin ( ) da kuke son ƙirƙirar. Danna Gaba.
- Tabbatar da cewa an zaɓi aikin wofi. Danna gaba sau biyu.
- A ƙarƙashin Iyali, zaɓi Intel Agilex.
- Karkashin tace suna, rubuta lambar sashin na'urar.
- Ƙarƙashin na'urori masu samuwa, zaɓi na'urar da ta dace.
- Danna Gama.
Ƙirƙirar da Ƙaddamar da EMIF IP
Matakan da ke gaba suna kwatanta yadda ake samarwa da daidaita IP ɗin EMIF. Wannan tafiyar ta haifar da ƙirar DDR4, amma matakan sun yi kama da sauran ka'idoji. (Wadannan matakan suna bin kasidar IP (daidaitacce) kwarara; idan kun zaɓi yin amfani da kwararar Platform Designer (tsarin) maimakon, matakan suna kama da juna.)
- A cikin taga IP Catalog, zaɓi Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwaƙwa tọn ne mai Ƙwaƙwalwa na Ƙwa ) na Ƙwaƙwalwa na Ɗaya ne na Ƙwaƙwal na Ƙwaƙwalwa na Ƙwaƙwawa na Ƙwaƙwalwa na Ƙwaƙwalwa na Ƙwa ) na Agilex FPGA . (Idan ba a ganin taga IP Catalog, zaɓi View Ƙaddamar da IP Catalog.)
- A cikin Editan Sigar IP, samar da sunan mahalli don EMIF IP (sunan da kuka bayar anan ya zama file suna don IP) kuma saka directory. Danna Ƙirƙiri.
- Editan sigar yana da shafuka masu yawa inda dole ne ku saita sigogi don nuna aiwatar da EMIF ɗin ku.
Intel Agilex EMIF Jagorar Editan Madaidaicin
Wannan batu yana ba da jagora mai girma don daidaita shafuka a cikin editan siginar IP na Intel Agilex EMIF.
Tebur 1. Jagororin Editan Ma'auni na EMIF
| Tab ɗin Editan Sigar | Jagorori |
| Gabaɗaya | Tabbatar cewa an shigar da sigogi masu zuwa daidai:
• Matsayin saurin na'urar. • Mitar agogon ƙwaƙwalwar ajiya. • Mitar agogon PLL. |
| Ƙwaƙwalwar ajiya | Koma zuwa takardar bayanai don na'urar ƙwaƙwalwar ajiya don shigar da sigogi akan Ƙwaƙwalwar ajiya tab.
• Hakanan ya kamata ku shigar da takamaiman wuri don fil ɗin ALERT#. (Ya shafi ka'idar ƙwaƙwalwar ajiyar DDR4 kawai.) |
| Mem I/O | • Don binciken aikin farko, zaku iya amfani da saitunan tsoho akan
Mem I/O tab. • Don ingantaccen ingantaccen ƙira, yakamata ku yi simintin allo don samun mafi kyawun saitunan ƙarewa. |
| FPGA I/O | • Don binciken aikin farko, zaku iya amfani da saitunan tsoho akan
FPGA I/O tab. • Don ingantacciyar ƙira ta ci gaba, yakamata ku yi kwaikwaiyon allo tare da samfuran IBIS masu alaƙa don zaɓar ƙa'idodin I/O masu dacewa. |
| Lokacin Mem | • Don binciken aikin farko, zaku iya amfani da saitunan tsoho akan
Lokacin Mem tab. • Don ingantaccen ingantaccen ƙira, yakamata ka shigar da sigogi bisa ga takardar bayanan na'urar ƙwaƙwalwar ajiyar ku. |
| Mai sarrafawa | Saita sigogin mai sarrafawa bisa ga tsari da halin da ake so don mai sarrafa ƙwaƙwalwar ajiyar ku. |
| Bincike | Za ka iya amfani da sigogi a kan Bincike shafin don taimakawa wajen gwadawa da yin zamba a wurin ƙwaƙwalwar ajiyar ku. |
| Exampda Designs | The Exampda Designs tab zai baka damar samar da zane examples don kira da kuma kwaikwayo. Zane da aka samar example cikakken tsarin EMIF ne wanda ya ƙunshi EMIF IP da direban da ke haifar da zirga-zirgar ababen hawa don tabbatar da ƙirar ƙwaƙwalwar ajiya. |
Don cikakkun bayanai kan sigogi guda ɗaya, koma zuwa babin da ya dace don ƙa'idar ƙwaƙwalwar ajiyar ku a cikin Jagorar Mai amfani na IP Agilex FPGA na waje.
Ƙirƙirar EMIF Design Example
Don kayan haɓakawa na Intel Agilex, ya isa ya bar yawancin saitunan IP na Intel Agilex EMIF a ƙimar su ta asali. Don samar da synthesizable zane exampko, bi waɗannan matakan:
- A kan ExampDon Zane-zane shafin, tabbatar da cewa an duba akwatin Magana.
- Idan kana aiwatar da dubawa guda ɗaya exampDon zane, saita EMIF IP kuma danna File➤ Ajiye don adana saitin yanzu a cikin bambancin IP mai amfani file ( .ip).
- Idan kuna aiwatar da exampzana tare da mahara musaya, saka Adadin IPs zuwa adadin da ake so musaya. Kuna iya ganin jimlar adadin ID na EMIF daidai da zaɓin Adadin IPs. Bi waɗannan matakan don saita kowace dubawa:
- Zaɓi Cal-IP don ƙididdige haɗin haɗin kai zuwa IP Calibration.
- Sanya IP ɗin EMIF daidai a cikin duk Tab Editan Sigar.
- Koma zuwa ExampZazzage shafin kuma danna Ɗauki akan ID ɗin EMIF da ake so.
- Maimaita mataki na zuwa c don duk ID na EMIF.
- Kuna iya danna maɓallin Share don cire sigogin da aka kama kuma ku maimaita mataki a zuwa c don yin canje-canje ga EMIF IP.
- Danna File➤ Ajiye don adana saitin yanzu a cikin bambancin IP mai amfani file ( .ip).
- Idan kana aiwatar da dubawa guda ɗaya exampDon zane, saita EMIF IP kuma danna File➤ Ajiye don adana saitin yanzu a cikin bambancin IP mai amfani file ( .ip).
- Danna Ƙirƙirar Example Zane a saman kusurwar dama na taga.
- Ƙayyade kundin adireshi don ƙirar EMIF example kuma danna OK. Nasarar ƙarni na ƙirar EMIF example haifar da wadannan filesaita ƙarƙashin shugabanci qii.
- Danna File ➤ Fita don fita tagar Editan IP Parameter Pro. Tsarin yana haifar da, canje-canje na kwanan nan ba a haifar da su ba. Ƙirƙira yanzu? Danna A'a don ci gaba da gudana na gaba.
- Don buɗe exampda zane, danna File ➤ Buɗe Project, kuma kewaya zuwa /ample_name>/qii/ed_synth.qpf kuma danna Buɗe.
Lura: Don bayani kan harhadawa da shirye-shirye na zane example, koma zuwa
Haɗa da Shirye-shiryen Intel Agilex EMIF Design Example.
Hoto 4. Ƙirƙirar Ƙirƙirar Ƙira Example File Tsarin
Don bayani kan gina tsarin tare da mu'amalar ƙwaƙwalwar ajiyar waje biyu ko fiye, koma zuwa Ƙirƙirar Zane Examptare da Multiple EMIF Interfaces, a cikin Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwallon Ƙwallon Ƙwallon Ƙwallon Ƙwararren Ƙwararren Ƙwararren Ƙwararru FPGA FPGA . Don bayani game da gyara musaya da yawa, koma zuwa Ba da damar kayan aikin EMIF a cikin Tsararren Tsare-tsare, a cikin Mutuwar Ƙwaƙwalwar Ƙwaƙwalwar Waje ta Intel Agilex FPGA IP Jagorar Mai Amfani.
Lura: Idan baku zaɓi Akwatin simulation ko Synthesis ba, jagorar manufa ta ƙunshi ƙirar Platform Designer kawai. files, waɗanda Intel Quartus Prime software ba su haɗa kai tsaye ba, amma waɗanda zaku iya view ko gyara a cikin Platform Designer. A wannan yanayin zaka iya gudanar da umarni masu zuwa don samar da kira da simulation file sets.
- Don ƙirƙirar aikin da aka haɗa, dole ne ku gudanar da quartus_sh -t make_qii_design.tclscript a cikin jagorar manufa.
- Don ƙirƙirar aikin simulation, dole ne ku gudanar da rubutun quartus_sh -t make_sim_design.tcl a cikin kundin adireshin wurin.
Lura: Idan kun ƙirƙira zane example sannan ku yi canje-canje gare shi a cikin editan sigar, dole ne ku sake haɓaka ƙirar ƙiraampdon ganin an aiwatar da canje-canjenku. Sabuwar ƙirar da aka samar example baya sake rubuta abin da ke akwai example files.
Samar da EMIF Design Example don Simulation
Don kayan haɓakawa na Intel Agilex, ya isa ya bar yawancin saitunan IP na Intel Agilex EMIF a ƙimar su ta asali. Don samar da zane exampDon simulation, bi waɗannan matakan:
- A kan ExampDon Designs tab, tabbatar da cewa an duba akwatin kwaikwaiyo. Hakanan zaɓi tsarin da ake buƙata na Simulation HDL, ko dai Verilog ko VHDL.
- Sanya EMIF IP kuma danna File ➤ Ajiye don adana saitin yanzu a cikin bambancin IP mai amfani file ( .ip).
- Danna Ƙirƙirar Example Zane a saman kusurwar dama na taga.
- Ƙayyade kundin adireshi don ƙirar EMIF example kuma danna OK. Nasarar ƙarni na ƙirar EMIF example halitta mahara file saiti don na'urori masu tallafi daban-daban, ƙarƙashin kundin adireshin sim/ed_sim.
- Danna File ➤ Fita don fita tagar Editan IP Parameter Pro. Tsarin yana haifar da, canje-canje na kwanan nan ba a haifar da su ba. Ƙirƙira yanzu? Danna A'a don ci gaba da gudana na gaba.
Ƙirƙirar Simulators Example File Tsarin
Lura: Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Waje ta Intel Agilex FPGA IP a halin yanzu tana goyan bayan VCS, ModelSim/QuestaSim, da na'urar kwaikwayo na Xcelium kawai. Ana shirin ƙarin tallafin na'urar kwaikwayo a cikin fitowar gaba.
Lura: Idan baku zaɓi Akwatin simulation ko Synthesis ba, jagorar manufa ta ƙunshi ƙirar Platform Designer kawai. files, waɗanda Intel Quartus Prime software ba su haɗa kai tsaye ba, amma waɗanda zaku iya view ko gyara a cikin Platform Designer. A wannan yanayin zaka iya gudanar da umarni masu zuwa don samar da kira da simulation file sets.
- Don ƙirƙirar aikin da aka haɗa, dole ne ku gudanar da rubutun quartus_sh -t make_qii_design.tcl a cikin kundin adireshin wurin.
- Don ƙirƙirar aikin simulation, dole ne ku gudanar da rubutun quartus_sh -t make_sim_design.tcl a cikin kundin adireshin wurin.
Lura: Idan kun ƙirƙira zane example sannan ku yi canje-canje gare shi a cikin editan sigar, dole ne ku sake haɓaka ƙirar ƙiraampdon ganin an aiwatar da canje-canjenku. Sabuwar ƙirar da aka samar example baya sake rubuta abin da ke akwai example files.
Simulation Versus Hardware Aiwatar da
Don ƙirar ƙirar ƙwaƙwalwar waje ta waje, zaku iya zaɓar ko dai tsallake daidaitawa ko cikakken daidaitawa akan shafin bincike yayin tsara IP.
EMIF Model Simulators
Wannan tebur yana kwatanta halayen ƙetare calibration da cikakkun samfuran daidaitawa.
Tebur 2. Samfuran Kwaikwayo na EMIF: Tsallake Calibration tare da Cikakken Daidaitawa
| Tsallake Calibration | Cikakken Daidaitawa |
| Simintin matakin-tsari yana mai da hankali kan dabarun mai amfani. | Ƙwaƙwalwar ƙirar ƙwaƙwalwar ajiya tana mai da hankali kan daidaitawa. |
| Ba a kama cikakkun bayanai na daidaitawa ba. | Kama duk stages of calibration. |
| Yana da ikon adanawa da dawo da bayanai. | Ya haɗa da daidaitawa, tebur kowane-bit, da sauransu. |
| Yana wakiltar ingantaccen aiki. | |
| Baya la'akari da skew allon. | |
RTL Simulation Versus Hardware Aiwatar da
Wannan tebur yana nuna mahimman bambance-bambance tsakanin simintin EMIF da aiwatar da kayan masarufi.
Tebur 3. EMIF RTL Simulation Versus Hardware Aiwatar da
| RTL Simulation | Aiwatar Hardware |
| Nios® farko da lambar daidaitawa suna aiki a layi daya. | Nios farawa da lambar daidaitawa suna aiwatar da bi-da-bi. |
| Hanyoyin sadarwa suna tabbatar da siginar cal_done lokaci guda a cikin siminti. | Ayyukan fitter suna ƙayyade tsari na daidaitawa, kuma musaya ba sa tabbatar da cal_done a lokaci guda. |
Ya kamata ku gudanar da simintin RTL bisa tsarin zirga-zirga don aikace-aikacen ƙirar ku. Lura cewa kwaikwaiyon RTL baya ƙirar PCB gano jinkiri wanda zai iya haifar da rashin daidaituwa tsakanin simintin RTL da aiwatar da hardware.
Simulating External Memory Interface IP Tare da ModelSim
Wannan hanya tana nuna yadda ake kwaikwayi ƙirar EMIF example.
- Kaddamar da Mentor Graphics* ModelSim software kuma zaɓi File ➤ Canza Jagora. Kewaya zuwa sim/ed_sim/ directory directory a cikin ƙirar ƙira da aka ƙirƙiraampda folder.
- Tabbatar cewa an nuna taga kwafin rubutu a ƙasan allon. Idan taga Rubutun ba a ganuwa, nuna shi ta dannawa View ➤ Kwafi.
- A cikin Tagar Rubutun, gudanar da tushen msim_setup.tcl.
- Bayan tushen msim_setup.tcl ya gama aiki, kunna ld_debug a cikin Tagar Rubutun.
- Bayan ld_debug ya gama aiki, tabbatar da cewa an nuna taga abubuwan. Idan taga abubuwan ba a bayyane, nuna shi ta dannawa View ➤ Abubuwa.
- A cikin taga abubuwan, zaɓi siginar da kuke son siffantawa ta danna dama kuma zaɓi Ƙara Wave.
- Bayan kun gama zaɓar sigina don simulation, aiwatar da gudu-duk a cikin Tagar Rubutun. Simulation yana gudana har sai an kammala shi.
- Idan ba'a ganin simintin, danna View ➤ Wave.
Sanya Pin don Intel Agilex EMIF IP
Wannan batu yana ba da jagororin sanya fil.
Ƙarsheview
Intel Agilex FPGAs suna da tsari mai zuwa:
- Kowace na'ura ta ƙunshi bankunan I/O har 8.
- Kowane banki na I/O ya ƙunshi bankunan sub-I/O guda 2.
- Kowane bankin sub-I/O ya ƙunshi hanyoyi guda 4.
- Kowane layi yana ƙunshe da filoli 12 na gaba ɗaya I/O (GPIO).
Gabaɗaya Jagoran Pin
Wadannan sune jagororin fil gabaɗaya.
Lura: Don ƙarin cikakkun bayanai na fil, koma zuwa Intel Agilex FPGA EMIF IP Pin da sashin Tsare-tsaren Albarkatu a cikin takamaiman babi na ƙayyadaddun ƙayyadaddun ƙayyadaddun ƙayyadaddun ƙayyadaddun ƙayyadaddun ƙayyadaddun ƙayyadaddun ƙayyadaddun ƙayyadaddun ƙayyadaddun ƙayyadaddun ƙayyadaddun ƙayyadaddun ƙayyadaddun ƙayyadaddun ƙayyadaddun ƙayyadaddun ƙayyadaddun ƙayyadaddun ƙayyadaddun ƙayyadaddun ƙayyadaddun ƙayyadaddun bayanai, a cikin Interfaces Interfaces Memory External Intel Agilex FPGA IP Guide.
- Tabbatar cewa fil ɗin don ƙayyadaddun ƙayyadaddun ƙwaƙwalwar ajiyar waje suna zaune a cikin jeren I/O iri ɗaya.
- Hanyoyin sadarwa da suka mamaye bankuna da yawa dole ne su cika buƙatu masu zuwa:
- Dole ne bankunan su kasance kusa da juna. Don bayani kan bankunan da ke kusa, koma zuwa EMIF Architecture: Taken Banki na I/O a cikin Interfaces External Memory Interfaces Intel Agilex FPGA IP Jagorar Mai Amfani.
- Duk adireshi da umarni da maƙalai masu alaƙa dole su kasance a cikin banki ɗaya.
- Adireshi da umarni da fil ɗin bayanai na iya raba ƙaramin banki a ƙarƙashin sharuɗɗan masu zuwa:
- Adireshi da umarni da fil ɗin bayanai ba za su iya raba layin I/O ba.
- Hanyar I/O da ba a yi amfani da ita ba a cikin adireshi da bankin umarni zai iya ƙunsar fil ɗin bayanai.
Tebur 4. Gabaɗaya Matsalolin Pin
| Nau'in sigina | Takura |
| Data Strobe | Duk sigina na ƙungiyar DQ dole ne su kasance a cikin layin I/O iri ɗaya. |
| Bayanai | Maɓallan DQ masu alaƙa dole ne su kasance a cikin layin I/O iri ɗaya. Don ƙa'idodin da ba su goyan bayan layukan bayanai biyu ba, ya kamata a haɗa siginonin karantawa dabam daga siginar rubutawa. |
| Adireshi da Umurni | Adireshi da fil ɗin umarni dole ne su kasance a wuraren da aka riga aka ƙayyade a cikin ƙaramin bankin I/O. |
Lura: Don ƙarin cikakkun bayanai na fil, koma zuwa Intel Agilex FPGA EMIF IP Pin da sashin Tsare-tsaren Albarkatu a cikin takamaiman babi na ƙayyadaddun ƙayyadaddun ƙayyadaddun ƙayyadaddun ƙayyadaddun ƙayyadaddun ƙayyadaddun ƙayyadaddun ƙayyadaddun ƙayyadaddun ƙayyadaddun ƙayyadaddun ƙayyadaddun ƙayyadaddun ƙayyadaddun ƙayyadaddun ƙayyadaddun ƙayyadaddun ƙayyadaddun ƙayyadaddun ƙayyadaddun ƙayyadaddun ƙayyadaddun ƙayyadaddun bayanai, a cikin Interfaces Interfaces Memory External Intel Agilex FPGA IP Guide.
- Tabbatar cewa fil ɗin don ƙayyadaddun ƙayyadaddun ƙwaƙwalwar ajiyar waje suna zaune a cikin jeren I/O iri ɗaya.
- Hanyoyin sadarwa da suka mamaye bankuna da yawa dole ne su cika buƙatu masu zuwa:
- Dole ne bankunan su kasance kusa da juna. Don bayani kan bankunan da ke kusa, koma zuwa EMIF Architecture: Taken Banki na I/O a cikin Interfaces External Memory Interfaces Intel Agilex FPGA IP Jagorar Mai Amfani.
- Duk adireshi da umarni da maƙalai masu alaƙa dole su kasance a cikin banki ɗaya.
- Adireshi da umarni da fil ɗin bayanai na iya raba ƙaramin banki a ƙarƙashin sharuɗɗan masu zuwa:
- Adireshi da umarni da fil ɗin bayanai ba za su iya raba layin I/O ba.
- Hanyar I/O da ba a yi amfani da ita ba a cikin adireshi da bankin umarni zai iya ƙunsar fil ɗin bayanai.
Samar da Zane Examptare da Zaɓin Kanfigareshan TG
Ƙirƙirar ƙirar EMIF exampLe ya haɗa da toshe janareta na zirga-zirga (TG). Ta hanyar tsoho, ƙirar example yana amfani da toshe TG mai sauƙi (altera_tg_avl) wanda za'a iya sake saita shi kawai don sake buɗe tsarin zirga-zirga mai wuya. Idan ya cancanta, zaku iya zaɓar kunna janareta mai daidaita zirga-zirga (TG2) maimakon. A cikin injin janareta na zirga-zirgar ababen hawa (TG2) (altera_tg_avl_2), zaku iya saita tsarin zirga-zirga a cikin ainihin lokacin ta hanyar rajistar sarrafawa — ma'ana ba sai kun sake tattara ƙirar don canza ko sake buɗe tsarin zirga-zirga ba. Wannan janareta na zirga-zirgar ababen hawa yana ba da iko mai kyau akan nau'in zirga-zirgar da yake aikawa akan hanyar sarrafa EMIF. Bugu da ƙari, yana ba da rajistar matsayi waɗanda ke ɗauke da cikakkun bayanan gazawa.
Bayar da Generator Traffic a cikin Zane Example
Kuna iya kunna janareta na zirga-zirga mai daidaitawa daga shafin Diagnostics a cikin editan sigar EMIF. Don kunna janareta na zirga-zirga mai daidaitawa, kunna Yi amfani da janareta na zirga-zirgar ababen hawa na Avalon 2.0 akan Diagnostics tab.
Hoto na 6.
- Kuna iya zaɓar don musaki tsoffin tsarin zirga-zirga stage ko mai amfani da tsarin zirga-zirga stage, amma dole ne ku sami akalla s guda ɗayatage kunna. Domin bayani akan wadannan stage, koma zuwa Tsarin Traffic na Tsohuwar da Tsararren Traffic Tsarin Mai-mai amfani a cikin Mutuwar Ƙwaƙwalwar Ƙwaƙwalwar Waje ta Intel Agilex FPGA Jagorar Mai amfani ta IP.
- Ma'auni na tsawon gwajin TG2 yana aiki ne kawai ga tsoffin tsarin zirga-zirga. Kuna iya zaɓar lokacin gwaji na gajere, matsakaici, ko mara iyaka.
- za ka iya zaɓar ɗaya daga cikin ƙima biyu don ma'auni na Kanfigareshan TG2:
- JTAG: Yana ba da damar amfani da GUI a cikin na'ura mai kwakwalwa. Don ƙarin bayani, koma zuwa Interface Kanfigareshan Kanfigareshan Traffic Generator a cikin Mutuwar Ƙwaƙwalwar Ƙwaƙwalwar Waje ta Intel Agilex FPGA Jagorar Mai amfani ta IP.
- fitarwa: Yana ba da damar amfani da dabaru na RTL na al'ada don sarrafa tsarin zirga-zirga.
Amfani da Design Examptare da EMIF Debug Toolkit
Kafin kaddamar da EMIF Debug Toolkit, tabbatar da cewa kun saita na'urar ku tare da shirye-shirye. file wanda ke da EMIF Debug Toolkit yana kunna. Don ƙaddamar da EMIF Debug Toolkit, bi waɗannan matakan:
- A cikin Intel Quartus Prime software, buɗe System Console ta zaɓi Kayan aiki ➤ Kayan aikin gyara kuskuren tsarin
- [ Tsallake wannan matakin idan aikinku ya riga ya buɗe a cikin Intel Quartus Prime software.] A cikin System Console, loda abin SRAM. file (.sof) wanda da shi kuka tsara allon (kamar yadda aka bayyana a cikin Abubuwan da ake buƙata don Amfani da EMIF Debug Toolkit, a cikin Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwa tọn na Gudanarwa ) na Gudanarwa na Gudanarwa na IP na Agilex FPGA )
- Zaɓi misalai don gyara kuskure.
- Zaɓi EMIF Calibration Debug Toolkit don gyara madaidaicin EMIF, kamar yadda aka bayyana a Ƙirƙirar Ƙira Ex.amptare da Zaɓin Debug Calibration. A madadin, zaɓi EMIF TG Kanfigareshan Kayan aikin don gyara janareta na zirga-zirga, kamar yadda aka bayyana a Samar da Ƙira Ex.amptare da Zaɓin Kanfigareshan TG.
- Danna Buɗe kayan aiki don buɗe babban view na EMIF Debug Toolkit.
- Idan akwai misalan EMIF da yawa a cikin ƙirar da aka tsara, zaɓi shafi (hanyar zuwa JTAG master) da ID na ƙwaƙwalwar ajiyar ƙwaƙwalwar ajiya na misalin EMIF wanda don kunna kayan aikin.
- Danna Kunna Interface don ba da damar kayan aikin kayan aiki don karanta sigogin dubawa da matsayi na daidaitawa.
- Dole ne ku yi kuskuren dubawa guda ɗaya a lokaci guda; don haka, don haɗawa zuwa wani keɓancewa a cikin ƙira, dole ne ka fara kashe abin dubawa na yanzu.
Wadannan su ne examples na rahotanni daga EMIF Calibration Debug Toolkit da EMIF TG Kanfigareshan Kayan aiki:, bi da bi.
Lura: Don cikakkun bayanai kan gyara gyara madaidaici, koma zuwa Zamewa tare da Kayan aikin Gyara Mahimman Bayanan Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwa, a cikin Ƙwararren Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Intel Agilex FPGA IP Jagorar Mai Amfani.
Lura: Don cikakkun bayanai game da lalata janareta na zirga-zirga, koma zuwa Interface Mai amfani da Kanfigareshan Kanfigareshan Traffic Generator, a cikin Matsalolin Ƙwaƙwalwar Waje na Intel Agilex FPGA IP Jagorar Mai Amfani.
Zane ExampBayanin Mahimman Bayanan Ƙwaƙwalwar Ƙwaƙwalwar Waje na Intel Agilex FPGA IP
Lokacin da kuka ƙirƙira da samar da EMIF IP ɗinku, zaku iya tantance cewa tsarin yana ƙirƙirar kundayen adireshi don simulation da haɗawa. file sets, da kuma haifar da file saita ta atomatik. Idan ka zaɓi Simulation ko Synthesis a ƙarƙashin Exampda Design Files na Example Designs shafin, tsarin yana haifar da cikakken simulation file saita ko cikakken kira file saita, daidai da zaɓinku.
Ƙirƙirar Ƙira Example
Ƙirƙirar ƙira example ya ƙunshi manyan tubalan da aka nuna a cikin hoton da ke ƙasa.
- Generator na zirga-zirga, wanda shine haɗakarwa Avalon®-MM exampdireban da ke aiwatar da tsarin bazuwar karantawa da rubutawa zuwa adadin adireshi masu ƙima. Har ila yau, janareta na zirga-zirgar ababen hawa yana lura da bayanan da aka karanta daga ƙwaƙwalwar ajiya don tabbatar da cewa sun yi daidai da rubutattun bayanan kuma yana tabbatar da gazawar in ba haka ba.
- Misali na hanyar sadarwa na ƙwaƙwalwar ajiya, wanda ya haɗa da:
- Mai sarrafa ƙwaƙwalwar ajiya wanda ke daidaitawa tsakanin haɗin Avalon-MM da AFI.
- PHY, wanda ke aiki azaman mu'amala tsakanin mai sarrafa ƙwaƙwalwar ajiya da na'urorin ƙwaƙwalwar ajiya na waje don aiwatar da ayyukan karatu da rubutu.
Hoto 7. Ƙirar Ƙira Example
Lura: Idan ɗaya ko fiye na PLL Sharing Mode, DLL Sharing Mode, ko OCT Sharing Mode an saita zuwa kowace ƙima ban da Babu Sharing, ƙirar ƙira.ampLe zai ƙunshi janareta na zirga-zirgar ababen hawa/samfurin ƙwaƙwalwar ƙwaƙwalwar ajiya. Misalan janareta na zirga-zirgar ababen hawa biyu/Misalan mu'amalar ƙwaƙwalwar ajiya suna da alaƙa kawai ta hanyar haɗin PLL/DLL/OCT kamar yadda saitunan sigina suka ayyana. Samfuran janareta na zirga-zirgar ababen more rayuwa/Misalan mu'amalar ƙwaƙwalwar ajiya suna nuna yadda zaku iya yin irin waɗannan haɗin gwiwa a cikin ƙirar ku.
Tsarin Simulators Example
Tsarin simulation example ya ƙunshi manyan tubalan da aka nuna a cikin adadi mai zuwa.
- Misali na ƙirar ƙira example. Kamar yadda aka bayyana a cikin sashin da ya gabata, ƙirar ƙira example yana ƙunshe da janareta na zirga-zirga, ɓangaren daidaitawa, da misalin ƙirar ƙwaƙwalwar ajiya. Waɗannan suna toshe tsoho zuwa ƙirar simintin ƙididdiga inda ya dace da saurin kwaikwayo.
- Samfurin ƙwaƙwalwar ajiya, wanda ke aiki azaman ƙirar ƙira wanda ke manne da ƙayyadaddun ƙayyadaddun ƙa'idar ƙwaƙwalwar ajiya. Yawancin lokaci, masu siyar da ƙwaƙwalwar ajiya suna ba da ƙirar simulation don takamaiman abubuwan ƙwaƙwalwar ajiya waɗanda zaku iya saukewa daga nasu webshafuka.
- Mai duba matsayi, wanda ke lura da siginonin matsayi daga keɓaɓɓiyar ƙwaƙwalwar ajiyar waje ta IP da janareta na zirga-zirga, don siginar wucewa gaba ɗaya ko yanayin gazawa.
Hoto 10. Zane-zane Example
Exampda Designs Interface Tab
Editan sigar ya haɗa da Example Designs tab wanda ke ba ku damar daidaitawa da samar da ƙirar kuamples.
Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwaƙwa tọn ne na Ƙwa ) na FPGAampRukunin Rubutun Jagorar Mai Amfani
Sifofin IP iri ɗaya ne da nau'ikan software na Intel Quartus Prime Design Suite har zuwa v19.1. Daga Intel Quartus Prime Design Suite software version 19.2 ko kuma daga baya, IPs suna da sabon tsarin sigar IP. Idan ba a jera sigar ainihin IP ba, jagorar mai amfani don sigar ainihin IP ta baya tana aiki.
Tarihin Bita na Takardu don Mutuwar Ƙwaƙwalwar Ƙwaƙwalwar Waje na Intel Agilex FPGA IP Design ExampJagorar Mai Amfani
| Sigar Takardu | Intel Quartus Prime Version | Sigar IP | Canje-canje |
| 2021.06.21 | 21.2 | 2.4.2 | A cikin Zane Exampda Quick Start babi:
• Ƙara rubutu zuwa ga Haɗa da Shirye-shiryen Intel Agilex EMIF Design Example batu. • Gyara take na Samar da Zane Examptare da Zaɓin Debug Calibration batu. • Ƙara da Samar da Zane Examptare da Zaɓin Kanfigareshan TG kuma Bayar da Generator Traffic a cikin Zane Example batutuwa. • Gyara matakai 2, 3, da 4, sabunta adadi da yawa, da ƙara bayanin kula, a cikin Amfani da Design Examptare da EMIF Debug Toolkit batu. |
| 2021.03.29 | 21.1 | 2.4.0 | A cikin Zane Exampda Quick Start babi:
• Ƙara rubutu zuwa ga Ƙirƙirar EMIF Design Example kuma Samar da EMIF Design Example don Simulation batutuwa. • An sabunta ta File Tsarin tsari a cikin Samar da EMIF Design Example don Simulation batu. |
| 2020.12.14 | 20.4 | 2.3.0 | A cikin Zane Exampda Quick Start babi, ya yi canje-canje masu zuwa:
• An sabunta ta Ƙirƙirar EMIF Design Example batun don haɗa da ƙira-EMIF da yawa. • An sabunta adadi don mataki na 3, a cikin Samar da EMIF Design Example don Simulation batu. |
| 2020.10.05 | 20.3 | 2.3.0 | A cikin Zane ExampJagorar Farawa Mai sauri babi, ya yi canje-canje masu zuwa:
• Ci Ƙirƙirar Aikin EMIF, sabunta hoton a mataki na 6. • Ci Ƙirƙirar EMIF Design Example, sabunta adadi a mataki na 3. • Ci Samar da EMIF Design Example don Simulation, sabunta adadi a mataki na 3. • Ci Simulation Versus Hardware Aiwatar da, gyara ƙaramin bugun rubutu a tebur na biyu. • Ci Amfani da Design Examptare da EMIF Debug Toolkit, gyara mataki na 6, ƙara matakai 7 da 8. |
| ci gaba… | |||
| Sigar Takardu | Intel Quartus Prime Version | Sigar IP | Canje-canje |
| 2020.04.13 | 20.1 | 2.1.0 | • A cikin Game da babi, gyara tebur a cikin
Bayanin Saki batu. • A cikin Zane ExampJagorar Farawa Mai sauri babi: - Gyara mataki na 7 da hoton da ke da alaƙa, a cikin Ƙirƙirar EMIF Design Example batu. - Gyara da Samar da Zane Examptare da Zaɓin Debug batu. - Gyara da Amfani da Design Examptare da EMIF Debug Toolkit batu. |
| 2019.12.16 | 19.4 | 2.0.0 | • A cikin Zane Exampda Quick Start babi:
- An sabunta hoton a mataki na 6 na Ƙirƙirar Aikin EMIF batu. - An sabunta hoton a mataki na 4 na Ƙirƙirar EMIF Design Example batu. - An sabunta hoton a mataki na 4 na Samar da EMIF Design Example don Simulation batu. - Gyara mataki na 5 a cikin Samar da EMIF Design Example don Simulation batu. - Gyara da Gabaɗaya Jagoran Pin kuma Bankunan da ke kusa sassan Sanya Pin don Intel Agilex EMIF IP batu. |
| 2019.10.18 | 19.3 | • A cikin Ƙirƙirar Aikin EMIF topic, sabunta hoton tare da batu 6.
• A cikin Ƙirƙirar da Ƙaddamar da EMIF IP topic, sabunta adadi tare da mataki 1. • A cikin tebur a cikin Intel Agilex EMIF Jagorar Editan Madaidaicin topic, canza bayanin ga Hukumar tab. • A cikin Ƙirƙirar EMIF Design Example kuma Samar da EMIF Design Example don Simulation batutuwa, sabunta hoton a mataki na 3 na kowane batu. • A cikin Samar da EMIF Design Example don Simulation topic, updated da Ƙirƙirar Simulators Example File Tsarin adadi kuma gyara bayanin kula yana bin adadi. • A cikin Ƙirƙirar EMIF Design Example batu, ƙara mataki da adadi don musaya masu yawa. |
|
| 2019.07.31 | 19.2 | 1.2.0 | • Ƙara Game da Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwaƙwalwa na Intel Agilex FPGA IP babi da Bayanin Saki.
• Sabunta kwanakin da lambobin sigar. • Ƙananan haɓakawa ga Ƙirƙirar Ƙira Example siffa a cikin Ƙirƙirar Ƙira Example batu. |
| 2019.04.02 | 19.1 | • Sakin farko. |
Tarihin Bita na Takardu don Mutuwar Ƙwaƙwalwar Ƙwaƙwalwar Waje na Intel Agilex FPGA IP Design ExampJagorar Mai Amfani
Takardu / Albarkatu
 |
intel UG-20219 Ƙwaƙwalwar Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwaƙwa tọn ne wanda aka yi da shi FPGAample [pdf] Jagorar mai amfani UG-20219 Ƙwaƙwalwar Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwaƙwa tọn ne wanda aka kafa ) na Agilex FPGA na IP Example, UG-20219, Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwaƙwa tọn ne mai Ƙaƙwalwa na Ƙwa ) na Ƙaddamar Ɗaya da ke da su na Ƙadda ) FPGAample, Interfaces Intel Agilex FPGA IP Design Example, Agilex FPGA IP Design Example |
