Intel MAX 10 FPGA Devices Over UART le Nios II processor

Tlhahisoleseding ya Sehlahiswa

Moralo oa litšupiso o fana ka ts'ebeliso e bonolo e sebelisang likarolo tsa mantlha tsa tlhophiso e hole lits'ebetsong tse thehiloeng ho Nios II bakeng sa lisebelisoa tsa MAX 10 FPGA. Khokahano ea UART e kenyellelitsoeng ho MAX 10 FPGA Development Kit e sebelisoa hammoho le Altera UART IP core ho fana ka ts'ebetso ea tlhophiso e hole. Lisebelisoa tsa MAX10 FPGA li fana ka bokhoni ba ho boloka litšoantšo tse fihlang ho tse peli tse ntlafatsang le ho feta karolo ea ntlafatso ea sistimi e hole.

Likgutsufatso

Kgutsufatso	Tlhaloso
Avalon-MM	Avalon Memory-Mapped Configuration Flash memori
CFM	Sehokelo sa mosebelisi se hlakileng
ICB	Bit ea Tlhophiso ea ho Qala
MAP/.mapa	'Mapa oa memori File
Nios II EDS	Nios II Embedded Design Suite Support
PFL	Parallel Flash Loader IP ea mantlha
POF/.pof	Ntho ea Lenaneo File
QSPI	Quad serial peripheral interface
RPD/.rpd	Lintlha tse tala tsa mananeo
SBT	Lisebelisoa tsa ho Haha Lisebelisoa
SOF/.sof	Ntho ea SRAM File
KOLOI	Universal asynchronous receiver/transmitter
UFM	Memori ea Flash ea mosebelisi

Litaelo tsa Tšebeliso ea Sehlahisoa

Tlhokahalo

Tšebeliso ea moralo ona oa litšupiso e hloka hore u be le boemo bo bontšitsoeng ba tsebo kapa boiphihlelo libakeng tse latelang:

Litlhoko:

Tse latelang ke litlhoko tsa hardware le software bakeng sa moralo oa litšupiso:

Moqapi oa Litšupiso Files

File Lebitso	Tlhaloso
Setšoantšo_sa feme	Ka mekhoa e 'meli ea tlhophiso ea litšoantšo, CFM1 le CFM2 li kopantsoe polokelong e le 'ngoe ea CFM.
app_image_1	Moralo oa hardware oa Quartus II file seo se nka sebaka sa app_image_2 nakong ea ntlafatso ea sistimi e hole.
app_image_2	Khoutu ea kopo ea software ea Nios II e sebetsa joalo ka molaoli oa moralo oa sistimi ea ntlafatso e hole.
Remote_system_upgrade.c
fektheri_application1.pof	Lenaneo la Quartus II file e nang le setšoantšo sa feme le setšoantšo sa ts'ebeliso ea 1, se tla hlophisoa ho CFM0 le CFM1 & CFM2 ka ho latellana qalong stage.
feme_application1.rpd
tshebediso_image_1.rpd
tshebediso_image_2.rpd
Nios_application.pof

Moralo oa litšupiso o fana ka ts'ebeliso e bonolo e sebelisang likarolo tsa mantlha tsa tlhophiso e hole lits'ebetsong tse thehiloeng ho Nios II bakeng sa lisebelisoa tsa MAX 10 FPGA. Khokahano ea UART e kenyellelitsoeng ho MAX 10 FPGA Development Kit e sebelisoa hammoho le Altera UART IP core ho fana ka ts'ebetso ea tlhophiso e hole.

Lintlha Tse Amanang

Moqapi oa Litšupiso Files

Ntlafatso ea Sisteme e Hole ka MAX 10 FPGA Overview

Ka karolo ea ntlafatso ea sistimi e hole, lintlafatso le tokiso ea liphoso bakeng sa lisebelisoa tsa FPGA li ka etsoa u le hole. Sebakeng sa sistimi e kentsoeng, firmware e hloka ho ntlafatsoa khafetsa ka mefuta e fapaneng ea protocol, joalo ka UART, Ethernet, le I2C. Ha sistimi e kentsoeng e kenyelletsa FPGA, lintlafatso tsa firmware li ka kenyelletsa lintlafatso tsa setšoantšo sa Hardware ho FPGA.
Lisebelisoa tsa MAX10 FPGA li fana ka bokhoni ba ho boloka litšoantšo tse fihlang ho tse peli tse ntlafatsang le ho feta karolo ea ntlafatso ea sistimi e hole. E 'ngoe ea litšoantšo e tla ba setšoantšo sa morao-rao se kentsoeng haeba phoso e hlaha setšoantšong sa hona joale.

Likgutsufatso

Lethathamo la 1: Lethathamo la Likgutsufatso

Kgutsufatso ya Tlhaloso
Avalon-MM	Avalon Memory-Mapped
CFM	Memori ea tlhophiso ea flash
GUI	Sehokelo sa mosebelisi se hlakileng
ICB	Bit ea Tlhophiso ea ho Qala
MAP/.mapa	'Mapa oa memori File
Nios II EDS	Nios II Embedded Design Suite Support
PFL	Parallel Flash Loader IP ea mantlha
POF/.pof	Ntho ea Lenaneo File

• Intel Corporation. Litokelo tsohle li sirelelitsoe. Intel, logo ea Intel, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus le Stratix mantsoe le li-logo ke matšoao a khoebo a Intel Corporation kapa litšehetso tsa eona tsa US le/kapa linaheng tse ling. Intel e tiisa ts'ebetso ea FPGA ea eona le lihlahisoa tsa semiconductor ho latela litlhaloso tsa hajoale ho latela waranti e tloaelehileng ea Intel, empa e na le tokelo ea ho etsa liphetoho ho lihlahisoa le lits'ebeletso life kapa life ka nako efe kapa efe ntle le tsebiso. Intel ha e nke boikarabello kapa boikarabello bo hlahang ka lebaka la kopo kapa ts'ebeliso ea tlhahisoleseling efe kapa efe, sehlahisoa, kapa ts'ebeletso e hlalositsoeng mona ntle le ha ho lumellane ka ho hlaka ka lengolo ke Intel. Bareki ba Intel ba eletsoa ho fumana mofuta oa morao-rao oa litlhaloso tsa sesebelisoa pele ba itšetleha ka tlhahisoleseling efe kapa efe e phatlalalitsoeng le pele ba beha litaelo tsa lihlahisoa kapa lits'ebeletso.
• Mabitso a mang le mabitso a mang a ka nkoa e le thepa ea ba bang.

Tlhokahalo

Kgutsufatso QSPI	Tlhaloso Quad serial peripheral interface
RPD/.rpd	Lintlha tse tala tsa mananeo
SBT	Lisebelisoa tsa ho Haha Lisebelisoa
SOF/.sof	Ntho ea SRAM File
UART	Universal asynchronous receiver/transmitter
UFM	Memori ea Flash ea mosebelisi

Tlhokahalo

• Tšebeliso ea moralo ona oa litšupiso e hloka hore u be le boemo bo bontšitsoeng ba tsebo kapa boiphihlelo libakeng tse latelang:
• Tsebo e sebetsang ea litsamaiso tsa Nios II le lisebelisoa tsa ho li haha. Litsamaiso le lisebelisoa tsena li kenyelletsa software ea Quartus® II, Qsys, le Nios II EDS.
• Tsebo ea mekhoa ea tlhophiso ea Intel FPGA le lisebelisoa, joalo ka tlhophiso ea kahare ea MAX 10 FPGA, tšobotsi ea ntlafatso ea sistimi e hole le PFL.

Litlhoko

• Tse latelang ke litlhoko tsa hardware le software bakeng sa moralo oa litšupiso:
• MAX 10 FPGA kit ea ntlafatso
• Mofuta oa Quartus II oa 15.0 o nang le Nios II EDS
• Khomphuta e nang le mokhanni oa UART ea sebetsang le sebopeho
• Leha e le efe binary/hexadecimal file mohlophisi

Moqapi oa Litšupiso Files

Lethathamo la 2: Moralo Files E kenyelelitsoe ho Moralo oa Litšupiso

File Lebitso Setšoantšo_sa feme	Tlhaloso • Moralo oa hardware oa Quartus II file e tla bolokoa ho CFM0. • The fallback setšoantšo/fektheri setšoantšo ho sebelisoa ha phoso etsahala kopo ya setshwantsho jarolla.
app_image_1	• Moralo oa hardware oa Quartus II file e tla bolokoa ho CFM1 le CFM2.(1) • Setšoantšo sa pele sa kopo se kentsoeng sesebelisoa.

1. Mokhoeng oa tlhophiso oa litšoantšo tse peli, CFM1 le CFM2 li kopantsoe ho polokelo e le 'ngoe ea CFM.

File Lebitso app_image_2	Tlhaloso Moralo oa hardware oa Quartus II file e nkelang app_image_2 sebaka nakong ea ntlafatso ea sistimi e hole.
Remote_system_ upgrade.c	Khoutu ea ts'ebeliso ea software ea Nios II e sebetsang e le molaoli oa moralo oa sistimi ea ntlafatso e hole.
Remote Terminal.exe	• Phethahatso file ka GUI. • E sebetsa e le setsi sa moamoheli ho sebelisana le lisebelisoa tsa ntlafatso tsa MAX 10 FPGA. • E romella lintlha tsa mananeo ka UART. • Mohloli oa khoutu bakeng sa terminal ena e kenyelelitsoe.

Lethathamo la 3: Monghali Files E kenyelelitsoe ho Moralo oa Litšupiso

U ka sebelisa tsena master files bakeng sa moralo oa litšupiso ntle le ho hlophisa moralo files.

File Lebitso   fektheri_application1.pof factory_application1.rpd	Tlhaloso Lenaneo la Quartus II file e nang le setšoantšo sa feme le sesebelisoa sa 1, se tla hlophisoa ho CFM0 le CFM1 & CFM2 ka ho latellana qalongtage.
fektheri_application2.pof factory_application2.rpd	• Lenaneo la Quartus II file e nang le setšoantšo sa feme le setšoantšo sa ts'ebeliso 2. • Setšoantšo sa 2 sa ts'ebeliso se tla ntšoa hamorao ho nkela setšoantšo sa 1 sebaka nakong ea ntlafatso ea sistimi e hole, e bitsoang application_ image_2.rpd ka tlase.
tshebediso_image_1.rpd	Quartus II data e tala ea lenaneo file e nang le setšoantšo sa ts'ebeliso ea 1 feela.
tshebediso_image_2.rpd	Quartus II data e tala ea lenaneo file e nang le setšoantšo sa ts'ebeliso ea 2 feela.
Nios_application.pof	• Lenaneo file e nang le ts'ebeliso ea software ea processor ea Nios II .hex file feela. • Ho hlophisoa ho flash ea kantle ea QSPI.
pfl.sof	• Quartus II .sof e nang le PFL. • E hlophiselitsoe ho QSPI flash ho MAX 10 FPGA Development kit.

Reference Design Tlhaloso ea Mosebetsi

Nios II Gen2 processor

• Nios II Gen2 processor ka moralo oa litšupiso e na le mesebetsi e latelang:
• Setsebi sa libese se sebetsanang le lits'ebetso tsohle tsa khokahano ka Altera On-Chip Flash IP core ho kenyelletsa ho bala, ho ngola le ho hlakola.
• E fana ka algorithm ho software ho amohela "programming bit stream" ho tsoa komporong e amohelang 'me e qalelle tokiso bocha ka "Dual Configuration IP core".
• U hloka ho seta vector ea reset ea processor ka nepo. Sena ke ho netefatsa hore processor e kenya khoutu e nepahetseng ea kopo ho tsoa ho UFM kapa flash ea QSPI ea kantle.
• Hlokomela: Haeba khoutu ea kopo ea Nios II e le kholo, Intel e khothalletsa hore u boloke khoutu ea kopo ho flash ea QSPI e ka ntle. Moqaping ona oa litšupiso, vector ea reset e supa khanya ea kantle ea QSPI moo khoutu ea kopo ea Nios II e bolokiloeng teng.

Lintlha Tse Amanang

• Thupelo ea ntlafatso ea lisebelisoa tsa Nios II Gen2
• E fana ka leseli le eketsehileng mabapi le ho nts'etsapele processor ea Nios II Gen2.

Altera On-Chip Flash IP Core

• Altera On-Chip Flash IP ea mantlha e sebetsa joalo ka sebopeho sa processor ea Nios II ho bala, ho ngola kapa ho hlakola ts'ebetso ho CFM le UFM. Altera On-Chip Flash IP ea mantlha e fana ka monyetla oa ho fihlella, ho hlakola le ho ntlafatsa CFM ka molatsoana o mocha oa tlhophiso. Altera On-Chip Flash IP paramethara e bonts'a lethathamo la liaterese le reriloeng esale pele bakeng sa karolo ka 'ngoe ea memori.

Lintlha Tse Amanang

• Altera On-Chip Flash IP Core
• E fana ka lintlha tse ling mabapi le Altera On-Chip Flash IP Core.

Altera Dual Configuration IP Core

• U ka sebelisa Altera Dual Configuration IP core ho fihlella sebaka sa ntlafatso sa sistimi e hole ho lisebelisoa tsa MAX 10 FPGA. Altera Dual Configuration IP core e u lumella hore u qalelle ho hlophisa bocha hang ha setšoantšo se secha se jarollotsoe.

Lintlha Tse Amanang

• Altera Dual Configuration IP Core
• E fana ka lintlha tse ling mabapi le Altera Dual Configuration IP Core

Mokhoa oa ho fetola UART IP Core

• UART IP ea mantlha e lumella puisano ea melapo ea litlhaku tsa serial lipakeng tsa sistimi e kentsoeng ho MAX 10 FPGA le sesebelisoa sa kantle. Joaloka setsebi sa Avalon-MM, processor ea Nios II e buisana le UART IP core, e leng lekhoba la Avalon-MM. Puisano ena e etsoa ka taolo ea ho bala le ho ngola le lirekoto tsa data.
• Ntho ea mantlha e sebelisa nako ea protocol ea RS-232 mme e fana ka lintlha tse latelang:
• sekhahla sa baud se feto-fetohang, ho lekana, ho emisa, le likotoana tsa data
• boikhethelo matshwao a taolo a phallo ya RTS/CTS

Lintlha Tse Amanang

• UART Core
• E fana ka lintlha tse ling mabapi le UART Core.

Generic Quad SPI Controller IP Core

• The Generic Quad SPI Controller IP core e sebetsa e le sehokelo lipakeng tsa MAX 10 FPGA, lebone la kantle le lebone la QSPI le leboteng. Konokono e fana ka phihlello ea khanya ea QSPI ka ho bala, ho ngola le ho hlakola ts'ebetso.
  Ha ts'ebeliso ea Nios II e hola ka litaelo tse ling, the file boholo ba hex file e hlahisoang ho tsoa ho kopo ea Nios II e tla ba kholoanyane. Ka ntle ho tekanyo e itseng ea boholo, UFM e ke ke ea ba le sebaka se lekaneng sa ho boloka hex ea kopo file. Ho rarolla sena, o ka sebelisa lebone la kantle la QSPI le fumanehang ho MAX 10 FPGA Development kit ho boloka hex ea kopo. file.

Moralo oa Kopo ea Nios II EDS Software

• Moralo oa litšupiso o kenyelletsa khoutu ea kopo ea software ea Nios II e laolang moralo oa sistimi ea ntlafatso e hole. Likarabo tsa khoutu ea kopo ea software ea Nios II ho terminal ea moamoheli ka UART ka ho etsa litaelo tse tobileng.

Ho Nchafatsa Lits'oants'o tsa Ts'ebeliso ka Remoutu

• Ka mor'a hore u fetise molaetsa oa "programming bit stream". file u sebelisa Remote Terminal, sesebelisoa sa software sa Nios II se etselitsoe ho etsa se latelang:

1. Beha Ngoliso ea Taolo ea mantlha ea Altera On-Chip Flash IP hore e se sireletse lekala la CFM1 & 2.
2. Etsa ts'ebetso ea ho hlakola lekala ho CFM1 le CFM2. Software e khetha rejisetara ea maemo ea Altera On-Chip Flash IP core ho netefatsa hore e phethiloe ka katleho.
3. Fumana li-byte tse 4 tsa bit stream ka nako ho tsoa ho stdin. Kenyelletso le tlhahiso e tloaelehileng e ka sebelisoa ho amohela data ka kotloloho ho tsoa ho terminal ea moamoheli le ho hatisa tlhahiso ho eona. Mefuta ea khetho e tloaelehileng ea ho kenya le ho tsoa e ka beoa ka BSP Editor ho sesebelisoa sa Nios II Eclipse Build.
4. E khutlisetsa morao tatellano ea biti bakeng sa baiti ka 'ngoe.
   • Hlokomela: Ka lebaka la tlhophiso ea Altera On-Chip Flash IP Core, byte e 'ngoe le e 'ngoe ea data e hloka ho khutlisoa pele e e ngola ho CFM.
5. Qala ho ngola li-byte tse 4 tsa data ka nako e le 'ngoe ho CFM1 le CFM2. Ts'ebetso ena e ntse e tsoela pele ho fihlela qetellong ea "programming bit stream".
6. Ho khetha rejisetara ea maemo ea Altera On-Chip Flash IP ho netefatsa ts'ebetso e atlehileng ea ho ngola. E fana ka molaetsa ho bontša hore phetiso e felile.
   • Hlokomela: Haeba ts'ebetso ea ho ngola e hloleha, terminal e tla emisa ts'ebetso ea ho romella bitana ebe e hlahisa molaetsa oa phoso.
7. E beha Rejistara ea Taolo ho sireletsa hape CFM1 le CFM2 ho thibela tšebetso efe kapa efe e sa batleheng ea ho ngola.

Lintlha Tse Amanang

• pof Generation ka Convert Programming Files ho
• E fana ka leseli mabapi le ho theha rpd files nakong ea ho fetolela mananeo files.

Ho Qetella Phetoho e Ncha ka Remoutu

• Ka mor'a hore u khethe ts'ebetso ea ts'ebetso ea ho tsosolosa setsing sa Remote Terminal, sesebelisoa sa Nios II se tla etsa se latelang:

1. Amohela taelo ho tsoa ho mokhoa o tloaelehileng.
2. Qala ho hlophisa bocha ka lits'ebetso tse peli tse latelang tsa ho ngola:

• Ngola 0x03 ho aterese ea offset ea 0x01 ho Dual Configuration IP core. Ts'ebetso ena e hlakola phini ea 'mele ea CONFIG_SEL ebe e beha Setšoantšo sa 1 e le setšoantšo se latelang sa tlhophiso ea boot.
• Ngola 0x01 ho aterese ea offset ea 0x00 ho Dual Configuration IP core. Ts'ebetso ena e etsa hore ho hlophisoe setšoantšo sa ts'ebeliso ho CFM1 le CFM2

Reference Design Walkthrough

Ho hlahisa Mananeo Files

• U tlameha ho hlahisa lenaneo le latelang files pele o khona ho sebelisa ntlafatso ea sistimi e hole ho MAX 10 FPGA Development kit:

Bakeng sa Lenaneo la QSPI:

• sof-sebelisa pfl.sof e kenyellelitsoe moetsong oa litšupiso kapa o ka khetha ho theha .sof e fapaneng e nang le moralo oa hau oa PFL
• pof - tlhophiso file e hlahisoang ho tsoa ho .hex 'me e hlophiselitsoe ho flash ea QSPI.
• Bakeng sa Ntlafatso ea Sisteme e hole:
• pof - tlhophiso file e hlahisoang ho tsoa ho .sof le ho hlophisoa ho flash e ka hare.
• rpd-e na le data bakeng sa flash e ka hare e kenyelletsang litlhophiso tsa ICB, CFM0, CFM1 le UFM.
• 'mapa-e tšoara aterese bakeng sa karolo ka 'ngoe ea memori ea litlhophiso tsa ICB, CFM0, CFM1 le UFM.

Ho hlahisa files bakeng sa QSPI Programming

Ho hlahisa .pof file bakeng sa lenaneo la QSPI, etsa mehato e latelang:

1. Haha Morero oa Nios II 'me u hlahise HEX file.
   • Hlokomela: Sheba AN730: Mekhoa ea ho qalisa processor ea Nios II ho Lisebelisoa tsa MAX 10 bakeng sa tlhaiso-leseling mabapi le ho aha morero oa Nios II le ho hlahisa HEX file.
2. Holima File menu, tobetsa Convert Programming Files.
3. Tlas'a Output programming file, khetha Ntho ea Lenaneo File (.pof) ho Lenaneo file lethathamo la mofuta.
4. Lethathamong la Mokhoa, khetha 1-bit Passive Serial.
5. Lethathamong la lisebelisoa tsa Configuration, khetha CFI_512Mb.
6. Ho File lebitso la lebokose, bolela the file lebitso la lenaneo file u batla ho bopa.
7. Kenyeletsong files ho fetolela lenane, tlosa likhetho le mola oa data oa SOF. Tobetsa Add Hex Data le lebokose la puisano la Add Hex Data le hlaha. Lebokoseng la Add Hex Data, khetha Absolute addressing ebe o kenya .hex file e hlahisoang ke Nios II EDS Build Tools.
8. Ka mor'a hore litlhophiso tsohle li behoe, tobetsa Hlahisa ho hlahisa mananeo a amanang file.

Lintlha Tse Amanang

AN730: Mekhoa ea ho qalisa processor ea Nios II ho lisebelisoa tsa MAX 10 FPGA
Ho hlahisa files bakeng sa Ntlafatso ea Sistimi ea Remote

Ho hlahisa .pof, .map le .rpd files bakeng sa ntlafatso ea sistimi e hole, etsa mehato e latelang:

1. Khutlisa Factory_image, application_image_1 le application_image_2, 'me u hlophise meralo e meraro.
2. Hlahisa tse peli .pof filee hlalositsoe tafoleng e latelang:
   • Hlokomela: Sheba .pof Generation through Convert Programming Files bakeng sa mehato ea ho hlahisa .pof files.
3. Bula app2.rpd u sebelisa mohlophisi ofe kapa ofe oa hex.
4. Ho hex editor, khetha "binary data block" ho latela mokhoa oa ho qala le oa ho qetela ka ho bua ka .map. file. Tsela ea ho qala le ea ho qetela bakeng sa sesebelisoa sa 10M50 ke 0x12000 le 0xB9FFF ka ho latellana. Kopitsa boloko bona ho e ncha file 'me u e boloke ka .rpd e fapaneng file. .rpd ena e ncha file e na le setšoantšo sa ts'ebeliso ea 2 feela.

pof Generation ka Convert Programming Files

Ho sokolla .sof files ho .pof files, latela mehato ena:

1. Holima File menu, tobetsa Convert Programming Files.
2. Tlas'a Output programming file, khetha Ntho ea Lenaneo File (.pof) ho Lenaneo file lethathamo la mofuta.
3. Lethathamong la Mekhoa, khetha Internal Configuration.
4. Ho File lebitso la lebokose, bolela the file lebitso la lenaneo file u batla ho bopa.
5. Ho hlahisa 'mapa oa memori File (.mapa), bulela Theha Memory Map File (Iketsetse tlhahiso ea boiketsetso_file.mapa). 'Mapa o na le aterese ea CFM le UFM e nang le litlhophiso tsa ICB tseo u li behang ka khetho ea Option/Boot Info.
6.  Ho hlahisa Raw Programming Data (.rpd), laeta Create config data RPD (Generate output_file_auto.rpd).
   Ka thuso ea 'Mapa oa Memori File, o ka tsebahatsa data habonolo bakeng sa boloko bo bong le bo bong bo sebetsang ho .rpd file. U ka boela ua ntša lintlha tsa flash bakeng sa lisebelisoa tsa mananeo a motho oa boraro kapa ua ntlafatsa tlhophiso kapa data ea mosebedisi ka Altera On-Chip Flash IP.
7. The .sof e ka eketsoa ka Input files ho sokolla lethathamo 'me u ka eketsa ho fihlela ho tse peli .sof files.
   • Bakeng sa merero ea ntlafatso ea sistimi e hole, o ka boloka lintlha tsa leqephe la 0 ho .pof, 'me u nkela lintlha tsa leqephe la 1 sebaka ka .sof e ncha. file. Ho etsa sena, o hloka ho eketsa .pof file leqepheng la 0, joale
     eketsa leqephe la .sof, ebe u eketsa .sof e ncha file ho
8. Ka mor'a hore litlhophiso tsohle li behoe, tobetsa Hlahisa ho hlahisa mananeo a amanang file.

Lenaneo la QSPI

Ho kenya khoutu ea kopo ea Nios II ho flash ea QSPI, etsa mehato e latelang:

1. Ho MAX 10 FPGA Development Kit, fetola MAX10_BYPASSn ho 0 ho feta sesebelisoa sa VTAP (MAX II).
2. Hokela Intel FPGA Download Cable (eo pele e neng e le USB Blaster) ho mochine oa JTAG hlooho.
3. Ka fensetere ea Programmer, tobetsa Setupo sa Hardware ebe u khetha USB Blaster.
4. Lethathamong la Mekhoa, khetha JTAG.
5. Tobetsa konopo ea Auto Detect karolong e ka ho le letšehali.
6. Khetha sesebelisoa se tla hlophisoa, ebe o tobetsa Eketsa File.
7. Khetha pfl.sof.
8. Tobetsa Qala ho qala mananeo.
9. Kamora hore lenaneo le atlehe, ntle le ho tima boto, tobetsa konopo ea Auto Detect karolong e ka ho le letšehali hape. U tla bona lebone la QSPI_512Mb le hlaha fensetereng ea mohlophisi.
10. Khetha sesebelisoa sa QSPI, ebe o tobetsa Eketsa File.
11. Khetha .pof file e hlahisitsoeng pejana ho tsoa ho .hex file.
12. Tobetsa Qala ho qala ho hlophisa lebone la QSPI.

Ho hlophisa FPGA ka Setšoantšo sa Pele u sebelisa JTAG

U tlameha ho kenya app1.pof ho FPGA e le setšoantšo sa pele sa sesebelisoa. Ho kenya app1.pof ho FPGA, etsa mehato e latelang:

1. Ka fensetere ea Programmer, tobetsa Setupo sa Hardware ebe u khetha USB Blaster.
2. Lethathamong la Mekhoa, khetha JTAG.
3. Tobetsa konopo ea Auto Detect karolong e ka ho le letšehali.
4. Khetha sesebelisoa se tla hlophisoa, ebe o tobetsa Eketsa File.
5. Khetha app1.pof.
6. Tobetsa Qala ho qala mananeo.

Ho nchafatsa setšoantšo le ho qala ho hlophisa bocha ho sebelisa UART

Ho lokisa lisebelisoa tsa hau tsa ntlafatso tsa MAX10 FPGA u le hole, etsa mehato e latelang:

1. Hlokomela: Pele o qala, etsa bonnete ba tse latelang:
   • CONFIG_SEL phini ea boto e behiloe ho 0
   • koung ea UART ea boto ea hau e hokahane le komporo ea hau
   • Bula Remote Terminal.exe mme sebopeho sa Remote Terminal sea buleha.
2. Tobetsa Litlhophiso 'me fensetere ea li-port tsa Serial e tla hlaha.
3. Beha liparamente tsa terminal e hole ho tsamaisana le litlhophiso tsa UART tse khethiloeng ho Quartus II UART IP core. Kamora hore ho seta ho phetheloe, tlanya OK.
4. Tobetsa konopo ea nCONFIG ho kit ea nts'etsopele kapa key-in 1 ka har'a Send text box, ebe o otla Enter.
   • Lenane la khetho ea ts'ebetso le tla hlaha ho terminal, joalo ka ha ho bonts'itsoe ka tlase:
   • Hlokomela: Ho khetha opereishene, kenya nomoro e lebokoseng la Send text, ebe o otla Enter.
5. Ho nchafatsa setšoantšo sa 1 sa ts'ebeliso ka setšoantšo sa 2 sa ts'ebeliso, khetha ts'ebetso 2. U tla khothaletsoa ho kenya aterese ea ho qala le ea ho qetela ea CFM1 le CFM2.
   • Hlokomela: Aterese e bontšitsoeng 'mapeng file e kenyelletsa litlhophiso tsa ICB, CFM le UFM empa Altera On-Chip
   • Flash IP e ka fihlella CFM le UFM feela. Kahoo, ho na le aterese pakeng tsa aterese e bontšitsoeng 'mapeng file le fensetere ea paramethara ea Altera On-Chip Flash IP.
6. Senotlolo atereseng e thehiloeng ho aterese e boletsoeng ke fensetere ea paramethara ea Altera On-Chip Flash IP.
   • Hlakola e tla qala ka bo eona ka mor'a hore u kenye aterese ea ho qetela.
7. Ka mor'a hore ho hlakoloe ho atlehe, u tla susumelletseha ho kenya lenaneo .rpd file bakeng sa setšoantšo sa ts'ebeliso ea 2.
   • Ho kenya setšoantšo, tobetsa SendFile konopo, ebe o khetha .rpd e nang le setšoantšo sa ts'ebeliso ea 2 feela ebe o tobetsa Open.
   • Hlokomela: Ntle le setšoantšo sa ts'ebeliso ea 2, u ka sebelisa setšoantšo leha e le sefe se secha seo u lakatsang ho se ntlafatsa ka har'a sesebelisoa.
   • Ts'ebetso ea ntlafatso e tla qala ka kotloloho mme o ka lekola tsoelo-pele ka terminal. Lenaneo la ts'ebetso le tla etsa hore ho Etsoe 'me joale u ka khetha ts'ebetso e latelang.
8. Ho qala tlhophiso bocha, khetha ts'ebetso ea 4. U ka shebella boits'oaro ba LED bo bonts'ang setšoantšo se fapaneng se kentsoeng sesebelisoa.

Setšoantšo	Boemo ba LED (E sebetsa Tlase)
Setšoantšo sa Feme	01010
Setšoantšo sa Tšebeliso 1	10101
Setšoantšo sa Tšebeliso 2	01110

Nalane ea Phetoho ea Litokomane

Letsatsi	Phetolelo	Liphetoho
Hlakola 2017	2017.02.21	E fetoletsoe joalo ka Intel.
Phuptjane 2015	2015.06.15	Tokollo ea pele.

Litokomane / Lisebelisoa

Intel MAX 10 FPGA Devices Over UART le Nios II processor [pdf] Bukana ea Mosebelisi MAX 10 FPGA Devices Over UART with Nios II Processor, MAX 10 FPGA Devices, Over UART e nang le Nios II processor, Over UART, Nios II processor UART, Nios II, processor UART

Litšupiso

• Bukana ea Mosebelisi