Ngwa intel MAX 10 FPGA karịrị UART nwere Nios II Processor

Ozi ngwaahịa

Atụmatụ ntụaka ahụ na-enye ngwa dị mfe nke na-arụ ọrụ nhazi nhazi dịpụrụ adịpụ na sistemụ Nios II maka ngwaọrụ MAX 10 FPGA. A na-eji interface UART gụnyere na MAX 10 FPGA Development Kit yana Altera UART IP core iji nye ọrụ nhazi dịpụrụ adịpụ. Ngwa MAX10 FPGA na-enye ike ịchekwa ihe ruru onyonyo nhazi abụọ nke na-emewanye njiri nkwalite sistemụ dịpụrụ adịpụ.

Ndebiri

Mbiri	Nkọwa
Avalon-MM	Ebe nchekwa Flash nhazi nke Avalon Ebe nchekwa
CFM	Orụ ọrụ eserese
ICB	Nhazi mmalite mmalite Bit
MAP/.map	Map ebe nchekwa File
Nios II EDS	Nkwado Nios II Embedded Design Suite
PFL	Parallel Flash Loader IP isi
POF/ .pof	Ihe mmemme File
QSPI	Oghere Usoro akụkụ anọ interface
RPD/.rpd	Data mmemme efu
SBT	Ngwa Nrụpụta Ngwanrọ
SOF / .sọf	Ihe SRAM File
ụgbọ ala	Ihe nnata/nfefe asynchronous zuru ụwa ọnụ
UFM	Ebe nchekwa flash onye ọrụ

Ntuziaka ojiji ngwaahịa

Ihe achọrọ

Ngwa nke nhazi ntụaka a chọrọ ka ị nweta ọkwa ọmụma ma ọ bụ ahụmịhe egosipụtara na mpaghara ndị a:

Ihe achọrọ:

Ndị a bụ ngwaike na ngwanrọ chọrọ maka nhazi ntụaka:

Atụmatụ ntụaka Files

File Aha	Nkọwa
Onyonyo ụlọ ọrụ	N'ọnọdụ nhazi ihe onyonyo abụọ, CFM1 na CFM2 na-ejikọta ya na otu nchekwa CFM.
app_image_1	Nhazi ngwaike Quartus II file nke na-anọchi app_image_2 n'oge a ime usoro nkwalite.
app_image_2	Koodu ngwa ngwa Nios II na-arụ ọrụ dị ka onye njikwa maka imewe usoro nkwalite nke ime ime.
Remote_system_upgrade.c
factory_application1.pof	Mmemme Quartus II file nke mejupụtara ihe oyiyi ụlọ ọrụ na onyonyo ngwa 1, ka emebere ya na CFM0 na CFM1 & CFM2 n'otu n'otu na mbido stage.
factory_application1.rpd
ngwa_image_1.rpd
ngwa_image_2.rpd
Nios_application.pof

Atụmatụ ntụaka ahụ na-enye ngwa dị mfe nke na-arụ ọrụ nhazi nhazi dịpụrụ adịpụ na sistemụ Nios II maka ngwaọrụ MAX 10 FPGA. A na-eji interface UART gụnyere na MAX 10 FPGA Development Kit yana Altera UART IP core iji nye ọrụ nhazi dịpụrụ adịpụ.

Ozi metụtara

Atụmatụ ntụaka Files

Nkwalite sistemụ dịpụrụ adịpụ yana MAX 10 FPGA karịrịview

Site na njirimara nkwalite sistemụ dịpụrụ adịpụ, nkwalite na ndozi maka ngwaọrụ FPGA nwere ike ime ya ozugbo. Na gburugburu sistemụ agbakwunyere, ọ dị mkpa ka emelite firmware ugboro ugboro karịa ụdị protocol dị iche iche, dị ka UART, Ethernet, na I2C. Mgbe sistemụ agbakwunyere gụnyere FPGA, mmelite firmware nwere ike ịgụnye mmelite nke onyonyo ngwaike na FPGA.
Ngwa MAX10 FPGA na-enye ike ịchekwa ihe ruru onyonyo nhazi abụọ nke na-emewanye njiri nkwalite sistemụ dịpụrụ adịpụ. Otu n'ime ihe onyonyo a ga-abụ onyonyo ndabere nke a na-ebugo ma ọ bụrụ na njehie emee na onyonyo dị ugbu a.

Ndebiri

Tebụl 1: Ndepụta nke ndebiri

Nkọwa Mbibiri
Avalon-MM	Ebe nchekwa Avalon
CFM	Ebe nchekwa flash nhazi nhazi
GUI	Orụ ọrụ eserese
ICB	Nhazi mmalite mmalite Bit
MAP/.map	Map ebe nchekwa File
Nios II EDS	Nkwado Nios II Embedded Design Suite
PFL	Parallel Flash Loader IP isi
POF/ .pof	Ihe mmemme File

• Ụlọ ọrụ Intel. Ikike niile echekwabara. Intel, akara Intel, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus na Stratix okwu na akara bụ ụghalaahịa nke ụlọ ọrụ Intel ma ọ bụ ndị enyemaka ya na US na/ma ọ bụ obodo ndị ọzọ. Intel nyere ikike ịrụ ọrụ nke FPGA na ngwaahịa semiconductor na nkọwapụta ugbu a dịka akwụkwọ ikike ọkọlọtọ Intel siri dị, mana nwere ikike ịme mgbanwe na ngwaahịa na ọrụ ọ bụla n'oge ọ bụla na-enweghị ọkwa. Intel anaghị ewere ọrụ ọ bụla ma ọ bụ ụgwọ sitere na ngwa ma ọ bụ iji ozi ọ bụla, ngwaahịa ma ọ bụ ọrụ akọwara n'ime ebe a belụsọ dị ka Intel kwetara na ederede. A dụrụ ndị ahịa Intel ọdụ ka ha nweta ụdị nkọwa ngwaọrụ kachasị ọhụrụ tupu ha adabere na ozi ọ bụla ebipụtara yana tupu ịnye iwu maka ngwaahịa ma ọ bụ ọrụ.
• Enwere ike ịzọrọ aha na akara ndị ọzọ dị ka ihe onwunwe nke ndị ọzọ.

Ihe achọrọ

Mbiri QSPI	Nkọwa Oghere Usoro akụkụ anọ interface
RPD/.rpd	Data mmemme efu
SBT	Ngwa Nrụpụta Ngwanrọ
SOF / .sọf	Ihe SRAM File
UART	Ihe nnata/nfefe asynchronous zuru ụwa ọnụ
UFM	Ebe nchekwa flash onye ọrụ

Ihe achọrọ

• Ngwa nke nhazi ntụaka a chọrọ ka ị nweta ọkwa ọmụma ma ọ bụ ahụmịhe egosipụtara na mpaghara ndị a:
• Ihe ọmụma na-arụ ọrụ nke sistemụ Nios II na ngwaọrụ iji wuo ha. Sistemu na ngwaọrụ ndị a gụnyere sọftụ Quartus® II, Qsys na Nios II EDS.
• Ọmụma nke usoro nhazi na ngwaọrụ Intel FPGA, dị ka nhazi ime MAX 10 FPGA, njiri nkwalite sistemụ dịpụrụ adịpụ na PFL.

Ihe achọrọ

• Ndị a bụ ngwaike na ngwanrọ chọrọ maka nhazi ntụaka:
• Ngwa mmepe MAX10 FPGA
• Ụdị Quartus II 15.0 nwere Nios II EDS
• Kọmputa nwere onye ọkwọ ụgbọ ala UART na interface na-arụ ọrụ
• ọnụọgụ abụọ/hexadecimal ọ bụla file nchịkọta akụkọ

Atụmatụ ntụaka Files

Tebụl 2: Nhazi Files Tinyere n'ime atụmatụ ntụaka

File Aha Onyonyo ụlọ ọrụ	Nkọwa • Quartus II ngwaike imewe file A ga-echekwa ya na CFM0. • Onyonyo ọdịda/onyinyo ụlọ nrụpụta ga-eji mgbe mperi pụtara na nbudata onyonyo ngwa.
app_image_1	• Quartus II ngwaike imewe file A ga-echekwa ya na CFM1 na CFM2.(1) • Onyonyo ngwa mbụ etinyere na ngwaọrụ.

1. Na ọnọdụ nhazi ihe onyonyo abụọ, CFM1 na CFM2 jikọtara na otu nchekwa CFM.

File Aha app_image_2	Nkọwa Nhazi ngwaike Quartus II file nke na-anọchi app_image_2 n'oge nkwalite sistemu dịpụrụ adịpụ.
Remote_system_ nkwalite.c	Koodu ngwa ngwa Nios II na-arụ ọrụ dị ka onye na-ahụ maka imewe sistemụ nkwalite dịpụrụ adịpụ.
Remote Terminal.exe	• Enwere ike ime ya file na GUI. • Arụ ọrụ dị ka ọnụ maka onye ọbịa na ngwa mmepe FPGA MAX 10. • Na-eziga data mmemme site na UART. • Koodu isi mmalite nke ọdụ a gụnyere.

Tebụl 3: Nna-ukwu Files Tinyere n'ime atụmatụ ntụaka

Ị nwere ike iji nna ukwu ndị a files maka ihe nrụtụ aka na-enweghị chịkọta nhazi ahụ files.

File Aha   factory_application1.pof factory_application1.rpd	Nkọwa Mmemme Quartus II file nke mejupụtara onyonyo ụlọ ọrụ na onyonyo ngwa 1, ka etinyere ya na CFM0 na CFM1 & CFM2 n'otu n'otu na s mbụ.tage.
factory_application2.pof factory_application2.rpd	• mmemme Quartus II file nke nwere foto ụlọ ọrụ na foto ngwa 2. • A ga-ewepụta foto ngwa 2 ma emechaa iji dochie onyonyo ngwa 1 n'oge nkwalite sistemụ dịpụrụ adịpụ, akpọrọ application_ image_2.rpd n'okpuru.
ngwa_image_1.rpd	Quartus II data mmemme akụrụngwa file nke nwere onyonyo ngwa 1 naanị.
ngwa_image_2.rpd	Quartus II data mmemme akụrụngwa file nke nwere onyonyo ngwa 2 naanị.
Nios_application.pof	• Mmemme file nke nwere Nios II processor software ngwa .hex file naanị. • Ka emebere ya ka ọ bụrụ flash QSPI dị na mpụga.
pfl.sf	• Quartus II .sf nwere PFL. • Emebere ya ka ọ bụrụ Flash QSPI na ngwa mmepe MAX 10 FPGA.

Nkọwapụta arụmọrụ nrụtụ aka

Nios II Gen2 Processor

• Nios II Gen2 Processor na ntinye aka nwere ọrụ ndị a:
• Onye isi ụgbọ ala nke na-eji Altera On-Chip Flash core na-ejikwa arụmọrụ interface niile gụnyere ịgụ, dee na ihichapụ.
• Na-enye algọridim na sọftụwia iji nata iyi ntanye mmemme site na kọmpụta nnabata wee kpalite nhazigharị site na isi nhazi Dual Configuration IP.
• Ịkwesịrị ịtọ vector nrụpụta nke nrụpụta otu a. Nke a bụ iji hụ na onye nrụpụta na-enweta koodu ngwa ziri ezi site na UFM ma ọ bụ flash QSPI mpụga.
• Mara: Ọ bụrụ na koodu ngwa Nios II buru ibu, Intel na-atụ aro ka ịchekwaa koodu ngwa na flash QSPI dị na mpụga. N'ime atụmatụ ntụaka a, vector nrụpụta na-atụ aka na flash QSPI mpụga ebe echekwara koodu Nios II ngwa.

Ozi metụtara

• Nios II Gen2 nkuzi mmepe akụrụngwa
• Na-enye ozi ndị ọzọ gbasara mmepe Nios II Gen2 Processor.

Altera On-Chip Flash IP Core

• Altera On-Chip Flash core na-arụ ọrụ dị ka interface maka nhazi Nios II ime ọgụgụ, dee ma ọ bụ hichapụ ọrụ na CFM na UFM. Altera On-Chip Flash core na-enye gị ohere ịnweta, hichapụ na melite CFM site na iji ntakịrị nhazi nhazi ọhụrụ. Ihe ndezi paramita IP Altera On-Chip Flash na-egosi oke adreesị agbagoro agbagoro maka ngalaba ebe nchekwa ọ bụla.

Ozi metụtara

• Altera On-Chip Flash IP Core
• Na-enye ozi ndị ọzọ gbasara Altera On-Chip Flash IP Core.

Altera Dual nhazi IP Core

• Ị nwere ike iji Altera Dual Configuration IP core iji nweta ngọngọ nkwalite sistemụ dịpụrụ adịpụ na ngwaọrụ MAX 10 FPGA. The Altera Dual Configuration IP core na-enye gị ohere ịkpalite nhazigharị ozugbo ebudatara onyonyo ọhụrụ a.

Ozi metụtara

• Altera Dual nhazi IP Core
• Na-enye ozi ndị ọzọ gbasara Altera Dual Configuration IP Core

Altera UART IP Core

• UART IP isi na-enye ohere nzikọrịta ozi nke iyi agwa agwa n'etiti sistemu agbakwunyere na MAX 10 FPGA na ngwaọrụ mpụga. Dị ka onye isi Avalon-MM, ihe nhazi Nios II na-ekwurịta okwu na UART IP core, nke bụ ohu Avalon-MM. A na-eme nkwurịta okwu a site n'ịgụ na njikwa ederede na ndekọ data.
• Isi ihe na-arụ ọrụ oge protocol RS-232 ma na-enye atụmatụ ndị a:
• ọnụego baud na-agbanwe agbanwe, nha nha, nkwụsị na ibe data
• Nhọrọ RTS/CTS akara njikwa mgbaba

Ozi metụtara

• UART isi
• Na-enye ozi ndị ọzọ gbasara UART Core.

Onye njikwa Quad SPI IP Core

• Generic Quad SPI Controller IP isi na-arụ ọrụ dị ka interface n'etiti MAX 10 FPGA, flash mpụga na ọkụ QSPI dị n'ime ụgbọ. Isi ihe na-enye ohere ịnweta ọkụ QSPI site na ịgụ, ide na ihichapụ arụmọrụ.
  Mgbe ngwa Nios II gbasaa site na ntuziaka ndị ọzọ, ihe file size nke hex file emepụtara site na ngwa Nios II ga-ebuwanye ibu. Na-agafe oke oke, UFM agaghị enwe ohere zuru oke iji chekwaa hex ngwa file. Iji dozie nke a, ịnwere ike iji flash QSPI mpụga dị na ngwa mmepe MAX 10 FPGA iji chekwaa hex ngwa. file.

Nhazi Ngwa Ngwa Nios II EDS

• Nrụtụ aka ahụ gụnyere koodu ngwa ngwa Nios II nke na-ejikwa nhazi sistemu nkwalite dịpụrụ adịpụ. Koodu ngwa ngwa ngwa Nios II na-azaghachi ọnụ ahịa ndị ọbịa site na UART site na ime ntuziaka akọwapụtara.

Na-emelite onyonyo ngwa ozugbo

• Mgbe ị bufere iyi ntakịrị mmemme file Iji Terminal Remote, emebere ngwa ngwanrọ Nios II mee ihe ndị a:

1. Tọọ Altera On-Chip Flash IP isi njikwa ndekọ iji chebe ngalaba CFM1 & 2.
2. Mee ọrụ mkpochapụ ngalaba na CFM1 na CFM2. Akụrụngwa a na-eme ntuli aka ndekọ ọkwa nke Altera On-Chip Flash IP core iji hụ na ihichapụ nke ọma.
3. Nweta 4 bytes nke iyi bit n'otu oge site na stdin. Enwere ike iji ntinye na mmepụta ọkọlọtọ nweta data ozugbo site na ọnụ ụlọ nnabata wee bipụta ya na ya. Enwere ike ịtọ ụdị ntinye ọkọlọtọ na nhọrọ mmepụta site na Editor BSP na ngwa Nios II Eclipse Build.
4. Weghachite usoro ntu maka byte ọ bụla.
   • Mara: N'ihi nhazi nke Altera On-Chip Flash IP Core, ọ bụla byte nke data kwesịrị ịgbanwe tupu ide ya na CFM.
5. Malite ide 4 bytes nke data n'otu oge n'ime CFM1 na CFM2. Usoro a na-aga n'ihu ruo mgbe ọgwụgwụ nke mmemme bit iyi.
6. Na-eme ntuli aka ndekọ ọkwa nke Altera On-Chip Flash IP iji hụ na ọrụ ide ihe na-aga nke ọma. Na-akpali ozi iji gosi na nnyefe ezuola.
   • Mara: Ọ bụrụ na ọrụ ide ada ada, ọnụ ala ga-akwụsị usoro izipu iyi bit wee mepụta ozi njehie.
7. Hazie ndekọ njikwa iji chekwa CFM1 na CFM2 iji gbochie ọrụ ide ihe ọ bụla achọghị.

Ozi metụtara

• pof Ọgbọ site na tọghatara mmemme Files na
• Na-enye ozi gbasara ịmepụta rpd files n'oge tọghatara mmemme files.

Na-akpalite nhazigharị anya

• Mgbe ịhọrọchara arụ ọrụ nhazigharị n'ime ụlọ ọrụ Remote Terminal, ngwa ngwa Nios II ga-eme ihe ndị a:

1. Nata iwu site na ntinye ọkọlọtọ.
2. Malite nhazigharị ahụ site na iji ọrụ ederede abụọ a:

• Dee 0x03 na adreesị nkwụsị nke 0x01 na Dual Configuration IP core. Ọrụ a na-edegharị pin CONFIG_SEL anụ ahụ wee tọọ onyonyo 1 ka onyonyo nhazi akpụkpọ ụkwụ na-esote.
• Dee 0x01 na adreesị nkwụsị nke 0x00 na Dual Configuration IP core. Ọrụ a na-akpalite nhazigharị na onyonyo ngwa na CFM1 na CFM2

Ntụgharị aka imewe ntụaka

Ịmepụta Mmemme Files

• Ị ga-emepụta mmemme ndị a files tupu inwe ike iji nkwalite sistemụ dịpụrụ adịpụ na ngwa mmepe MAX 10 FPGA:

Maka mmemme QSPI:

• sof-eji pfl.sof gụnyere na ntinye aka ma ọ bụ ị nwere ike ịhọrọ ịmepụta ihe dị iche iche .sof nwere nhazi PFL nke gị.
• pof-nhazi file emepụtara site na .hex wee hazie ya n'ime flash QSPI.
• Maka Nkwalite sistemu ime ime:
• pof-nhazi file emepụtara site na .sof wee tinye ya n'ime ọkụ ọkụ.
• rpd-nwere data maka flash ime nke gụnyere ntọala ICB, CFM0, CFM1 na UFM.
• map - jide adreesị maka ngalaba ebe nchekwa ọ bụla nke ntọala ICB, CFM0, CFM1 na UFM.

Na-emepụta files maka mmemme QSPI

Iji mepụta .pof file maka mmemme QSPI, mee usoro ndị a:

1. Mee Nios II Project ma mepụta HEX file.
   • Mara: Rụtụ aka na AN730: Nios II Processor Booting Methods Na ngwaọrụ MAX 10 maka ozi gbasara iwu Nios II oru na imepụta HEX file.
2. Na File menu, pịa tọghata Programming Files.
3. N'okpuru mmepụta mmemme file, họrọ Ihe mmemme File (.pof) na mmemme file ụdị ndepụta.
4. Na ndepụta ọnọdụ, họrọ 1-bit Passive Serial.
5. N'ime ndepụta ngwaọrụ nhazi, họrọ CFI_512Mb.
6. N'ime File igbe aha, kọwaa ya file aha maka mmemme file ị chọrọ imepụta.
7. N'ime ntinye files iji tọghata ndepụta, wepụ Nhọrọ na ahịrị data SOF. Pịa Tinye Hex Data na igbe okwu Tinye Hex Data pụtara. N'ime igbe Tinye Hex Data, họrọ adreesị zuru oke wee tinye .hex file emepụtara site na Nios II EDS Build Tools.
8. Mgbe emechara ntọala niile, pịa N'ịwa ka ịmepụta mmemme metụtara ya file.

Ozi metụtara

AN730: Nios II Processor Ụzọ nbio n'ime ngwaọrụ MAX 10 FPGA
Na-emepụta files maka Nwelite Sistemụ Ime Ime

Iji mepụta .pof, .map na .rpd files maka nkwalite sistemụ dịpụrụ adịpụ, mee usoro ndị a:

1. Weghachite Factory_image, application_image_1 na application_image_2, wee chịkọta atụmatụ atọ niile.
2. Mepụta abụọ .pof files kọwara na tebụl na-esonụ:
   • Mara: Rụtụ aka .pof Ọgbọ site na tọghatara mmemme Files maka nzọụkwụ na ịmepụta .pof files.
3. Mepee ngwa2.rpd site na iji ndezi hex ọ bụla.
4. Na hex nchịkọta akụkọ, họrọ ọnụọgụ abụọ data ngọngọ dabere na mmalite na njedebe nkwụsị site na-ezo aka na .map. file. Mmalite na njedebe maka ngwaọrụ 10M50 bụ 0x12000 na 0xB9FFF n'otu n'otu. Detuo ngọngọ a ka ọ bụrụ nke ọhụrụ file ma chekwaa ya na .rpd dị iche file. Nke a ọhụrụ .rpd file nwere naanị onyonyo ngwa 2.

pof Ọgbọ site na tọghatara mmemme Files

Iji tọghata .sof files ka .pof files, soro usoro ndị a:

1. Na File menu, pịa tọghata Programming Files.
2. N'okpuru mmepụta mmemme file, họrọ Ihe mmemme File (.pof) na mmemme file ụdị ndepụta.
3. N'ime ndepụta ọnọdụ, họrọ Nhazi ime.
4. N'ime File igbe aha, kọwaa ya file aha maka mmemme file ị chọrọ imepụta.
5. Ka ịmepụta map ebe nchekwa File (.map), gbanye Mepụta Map ebe nchekwa File (Mepụta mmepụta akpaaka_file.map). Map ahụ nwere adreesị CFM na UFM nwere ntọala ICB nke ị debere site na nhọrọ Ozi Nhọrọ/Boot.
6.  Iji mepụta Data Programming Raw (.rpd), gbanye Mepụta data nhazi RPD (Mepụta mmepụta_file_auto.rpd).
   Site n'enyemaka nke Map ebe nchekwa File, ị nwere ike ịchọpụta ngwa ngwa data maka ngọngọ ọrụ ọ bụla na .rpd file. Ị nwekwara ike wepụ data flash maka ngwaọrụ mmemme ndị ọzọ ma ọ bụ melite nhazi ma ọ bụ data onye ọrụ site na Altera On-Chip Flash IP.
7. Enwere ike ịgbakwunye .sof site na ntinye files iji tọghata ndepụta ma ị nwere ike ịgbakwunye abụọ .sof files.
   • Maka ebumnuche nkwalite sistemụ dịpụrụ adịpụ, ị nwere ike idowe data mbụ 0 na .pof, wee jiri .sof ọhụrụ dochie data ibe 1. file. Iji mee nke a, ịkwesịrị ịgbakwunye .pof file na ibe 0, mgbe ahụ
     tinye .sof ibe, wee tinye ọhụrụ .sof file ka
8. Mgbe emechara ntọala niile, pịa N'ịwa ka ịmepụta mmemme metụtara ya file.

Ịmepụta QSPI

Iji hazie koodu ngwa Nios II n'ime flash QSPI, mee usoro ndị a:

1. Na MAX 10 FPGA Development Kit, gbanwee MAX10_BYPASSn ka ọ bụrụ 0 ka ịgafe ngwaọrụ VTAP (MAX II) na bọọdụ.
2. Jikọọ eriri nbudata Intel FPGA (nke bụbu USB Blaster) na JTAG nkụnye eji isi mee.
3. Na mpio mmemme, pịa Ntọala ngwaike wee họrọ USB Blaster.
4. N'ime ndepụta ọnọdụ, họrọ JTAG.
5. Pịa bọtịnụ Chọpụta akpaaka na pane aka ekpe.
6. Họrọ ngwaọrụ a ga-ahazi, wee pịa Tinye File.
7. Họrọ pfl.sof.
8. Pịa Malite ka ịmalite mmemme.
9. Mgbe mmemme gachara nke ọma, na-agbanyụghị bọọdụ ahụ, pịa bọtịnụ Auto Detect na pane aka ekpe ọzọ. Ị ga-ahụ flash QSPI_512Mb na-apụta na mpio mmemme.
10. Họrọ ngwaọrụ QSPI, wee pịa Tinye File.
11. Họrọ .pof file ewepụtara na mbụ site na .hex file.
12. Pịa Malite ka ịmalite mmemme QSPI flash.

Iji ihe onyonyo izizi hazie FPGA site na iji JTAG

Ị ga-emepe ngwa1.pof n'ime FPGA dị ka ihe oyiyi mbụ ngwaọrụ. Iji hazie app1.pof n'ime FPGA, mee usoro ndị a:

1. Na mpio mmemme, pịa Ntọala ngwaike wee họrọ USB Blaster.
2. N'ime ndepụta ọnọdụ, họrọ JTAG.
3. Pịa bọtịnụ Chọpụta akpaaka na pane aka ekpe.
4. Họrọ ngwaọrụ a ga-ahazi, wee pịa Tinye File.
5. Họrọ ngwa1.pof.
6. Pịa Malite ka ịmalite mmemme.

Na-emelite onyonyo na ịkpalite nhazi site na iji UART

Iji hazie ngwa mmepe MAX10 FPGA gị, mee usoro ndị a:

1. Mara: Tupu ịmalite, hụ ihe ndị a:
   • pin CONFIG_SEL dị na bọọdụ ka atọrọ ka ọ bụrụ 0
   • ejikọrọ ọdụ ụgbọ mmiri UART gị na kọmputa gị
   • Mepee Remote Terminal.exe wee meghee ebe dị anya.
2. Pịa Settings na Serial port settings window ga-apụta.
3. Tọọ paramita nke ọdụ dịpụrụ adịpụ ka ọ dabara na ntọala UART ahọpụtara na Quartus II UART IP core. Mgbe emechara ntọala, pịa OK.
4. Pịa bọtịnụ nCONFIG na ngwa mmepe ma ọ bụ igodo-ime 1 na igbe ederede Zipụ, wee pịa Tinye.
   • Ndepụta nhọrọ ọrụ ga-apụta na njedebe, dị ka egosiri n'okpuru:
   • Mara: Ka ịhọrọ ọrụ, igodo na nọmba dị n'igbe ederede Zipụ, wee pịa Tinye.
5. Ka imelite onyonyo ngwa 1 na onyonyo ngwa 2, họrọ ọrụ 2. A ga-akpali gị itinye adreesị mmalite na njedebe nke CFM1 na CFM2.
   • Mara: Adreesị egosiri na maapụ file gụnyere ntọala ICB, CFM na UFM mana Altera On-Chip
   • Flash IP nwere ike ịnweta CFM na UFM naanị. N'ihi ya, enwere nkwụghachi adreesị n'etiti adreesị egosiri na maapụ file na windo paramita IP Altera On-Chip Flash.
6. Key na adreesị dabere na adreesị nke mpio paramita IP Altera On-Chip Flash akọwapụtara.
   • Nhicha ga-amalite na-akpaghị aka ka itinyere adreesị njedebe.
7. Mgbe emechara nke ọma, a ga-akpali gị ịbanye programming .rpd file maka foto ngwa 2.
   • Iji bulite onyonyo, pịa ZipụFile bọtịnụ, wee họrọ .rpd nwere onyonyo ngwa 2 naanị wee pịa Mepee.
   • Mara: Ewezuga onyonyo ngwa 2, ị nwere ike iji onyonyo ọhụrụ ọ bụla ịchọrọ imelite na ngwaọrụ ahụ.
   • Usoro mmelite ga-amalite ozugbo ma ị nwere ike nyochaa ọganihu site na ọnụ. Menu arụ ọrụ ga-eme ka emela ya ma ị nwere ike họrọ ọrụ ọzọ.
8. Iji kpalite nhazigharị, họrọ ọrụ 4. Ị nwere ike ịhụ omume LED nke na-egosi ihe oyiyi dị iche iche etinyere na ngwaọrụ ahụ.

Onyonyo	Ọnọdụ LED (dị ala na-arụ ọrụ)
Foto ụlọ ọrụ	01010
Foto ngwa 1	10101
Foto ngwa 2	01110

Akụkọ ngbanwe akwụkwọ

Ụbọchị	Ụdị	Mgbanwe
Febụwarị 2017	2017.02.21	Emegharịrị aha ya dị ka Intel.
June 2015	2015.06.15	Ntọhapụ mbụ.

Akwụkwọ / akụrụngwa

Ngwa intel MAX 10 FPGA karịrị UART nwere Nios II Processor [pdf] Ntuziaka onye ọrụ Ngwaọrụ MAX 10 FPGA karịrị UART nwere Nios II Nhazi, Ngwa MAX 10 FPGA, N'elu UART nwere Nios II Processor, Over UART, Nios II Processor UART, Nios II, Processor UART

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