intel MAX 10 FPGA Devices I luga ole UART ma le Nios II Processor

Fa'amatalaga o oloa

O le faʻataʻitaʻiga faʻataʻitaʻiga e maua ai se faʻaoga faigofie e faʻaogaina ai le faʻaogaina o faʻatulagaga mamao mamao i faiga faʻavae Nios II mo MAX 10 FPGA masini. O le UART interface e aofia i le MAX 10 FPGA Development Kit o loʻo faʻaogaina faʻatasi ma le Altera UART IP autu e tuʻuina atu ai le faʻaogaina mamao. MAX10 FPGA masini e maua ai le gafatia e teu ai i luga o ata faʻatulagaina e lua e faʻaleleia atili ai le faʻaleleia o le faʻaogaina o mea mamao.

Faapuupuuga

Faapuupuuga	Fa'amatalaga
Avalon-MM	Avalon Memory-Mapped Configuration Flash memory
CFM	Ata fa'aoga fa'aoga
ICB	Bit o le Fa'atulagaina o le amataga
MAP/.faafanua	Fa'afanua Manatu File
Nios II EDS	Nios II Embedded Design Suite Support
PFL	Fa'atutusa le Flash Loader IP autu
POF/.pof	Polokalama Mea File
QSPI	Fa'ata'ita'i fa'asologa fa'asologa fa'afafa
RPD/.rpd	Fa'amatalaga fa'apolokalame mata'utia
SBT	Software Fausia Meafaigaluega
SOF/.sof	SRAM Mea File
TATA	Universal asynchronous receiver/transmitter
UFM	Fa'aoga flash memory

Fa'atonuga o le Fa'aaogaina o Mea

Manaomia muamua

O le faʻaogaina o lenei faʻataʻitaʻiga mamanu e manaʻomia ai oe e maua le tulaga faʻaalia o le malamalama poʻo le poto masani i vaega nei:

Manaoga:

O lo'o taua i lalo mea e mana'omia mo masini ma polokalame mo le mamanu fa'asino:

Fa'ailoga Fa'asino Files

File Igoa	Fa'amatalaga
Factory_image	I le fa'atulagaina o ata fa'atusa fa'atusa, CFM1 ma le CFM2 ua tu'ufa'atasia i totonu o le CFM se tasi e teu ai.
app_image_1	Fuafuaga meafaigaluega a le Quartus II file e suitulaga i le app_image_2 i le taimi o le faʻaleleia o le polokalama mamao.
app_image_2	Nios II polokalama faakomepiuta talosaga code galue e pei o le pule mo le mamanu faiga fa'aleleia mamao.
Remote_system_upgrade.c
factory_application1.pof	Polokalama Quartus II file e aofia ai ata falegaosimea ma ata talosaga 1, e fa'apolokalame ile CFM0 ma le CFM1 & CFM2 fa'asologa i le amataga stage.
factory_application1.rpd
application_image_1.rpd
application_image_2.rpd
Nios_application.pof

O le faʻataʻitaʻiga faʻataʻitaʻiga e maua ai se faʻaoga faigofie e faʻaogaina ai le faʻaogaina o faʻatulagaga mamao mamao i faiga faʻavae Nios II mo MAX 10 FPGA masini. O le UART interface e aofia i le MAX 10 FPGA Development Kit o loʻo faʻaogaina faʻatasi ma le Altera UART IP autu e tuʻuina atu ai le faʻaogaina mamao.

Fa'amatalaga Fa'atatau

Fa'ailoga Fa'asino Files

Fa'afou le Fa'atonuga mamao ma MAX 10 FPGA Ovaview

Fa'atasi ai ma le fa'aleleia o le fa'aoga mamao, fa'alelei ma fa'alelei pusi mo masini FPGA e mafai ona fai mamao. I totonu o se siosiomaga faʻapipiʻiina, e manaʻomia le faʻafouina pea o le firmware i luga o ituaiga eseese o faʻasalalauga, e pei ole UART, Ethernet, ma le I2C. Afai o le faʻapipiʻi faʻapipiʻiina e aofia ai se FPGA, faʻafouga firmware e mafai ona aofia ai faʻafouga o le ata meafaigaluega i luga o le FPGA.
MAX10 FPGA masini e maua ai le gafatia e teu ai i luga o ata faʻatulagaina e lua e faʻaleleia atili ai le faʻaleleia o le faʻaogaina o mea mamao. O se tasi o ata o le a avea ma ata pito i tua o loʻo utaina pe a tupu se mea sese i le ata o loʻo iai nei.

Faapuupuuga

Laulau 1: Lisi o Fa'apuupuuga

Fa'apuupuuga Fa'amatalaga
Avalon-MM	Avalon Memory-Mapped
CFM	Fa'atonuga manatua flash
GUI	Ata fa'aoga fa'aoga
ICB	Bit o le Fa'atulagaina o le amataga
MAP/.faafanua	Fa'afanua Manatu File
Nios II EDS	Nios II Embedded Design Suite Support
PFL	Fa'atutusa le Flash Loader IP autu
POF/.pof	Polokalama Mea File

• Intel Corporation. Ua taofia aia tatau uma. Intel, le Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus ma Stratix upu ma logos o faʻailoga a le Intel Corporation poʻo ana lala i le US ma/poʻo isi atunuu. E fa'amaonia e Intel le fa'atinoina o ana oloa FPGA ma semiconductor i fa'amatalaga o lo'o iai nei e tusa ai ma le fa'atonuga masani a Intel, ae fa'asaoina le aia tatau e fai ai suiga i so'o se oloa ma auaunaga i so'o se taimi e aunoa ma se fa'aaliga. E leai se tiute po'o se noataga e afua mai i le talosaga po'o le fa'aogaina o so'o se fa'amatalaga, oloa, po'o se auaunaga o lo'o fa'amatalaina i i'i se'i vagana ua malilie i ai i se faiga tusitusia e Intel. Ua fautuaina tagata fa'atau Intel ina ia maua le fa'amatalaga lata mai o fa'amatalaga masini a'o le'i fa'alagolago i so'o se fa'amatalaga fa'asalalau ma a'o le'i tu'uina atu oka mo oloa po'o tautua.
• O isi igoa ma fa'ailoga e mafai ona ta'ua o se meatotino a isi.

Manaomia muamua

Faapuupuuga QSPI	Fa'amatalaga Fa'ata'ita'i fa'asologa fa'asologa fa'afafa
RPD/.rpd	Fa'amatalaga fa'apolokalame mata'utia
SBT	Software Fausia Meafaigaluega
SOF/.sof	SRAM Mea File
UART	Universal asynchronous receiver/transmitter
UFM	Fa'aoga flash memory

Manaomia muamua

• O le faʻaogaina o lenei faʻataʻitaʻiga mamanu e manaʻomia ai oe e maua le tulaga faʻaalia o le malamalama poʻo le poto masani i vaega nei:
• Malamalama galue o faiga Nios II ma meafaigaluega e fausia ai. O nei faiga ma meafaigaluega e aofia ai le polokalama Quartus® II, Qsys, ma le Nios II EDS.
• Malamalama i auala ma meafaigaluega faʻapipiʻi Intel FPGA, e pei o le MAX 10 FPGA faʻapipiʻi totonu, faʻaoga mamao faʻaleleia faiga ma PFL.

Manaoga

• O lo'o taua i lalo mea e mana'omia mo masini ma polokalame mo le mamanu fa'asino:
• MAX 10 FPGA atina'e pusa
• Quartus II version 15.0 ma Nios II EDS
• O se komepiuta o lo'o i ai se aveta'avale UART galue ma se atina'e
• Soo se binary/hexadecimal file faatonu

Fa'ailoga Fa'asino Files

Laulau 2: Fuafuaga Files Fa'aaofia i le Fa'asinoga Fa'asinomaga

File Igoa Factory_image	Fa'amatalaga • Fuafuaga meafaigaluega a le Quartus II file e teu i le CFM0. • O le ata fa'afo'i/fa'ailoga falegaosi e fa'aaoga pe a tupu le mea sese i le fa'aoga ata fa'apipi'i.
app_image_1	• Fuafuaga meafaigaluega a le Quartus II file ia teuina i le CFM1 ma le CFM2.(1) • O le ata muamua o le talosaga na utaina i le masini.

1. I le fa'atulagaina o ata fa'aopoopo fa'alua, o le CFM1 ma le CFM2 o lo'o tu'ufa'atasia i le teuina o le CFM e tasi.

File Igoa app_image_2	Fa'amatalaga Fuafuaga meafaigaluega a le Quartus II file e suitulaga i le app_image_2 i le taimi o le faʻaleleia o le polokalama mamao.
Fa'afou_system_mamao.c	Nios II polokalama faakomepiuta talosaga code galue e fai ma pule mo le mamanu faiga faaleleia mamao.
Terminal.exe mamao	• Fa'atinoina file ma se GUI. • Fa'atino e fai ma fa'au'uga mo le talimalo e fegalegaleai ai ma MAX 10 FPGA ati a'e pusa. • Auina atu fa'amatalaga polokalame e ala ile UART. • O lo'o iai le fa'ailoga fa'apogai mo lenei nofoaga.

Laulau 3: Matai Files Fa'aaofia i le Fa'asinoga Fa'asinomaga

E mafai ona e faʻaogaina nei matai files mo le mamanu faasinomaga e aunoa ma le tuufaatasia o le mamanu files.

File Igoa   factory_application1.pof factory_application1.rpd	Fa'amatalaga Polokalama Quartus II file e aofia ai ata falegaosimea ma ata fa'aoga 1, e fa'apolokalameina i le CFM0 ma le CFM1 & CFM2 fa'asologa i le amataga s.tage.
factory_application2.pof factory_application2.rpd	• Polokalama Quartus II file e aofia ai ata falegaosimea ma ata talosaga 2. • O le ata o le talosaga 2 o le a aveesea mulimuli ane e sui ai le ata o le talosaga 1 i le taimi o le faʻaleleia mamao o le polokalama, faʻaigoaina application_ image_2.rpd i lalo.
application_image_1.rpd	Quartus II fa'amaumauga mata'utia polokalame file o lo'o iai na'o le ata talosaga 1.
application_image_2.rpd	Quartus II fa'amaumauga mata'utia polokalame file o lo'o i ai na'o le ata talosaga 2.
Nios_application.pof	• Polokalama file e aofia ai Nios II processor software applica-tion .hex file na'o. • Ia fa'apolokalame i fafo QSPI flash.
pfl.sof	• Kuatus II .sof e iai le PFL. • Polokalama ile QSPI flash ile MAX 10 FPGA Development kit.

Fa'amatalaga Fa'atino Fuafuaga Fa'amatalaga

Nios II Gen2 Processor

• O le Nios II Gen2 Processor i le mamanu faʻasino o loʻo i ai galuega nei:
• Ose matai pasi e fa'atautaia uma fa'agaioiga fa'atasi ma le Altera On-Chip Flash IP autu e aofia ai le faitau, tusi, ma tape.
• Tuuina atu se algorithm i polokalama faakomepiuta e maua ai le polokalame bit stream mai se komepiuta talimalo ma faʻaoso le toe fetuunaiga e ala i le Dual Configuration IP core.
• E tatau ona e setiina le reset vector o le processor e tusa ai. O le mea lea e faʻamautinoa ai e faʻapipiʻi e le processor le code talosaga saʻo mai UFM poʻo fafo QSPI flash.
• Fa'aaliga: Afai e tele le numera o le talosaga a le Nios II, e fautuaina e Intel e te teuina le code talosaga i le QSPI flash fafo. I lenei faʻataʻitaʻiga, o le reset vector o loʻo faʻasino i le QSPI flash i fafo o loʻo teuina ai le code talosaga Nios II.

Fa'amatalaga Fa'atatau

• Nios II Gen2 Atina'e Meafaigaluega A'oa'oga
• Tuuina atu nisi faʻamatalaga e uiga i le atinaʻeina o le Nios II Gen2 Processor.

Altera On-Chip Flash IP Core

• O le Altera On-Chip Flash IP autu o loʻo galue o se atinaʻe mo le Nios II processor e fai se faitau, tusi pe tape le gaioiga i le CFM ma le UFM. Ole Altera On-Chip Flash IP core e maua ai le avanoa e te maua ai, tape ma fa'afou le CFM i se fa'asologa fou. O le Altera On-Chip Flash IP fa'asologa o fa'amaumauga o lo'o fa'aalia ai se fa'asologa o tuatusi mo vaega ta'itasi e manatua.

Fa'amatalaga Fa'atatau

• Altera On-Chip Flash IP Core
• Tuuina atu nisi fa'amatalaga e uiga i le Altera On-Chip Flash IP Core.

Altera Dual Configuration IP Core

• E mafai ona e fa'aogaina le Altera Dual Configuration IP core e fa'aoga ai le poloka fa'aleleia mamao mamao i masini MAX 10 FPGA. O le Altera Dual Configuration IP core e mafai ai ona e fa'aosoina le toe fetuutuunai pe a uma ona sii mai le ata fou.

Fa'amatalaga Fa'atatau

• Altera Dual Configuration IP Core
• Tuuina atu nisi fa'amatalaga e uiga i le Altera Dual Configuration IP Core

Altera UART IP Core

• O le UART IP autu e mafai ai ona fesoʻotaʻi faʻasalalauga faʻasalalau i le va o se faiga faʻapipiʻi i MAX 10 FPGA ma se masini fafo. I le avea ai o se Avalon-MM matai, o le Nios II processor e fesoʻotaʻi ma le UART IP core, o se pologa Avalon-MM. O lenei feso'ota'iga e faia i le faitau ma le tusitusi fa'atonutonu ma fa'amaumauga fa'amaumauga.
• O le autu o loʻo faʻatinoina le RS-232 taimi faʻatulagaina ma tuʻuina atu vaega nei:
• fetuutuunai fua pa'u, parity, taofi, ma fasi faamatalaga
• fa'ailoga RTS/CTS fa'atonuga ole tafega

Fa'amatalaga Fa'atatau

• UART Autu
• Tuuina atu nisi fa'amatalaga e uiga i le UART Core.

Generic Quad SPI Pule IP Core

• Ole Generic Quad SPI Controller IP autu o lo'o galue o se feso'ota'iga i le va o le MAX 10 FPGA, le moli i fafo ma le moli QSPI i luga ole laupapa. O le autu e maua ai le avanoa i le QSPI flash e ala i le faitau, tusi ma tape galuega.
  A faʻalauteleina le talosaga a le Nios II ma nisi faʻatonuga, o le file tele o le hex file gaosia mai Nios II talosaga o le a sili atu. I tua atu o se tapula'a fa'apitoa, o le UFM o le a le lava se avanoa e teu ai le talosaga hex file. Ina ia foia lenei mea, e mafai ona e faʻaogaina le QSPI flash fafo o loʻo maua ile MAX 10 FPGA Development kit e teu ai le talosaga hex file.

Le Nios II EDS Software Application Design

• O le mamanu fa'asinomaga e aofia ai le Nios II software application code lea e pulea ai le fa'aleleia mamao o le fa'aogaina o le fa'aogaina o le polokalama. O le Nios II polokalama faakomepiuta code code tali i le nofoaga talimalo e ala i le UART e ala i le faatinoina o faatonuga patino.

Fa'afouina Ata o Talosaga Mamao

• A mae'a ona e fa'asalalauina se fa'asologa o polokalame file i le faʻaaogaina o le Terminal Mamao, o le Nios II polokalama faakomepiuta ua mamanuina e faia mea nei:

1. Seti le Altera On-Chip Flash IP core Control Register e aveese ai le puipuiga o le vaega CFM1 & 2.
2. Fa'atino galuega tape vaega ile CFM1 ma le CFM2. E su'esu'e e le polokalame le resitala tulaga o le Altera On-Chip Flash IP core ina ia mautinoa ua mae'a solo lelei.
3. Maua le 4 paita ole vaitafe i le taimi mai le stdin. E mafai ona fa'aogaina fa'aoga masani ma mea e maua e maua sa'o mai ai fa'amaumauga mai le fale talimalo ma lolomi ai i luga. E mafai ona fa'atulaga ituaiga o fa'aoga masani ma filifiliga fa'atino e ala ile BSP Editor ile Nios II Eclipse Build tool.
4. Fa'aliliuina le fa'atonuga mo paita ta'itasi.
   • Fa'aaliga: Ona o le fa'atulagaina o le Altera On-Chip Flash IP Core, e mana'omia ona toe fesuia'i paita uma o fa'amaumauga a'o le'i tusia i le CFM.
5. Amata ona tusi le 4 paita o faʻamaumauga i le taimi e tasi i le CFM1 ma le CFM2. E fa'aauau pea lenei fa'agasologa se'ia o'o i le fa'ai'uga o le polokalame bit stream.
6. Palota le tusi resitala o le Altera On-Chip Flash IP ina ia mautinoa le manuia o le tusitusi. Uunaia se fe'au e ta'u mai ai ua mae'a le fa'asalalauga.
   • Fa'aaliga: Afai e le manuia le galuega tusitusi, o le a taofia e le laina le faagasologa o le auina atu o le vaitafe ma maua ai se savali sese.
7. Seti le Resitala Fa'atonu e toe puipui ai le CFM1 ma le CFM2 e puipuia ai so'o se galuega tusitusi e le mana'omia.

Fa'amatalaga Fa'atatau

• pof Tupulaga e ala i Polokalame Faaliliu Fileatali'i
• Tuuina atu faʻamatalaga e uiga i le fatuina o rpd files i le taimi o polokalame liliu mai files.

Fa'aosoina le Fa'atonuga mamao

• A maeʻa ona e filifilia le faʻaosoina o le faʻaogaina o le faʻatonuga i le fale talimalo Remote Terminal, o le Nios II polokalama faakomepiuta o le a faia mea nei:

1. Maua le fa'atonuga mai fa'aoga masani.
2. Amata le toe fetuutuunaiga i gaioiga tusitusi e lua nei:

• Tusi le 0x03 ile tuatusi offset ole 0x01 ile Dual Configuration IP core. O lenei fa'agaioiga e fa'asolo ai le pine CONFIG_SEL fa'aletino ma tu'u le Ata 1 e fai ma ata fa'aopoopo fa'a ta'a.
• Tusi le 0x01 i le tuatusi offset o le 0x00 ile Dual Configuration IP core. O lenei fa'agaioiga e fa'aoso ai le toe fa'atulagaina i ata fa'atatau ile CFM1 ma le CFM2

Fa'asinomaga Design Walkthrough

Fausia Polokalama Files

• E tatau ona e fatuina polokalame nei files a'o le'i mafai ona fa'aogaina le fa'aleleia mamao o le polokalama ile MAX 10 FPGA Development kit:

Mo Polokalame QSPI:

• sof—fa'aoga o le pfl.sof o loʻo aofia i totonu o le mamanu faʻasino pe e mafai ona e filifili e fai se .sof ese e iai lau lava mamanu PFL
• pof—faatulagaina file fa'atupu mai le .hex ma fa'apolokalame i le QSPI flash.
• Mo Fa'afou le fa'aogaina mamao:
• pof—faatulagaina file fa'atupu mai se .sof ma fa'apolokalame i totonu o le moli i totonu.
• rpd—o iai o faʻamatalaga mo moli i totonu e aofia ai faʻatulagaga ICB, CFM0, CFM1 ma UFM.
• faafanua—uuina le tuatusi mo vaega ta'itasi manatua o fa'atulagaga ICB, CFM0, CFM1 ma UFM.

Fa'atupuina files mo Polokalama QSPI

Ina ia maua le .pof file mo polokalame QSPI, fai laasaga nei:

1. Fausia le Nios II Poloketi ma fa'atupuina le HEX file.
   • Fa'aaliga: Vaʻai ile AN730: Nios II Processor Booting Methods I MAX 10 Devices mo faʻamatalaga e uiga i le fausiaina o le Nios II poloketi ma le gaosia o le HEX file.
2. I luga o le File menu, kiliki Faaliliu Polokalama Files.
3. I lalo o le polokalame Output file, filifili Polokalama Mea File (.pof) i le Polokalama file ituaiga lisi.
4. I le lisi o Faiga, filifili le 1-bit Passive Serial.
5. I le lisi o masini Configuration, filifili CFI_512Mb.
6. I le File igoa pusa, fa'amaonia le file igoa mo le polokalame file e te manaʻo e fai.
7. I le Ulufale files e faaliliu lisi, aveese le Filifiliga ma SOF laina faʻamaumauga. Kiliki Fa'aopoopo Fa'amatalaga Hex ma fa'aalia se pusa fa'amatalaga Fa'aopoopo Hex Data. I le Add Hex Data pusa, filifili Absolute addressing ma faaofi le .hex file gaosia mai Nios II EDS Build Tools.
8. A uma ona seti uma tulaga, kiliki Fausia e faʻatupu polokalame e fesoʻotaʻi file.

Fa'amatalaga Fa'atatau

AN730: Nios II Processor Booting Methods I MAX 10 FPGA Devices
Fa'atupuina files mo Fa'alelei Faiga Fa'atonu

Ina ia gaosia le .pof, .map ma le .rpd files mo le faʻaleleia o le polokalama mamao, fai laasaga nei:

1. Toe faʻafoʻi le Factory_image, application_image_1 ma le application_image_2, ma faʻapipiʻi uma mamanu e tolu.
2. Fausia .pof se lua files o loʻo faʻamatalaina i le laulau o loʻo i lalo:
   • Fa'aaliga: Fa'asino i le .pof Generation e ala i le Fa'aliliuina Polokalama Files mo laasaga i le fausiaina o .pof files.
3. Tatala le app2.rpd fa'aaoga so'o se fa'atonu hex.
4. I le faatonu hex, filifili le poloka faʻamaumauga binary e faʻavae i luga o le amataga ma le faʻaiʻuga offset e ala i le faasino i le .map file. O le amataga ma le fa'ai'uga offset mo le masini 10M50 o le 0x12000 ma le 0xB9FFF fa'asologa. Kopi le poloka lea i se mea fou file ma sefe i se .rpd ese file. O lenei .rpd fou file o lo'o i ai na'o le ata talosaga 2.

pof Tupulaga e ala i Polokalame Faaliliu Files

E faaliliu .sof files ia .pof files, mulimuli i laasaga nei:

1. I luga o le File menu, kiliki Faaliliu Polokalama Files.
2. I lalo o le polokalame Output file, filifili Polokalama Mea File (.pof) i le Polokalama file ituaiga lisi.
3. I le Faiga lisi, filifili Faiga Fa'alotoifale.
4. I le File igoa pusa, fa'amaonia le file igoa mo le polokalame file e te manaʻo e fai.
5. Le fa'atupuina o se Fa'afanua Fa'amanatu File (.map), ki le Fausiaina o Faafanua File (Otometi le fa'atupuina o galuega_file.faafanua). O le .map o loʻo i ai le tuatusi o le CFM ma le UFM faʻatasi ai ma le faʻatulagaina o le ICB na e setiina e ala i le filifiliga Option/Boot Info.
6.  Ina ia maua se Raw Programming Data (.rpd), ki le Fausia config data RPD (Fa'atupu galuega_file_auto.rpd).
   Fa'atasi ai ma le fesoasoani a le Fa'afanua Fa'amanatu File, e faigofie ona e iloa faʻamatalaga mo poloka taʻitasi taʻitasi i le .rpd file. E mafai fo'i ona e su'eina fa'amatalaga moli mo meafaigaluega fa'apolokalame a isi vaega po'o le fa'afouina o fa'amaumauga po'o fa'amatalaga fa'aoga e ala i le Altera On-Chip Flash IP.
7. O le .sof e mafai ona fa'aopoopo e ala ile Input files e faaliliu le lisi ma e mafai ona e faaopoopo atu i le lua .sof files.
   • Mo faamoemoega fa'aleleia faiga mamao, e mafai ona e taofia le uluai itulau 0 fa'amaumauga i le .pof, ma sui le itulau 1 fa'amaumauga i le .sof fou. file. Ina ia faia lenei mea, e tatau ona e faaopoopo le .pof file i le itulau 0, ona
     fa'aopoopo le .sof itulau, ona fa'aopoopo lea o le .sof fou file ia
8. A uma ona seti uma tulaga, kiliki Fausia e faʻatupu polokalame e fesoʻotaʻi file.

Polokalama le QSPI

Ina ia faʻapolokalame le code talosaga a le Nios II i le QSPI flash, fai laasaga nei:

1. I luga o le MAX 10 FPGA Development Kit, sui le MAX10_BYPASSn i le 0 e pasi ai le masini VTAP (MAX II) i luga ole laupapa.
2. Faʻafesoʻotaʻi le Intel FPGA Download Cable (muamua USB Blaster) i le JTAG ulutala.
3. I le faʻamalama o le Polokalama, kiliki Faʻatonu Setup ma filifili USB Blaster.
4. I le lisi o auala, filifili JTAG.
5. Kiliki Auto Detect button i le itu tauagavale.
6. Filifili le masini e fa'apolokalameina, ma kiliki le Add File.
7. Filifili le pfl.sof.
8. Kiliki Amata e amata polokalame.
9. A uma ona manuia polokalame, e aunoa ma le tapeina o le laupapa, toe kiliki le Auto Detect button i le itu tauagavale. O le a e va'ai i se moli QSPI_512Mb o loʻo faʻaalia i le faamalama o le polokalame.
10. Filifili le masini QSPI, ma kiliki Add File.
11. Filifili le .pof file na gaosia muamua mai le .hex file.
12. Kiliki Amata e amata fa'apolokalame le QSPI flash.

Polokalama le FPGA ma le Ata Muamua e faʻaaoga ai le JTAG

E tatau ona e polokalame le app1.pof i totonu o le FPGA e pei o le ata muamua o le masini. Ina ia polokalame le app1.pof i le FPGA, fai laasaga nei:

1. I le faʻamalama o le Polokalama, kiliki Faʻatonu Setup ma filifili USB Blaster.
2. I le lisi o auala, filifili JTAG.
3. Kiliki Auto Detect button i le itu tauagavale.
4. Filifili le masini e fa'apolokalameina, ma kiliki le Add File.
5. Filifili le app1.pof.
6. Kiliki Amata e amata polokalame.

Fa'afou Ata ma Fa'aosoina Toe Fa'atonu e fa'aaoga ai le UART

Ina ia faʻapipiʻi mamao lau pusa atinaʻe MAX10 FPGA, fai laasaga nei:

1. Fa'aaliga: Ae e te leʻi amataina, ia mautinoa mea nei:
   • o le CONFIG_SEL pine i luga o le laupapa ua seti i le 0
   • ua feso'ota'i le uafu UART a lau laupapa i lau komepiuta
   • Tatala Remote Terminal.exe ma tatala le fa'aoga mamao mamao.
2. Kiliki Fa'atonu ma fa'amalama fa'atūlaga tau Serial o le a aliali mai.
3. Seti fa'amaufa'ailoga mamao e fetaui ma fa'atulagaga UART ua filifilia ile Quartus II UART IP core. A uma le seti, kiliki OK.
4. Oomi le faamau nCONFIG i luga o le atigipusa atinaʻe poʻo le ki-i le 1 i le Auina atu le atigipusa, ona kiliki ai lea o le Enter.
   • O se lisi o filifiliga fa'agaioiga o le a fa'aalia i luga o le laina, e pei ona fa'aalia i lalo:
   • Fa'aaliga: Ina ia filifili se gaioiga, ki i totonu le numera i le Auina atu o tusitusiga pusa, ona kiliki ai lea o le Enter.
5. Ina ia fa'afou le ata talosaga 1 ma le ata talosaga 2, filifili le gaioiga 2. O le a fa'aosofia oe e fa'aofi le tuatusi amata ma le fa'ai'uga o le CFM1 ma le CFM2.
   • Fa'aaliga: Le tuatusi o lo'o fa'aalia i le fa'afanua file e aofia ai tulaga ICB, CFM ma UFM ae o le Altera On-Chip
   • Flash IP e mafai ona maua CFM ma UFM na'o. O le mea lea, o loʻo i ai se tuatusi faʻapipiʻi i le va o le tuatusi o loʻo faʻaalia i le faafanua file ma Altera On-Chip Flash IP fa'amalama fa'amalama.
6. Fa'amau le tuatusi e fa'atatau i le tuatusi o lo'o fa'ailoa mai e le Altera On-Chip Flash IP fa'amalama fa'amalama.
   • E otometi lava ona amata tape pe a uma ona e ulufale i le tuatusi pito.
7. A maeʻa ona soloia manuia, o le a faʻamalosia oe e ulufale i le polokalame .rpd file mo ata talosaga 2.
   • Ina ia lafoina ata, kiliki AuinaFile faamau, ona filifili lea o le .rpd o loo i ai le ata talosaga 2 na o ma kiliki Tatala.
   • Fa'aaliga: E ese mai i le ata talosaga 2, e mafai ona e faʻaogaina soʻo se ata fou e te manaʻo e faʻafouina i totonu o le masini.
   • O le a amata sa'o le faiga fa'afou ma e mafai ona e mata'ituina le alualu i luma e ala i le fa'amau. Ole fa'agaioiga lisi o le a fa'aoso Fa'ai ma e mafai nei ona e filifili le isi gaioiga.
8. Ina ia faʻaosoina le toe faʻatulagaina, filifili le gaioiga 4. E mafai ona e vaʻaia le amio a le LED e faʻaalia ai ata eseese o loʻo utaina i totonu o le masini.

Ata	Tulaga LED (Fa'agaoioi maualalo)
Ata Falegaosi	01010
Fa'aoga Ata 1	10101
Fa'aoga Ata 2	01110

Talafaasolopito Toe Iloiloga o Pepa

Aso	Fa'aliliuga	Suiga
Fepuari 2017	2017.02.21	Toe fa'ailogaina o le Intel.
Iuni 2015	2015.06.15	Fa'asalalauga muamua.

Pepa / Punaoa

intel MAX 10 FPGA Devices I luga ole UART ma le Nios II Processor [pdf] Taiala mo Tagata Fa'aoga MAX 10 FPGA Devices I luga ole UART ma le Nios II Processor, MAX 10 FPGA Devices, I luga ole UART ma le Nios II Processor, Over UART, Nios II Processor UART, Nios II, Processor UART

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