intel MAX 10 FPGA Na'urorin Sama da UART tare da Nios II Processor

Bayanin samfur

Ƙirar ƙira tana ba da aikace-aikace mai sauƙi wanda ke aiwatar da mahimman abubuwan daidaitawa na nesa a cikin tsarin tushen Nios II don na'urorin MAX 10 FPGA. Ana amfani da fasahar UART da aka haɗa a cikin MAX 10 FPGA Development Kit tare da Altera UART IP core don samar da aikin daidaitawa mai nisa. Na'urorin MAX10 FPGA suna ba da damar adana hotuna har guda biyu waɗanda ke ƙara haɓaka fasalin haɓaka tsarin nesa.

Taqaitaccen bayani

Gajarta	Bayani
Avalon-MM	Avalon ƙwaƙwalwar ajiya
Farashin CFM	Ƙwararren mai amfani da hoto
ICB	Ƙaddamarwar Kanfigareshan Bit
MAP/. taswira	Taswirar ƙwaƙwalwa File
Nios II EDS	Taimakon Nios II Cikakkiyar Design Suite
PFL	Parallel Flash Loader IP core
POF/.pof	Abubuwan Shirye-shirye File
QSPI	Quad serial peripheral interface
RPD/.rpd	Raw shirye-shiryen bayanai
SBT	Kayan Aikin Gina Software
SOF / .sof	Abun SRAM File
CART	Mai karɓa/mai watsawa asynchronous na duniya
UFM	Mai amfani flash memory

Umarnin Amfani da samfur

Abubuwan da ake bukata

Aiwatar da wannan ƙirar ƙira tana buƙatar ku sami matakin ilimi da aka nuna ko gogewa a cikin fagage masu zuwa:

Bukatun:

Masu zuwa sune buƙatun hardware da software don ƙirar ƙira:

Tsarin Magana Files

File Suna	Bayani
Hoton masana'anta	A cikin yanayin sanyi na hotuna biyu, CFM1 da CFM2 an haɗa su cikin ma'ajiyar CFM guda ɗaya.
app_image_1	Tsarin kayan aikin Quartus II file wanda ke maye gurbin app_image_2 yayin haɓaka tsarin nesa.
app_image_2	Lambar aikace-aikacen software na Nios II yana aiki azaman mai sarrafawa don da m haɓaka tsarin zane.
Remote_system_upgrade.c
factory_application1.pof	Quartus II shirye-shirye file wanda ya ƙunshi hoton masana'anta da Hoton aikace-aikacen 1, wanda za a tsara shi zuwa CFM0 da CFM1 & CFM2 bi da bi a farkon stage.
factory_application1.rpd
aikace-aikace_image_1.rpd
aikace-aikace_image_2.rpd
Nios_application.pof

Ƙirar ƙira tana ba da aikace-aikace mai sauƙi wanda ke aiwatar da mahimman abubuwan daidaitawa na nesa a cikin tsarin tushen Nios II don na'urorin MAX 10 FPGA. Ana amfani da fasahar UART da aka haɗa a cikin MAX 10 FPGA Development Kit tare da Altera UART IP core don samar da aikin daidaitawa mai nisa.

Bayanai masu alaƙa

Tsarin Magana Files

Haɓaka Tsarin nesa tare da MAX 10 FPGA Overview

Tare da fasalin haɓaka tsarin nesa, haɓakawa da gyaran kwaro don na'urorin FPGA ana iya yin su daga nesa. A cikin yanayin tsarin da aka haɗa, firmware yana buƙatar sabuntawa akai-akai akan nau'in yarjejeniya daban-daban, kamar UART, Ethernet, da I2C. Lokacin da tsarin da aka haɗa ya haɗa da FPGA, sabunta firmware na iya haɗawa da ɗaukakawar hoton kayan aikin akan FPGA.
Na'urorin MAX10 FPGA suna ba da damar adana hotuna har guda biyu waɗanda ke ƙara haɓaka fasalin haɓaka tsarin nesa. Ɗayan hotunan zai zama hoton baya wanda aka loda idan kuskure ya faru a hoton na yanzu.

Taqaitaccen bayani

Tebur 1: Jerin Gajartawa

Bayanin Taƙaice
Avalon-MM	Avalon Memory-Mapped
Farashin CFM	Ƙwaƙwalwar ƙwaƙwalwar ajiyar saiti
GUI	Ƙwararren mai amfani da hoto
ICB	Ƙaddamarwar Kanfigareshan Bit
MAP/. taswira	Taswirar ƙwaƙwalwa File
Nios II EDS	Taimakon Nios II Cikakkiyar Design Suite
PFL	Parallel Flash Loader IP core
POF/.pof	Abubuwan Shirye-shirye File

• Kamfanin Intel. An kiyaye duk haƙƙoƙi. Intel, tambarin Intel, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus da Stratix kalmomi da tambura alamun kasuwanci ne na Intel Corporation ko rassan sa a Amurka da/ko wasu ƙasashe. Intel yana ba da garantin aiwatar da samfuran FPGA da semiconductor zuwa ƙayyadaddun bayanai na yanzu daidai da daidaitaccen garanti na Intel, amma yana da haƙƙin yin canje-canje ga kowane samfuri da sabis a kowane lokaci ba tare da sanarwa ba. Intel ba ya ɗaukar wani nauyi ko alhaki da ya taso daga aikace-aikacen ko amfani da kowane bayani, samfur, ko sabis da aka kwatanta a nan sai dai kamar yadda Intel ya yarda da shi a rubuce. An shawarci abokan cinikin Intel su sami sabon sigar ƙayyadaddun na'urar kafin su dogara ga kowane bayanan da aka buga kuma kafin sanya oda don samfur ko ayyuka.
• Ana iya da'awar wasu sunaye da alamun a matsayin mallakin wasu.

Abubuwan da ake bukata

Gajarta QSPI	Bayani Quad serial peripheral interface
RPD/.rpd	Raw shirye-shiryen bayanai
SBT	Kayan Aikin Gina Software
SOF / .sof	Abun SRAM File
UART	Mai karɓa/mai watsawa asynchronous na duniya
UFM	Mai amfani flash memory

Abubuwan da ake bukata

• Aiwatar da wannan ƙirar ƙira tana buƙatar ku sami matakin ilimi da aka nuna ko gogewa a cikin fagage masu zuwa:
• Ilimin aiki na tsarin Nios II da kayan aikin gina su. Waɗannan tsarin da kayan aikin sun haɗa da software na Quartus® II, Qsys, da Nios II EDS.
• Sanin hanyoyin daidaitawa da kayan aikin Intel FPGA, kamar daidaitawar ciki na MAX 10 FPGA, fasalin haɓaka tsarin nesa da PFL.

Abubuwan bukatu

• Masu zuwa sune buƙatun hardware da software don ƙirar ƙira:
• MAX 10 FPGA kayan haɓakawa
• Quartus II sigar 15.0 tare da Nios II EDS
• Kwamfuta tare da direban UART mai aiki da dubawa
• Kowane binary/hexadecimal file edita

Tsarin Magana Files

Tebur 2: Zane Files Haɗe a cikin Tsarin Magana

File Suna Hoton masana'anta	Bayani • Tsarin kayan aikin Quartus II file Rahoton da aka ƙayyade na CFM0. • Hoton koma baya/hoton masana'anta da za a yi amfani da shi lokacin da kuskure ya faru a zazzage hoton aikace-aikacen.
app_image_1	• Tsarin kayan aikin Quartus II file za a adana a cikin CFM1 da CFM2.(1) • Hoton aikace-aikacen farko da aka ɗora a cikin na'urar.

1. A cikin yanayin sanyi na hotuna biyu, CFM1 da CFM2 an haɗa su zuwa ma'ajin CFM guda ɗaya.

File Suna app_image_2	Bayani Tsarin kayan aikin Quartus II file wanda ke maye gurbin app_image_2 yayin haɓaka tsarin nesa.
Remote_system_ haɓakawa.c	Lambar aikace-aikacen software na Nios II yana aiki azaman mai sarrafawa don ƙirar tsarin haɓaka nesa.
Nesa Terminal.exe	• Mai aiwatarwa file da GUI. • Ayyuka azaman tashar tashar mai masaukin don yin hulɗa tare da kayan haɓaka haɓaka FPGA MAX 10. • Aika bayanan shirye-shirye ta hanyar UART. • An haɗa lambar tushe na wannan tashar.

Table 3: Jagora Files Haɗe a cikin Tsarin Magana

Kuna iya amfani da waɗannan masters files don ƙirar ƙira ba tare da haɗa zane ba files.

File Suna   factory_application1.pof factory_application1.rpd	Bayani Quartus II shirye-shirye file wanda ya ƙunshi hoton masana'anta da hoton aikace-aikacen 1, wanda za a tsara shi zuwa CFM0 da CFM1 & CFM2 bi da bi a farkon s.tage.
factory_application2.pof factory_application2.rpd	• Quartus II shirye-shirye file wanda ya ƙunshi hoton masana'anta da hoton aikace-aikacen 2. • Za a fitar da hoton aikace-aikacen 2 daga baya don maye gurbin hoton aikace-aikacen 1 yayin haɓaka tsarin nesa, mai suna application_ image_2.rpd a ƙasa.
aikace-aikace_image_1.rpd	Quartus II albarkatun shirye-shirye file wanda ya ƙunshi hoton aikace-aikacen 1 kawai.
aikace-aikace_image_2.rpd	Quartus II albarkatun shirye-shirye file wanda ya ƙunshi hoton aikace-aikacen 2 kawai.
Nios_application.pof	• Shirye-shirye file wanda ya ƙunshi Nios II processor software applica-tion .hex file kawai. • Don tsara shi cikin filasha QSPI na waje.
pfl.sof	• Quartus II . sof dauke da PFL. • An tsara shi cikin walƙiya QSPI akan kayan haɓakawa na MAX 10 FPGA.

Bayanin Aiki na Ƙirar Magana

Nios II Gen2 Processor

• Nios II Gen2 Processor a cikin ƙirar ƙira yana da ayyuka masu zuwa:
• Ma'aikacin bas wanda ke sarrafa duk ayyukan dubawa tare da Altera On-Chip Flash core IP gami da karantawa, rubutu, da gogewa.
• Yana ba da algorithm a cikin software don karɓar rafi na shirye-shirye daga kwamfutar mai watsa shiri da jawo sake daidaitawa ta hanyar Dual Configuration IP core.
• Kuna buƙatar saita sake saita vector na processor daidai da haka. Wannan shi ne don tabbatar da cewa mai sarrafawa yana yin takalma daidai lambar aikace-aikacen daga ko dai UFM ko filasha QSPI na waje.
• Lura: Idan lambar aikace-aikacen Nios II babba ce, Intel tana ba da shawarar adana lambar aikace-aikacen a cikin filasha QSPI na waje. A cikin wannan ƙirar ƙira, vector na sake saiti yana nuni zuwa filasha QSPI na waje inda aka adana lambar aikace-aikacen Nios II.

Bayanai masu alaƙa

• Nios II Gen2 Koyarwar Haɓaka Hardware
• Yana ba da ƙarin bayani game da haɓaka Nios II Gen2 Processor.

Altera On-Chip Flash IP Core

• Altera On-Chip Flash core yana aiki azaman abin dubawa don mai sarrafa Nios II don karantawa, rubuta ko goge aiki zuwa CFM da UFM. Altera On-Chip Flash core yana ba ku damar samun dama, gogewa da sabunta CFM tare da sabon rafi mai daidaitawa. Editan sigar IP na Altera On-Chip Flash yana nuna kewayon adireshi da aka riga aka ƙaddara don kowane ɓangaren ƙwaƙwalwar ajiya.

Bayanai masu alaƙa

• Altera On-Chip Flash IP Core
• Yana ba da ƙarin bayani game da Altera On-Chip Flash IP Core.

Altera Dual Kanfigareshan IP Core

• Kuna iya amfani da Altera Dual Configuration IP core don samun damar toshe haɓakar tsarin nesa a cikin na'urorin MAX 10 FPGA. Altera Dual Configuration IP core yana ba ku damar kunna sake fasalin da zarar an sauke sabon hoton.

Bayanai masu alaƙa

• Altera Dual Kanfigareshan IP Core
• Yana ba da ƙarin bayani game da Altera Dual Configuration IP Core

Altera UART IP Core

• UART IP core yana ba da damar sadarwa na rafukan halayen serial tsakanin tsarin da aka haɗa a cikin MAX 10 FPGA da na'urar waje. A matsayin mai kula da Avalon-MM, mai sarrafa Nios II yana sadarwa tare da UART IP core, wanda bawan Avalon-MM ne. Ana yin wannan sadarwa ta hanyar karantawa da rubuta iko da rajistar bayanai.
• Jigon yana aiwatar da lokacin ka'idar RS-232 kuma yana ba da fasali masu zuwa:
• daidaitaccen ƙimar baud, daidaito, tsayawa, da ragowar bayanai
• na zaɓi RTS/CTS siginar sarrafa kwararar kwarara

Bayanai masu alaƙa

• UART Core
• Yana ba da ƙarin bayani game da UART Core.

Generic Quad SPI Mai Kula da IP Core

• Generic Quad SPI Controller IP core yana aiki azaman mu'amala tsakanin MAX 10 FPGA, filasha na waje da filasha QSPI a kan jirgi. Jigon yana ba da dama ga filasha QSPI ta hanyar karantawa, rubutu da goge ayyukan.
  Lokacin da aikace-aikacen Nios II ya faɗaɗa tare da ƙarin umarni, da file girman hex file wanda aka samar daga aikace-aikacen Nios II zai fi girma. Bayan ƙayyadaddun ƙayyadaddun girman, UFM ba za ta sami isasshen sarari don adana hex ɗin aikace-aikacen ba file. Don magance wannan, zaku iya amfani da filasha QSPI na waje da ke akwai akan kayan haɓaka MAX 10 FPGA don adana hex ɗin aikace-aikacen. file.

Tsarin Aikace-aikacen Software na Nios II EDS

• Ƙirar ƙira ta ƙunshi lambar aikace-aikacen software na Nios II wanda ke sarrafa ƙirar tsarin haɓaka nesa. Lambar aikace-aikacen software na Nios II martani ga tashar mai masaukin baki ta hanyar UART ta aiwatar da takamaiman umarni.

Ana ɗaukaka Hotunan Aikace-aikacen Nesa

• Bayan kun watsa shirye-shiryen bit stream file ta amfani da Terminal mai nisa, an ƙirƙiri aikace-aikacen software na Nios II yin haka:

1. Saita Altera On-Chip Flash IP core Control Register don rashin kare sashin CFM1 & 2.
2. Yi aikin shafe sashe akan CFM1 da CFM2. Software ɗin yana yin rajistar matsayi na Altera On-Chip Flash IP core don tabbatar da nasarar shafewa.
3. Karɓi bytes 4 na rafi bit lokaci guda daga stdin. Ana iya amfani da daidaitaccen shigarwa da fitarwa don karɓar bayanai kai tsaye daga tashar mai watsa shiri da buga fitarwa akansa. Za a iya saita nau'ikan madaidaicin shigar da zaɓin fitarwa ta hanyar Editan BSP a cikin kayan aikin Gina Eclipse na Nios II.
4. Yana mayar da odar bit na kowane byte.
   • Lura: Saboda daidaitawar Altera On-Chip Flash IP Core, kowane byte na bayanai yana buƙatar juyawa kafin rubuta shi cikin CFM.
5. Fara rubuta 4 bytes na bayanai lokaci guda cikin CFM1 da CFM2. Wannan tsari yana ci gaba har zuwa ƙarshen shirye-shiryen bit stream.
6. Zaɓen rijistar matsayi na Altera On-Chip Flash IP don tabbatar da nasarar rubuta aiki. Yana buƙatar saƙo don nuna an gama watsawa.
   • Lura: Idan aikin rubuta ya gaza, tashar tashar za ta dakatar da aikin aika rafi da samar da saƙon kuskure.
7. Yana saita Rijistar Sarrafa don sake kare CFM1 da CFM2 don hana duk wani aiki na rubutu maras so.

Bayanai masu alaƙa

• pof Generation ta hanyar Convert Programming Files a yi
• Yana ba da bayanai game da ƙirƙirar rpd files a lokacin maida shirye-shirye files.

Yana haifar da sake daidaitawa daga nesa

• Bayan ka zaɓi aikin sake fasalin faɗakarwa a cikin Mai watsa shiri Remote Terminal, aikace-aikacen software na Nios II zai yi haka:

1. Karɓi umarni daga daidaitaccen shigarwa.
2. Fara sake fasalin tare da ayyuka biyu masu zuwa:

• Rubuta 0x03 zuwa adireshin biya na 0x01 a cikin Dual Configuration IP core. Wannan aikin yana sake rubuta fil ɗin CONFIG_SEL na zahiri kuma yana saita Hoto 1 azaman hoton daidaitawar taya na gaba.
• Rubuta 0x01 zuwa adireshin biya na 0x00 a cikin Dual Configuration IP core. Wannan aikin yana haifar da sake daidaitawa zuwa hoton aikace-aikacen a cikin CFM1 da CFM2

Tafiyar Tsara Nasiha

Samar da Shirye-shirye Files

• Dole ne ku samar da shirye-shirye masu zuwa files kafin samun damar yin amfani da haɓakar tsarin nesa akan kayan haɓakawa na MAX 10 FPGA:

Don Shirye-shiryen QSPI:

• sof - amfani pfl.sof da aka haɗa a cikin ƙirar ƙira ko za ku iya zaɓar ƙirƙirar .sof daban-daban wanda ke ɗauke da ƙirar PFL na ku.
• pof - daidaitawa file an ƙirƙira daga .hex kuma an tsara shi cikin filasha QSPI.
• Domin Haɓaka Tsari mai nisa:
• pof - daidaitawa file halitta daga .sof kuma an tsara shi cikin filasha na ciki.
• rpd- ya ƙunshi bayanan don walƙiya na ciki wanda ya haɗa da saitunan ICB, CFM0, CFM1 da UFM.
• taswira - yana riƙe adireshin kowane ɓangaren ƙwaƙwalwar ajiya na saitunan ICB, CFM0, CFM1 da UFM.

Kerawa files don Shirye-shiryen QSPI

Don samar da .pof file don shirye-shiryen QSPI, yi matakai masu zuwa:

1. Gina Nios II Project kuma samar da HEX file.
   • Lura: Koma zuwa AN730: Hanyoyin Booting na Nios II A cikin na'urori MAX 10 don bayani game da gina aikin Nios II da samar da HEX file.
2. A kan File menu, danna Convert Programming Files.
3. Ƙarƙashin shirye-shiryen fitarwa file, zaži Programmer Object File (.pof) a cikin Programming file rubuta jerin.
4. A cikin Lissafin Yanayin, zaɓi Serial Passive 1-bit.
5. A cikin lissafin na'urar Kanfigareshan, zaɓi CFI_512Mb.
6. A cikin File akwatin suna, saka file suna don shirye-shiryen file kuna so ku ƙirƙiri.
7. A cikin Input files don canza lissafin, cire Zabuka da layin bayanan SOF. Danna Ƙara Hex Data kuma akwatin maganganu na Ƙara Hex Data ya bayyana. A cikin Ƙara Hex Data akwatin, zaɓi Cikakkiyar adireshi kuma saka .hex file wanda aka samar daga Nios II EDS Gina Kayan aikin.
8. Bayan an saita duk saituna, danna Ƙirƙiri don ƙirƙirar shirye-shirye masu alaƙa file.

Bayanai masu alaƙa

AN730: Hanyoyin Booting na Nios II A cikin na'urorin FPGA MAX 10
Kerawa files don Haɓaka Tsarin Nisa

Don samar da .pof, .map da .rpd files don haɓaka tsarin nesa, yi matakai masu zuwa:

1. Mayar da Factory_image, aikace-aikacen_image_1 da aikace-aikacen_image_2, kuma a haɗa duka ƙira uku.
2. Ƙirƙirar biyu .pof files da aka bayyana a cikin tebur mai zuwa:
   • Lura: Koma .pof Generation ta hanyar Maida Shirye-shiryen Files don matakai akan samar da .pof files.
3. Bude app2.rpd ta amfani da kowane editan hex.
4. A cikin editan hex, zaɓi toshe bayanan binary dangane da farawa da ƙarshen biya ta hanyar komawa zuwa taswirar . file. Farawa da ƙarewa na na'urar 10M50 shine 0x12000 da 0xB9FFF bi da bi. Kwafi wannan toshe zuwa sabon file kuma ajiye shi a cikin wani .rpd daban file. Wannan sabon .rpd file ya ƙunshi hoton aikace-aikacen 2 kawai.

pof Generation ta hanyar Convert Programming Files

Don canza .sof files zuwa .pof files, bi waɗannan matakan:

1. A kan File menu, danna Convert Programming Files.
2. Ƙarƙashin shirye-shiryen fitarwa file, zaži Programmer Object File (.pof) a cikin Programming file rubuta jerin.
3. A cikin Lissafin Yanayin, zaɓi Kanfigareshan na ciki.
4. A cikin File akwatin suna, saka file suna don shirye-shiryen file kuna so ku ƙirƙiri.
5. Don ƙirƙirar taswirar ƙwaƙwalwa File (.map), kunna Ƙirƙiri taswirar ƙwaƙwalwa File (Samar da fitarwa ta atomatik_file.map). Taswirar tana ƙunshe da adireshin CFM da UFM tare da saitin ICB wanda kuka saita ta zaɓin Bayanin Zaɓi/Boot.
6.  Don samar da Raw Programming Data (.rpd), kunna Ƙirƙiri bayanan saitin RPD (Ƙirƙirar fitarwa_)file_auto.rpd).
   Tare da taimakon Memory Map File, zaka iya gano bayanai cikin sauƙi don kowane shingen aiki a cikin .rpd file. Hakanan zaka iya cire bayanan walƙiya don kayan aikin shirye-shirye na ɓangare na uku ko sabunta ƙa'idar ko bayanan mai amfani ta Altera On-Chip Flash IP.
7. Ana iya ƙara .sof ta hanyar Input files don canza lissafin kuma za ku iya ƙara har zuwa biyu .sof files.
   • Don dalilai na haɓaka tsarin nesa, zaku iya riƙe ainihin bayanan shafi na 0 a cikin .pof, kuma ku maye gurbin bayanan shafi na 1 tare da sabon .sof file. Don yin wannan, kuna buƙatar ƙara .pof file a shafi na 0, sannan
     ƙara .sof page, sa'an nan kuma ƙara sabon .sof file ku
8. Bayan an saita duk saituna, danna Ƙirƙiri don ƙirƙirar shirye-shirye masu alaƙa file.

Shirya QSPI

Don tsara lambar aikace-aikacen Nios II cikin filasha QSPI, yi matakai masu zuwa:

1. A kan MAX 10 FPGA Development Kit, canza MAX10_BYPASSn zuwa 0 don ketare na'urar VTAP (MAX II) kan jirgi.
2. Haɗa Intel FPGA Zazzage Cable (tsohon USB Blaster) zuwa JTAG kai.
3. A cikin taga Programmer, danna Saitin Hardware kuma zaɓi USB Blaster.
4. A cikin Lissafin Yanayin, zaɓi JTAG.
5. Danna Maɓallin Gano Kai a kan sashin hagu.
6. Zaɓi na'urar da za a tsara, kuma danna Ƙara File.
7. Zaɓi pfl.sof.
8. Danna Fara don fara shirye-shirye.
9. Bayan shirin ya yi nasara, ba tare da kashe allon ba, danna maɓallin Ganewa ta atomatik a ɓangaren hagu kuma. Za ku ga QSPI_512Mb flash yana bayyana a cikin taga mai tsara shirye-shirye.
10. Zaɓi na'urar QSPI, kuma danna Ƙara File.
11. Zaɓi .pof file wanda aka samar a baya daga .hex file.
12. Danna Fara don fara shirye-shiryen filasha QSPI.

Shirya FPGA tare da Hoton Farko ta amfani da JTAG

Dole ne ku tsara app1.pof cikin FPGA azaman hoton farko na na'urar. Don tsara app1.pof cikin FPGA, yi matakai masu zuwa:

1. A cikin taga Programmer, danna Saitin Hardware kuma zaɓi USB Blaster.
2. A cikin Lissafin Yanayin, zaɓi JTAG.
3. Danna Maɓallin Gano Kai a kan sashin hagu.
4. Zaɓi na'urar da za a tsara, kuma danna Ƙara File.
5. Zaɓi app1.pof.
6. Danna Fara don fara shirye-shirye.

Ana ɗaukaka Hoto da Ƙarfafa Sake daidaitawa ta amfani da UART

Don saita kayan haɓakawa na MAX10 FPGA ɗinku daga nesa, yi matakai masu zuwa:

1. Lura: Kafin ka fara, tabbatar da waɗannan abubuwa:
   • an saita fil ɗin CONFIG_SEL akan allo zuwa 0
   • An haɗa tashar tashar UART ta hukumar zuwa kwamfutarka
   • Bude Terminal.exe mai nisa kuma ana buɗe Maɓallin Nesa.
2. Danna Saituna kuma taga saitunan tashar tashar Serial zai bayyana.
3. Saita sigogi na tasha mai nisa don dacewa da saitunan UART da aka zaɓa a cikin Quartus II UART IP core. Bayan an gama saitin, danna Ok.
4. Danna maɓallin nCONFIG akan kayan haɓakawa ko maɓalli na 1 a cikin akwatin Aika rubutu, sannan danna Shigar.
   • Jerin zaɓin aiki zai bayyana akan tashar, kamar yadda aka nuna a ƙasa:
   • Lura: Don zaɓar aiki, maɓalli a lambar a cikin akwatin Aika rubutu, sannan danna Shigar.
5. Don sabunta hoton aikace-aikacen 1 tare da hoton aikace-aikacen 2, zaɓi aiki 2. Za a umarce ku don saka adireshin farawa da ƙarshen CFM1 da CFM2.
   • Lura: Adireshin da aka nuna a taswira file ya haɗa da saitunan ICB, CFM da UFM amma Altera On-Chip
   • Filashin IP na iya samun damar CFM da UFM kawai. Don haka, akwai kashe adireshi tsakanin adireshin da aka nuna a taswira file da taga Altera On-Chip Flash na sigar IP.
6. Maɓalli a cikin adireshi dangane da adireshin da aka ayyana ta taga siginar IP na Altera On-Chip Flash.
   • Goge zai fara ta atomatik bayan shigar da adireshin ƙarshe.
7. Bayan nasarar gogewa, za a tura ku don shigar da programming .rpd file don aikace-aikacen hoto 2.
   • Don loda hoto, danna AikaFile maballin, sannan zaɓi .rpd mai ɗauke da hoton aikace-aikacen 2 kawai sannan danna Buɗe.
   • Lura: Banda hoton aikace-aikacen 2, zaku iya amfani da kowane sabon hoto da kuke son ɗaukakawa cikin na'urar.
   • Tsarin sabuntawa zai fara kai tsaye kuma zaka iya saka idanu akan ci gaba ta hanyar tashar. Menu na aiki zai sa An gama kuma yanzu zaku iya zaɓar aiki na gaba.
8. Don haifar da sake daidaitawa, zaɓi aiki 4. Kuna iya lura da halayen LED wanda ke nuna hoto daban-daban da aka ɗora a cikin na'urar.

Hoto	Matsayin LED (Ƙasashen Mai Aiki)
Hoton masana'anta	01010
Hoton aikace-aikace 1	10101
Hoton aikace-aikace 2	01110

Tarihin Bita daftarin aiki

Kwanan wata	Sigar	Canje-canje
Fabrairu 2017	2017.02.21	An sake sanyawa a matsayin Intel.
Yuni 2015	2015.06.15	Sakin farko.

Takardu / Albarkatu

intel MAX 10 FPGA Na'urorin Sama da UART tare da Nios II Processor [pdf] Jagorar mai amfani Na'urorin MAX 10 FPGA Sama da UART tare da Mai sarrafa Nios II, Na'urorin MAX 10 FPGA, Sama da UART tare da Mai sarrafa Nios II, Sama da UART, Nios II Mai sarrafa UART, Nios II, Mai sarrafawa UART

Magana

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