intel UG-20118 Yekunze Memory Interfaces Arria 10 FPGA IP Dhizaini Example

Design Exampuye Kurumidza Kutanga Gwaro reKunze Memory Interfaces Intel® Arria® 10 FPGA IP

Iyo nyowani interface uye yakawanda otomatiki dhizaini example kuyerera inowanikwa yeIntel® Arria® 10 yekunze ndangariro nzvimbo.
The Example Dhizaini tebhu mune paramende dhizaini inobvumidza iwe kutsanangura kusikwa kweiyo synthesis uye simulation file seti dzaunogona kushandisa kusimbisa yako EMIF IP.
Unogona kugadzira example dhizaini yakanangana neIntel FPGA yekuvandudza kit, kana chero EMIF IP yaunogadzira.

Mufananidzo 1. General Design Example Workflows

Design Example

Mufananidzo 2. Kugadzira EMIF Example Dhizaini NeIntel Arria 10 Yekuvandudza Kit

Intel Corporation. Kodzero dzese dzakachengetwa. Intel, iyo Intel logo, uye mamwe maIntel mamaki zviratidzo zveIntel Corporation kana vatsigiri vayo. Intel inobvumira kushanda kweFPGA yayo uye semiconductor zvigadzirwa kune zvazvino zvakatemwa zvinoenderana neIntel yakajairwa waranti asi inochengeta kodzero yekuita shanduko kune chero zvigadzirwa nemasevhisi chero nguva pasina chiziviso. Intel haitore mutoro kana mutoro unobva mukushandisa kana kushandiswa kwechero ruzivo, chigadzirwa, kana sevhisi inotsanangurwa pano kunze kwekunge yakabvumiranwa nekunyora neIntel. Vatengi veIntel vanorairwa kuti vawane yazvino vhezheni yezvakatemwa zvemudziyo vasati vavimba nechero ruzivo rwakaburitswa uye vasati vaisa maodha ezvigadzirwa kana masevhisi.

• Mamwe mazita nemhando anogona kunzi zvinhu zvevamwe.

Kugadzira chirongwa cheEMIF

Kune Intel Quartus® Prime software vhezheni 17.1 uye gare gare, iwe unofanirwa kugadzira Intel Quartus Prime purojekiti usati wagadzira iyo EMIF IP uye dhizaini ex.ample.

1. Tangisa Intel Quartus Prime software uye sarudza File ➤ New Project Wizard. Click Next.
2. Nyora dhairekitori uye zita repurojekiti yaunoda kugadzira. Click Next.
3. Tarisa kuti Empty Project yakasarudzwa. Dzvanya Next kaviri.
4. Pasi peZita sefa, nyora nhamba yechikamu chemudziyo.
5. Pazasi Zvishandiso Zvinowanikwa, sarudza mudziyo wakakodzera.
6. Dzvanya Finish.

Kugadzira uye Kugadzirisa iyo EMIF IP

Matanho anotevera anoratidza maitiro ekugadzira uye kugadzirisa iyo EMIF IP. Matanho acho akafanana zvisinei nememory protocol yauri kunanga.

1. MuIP Catalog hwindo, sarudza Intel Arria 10 Yekunze Memory Interfaces. (Kana iyo IP Catalog hwindo isingaonekwe, sarudza View ➤ Utility Windows ➤ IP Catalog.)
2. MuIP Parameter Mharidzo, ipa zita remubatanidzwa reEMIF IP (zita raunopa pano rinova file zita reIP) uye tsanangura dhairekitori. Dzvanya Gadzira.
3. Iyo parameter mupepeti ine akawanda ma tabo kwaunofanirwa kugadzirisa ma paramita kuratidza yako EMIF kuita:

Intel Arria 10 EMIF Parameter Edhita Mazano

Tafura 1. EMIF Parameter Editor Guidelines

Parameter Editor Tab	Guidelines
General	Ita shuwa kuti anotevera ma parameter aiswa nemazvo: • The kumhanya giredhi kuti mudziyo. • Kuwanda kwewachi yendangariro. • The PLL referensi wachi frequency.
Memory	• Tarisa kune dhetabheti yemudziyo wako wekuyeuka kuti uise ma paramita pa Memory tab. • Unofanira kuisawo nzvimbo chaiyo yepini yeALERT#. (Inoshanda kuDDR4 memory protocol chete.)
Mem I/O	• Pakuferefeta kwekutanga kweprojekiti, unogona kushandisa marongero akasarudzika pa Mem I/O tab. • Kuti ugadzirise dhizaini yepamusoro, unofanirwa kuita simulation yebhodhi kuti uwane marongero ekupedzisira ekupedzisira.
FPGA I/O	• Pakuferefeta kwekutanga kweprojekiti, unogona kushandisa marongero akasarudzika pa FPGA I/O tab. • Pakusimbisa magadzirirwo epamusoro, unofanira kuita simulation yebhodhi nemhando dzeBIS dzakabatana kuti usarudze maitiro akakodzera eI/O.
Mem Timing	• Pakuferefeta kwekutanga kweprojekiti, unogona kushandisa marongero akasarudzika pa Mem Timing tab. • Kuti ugadzirise dhizaini yepamusoro, iwe unofanirwa kuisa paramita zvinoenderana nedatateta remudziyo wako.
Board	• Pakuferefeta kwekutanga kweprojekiti, unogona kushandisa marongero akasarudzika pa Board tab. • Kuti ugadzirise dhizaini yepamusoro uye kuvharwa kwenguva kwakaringana, unofanira kuita simulation yebhodhi kuti utore intersymbol interference (ISI)/ crosstalk and board and package skew information, woiisa pa Board tab.
Controller	Seta iyo controller paramita zvinoenderana nekwaunoda kumisikidzwa uye maitiro kune yako ndangariro controller.
Diagnostics	Iwe unogona kushandisa iyo parameter pane Diagnostics tab yekubatsira mukuyedza uye kugadzirisa ndangariro yako.
Example Designs	The Example Designs tab inokutendera iwe kugadzira dhizaini examples yekubatanidza uye yekufananidza. Iyo yakagadzirwa yakagadzirwa example ndeye yakakwana EMIF sisitimu inosanganisira iyo EMIF IP uye mutyairi anogadzira isina kujairika traffic kusimbisa iyo memory interface.

Kuti uwane ruzivo rwakadzama pamaparamita ega ega, tarisa kuchitsauko chakakodzera chendangariro yako protocol muIntel Arria 10 External Memory Interfaces IP User Guide.

Kugadzira iyo Synthesizable EMIF Dhizaini Example

Kune iyo Intel Arria 10 yekuvandudza kits, kune presets inoisa otomatiki iyo EMIF IP uye inogadzira mapiniti eiyo chaiyo bhodhi.

1. Tarisa kuti Presets hwindo rinoonekwa. Kana iyo Presets hwindo isingaonekwe, iratidze nekusarudza View ➤ Presets.
2. Muwindo re Presets, sarudza yakakodzera kit kit preset uye tinya Shandisa.
3. Gadzirisa iyo EMIF IP uye tinya Gadzira Example Dhizaini mukona yepamusoro-kurudyi yehwindo.
4. Taura dhairekitori reiyo EMIF dhizaini example uye tinya OK. Kubudirira kugadzirwa kweEMIF dhizaini example anogadzira zvinotevera files pasi peWii dhairekitori.

Mufananidzo 3. Yakagadzirwa Synthesizable Design Example File Chimiro

Cherechedza: Kana ukasasarudza bhokisi reSimulation kana Synthesis, dhairekitori rekuenda rinenge riine Platform Designer dhizaini. files, iyo isingabatanidzwe neIntel Quartus Prime software zvakananga, asi inogona kuva viewed kana kugadziridzwa pasi pePlatform Designer. Mune ino mamiriro, unogona kumhanyisa inotevera mirairo kugadzira synthesis uye simulation file sets.

• Kuti ugadzire chirongwa chinosanganiswa, unofanira kumhanya quartus_sh -t make_qii_design.tcl script mudhairekitori rekuenda.
• Kuti ugadzire purojekiti yekufananidza, unofanirwa kumhanya quartus_sh -t make_sim_design.tcl script mudhairekitori rekuenda.
• Iyo Sarudza bhodhi kudonhedza muchikamu chino inoshandisa yakakodzera kit pini yepini migove kune example design.
• Setting iyi inowanikwa chete kana ukabatidza Synthesis checkbox muExample Dhizaini Files chikamu.
• Kuseta uku kunofanirwa kuenderana neyakaiswa yekuvandudza kit iripo, kana zvikasadaro meseji yekukanganisa inobuda.
• Kana iyo kukosha Hapana inoonekwa muSarudzo bhodhi kudhonzera, inoratidza kuti yazvino parameta sarudzo haienderane nechero yekuvandudza kit masisitimu. Iwe unogona kushandisa kit yekuvandudza-chaiyo IP uye inoenderana parameter marongero nekusarudza imwe yepreset kubva kupreset raibhurari. Kana iwe ukaisa preset, iyo IP iripo uye mamwe ma parameter marongero anoiswa kuti aenderane neakasarudzwa preset. Kana iwe uchida kuchengetedza zvigadziriso zvako zvazvino, unofanirwa kuzviita usati wasarudza preset. Kana iwe ukasarudza preset usina kuchengetedza yako yekutanga marongero, unogona kugara uchichengetedza iyo nyowani preset marongero pasi pezita rakasiyana
• Kana iwe uchida kugadzira iyo example dhizaini yekushandisa pane yako bhodhi, isa Sarudza bhodhi kune Hapana, gadzira iyo example dhizaini, uye wobva wawedzera pini nzvimbo zvipingaidzo.

Related Information

• Synthesis Example Dhizaini papeji 17
• Intel Arria 10 EMIF IP Parameter Tsananguro yeDDR3
• Intel Arria 10 EMIF IP Parameter Tsananguro yeDDR4
• Intel Arria 10 EMIF IP Parameter Tsananguro yeQDRII/II+/Xtreme
• Intel Arria 10 EMIF IP Parameter Tsananguro yeQDR-IV
• Intel Arria 10 EMIF IP Parameter Tsananguro yeRLDRAM 3
• Intel Arria 10 EMIF IP Parameter Tsananguro yeLPDDR3

Kugadzira iyo EMIF Dhizaini Example for Simulation

Kune iyo Intel Arria 10 yekuvandudza kits, kune presets inoisa otomatiki iyo EMIF IP uye inogadzira mapiniti eiyo chaiyo bhodhi.

1. Tarisa kuti Presets hwindo rinoonekwa. Kana iyo Presets hwindo isingaonekwe, iratidze nekusarudza View ➤ Presets.
2. Muwindo re Presets, sarudza yakakodzera kit kit preset uye tinya Shandisa.
3. Gadzirisa iyo EMIF IP uye tinya Gadzira Example Dhizaini mukona yepamusoro-kurudyi yehwindo.
4. Taura dhairekitori reiyo EMIF dhizaini example uye tinya OK.

Kubudirira kugadzirwa kweEMIF dhizaini example inogadzira akawanda file seti yeakasiyana anotsigirwa simulators, pasi pe sim/ed_sim dhairekitori.
Mufananidzo 4. Yakagadzirwa Simulation Dhizaini Example File Chimiro

Cherechedza: Kana ukasasarudza bhokisi rekutarisa reSimulation kana Synthesis, dhairekitori rekuenda rinenge riine Platform Designer dhizaini. files, iyo isingabatanidzwe neIntel Quartus Prime software zvakananga, asi inogona kuva viewyakakwenenzverwa kana kupepetwa pasi pePlatform Designer. Mune ino mamiriro iwe unogona kumhanya inotevera mirairo kugadzira synthesis uye simulation file sets.

• Kuti ugadzire chirongwa chinosanganiswa, unofanira kumhanya quartus_sh -t make_qii_design.tcl script mudhairekitori rekuenda.
• Kuti ugadzire purojekiti yekufananidza, unofanirwa kumhanya quartus_sh -t make_sim_design.tcl script mudhairekitori rekuenda.

Related Information

• Simulation Example Dhizaini papeji 19
• Intel Arria 10 EMIF IP - Simulating Memory IP

Simulation Versus Hardware Implementation

Kune ekunze ndangariro interface simulation, unogona kusarudza kusvetuka calibration kana yakazara calibration paDiagnostics tab panguva yeIP chizvarwa.
EMIF Simulation Models
Iyi tafura inofanidza maitiro eiyo skip calibration uye yakazara calibration modhi.
Tafura 2. EMIF Simulation Models: Skip Calibration maringe ne Full Calibration

Skip Calibration	Full Calibration
System-level simulation inotarisa pane mushandisi mantiki.	Memory interface simulation inotarisa pane calibration.
Details of calibration haina kutorwa.	Inobata zvese stages of calibration.
akaenderera…

Skip Calibration	Full Calibration
Inokwanisa kuchengetedza uye kutora data.	Inosanganisira kuenzana, per-bit deskew, nezvimwe.
Inomiririra kunyatsoshanda.
Haisi kufunga bhodhi skew.

RTL Simulation Versus Hardware Implementation
Iyi tafura inoburitsa misiyano yakakosha pakati peEMIF simulation uye kuita kwehardware.
Tafura 3. EMIF RTL Simulation Versus Hardware Implementation

RTL Simulation	Hardware Implementation
Nios® yekutanga uye calibration kodhi inoteedzera zvakafanana.	Nios kutanga uye calibration kodhi inoteedzana.
Mainterface anoti cal_done chiratidzo chechiratidzo panguva imwe chete mukufananidza.	Fitter mashandiro anotarisisa marongero ekugadzirisa, uye nzvimbo dzekupindirana hadzitaure cal_done panguva imwe chete.

Iwe unofanirwa kumhanyisa RTL simulations zvichienderana netraffic mapatani ekushandisa kwedhizaini yako. Ziva kuti RTL simulation haifanire PCB kunonoka kuteedzera izvo zvinogona kukonzera mutsauko mukunonoka pakati peRTL simulation nekuitwa kwehardware.

Simulating Yekunze Memory Interface IP ine ModelSim

Iyi nzira inoratidza maitiro ekutevedzera iyo EMIF dhizaini example.

1. Tangisa iyo Mentor Graphics * ModelSim software uye sarudza File ➤ Chinja Dhairekitori. Enda kune sim/ed_sim/mentor dhairekitori mukati meyakagadzirwa dhizaini example folder.
2. Tarisa kuti iyo Transcript hwindo inoratidzwa pazasi pechidzitiro. Kana iyo Transcript hwindo isingaonekwe, iratidze nekudzvanya View ➤ Zvinyorwa.
3. Muhwindo reTranscript, mhanya kunobva msim_setup.tcl.
4. Kana source msim_setup.tcl yapedza kushanda, mhanya ld_debug muTranscript window.
5. Mushure mokunge ld_debug yapedza kushanda, simbisa kuti hwindo reZvinhu rinoratidzwa. Kana hwindo reZvinhu risingaonekwe, riratidze nekudzvanya View ➤ Zvinhu.
6. Muwindo reZvinhu, sarudza masaini aunoda kutevedzera nekudzvanya-kurudyi uye kusarudza Wedzera Wave.
7. Mushure mekunge wapedza kusarudza masaini ekufananidza, ita run -ese muTranscript hwindo. Iyo simulation inomhanya kusvika yapera.
8. Kana simulation isingaonekwe, tinya View ➤ Wave.

Related Information

Intel Arria 10 EMIF IP - Simulating Memory IP

Pin Kuiswa kweIntel Arria 10 EMIF IP

Ichi chinyorwa chinopa nhungamiro yekuiswa kwepini.

Overview

Intel Arria 10 FPGAs ine inotevera chimiro:

• Chishandiso chega chega chine makoramu maviri eI/O.
• Imwe neimwe I/O column ine anosvika masere I/O mabhangi.
• Bhangi rega rega reI/O rine nzira ina.
• Imwe neimwe nzira ine 12 general-chinangwa I/O (GPIO) pini.

General Pin Guidelines

Aya mapoinzi anotevera anopa general pini nhungamiro:

• Ita shuwa kuti mapini eiyo yakapihwa yekunze ndangariro interface anogara mukati meiyo imwechete I / O column.
• Interfaces inotora mabhangi akawanda inofanirwa kuzadzisa zvinotevera zvinodiwa:
  • Mabhangi anofanira kunge ari padyo neimwe. Kuti uwane ruzivo rwemabhangi ari padyo, tarisa kuIntel Arria 10 External Memory Interfaces IP User Guide.
  • Kero uye bhangi rekuraira zvinofanirwa kugara mubhangi repakati kuti uderedze latency. Kana iyo ndangariro interface ichishandisa kunyange nhamba yemabhangi, iyo kero uye yekuraira bhangi inogona kugara mune imwe yemabhangi maviri epakati.
• Mapini asina kushandiswa anogona kushandiswa seyakajairwa-chinangwa I/O pini.
• Yese kero uye yekuraira uye mapini anobatanidzwa anofanira kugara mukati mebhangi rimwe chete.
• Kero uye kuraira uye mapini edata anogona kugovera bhangi pasi pemamiriro anotevera:
  • Kero uye kuraira uye pini yedata haigone kugovera I/O mugwagwa.
  • Chete nzira isina kushandiswa yeI/O mukero nebhangi rekuraira ndiyo inogona kushandiswa pamapini edata.

Tafura 4. General Pin Constraints

Signal Type	Constraint
Data Strobe	Zvese zviratidzo zveboka reDQ zvinofanirwa kugara munzira imwechete yeI/O.
Data	Mapini eDQ ane hukama anofanirwa kugara munzira imwechete yeI/O. Mapini eDM/DBI anofanira kupetwa nepini yeDQ kuti ashande zvakanaka. Kune maprotocol asingatsigire bidirectional data mitsara, masaini ekuverenga anofanirwa kuiswa mumapoka akaparadzana kubva pakunyora masaini.
Kero uye Raira	Kero uye Raira pini dzinofanirwa kugara munzvimbo dzakafanotsanangurwa mukati meI/O bhangi.

Pini Mabasa
Kana waisa preset kit panguva yekugadzira IP, mabasa ese epini ekiti yekuvandudza anogadzirwa otomatiki uye anogona kusimbiswa mu.qsf. file iyo inogadzirwa neyakagadzirwa example.

Related Information

• Intel Arria 10 EMIF IP DDR3
• Intel Arria 10 EMIF IP yeDDR4
• Intel Arria 10 EMIF IP yeQDRII/II+/Xtreme
• Intel Arria 10 EMIF IP yeQDR-IV
• Intel Arria 10 EMIF IP yeRLDRAM 3
• Intel Arria 10 EMIF IP yeLPDDR3

Kunyora uye Kuronga iyo Intel Arria 10 EMIF Dhizaini Example

Mushure mekunge maita mabasa epini anodiwa mu.qsf file, unogona kuunganidza dhizaini exampuye mune Intel Quartus Prime software.

1. Enda kuIntel Quartus Prime folda ine dhizaini example directory.
2. Vhura iyo Intel Quartus Prime chirongwa file, (.qpf).
3. Kuti utange kuunganidza, tinya Kugadzirisa ➤ Tanga Kuunganidza. Kupedzwa kunobudirira kwekubatanidza kunoburitsa .sof file, iyo inoita kuti dhizaini ishande pane Hardware.
4. Kuronga mudziyo wako nedhizaini yakaunganidzwa, vhura iyo programmer nekudzvanya Zvishandiso ➤ Chirongwa.
5. Muchirongwa, tinya Auto Detect kuti uone zvishandiso zvinotsigirwa.
6. Sarudza iyo Intel Arria 10 mudziyo uye wobva wasarudza Shandura File.
7. Enda kune yakagadzirwa ed_synth.sof file uye sarudza Vhura.
8. Dzvanya Tanga kuti utange kuronga iyo Intel Arria 10 mudziyo. Kana mudziyo ukarongwa zvinobudirira, bhaa yekufambira mberi kumusoro-kurudyi kwehwindo inofanira kuratidza 100% (Yakabudirira).

Kugadzirisa iyo Intel Arria 10 EMIF Dhizaini Example

Iyo EMIF Debug Toolkit inowanikwa kubatsira mukugadzirisa ekunze memory interface dhizaini. Iyo Toolkit inobvumidza iwe kuti uratidze kuverenga nekunyora miganho uye kugadzira dhayagiramu yeziso. Mushure mekunge waronga iyo Intel Arria 10 yekuvandudza kit, unogona kuona kushanda kwayo uchishandisa EMIF Debug Toolkit.

1. Kuti utange iyo EMIF Debug Toolkit, enda kuZvishandiso ➤ System Debugging Zvishandiso ➤ Yekunze Memory Interface Toolkit.
2. Click Initialize Connections.
3. Dzvanya Batanidza Project kune mudziyo. Hwindi rinobuda; simbisa kuti mudziyo wakakodzera wakasarudzwa uye kuti .sof yakarurama file inosarudzwa.
4. Dzvanya Gadzira Memory Interface Connection. Gamuchira marongero ekutanga nekudzvanya OK.
5. Iyo Intel Arria 10 yekuvandudza kit ikozvino yakagadzirirwa kushanda neEMIF Debug Toolkit, uye unogona kugadzira chero yeinotevera mishumo nekudzvanya kaviri pane inoenderana sarudzo.

• Rerun calibration. Inoburitsa mushumo wekuenzanisa inopfupikisa mamiriro ekuenzanisa paboka reDQ/DQS pamwe chete nemamariji epini yega yega yeDQ/DQS.
• Mutyairi Margining. Inoburitsa mushumo unopfupikisa kuverenga nekunyora miganho paI/O pini. Izvi zvinosiyana necalibration margining nekuti mutyairi margining anotorwa panguva yemushandisi modhi traffic kwete panguva yekuenzanisa.
• Gadzira Diyagiramu Yeziso. Inogadzira kuverenga uye kunyora dhayagiramu yeziso yega yega DQ pini zvichibva pane calibration data mapatani.
• Calibrate Termination. Inotsvaira tsika dzakasiyana dzekumisa uye inoshuma miganho iyo kukosha kwega kwega kwekugumisa kunopihwa. Shandisa iyi ficha kuti ibatsire kusarudza iyo yakakwana kumisa yeiyo memory interface.

Design Example Tsanangudzo yeKunze Memory Interfaces Intel Arria 10 FPGA IP

Paunoisa parameter uye kugadzira yako EMIF IP, unogona kutsanangura kuti sisitimu inogadzira madhairekitori ekufananidza uye synthesis. file sets, uye kugadzira iyo file anoseta otomatiki. Kana ukasarudza Simulation kana Synthesis pasi Example Dhizaini Files paEksample Dhizaini tab, iyo sisitimu inogadzira simulation yakakwana file seti kana mubatanidzwa wakakwana file seta, zvinoenderana nesarudzo yako.

Synthesis Example Dhizaini

The synthesis example dhizaini ine mabhuroko makuru anoratidzwa mumufananidzo uri pazasi.

• Iyo traffic jenareta, inova synthesizable Avalon®-MM exampmutyairi anoshandisa pseudo-random pateni yekuverenga uye anonyora kune parameterized nhamba yekero. Iyo jenareta yetraffic zvakare inotarisisa iyo data yakaverengwa kubva mundangariro kuti ive nechokwadi chekuti inoenderana neiyo yakanyorwa data uye ichiti kukundikana neimwe nzira.
• Muenzaniso weiyo memory interface, inosanganisira:
  • Mutongi wekurangarira anoyera pakati peAvalon-MM interface uye AFI interface.
  • Iyo PHY, inoshanda senge interface pakati peyekurangarira controller uye ekunze ndangariro zvishandiso kuita kuverenga nekunyora mashandiro.

Mufananidzo 5. Synthesis Example Dhizaini

Kana iwe uri kushandisa iyo Ping Pong PHY chimiro, iyo synthesis example dhizaini inosanganisira maviri majenareta emotokari anoburitsa mirairo kune maviri akazvimirira endangariro zvishandiso kuburikidza neaviri akazvimirira controller uye yakajairika PHY, sezvakaratidzwa mumufananidzo unotevera.

Mufananidzo 6. Synthesis Example Dhizaini yePing Pong PHY

Kana iwe uri kushandisa RLDRAM 3, iyo traffic jenareta mune synthesis example dhizaini inotaurirana zvakananga nePHY uchishandisa AFI, sezvakaratidzwa mumufananidzo unotevera.
Mufananidzo 7. Synthesis Example Dhizaini yeRLDRAM 3 Interfaces

Cherechedza: Kana imwe kana kupfuura yePLL yekugovera Mode, DLL yekugovera Mode, kana OCT yekugovera Mode paramita yakaiswa kune chero kukosha kunze kweKwete Kugovera, iyo synthesis ex.ample dhizaini ichange iine maviri traffic jenareta/memory interface zviitiko. Iwo maviri traffic jenareta/memory interface mamiriro ane hukama chete nekugovaniswa kwePLL/DLL/OCT sekutsanangurwa kwazvinoitwa neparameter. Iyo traffic jenareta / memory interface mamiriro anoratidza maitiro aungaita aya makubatanidza mune ako madhizaini.

Cherechedza: Yechitatu-bato synthesis inoyerera sezvakatsanangurwa muIntel Quartus Prime Standard Edition Mushandisi Gadhi: Yechitatu-bato Synthesis haisi inotsigirwa inoyerera yeEMIF IP.
Related Information
Kugadzira iyo Synthesizable EMIF Dhizaini Exampiri papeji 7

Simulation Example Dhizaini

The simulation example dhizaini ine mabhuroko makuru anoratidzwa mumufananidzo unotevera.

• Muenzaniso we synthesis example design. Sezvakatsanangurwa muchikamu chapfuura, synthesis example dhizaini ine jenareta yetraffic uye muenzaniso weiyo memory interface. Izvi zvinovharira kusarudzika kune abstract simulation modhi pazvinokodzera kukurumidza kutevedzera.
• Modhi yekurangarira, iyo inoshanda seyakajairwa modhi inoomerera kune ndangariro protocol yakatarwa. Kazhinji, vatengesi vekuyeuka vanopa mamodheru ekufananidza kune avo chaiwo endangariro zvikamu zvaunogona kudhawunirodha kubva kwavari webnzvimbo.
• Chitarisiko chekutarisa, chinotarisisa masiginecha kubva kune yekunze memory interface IP uye traffic jenareta, kuratidza kupasa kwese kana kutadza mamiriro.

Mufananidzo 8. Simulation Example Dhizaini

Kana iwe uri kushandisa iyo Ping Pong PHY chimiro, simulation example dhizaini inosanganisira maviri majenareta emotokari anoburitsa mirairo kune maviri akazvimirira endangariro zvishandiso kuburikidza neaviri akazvimirira controller uye yakajairika PHY, sezvakaratidzwa mumufananidzo unotevera.

Mufananidzo 9. Simulation Example Dhizaini yePing Pong PHY

Kana iwe uri kushandisa RLDRAM 3, iyo traffic jenareta mune yekufananidza example dhizaini inotaurirana zvakananga nePHY uchishandisa AFI, sezvakaratidzwa mumufananidzo unotevera.

Mufananidzo 10. Simulation Example Dhizaini yeRLDRAM 3 Interfaces

Related Information
Kugadzira iyo EMIF Dhizaini Example yeSimulation iri papeji 10

Example Dhizaini Interface Tab

Iyo parameter editor inosanganisira Example Dhizaini tab iyo inokutendera iwe kumisa uye kugadzira yako yekareample designs.l

Mufananidzo 11. Example Dhizaini Tab mune Yekunze Memory Interfaces Parameter Mharidzo

Inowanikwa Example Designs Chikamu
Iyo Sarudza dhizaini yekudhonza inobvumidza iwe kusarudza yaunoda example design. Parizvino, EMIF Example Dhizaini ndiyo yega sarudzo iripo, uye inosarudzwa neyakagadzika.

Gwaro Rekudzokorora Nhoroondo yeKunze Memory Interfaces Intel Arria 10 FPGA IP Dhizaini Example User Guide

Document Version	Intel Quartus Prime Version	Kuchinja
2021.03.29	21.1	• Mu Exampuye Dhizaina Kurumidza Kutanga chitsauko, yakabviswa mareferenzi kuNCSim* simulator.
2018.09.24	18.1	• Nhamba dzakavandudzwa mu Kugadzira iyo Synthesizable EMIF Dhizaini Example uye Kugadzira iyo EMIF Dhizaini Example for Simulation misoro.
2018.05.07	18.0	• Yakachinjwa zita regwaro kubva Intel Arria 10 Yekunze Memory Interfaces IP Dhizaini Example User Guide ku Yekunze Memory Interfaces Intel Arria 10 FPGA IP Dhizaini Example User Guide. • Mabullet mapoinzi akagadziriswa mu Overview chikamu che Pin Kuiswa kweIntel Arria 10 EMIF IP topic.

Date	Version	Kuchinja
Mbudzi 2017	2017.11.06	Kusunungurwa kwekutanga.

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• Mamwe mazita nemhando anogona kunzi zvinhu zvevamwe.

Zvinyorwa / Zvishandiso

intel UG-20118 Yekunze Memory Interfaces Arria 10 FPGA IP Dhizaini Example [pdf] Bhuku reMushandisi UG-20118 External Memory Interfaces Arria 10 FPGA IP Dhizaini Example, UG-20118, External Memory Interfaces Arria 10 FPGA IP Dhizaini Ex.ample, Interfaces Arria 10 FPGA IP Dhizaini Example, 10 FPGA IP Dhizaini Example

References

• User Manual