intel UG-20118 Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwaƙwa tọn ne na Ƙwa ) na 10 FPGAample

Zane ExampJagoran Farawa Mai sauri don Mutuwar Ƙwaƙwalwar Ƙwaƙwalwar Waje Intel® Arria® 10 FPGA IP

Wani sabon dubawa da ƙarin ƙira mai sarrafa kansa example kwarara yana samuwa don Intel® Arria® 10 na waje ƙwaƙwalwar musaya.
Example Designs shafin a cikin madaidaicin editan yana ba ku damar ƙirƙira ƙirƙira da simulation file saitin da za ku iya amfani da su don inganta EMIF IP ɗin ku.
Kuna iya haifar da example ƙira musamman don kayan haɓakawa na Intel FPGA, ko don kowane EMIF IP ɗin da kuke samarwa.

Hoto 1. Babban Zane Exampda Ayyukan Aiki

Zane Example

Hoto 2. Samar da EMIF ExampZayyana Tare da Kayan Ci gaba na Intel Arria 10

Kamfanin Intel. An kiyaye duk haƙƙoƙi. Intel, tambarin Intel, da sauran alamun Intel alamun kasuwanci ne na Kamfanin Intel Corporation ko rassan sa. Intel yana ba da garantin aikin FPGA da samfuran semiconductor zuwa ƙayyadaddun bayanai na yanzu daidai da daidaitaccen garanti na Intel amma yana da haƙƙin yin canje-canje ga kowane samfuri da sabis a kowane lokaci ba tare da sanarwa ba. Intel ba ya ɗaukar wani nauyi ko alhaki da ya taso daga aikace-aikacen ko amfani da kowane bayani, samfur, ko sabis da aka kwatanta a nan sai dai kamar yadda Intel ya yarda da shi a rubuce. An shawarci abokan cinikin Intel su sami sabon sigar ƙayyadaddun na'urar kafin su dogara ga kowane bayanan da aka buga kuma kafin sanya oda don samfur ko ayyuka.

• Ana iya da'awar wasu sunaye da alamun a matsayin mallakin wasu.

Ƙirƙirar Aikin EMIF

Don nau'in software na Intel Quartus® Prime 17.1 da kuma daga baya, dole ne ku ƙirƙiri aikin Intel Quartus Prime kafin samar da EMIF IP da ƙirar ƙira.ample.

1. Kaddamar da Intel Quartus Prime software kuma zaɓi File ➤ Sabon Mayen Aikin. Danna Gaba.
2. Ƙayyade adireshi da suna don aikin da kake son ƙirƙira. Danna Gaba.
3. Tabbatar da cewa an zaɓi aikin wofi. Danna gaba sau biyu.
4. A ƙarƙashin Tacewar Suna, rubuta lambar ɓangaren na'urar.
5. Ƙarƙashin na'urori masu samuwa, zaɓi na'urar da ta dace.
6. Danna Gama.

Ƙirƙirar da Ƙaddamar da EMIF IP

Matakan da ke gaba suna kwatanta yadda ake samarwa da daidaita IP ɗin EMIF. Matakan suna kama da juna ba tare da la'akari da ka'idar ƙwaƙwalwar ajiya da kuke niyya ba.

1. A cikin taga IP Catalog, zaɓi Intel Arria 10 External Memory Interfaces. (Idan ba a ganin taga IP Catalog, zaɓi View Mai amfani Windows ➤ IP Catalog.)
2. A cikin Editan Sigar IP, samar da sunan mahalli don EMIF IP (sunan da kuka bayar anan ya zama file suna don IP) kuma saka directory. Danna Ƙirƙiri.
3. Editan sigar yana da shafuka masu yawa inda dole ne ku saita sigogi don nuna aiwatar da EMIF ɗin ku:

Intel Arria 10 EMIF Jagorar Editan Madaidaicin

Tebur 1. Jagororin Editan Ma'auni na EMIF

Tab ɗin Editan Sigar	Jagorori
Gabaɗaya	Tabbatar cewa an shigar da sigogi masu zuwa daidai: • Matsayin saurin na'urar. • Mitar agogon ƙwaƙwalwar ajiya. • Mitar agogon PLL.
Ƙwaƙwalwar ajiya	Koma zuwa takardar bayanan don na'urar ƙwaƙwalwar ajiya don shigar da sigogi akan Ƙwaƙwalwar ajiya tab. • Hakanan ya kamata ku shigar da takamaiman wuri don fil ɗin ALERT#. (Ya shafi ka'idar ƙwaƙwalwar ajiyar DDR4 kawai.)
Mem I/O	• Don binciken aikin farko, zaku iya amfani da saitunan tsoho akan Mem I/O tab. • Don ingantaccen ingantaccen ƙira, yakamata ku yi simintin allo don samun mafi kyawun saitunan ƙarewa.
FPGA I/O	• Don binciken aikin farko, zaku iya amfani da saitunan tsoho akan FPGA I/O tab. • Don ingantacciyar ƙira ta ci gaba, yakamata ku yi kwaikwaiyon allo tare da samfuran IBIS masu alaƙa don zaɓar ƙa'idodin I/O masu dacewa.
Lokacin Mem	• Don binciken aikin farko, zaku iya amfani da saitunan tsoho akan Lokacin Mem tab. • Don ingantaccen ingantaccen ƙira, ya kamata ka shigar da sigogi bisa ga takardar bayanan na'urar ƙwaƙwalwar ajiya.
Hukumar	• Don binciken aikin farko, zaku iya amfani da saitunan tsoho akan Hukumar tab. Don ingantaccen ingantaccen ƙira da ingantaccen lokacin rufewa, ya kamata ku yi simulation na allo don samun ingantacciyar tsangwama (ISI)/take magana da allo da bayanan skew na fakiti, sannan shigar da shi akan Hukumar tab.
Mai sarrafawa	Saita sigogin mai sarrafawa bisa ga tsari da halin da ake so don mai sarrafa ƙwaƙwalwar ajiyar ku.
Bincike	Za ka iya amfani da sigogi a kan Bincike shafin don taimakawa wajen gwadawa da yin zamba a wurin ƙwaƙwalwar ajiyar ku.
Exampda Designs	The Exampda Designs tab zai baka damar samar da zane examples don kira da kuma kwaikwayo. Zane da aka samar example cikakken tsarin EMIF ne wanda ya ƙunshi EMIF IP da direban da ke haifar da zirga-zirgar ababen hawa don tabbatar da ƙirar ƙwaƙwalwar ajiya.

Don cikakkun bayanai kan sigogi guda ɗaya, koma zuwa babin da ya dace don ƙa'idar ƙwaƙwalwar ajiyar ku a cikin Jagorar Mai amfani ta IP na Intel Arria 10 External Memory Interfaces.

Ƙirƙirar EMIF Design Example

Don kayan haɓakawa na Intel Arria 10, akwai saiti waɗanda ke daidaita EMIF IP ta atomatik kuma suna samar da pinouts don takamaiman allo.

1. Tabbatar da cewa saitattun taga yana bayyane. Idan taga saitattun ba a bayyane, nuna shi ta zaɓi View ➤ Saita.
2. A cikin Saitattun taga, zaɓi saitin kayan haɓaka da ya dace kuma danna Aiwatar.
3. Sanya EMIF IP kuma danna Ƙirƙirar Example Zane a saman kusurwar dama na taga.
4. Ƙayyade kundin adireshi don ƙirar EMIF example kuma danna OK. Nasarar ƙarni na ƙirar EMIF example haifar da wadannan files karkashin Wii directory.

Hoto 3. Ƙirƙirar Ƙirƙirar Ƙira Example File Tsarin

Lura: Idan baku zaɓi Akwatin simulation ko Synthesis ba, kundin adireshin wurin zai ƙunshi ƙirar Platform Designer. files, wanda Intel Quartus Prime software ba ya haɗa kai tsaye, amma yana iya zama viewed ko gyara a ƙarƙashin Platform Designer. A wannan yanayin, zaku iya gudanar da umarni masu zuwa don samar da kira da kwaikwayo file sets.

• Don ƙirƙirar aikin da aka haɗa, dole ne ku gudanar da rubutun quartus_sh -t make_qii_design.tcl a cikin kundin adireshin wurin.
• Don ƙirƙirar aikin simulation, dole ne ku gudanar da rubutun quartus_sh -t make_sim_design.tcl a cikin kundin adireshin wurin.
• Rushe allon Zaɓin a cikin wannan sashe yana aiki daidai da ayyukan fitin kayan haɓaka haɓaka ga tsohonampzane.
• Wannan saitin yana samuwa ne kawai lokacin da ka kunna akwatin bincike na Synthesis a cikin Exampda Design Filesashen s.
• Dole ne wannan saitin ya dace da kayan haɓaka da aka yi amfani da su a yanzu, in ba haka ba saƙon kuskure ya bayyana.
• Idan darajar Babu ɗaya ta bayyana a cikin Zaɓin allo, yana nuna cewa zaɓin siga na yanzu bai yi daidai da kowane saitin kayan haɓakawa ba. Kuna iya amfani da ƙayyadaddun IP na kit ɗin haɓakawa da saitunan sigina masu alaƙa ta zaɓi ɗaya daga cikin saitattu daga ɗakin karatu da aka saita. Lokacin da kuka yi amfani da saiti, ana saita IP na yanzu da sauran saitunan sigina don dacewa da saitattun da aka zaɓa. Idan kana son adana saitunanka na yanzu, yakamata kayi haka kafin ka zaɓi saiti. Idan ka zaɓi saiti ba tare da adana saitunanka na farko ba, koyaushe zaka iya ajiye sabon saiti a ƙarƙashin wani suna daban
• Idan kana son samar da exampZane don amfani akan allon ku, saita Zaɓi allo zuwa Babu, haifar da tsohonample zane, sa'an nan kuma ƙara fil wurin takurawa.

Bayanai masu alaƙa

• Magana Example Zane a shafi na 17
• Intel Arria 10 EMIF Bayanin Sigar IP don DDR3
• Intel Arria 10 EMIF Bayanin Sigar IP don DDR4
• Intel Arria 10 EMIF Bayanin Sigar IP don QDRII/II+/Xtreme
• Intel Arria 10 EMIF Bayanin Sigar IP don QDR-IV
• Intel Arria 10 EMIF Bayanin Sigar IP don RLDRAM 3
• Intel Arria 10 EMIF Bayanin Sigar IP don LPDDR3

Samar da EMIF Design Example don Simulation

Don kayan haɓakawa na Intel Arria 10, akwai saiti waɗanda ke daidaita EMIF IP ta atomatik kuma suna samar da pinouts don takamaiman allo.

1. Tabbatar da cewa saitattun taga yana bayyane. Idan taga saitattun ba a bayyane, nuna shi ta zaɓi View ➤ Saita.
2. A cikin Saitattun taga, zaɓi saitin kayan haɓaka da ya dace kuma danna Aiwatar.
3. Sanya EMIF IP kuma danna Ƙirƙirar Example Zane a saman kusurwar dama na taga.
4. Ƙayyade kundin adireshi don ƙirar EMIF example kuma danna OK.

Nasarar ƙarni na ƙirar EMIF example halitta mahara file saiti don na'urori masu tallafi daban-daban, ƙarƙashin kundin adireshin sim/ed_sim.
Hoto 4. Ƙirƙirar Simulators Example File Tsarin

Lura: Idan baku zaɓi Akwatin simulation ko Synthesis ba, kundin adireshin wurin zai ƙunshi ƙirar Platform Designer. files, wanda Intel Quartus Prime software ba ya haɗa kai tsaye, amma yana iya zama viewed ko gyara a ƙarƙashin Platform Designer. A wannan yanayin zaka iya gudanar da umarni masu zuwa don samar da kira da simulation file sets.

• Don ƙirƙirar aikin da aka haɗa, dole ne ku gudanar da rubutun quartus_sh -t make_qii_design.tcl a cikin kundin adireshin wurin.
• Don ƙirƙirar aikin simulation, dole ne ku gudanar da rubutun quartus_sh -t make_sim_design.tcl a cikin kundin adireshin wurin.

Bayanai masu alaƙa

• Simulation Example Zane a shafi na 19
• Intel Arria 10 EMIF IP - Simulating Memory IP

Simulation Versus Hardware Aiwatar da

Don ƙirar ƙirar ƙwaƙwalwar waje ta waje, zaku iya zaɓar ko dai tsallake daidaitawa ko cikakken daidaitawa akan shafin bincike yayin tsara IP.
EMIF Model Simulators
Wannan tebur yana kwatanta halayen ƙetare calibration da cikakkun samfuran daidaitawa.
Tebur 2. Samfuran Kwaikwayo na EMIF: Tsallake Calibration tare da Cikakken Daidaitawa

Tsallake Calibration	Cikakken Daidaitawa
Simintin matakin-tsari yana mai da hankali kan dabarun mai amfani.	Ƙwaƙwalwar ƙirar ƙwaƙwalwar ajiya tana mai da hankali kan daidaitawa.
Ba a kama cikakkun bayanai na daidaitawa ba.	Kama duk stages of calibration.
ci gaba…

Tsallake Calibration	Cikakken Daidaitawa
Yana da ikon adanawa da dawo da bayanai.	Ya haɗa da daidaitawa, tebur kowane-bit, da sauransu.
Yana wakiltar ingantaccen aiki.
Baya la'akari da skew allon.

RTL Simulation Versus Hardware Aiwatar da
Wannan tebur yana nuna mahimman bambance-bambance tsakanin simintin EMIF da aiwatar da kayan masarufi.
Tebur 3. EMIF RTL Simulation Versus Hardware Aiwatar da

RTL Simulation	Aiwatar Hardware
Nios® farko da lambar daidaitawa suna aiki a layi daya.	Nios farawa da lambar daidaitawa suna aiwatar da bi-da-bi.
Hanyoyin sadarwa suna tabbatar da siginar cal_done a lokaci guda a cikin siminti.	Ayyukan fitter suna ƙayyade tsari na daidaitawa, kuma musaya ba sa tabbatar da cal_done a lokaci guda.

Ya kamata ku gudanar da simintin RTL bisa tsarin zirga-zirga don aikace-aikacen ƙirar ku. Lura cewa kwaikwaiyon RTL baya ƙirar PCB gano jinkiri wanda zai iya haifar da rashin daidaituwa tsakanin simintin RTL da aiwatar da hardware.

Simulating External Memory Interface IP Tare da ModelSim

Wannan hanya tana nuna yadda ake kwaikwayi ƙirar EMIF example.

1. Kaddamar da Mentor Graphics* ModelSim software kuma zaɓi File ➤ Canza Jagora. Kewaya zuwa sim/ed_sim/ directory directory a cikin ƙirar ƙira da aka ƙirƙiraampda folder.
2. Tabbatar cewa an nuna taga kwafin rubutu a ƙasan allon. Idan taga Rubutun ba a ganuwa, nuna shi ta dannawa View ➤ Kwafi.
3. A cikin Tagar Rubutun, gudanar da tushen msim_setup.tcl.
4. Bayan tushen msim_setup.tcl ya gama aiki, kunna ld_debug a cikin Tagar Rubutun.
5. Bayan ld_debug ya gama aiki, tabbatar da cewa an nuna taga abubuwan. Idan taga abubuwan ba a bayyane, nuna shi ta dannawa View ➤ Abubuwa.
6. A cikin taga abubuwan, zaɓi siginar da kuke son siffantawa ta danna dama kuma zaɓi Ƙara Wave.
7. Bayan kun gama zaɓar sigina don simulation, aiwatar da gudu-duk a cikin Tagar Rubutun. Simulation yana gudana har sai an kammala shi.
8. Idan ba'a ganin simintin, danna View ➤ Wave.

Bayanai masu alaƙa

Intel Arria 10 EMIF IP - Simulating Memory IP

Sanya Pin don Intel Arria 10 EMIF IP

Wannan batu yana ba da jagororin sanya fil.

Ƙarsheview

Intel Arria 10 FPGAs suna da tsari mai zuwa:

• Kowace na'ura ta ƙunshi ginshiƙan I/O 2.
• Kowane ginshiƙi na I/O ya ƙunshi har zuwa bankunan I/O guda 8.
• Kowane bankin I/O ya ƙunshi hanyoyi 4.
• Kowane layi yana ƙunshe da filoli 12 na gaba ɗaya I/O (GPIO).

Gabaɗaya Jagoran Pin

Abubuwan da ke gaba suna ba da jagororin fil gabaɗaya:

• Tabbatar cewa fil ɗin don ƙayyadaddun ƙayyadaddun ƙwaƙwalwar ajiyar waje suna zaune a cikin ginshiƙin I/O guda ɗaya.
• Hanyoyin sadarwa da suka mamaye bankuna da yawa dole ne su cika buƙatu masu zuwa:
  • Dole ne bankunan su kasance kusa da juna. Don bayani kan bankunan da ke kusa, koma zuwa Intel Arria 10 External Memory Interfaces IP Jagorar mai amfani.
  • Adireshin da bankin umarni dole ne su zauna a cikin babban bankin don rage jinkiri. Idan ƙwaƙwalwar ajiyar ƙwaƙwalwar ajiyar tana amfani da ko da adadin bankuna, adireshi da bankin umarni na iya zama a ɗayan bankunan tsakiya guda biyu.
• Ana iya amfani da fil ɗin da ba a yi amfani da su azaman maƙasudin I/O na gaba ɗaya.
• Duk adireshi da umarni da maƙalai masu alaƙa dole su zauna a cikin banki ɗaya.
• Adireshi da umarni da fil ɗin bayanai na iya raba banki a ƙarƙashin waɗannan sharuɗɗa:
  • Adireshi da umarni da fil ɗin bayanai ba za su iya raba layin I/O ba.
  • Hanyar I/O da ba a yi amfani da ita ba a cikin adireshi da bankin umarni kawai za a iya amfani da su don fil ɗin bayanai.

Tebur 4. Gabaɗaya Matsalolin Pin

Nau'in sigina	Takura
Data Strobe	Duk sigina na ƙungiyar DQ dole ne su kasance a cikin layin I/O iri ɗaya.
Bayanai	Maɓallan DQ masu alaƙa dole ne su kasance a cikin layin I/O iri ɗaya. Dole ne a haɗa fitilun DM/DBI tare da fil ɗin DQ don aikin da ya dace. Don ƙa'idodin da ba su goyan bayan layukan bayanai biyu ba, ya kamata a haɗa siginonin karantawa dabam daga siginar rubutawa.
Adireshi da Umurni	Adireshi da fil ɗin umarni dole ne su kasance a wuraren da aka ƙayyade a cikin bankin I/O.

Sanya Ayyuka
Idan kun yi amfani da saitin kayan haɓakawa yayin tsara IP, duk ayyukan fil na kayan haɓaka ana yin su ta atomatik kuma ana iya tantance su a cikin .qsf file wanda aka samar tare da zane example.

Bayanai masu alaƙa

• Intel Arria 10 EMIF IP DDR3
• Intel Arria 10 EMIF IP don DDR4
• Intel Arria 10 EMIF IP don QDRII/II+/Xtreme
• Intel Arria 10 EMIF IP don QDR-IV
• Intel Arria 10 EMIF IP don RLDRAM 3
• Intel Arria 10 EMIF IP don LPDDR3

Haɗa da Shirye-shiryen Intel Arria 10 EMIF Design Example

Bayan kun yi mahimman ayyukan fil a cikin .qsf file, za ku iya tattara zane exampa cikin Intel Quartus Prime software.

1. Kewaya zuwa babban fayil ɗin Intel Quartus Prime mai ɗauke da ƙira exampda directory.
2. Bude aikin Intel Quartus Prime file, (.qpf).
3. Don fara haɗawa, danna Gudanarwa ➤ Fara Tarin. Nasarar kammala tattarawa yana haifar da .sof file, wanda ke ba da damar ƙira don aiki akan kayan aiki.
4. Don tsara na'urarka tare da tsararrun ƙira, buɗe shirye-shiryen ta danna kayan aiki ➤ Programmer.
5. A cikin mai tsara shirye-shirye, danna Gane Auto don gano na'urori masu tallafi.
6. Zaɓi na'urar Intel Arria 10 sannan zaɓi Canji File.
7. Kewaya zuwa ed_synth.sof da aka samar file kuma zaɓi Buɗe.
8. Danna Fara don fara shirye-shiryen na'urar Intel Arria 10. Lokacin da aka yi nasarar tsara na'urar, maɓallin ci gaba a saman dama na taga ya kamata ya nuna 100% (Nasara).

Zazzagewar Intel Arria 10 EMIF Design Example

Ana samun kayan aikin gyara kuskure na EMIF don taimakawa wajen gyara ƙirar ƙirar ƙwaƙwalwar ajiyar waje. Kayan aikin kayan aiki yana ba ku damar nuna karantawa da rubuta tazara da samar da zane-zanen ido. Bayan kun tsara kayan haɓakawa na Intel Arria 10, zaku iya tabbatar da aikinsa ta amfani da EMIF Debug Toolkit.

1. Don ƙaddamar da EMIF Debug Toolkit, kewaya zuwa Kayan aiki ➤ Kayan aikin Gyaran Tsari ➤ Kayan aikin Interface Ƙwaƙwalwar Ƙwaƙwalwa na waje.
2. Danna Fara Haɗi.
3. Danna Haɗin Project zuwa na'urar. Taga yana bayyana; tabbatar da cewa an zaɓi na'urar da ta dace da kuma cewa daidai .sof file aka zaba.
4. Danna Ƙirƙirar Haɗin Ƙwaƙwalwar Ƙwaƙwalwa. Karɓi saitunan tsoho ta danna Ok.
5. An saita kayan haɓakawa na Intel Arria 10 don yin aiki tare da kayan aikin EMIF Debug Toolkit, kuma zaku iya samar da kowane ɗayan rahotanni masu zuwa ta danna sau biyu akan zaɓi mai dacewa:

• Sake kunna daidaitawa. Yana samar da rahoton daidaitawa wanda ke taƙaita matsayin daidaitawa ga ƙungiyar DQ/DQS tare da gefen kowane fil ɗin DQ/DQS.
• Direba Margining. Yana fitar da rahoto mai taƙaita karantawa da rubuta tazarar kowane fil I/O. Wannan ya sha bamban da maginin daidaitawa saboda ana kama alamar direba yayin zirga-zirgar yanayin mai amfani maimakon lokacin daidaitawa.
• Ƙirƙirar zanen Ido. Yana haifar da karantawa da rubuta zane-zanen ido don kowane fil ɗin DQ dangane da tsarin bayanan daidaitawa.
• Calibrate Ƙarshe. Yana share ƙima daban-daban na ƙarewa kuma yana ba da rahoton iyakokin da kowace ƙimar ƙarewa ke bayarwa. Yi amfani da wannan fasalin don taimakawa zaɓi mafi kyawun ƙarewa don haɗin ƙwaƙwalwar ajiya.

Zane ExampBayanin Mahimman Bayanan Ƙwaƙwalwar Ƙwaƙwalwar Waje na Intel Arria 10 FPGA IP

Lokacin da kuka ƙirƙira da samar da EMIF IP ɗinku, zaku iya tantance cewa tsarin yana ƙirƙirar kundayen adireshi don simulation da haɗawa. file sets, da kuma haifar da file saita ta atomatik. Idan ka zaɓi Simulation ko Synthesis a ƙarƙashin Exampda Design Files na Example Designs shafin, tsarin yana haifar da cikakken simulation file saita ko cikakken kira file saita, daidai da zaɓinku.

Magana Exampda Design

Haɗin kai example zane ya ƙunshi manyan tubalan da aka nuna a cikin hoton da ke ƙasa.

• Generator na zirga-zirga, wanda shine haɗakarwa Avalon®-MM exampdireban da ke aiwatar da tsarin bazuwar karantawa da rubutawa zuwa adadin adireshi masu ƙima. Har ila yau, janareta na zirga-zirgar ababen hawa yana lura da bayanan da aka karanta daga ƙwaƙwalwar ajiya don tabbatar da cewa sun yi daidai da rubutattun bayanan kuma yana tabbatar da gazawar in ba haka ba.
• Misali na hanyar sadarwa na ƙwaƙwalwar ajiya, wanda ya haɗa da:
  • Mai sarrafa ƙwaƙwalwar ajiya wanda ke daidaitawa tsakanin haɗin Avalon-MM da AFI.
  • PHY, wanda ke aiki azaman mu'amala tsakanin mai sarrafa ƙwaƙwalwar ajiya da na'urorin ƙwaƙwalwar ajiya na waje don aiwatar da ayyukan karatu da rubutu.

Hoto 5. Haɗin kai Exampda Design

Idan kuna amfani da fasalin Ping Pong PHY, haɗawar example zane ya ƙunshi janareta na zirga-zirga guda biyu waɗanda ke ba da umarni zuwa na'urorin ƙwaƙwalwar ajiya masu zaman kansu ta hanyar masu sarrafawa biyu masu zaman kansu da PHY gama gari, kamar yadda aka nuna a cikin adadi mai zuwa.

Hoto 6. Haɗin kai ExampZane don Ping Pong PHY

Idan kana amfani da RLDRAM 3, mai samar da zirga-zirgar ababen hawa a cikin haɗin kai example zane yana sadarwa kai tsaye tare da PHY ta amfani da AFI, kamar yadda aka nuna a cikin adadi mai zuwa.
Hoto 7. Haɗin kai ExampZane na RLDRAM 3 Interfaces

Lura: Idan ɗaya ko fiye na PLL Sharing Mode, DLL Sharing Mode, ko OCT Sharing Mode an saita zuwa kowace ƙima ban da Babu Sharing, haɗawar ex.ampTsarin zai ƙunshi janareta na zirga-zirgar ababen hawa/samfurin ƙwaƙwalwar ajiyar ƙwaƙwalwar ajiya. Misalan janareta na zirga-zirgar ababen hawa biyu/Misalan mu'amalar ƙwaƙwalwar ajiya suna da alaƙa kawai ta haɗin haɗin PLL/DLL/OCT kamar yadda saitunan sigina suka ayyana. Samfuran janareta na zirga-zirgar ababen more rayuwa/Misalan mu'amalar ƙwaƙwalwar ajiya suna nuna yadda zaku iya yin irin waɗannan haɗin gwiwa a cikin ƙirar ku.

Lura: Gudun haɗin haɗin ɓangare na uku kamar yadda aka bayyana a cikin Jagorar Mai amfani na Intel Quartus Prime Standard Edition: Ƙungiya ta ɓangare na uku ba ta da tallafi ga EMIF IP.
Bayanai masu alaƙa
Ƙirƙirar EMIF Design Example a shafi na 7

Simulation Exampda Design

Simulation example zane ya ƙunshi manyan tubalan da aka nuna a cikin wannan adadi.

• Misali na hadawa exampda zane. Kamar yadda aka bayyana a cikin sashin da ya gabata, haɗin example zane ya ƙunshi janareta na zirga-zirga da misalin ƙirar ƙwaƙwalwar ajiya. Waɗannan suna toshe tsoho zuwa ƙirar simintin ƙididdiga inda ya dace da saurin kwaikwayo.
• Samfurin ƙwaƙwalwar ajiya, wanda ke aiki azaman ƙirar ƙira wanda ke manne da ƙayyadaddun ƙayyadaddun ƙa'idar ƙwaƙwalwar ajiya. Yawancin lokaci, masu siyar da ƙwaƙwalwar ajiya suna ba da ƙirar simulation don takamaiman abubuwan ƙwaƙwalwar ajiya waɗanda zaku iya saukewa daga nasu webshafuka.
• Mai duba matsayi, wanda ke lura da siginonin matsayi daga keɓaɓɓiyar ƙwaƙwalwar ajiyar waje ta IP da janareta na zirga-zirga, don siginar wucewa gaba ɗaya ko yanayin gazawa.

Hoto 8. Kwaikwayo Exampda Design

Idan kana amfani da fasalin Ping Pong PHY, simulation example zane ya ƙunshi janareta na zirga-zirga guda biyu waɗanda ke ba da umarni zuwa na'urorin ƙwaƙwalwar ajiya masu zaman kansu ta hanyar masu sarrafawa biyu masu zaman kansu da PHY gama gari, kamar yadda aka nuna a cikin adadi mai zuwa.

Hoto 9. Kwaikwayo ExampZane don Ping Pong PHY

Idan kana amfani da RLDRAM 3, mai samar da zirga-zirga a cikin simulation example zane yana sadarwa kai tsaye tare da PHY ta amfani da AFI, kamar yadda aka nuna a cikin adadi mai zuwa.

Hoto 10. Kwaikwayo ExampZane na RLDRAM 3 Interfaces

Bayanai masu alaƙa
Samar da EMIF Design Example don Simulation a shafi na 10

Exampda Designs Interface Tab

Editan sigar ya haɗa da Example Designs tab wanda ke ba ku damar daidaitawa da samar da tsohon kuampda zane-zane.l

Hoto 11. ExampZayyana Tab a cikin Editan Sigar Ma'aunin Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwa

Akwai ExampSashen Zane-zane
Zaɓin ƙirar ƙira yana ba ku damar zaɓar tsohon da ake soampda zane. A halin yanzu, EMIF ExampLe Design shine kawai zaɓi na samuwa, kuma an zaɓa ta tsohuwa.

Tarihin Bita na Takardu don Mutuwar Ƙwaƙwalwar Waje ta Intel Arria 10 FPGA IP Design ExampJagorar Mai Amfani

Sigar Takardu	Intel Quartus Prime Version	Canje-canje
2021.03.29	21.1	• A cikin Exampda Design Quick Start babi, cire nassoshi zuwa na'urar kwaikwayo ta NCsim*.
2018.09.24	18.1	• Sabbin alkaluma a cikin Ƙirƙirar EMIF Design Example kuma Samar da EMIF Design Example don Simulation batutuwa.
2018.05.07	18.0	• Canza taken daftarin aiki daga Intel Arria 10 Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararriyar IP ExampJagorar Mai Amfani ku Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Waje ta Intel Arria 10 FPGA IP Design ExampJagorar Mai Amfani. • Madaidaitan harsashi a cikin Ƙarsheview sashe na Sanya Pin don Intel Arria 10 EMIF IP batu.

Kwanan wata	Sigar	Canje-canje
Nuwamba 2017	2017.11.06	Sakin farko.

Kamfanin Intel. An kiyaye duk haƙƙoƙi. Intel, tambarin Intel, da sauran alamun Intel alamun kasuwanci ne na Kamfanin Intel Corporation ko rassan sa. Intel yana ba da garantin aiwatar da samfuran FPGA da semiconductor zuwa ƙayyadaddun bayanai na yanzu daidai da daidaitaccen garanti na Intel, amma yana da haƙƙin yin canje-canje ga kowane samfuri da sabis a kowane lokaci ba tare da sanarwa ba. Intel ba ya ɗaukar wani nauyi ko alhaki da ya taso daga aikace-aikacen ko amfani da kowane bayani, samfur, ko sabis da aka kwatanta a nan sai dai kamar yadda Intel ya yarda da shi a rubuce. An shawarci abokan cinikin Intel su sami sabon sigar ƙayyadaddun na'urar kafin su dogara ga kowane bayanan da aka buga kuma kafin sanya oda don samfur ko ayyuka.

• Ana iya da'awar wasu sunaye da alamun a matsayin mallakin wasu.

Takardu / Albarkatu

intel UG-20118 Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwaƙwa tọn ne na Ƙwa ) na 10 FPGAample [pdf] Jagorar mai amfani UG-20118 Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwaƙwalwa na Ƙwaƙwalwa na Ƙwaƙwalwa na Ƙwaƙwalwa ) 10 FPGA XNUMX FPGAample, UG-20118, Mahimman Bayanan Ƙwaƙwalwar Ƙwaƙwalwar Waje Arria 10 FPGA IP Design Example, Mutunan Sadarwa Arria 10 FPGA IP Design Example, 10 FPGA IP Design Example

Magana

• Manual mai amfani