Intel MAX 10 FPGA Zida Pa UART yokhala ndi Nios II processor

Zambiri Zamalonda

Mapangidwe amawu amapereka ntchito yosavuta yomwe imagwiritsa ntchito zoyambira zakutali mumayendedwe a Nios II a zida za MAX 10 FPGA. Mawonekedwe a UART omwe akuphatikizidwa mu MAX 10 FPGA Development Kit amagwiritsidwa ntchito limodzi ndi Altera UART IP core kuti apereke magwiridwe antchito akutali. Zipangizo za MAX10 FPGA zimapereka kuthekera kosunga mpaka zithunzi ziwiri zosinthira zomwe zimapititsa patsogolo mawonekedwe akutali.

Chidule cha mawu

Chidule	Kufotokozera
Avalon-MM	Avalon Memory-Mapped Configuration Flash memory
CFM	Mawonekedwe a ogwiritsa ntchito
Mtengo wa ICB	Initialization Configuration Bit
MAP/.mapu	Memory Mapu File
Nios II EDS	Nios II Embedded Design Suite Support
PFL	Parallel Flash Loader IP pachimake
POF/.pof	Pulogalamu ya Pulogalamu File
Mtengo wa QSPI	Quad serial peripheral interface
RPD/.rpd	Zambiri zamapulogalamu
Mtengo wa SBT	Zida Zopangira Mapulogalamu
SOF/.sof	Ntchito ya SRAM File
NGOLI	Universal asynchronous receiver/transmitter
UFM	Ogwiritsa flash memory

Malangizo Ogwiritsira Ntchito Zogulitsa

Chofunikira

Kugwiritsa ntchito kalembedwe kameneka kumafuna kuti mukhale ndi chidziwitso kapena chidziwitso m'magawo otsatirawa:

Zofunikira:

Zotsatirazi ndi zofunika pa hardware ndi mapulogalamu pakupanga maumboni:

Reference Design Files

File Dzina	Kufotokozera
Factory_image	Mumitundu iwiri yosinthira zithunzi, CFM1 ndi CFM2 amaphatikizidwa kukhala chosungira chimodzi cha CFM.
app_image_1	Quartus II hardware design file zomwe zimalowa m'malo app_image_2 pakusintha kwadongosolo lakutali.
app_image_2	Nambala ya pulogalamu ya Nios II imakhala ngati wowongolera dongosolo lokwezera kutali.
Remote_system_upgrade.c
factory_application1.pof	Pulogalamu ya Quartus II file zomwe zimakhala ndi fakitale fano ndi chithunzi chogwiritsira ntchito 1, kuti chisankhidwe kukhala CFM0 ndi CFM1 & CFM2 motsatana koyambirira kwa stage.
factory_application1.rpd
application_image_1.rpd
application_image_2.rpd
Nios_application.pof

Kapangidwe kazofotokozera kumapereka ntchito yosavuta yomwe imagwiritsa ntchito zoyambira zakutali mumayendedwe a Nios II a zida za MAX 10 FPGA. Mawonekedwe a UART omwe akuphatikizidwa mu MAX 10 FPGA Development Kit amagwiritsidwa ntchito limodzi ndi Altera UART IP core kuti apereke magwiridwe antchito akutali.

Zambiri Zogwirizana

Reference Design Files

Kukwezera Kwakutali Kwambiri ndi MAX 10 FPGA Overview

Ndi mawonekedwe okweza makina akutali, zowonjezera ndi kukonza zolakwika pazida za FPGA zitha kuchitika patali. M'malo ophatikizidwa, firmware iyenera kusinthidwa pafupipafupi pamitundu yosiyanasiyana ya protocol, monga UART, Ethernet, ndi I2C. Pamene dongosolo lophatikizidwa likuphatikiza FPGA, zosintha za firmware zingaphatikizepo zosintha za chithunzi cha hardware pa FPGA.
Zipangizo za MAX10 FPGA zimapereka kuthekera kosunga mpaka zithunzi ziwiri zosinthira zomwe zimapititsa patsogolo mawonekedwe akutali. Chimodzi mwazithunzizo chidzakhala chithunzi chakumbuyo chomwe chakwezedwa ngati cholakwika chikuchitika pachithunzichi.

Chidule cha mawu

Gulu 1: Mndandanda wa Mafupipafupi

Kufotokozera Mwachidule
Avalon-MM	Avalon Memory-Mapu
CFM	Kusintha kwa flash memory
GUI	Mawonekedwe a ogwiritsa ntchito
Mtengo wa ICB	Initialization Configuration Bit
MAP/.mapu	Memory Mapu File
Nios II EDS	Nios II Embedded Design Suite Support
PFL	Parallel Flash Loader IP pachimake
POF/.pof	Pulogalamu ya Pulogalamu File

• Malingaliro a kampani Intel Corporation Maumwini onse ndi otetezedwa. Intel, logo ya Intel, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus ndi Stratix mawu ndi logo ndi zizindikiro za Intel Corporation kapena mabungwe ake ku US ndi/kapena mayiko ena. Intel imatsimikizira kugwira ntchito kwa FPGA yake ndi zida za semiconductor malinga ndi zomwe zili pano malinga ndi chitsimikizo cha Intel, koma ili ndi ufulu wosintha zinthu ndi ntchito zilizonse nthawi iliyonse popanda kuzindikira. Intel sakhala ndi udindo kapena udindo chifukwa cha kugwiritsa ntchito kapena kugwiritsa ntchito zidziwitso zilizonse, malonda, kapena ntchito zomwe zafotokozedwa pano kupatula monga momwe Intel adavomerezera momveka bwino. Makasitomala a Intel amalangizidwa kuti apeze mtundu waposachedwa kwambiri wamakina a chipangizocho asanadalire zidziwitso zilizonse zosindikizidwa komanso asanayike maoda azinthu kapena ntchito.
• Mayina ena ndi mtundu zitha kunenedwa kuti ndi za ena.

Chofunikira

Chidule Mtengo wa QSPI	Kufotokozera Quad serial peripheral interface
RPD/.rpd	Zambiri zamapulogalamu
Mtengo wa SBT	Zida Zopangira Mapulogalamu
SOF/.sof	Ntchito ya SRAM File
UART	Universal asynchronous receiver/transmitter
UFM	Ogwiritsa flash memory

Chofunikira

• Kugwiritsa ntchito kalembedwe kameneka kumafuna kuti mukhale ndi chidziwitso kapena chidziwitso m'magawo otsatirawa:
• Chidziwitso chogwira ntchito cha machitidwe a Nios II ndi zida zopangira. Machitidwe ndi zida izi zikuphatikiza pulogalamu ya Quartus® II, Qsys, ndi Nios II EDS.
• Kudziwa njira zosinthira za Intel FPGA ndi zida, monga kasinthidwe kamkati ka MAX 10 FPGA, mawonekedwe okweza makina akutali ndi PFL.

Zofunikira

• Zotsatirazi ndi zofunika pa hardware ndi mapulogalamu pakupanga maumboni:
• Zida zachitukuko za MAX 10 FPGA
• Mtundu wa Quartus II 15.0 wokhala ndi Nios II EDS
• Kompyuta yokhala ndi dalaivala ya UART yogwira ntchito komanso mawonekedwe
• Binary/hexadecimal iliyonse file mkonzi

Reference Design Files

Gulu 2: Kupanga Files Kuphatikizidwa mu Reference Design

File Dzina Factory_image	Kufotokozera • Mapangidwe a hardware a Quartus II file kusungidwa kwa CFM0. • The fallback chifaniziro / fakitale kuti ntchito pamene cholakwika zimachitika ntchito fano download.
app_image_1	• Mapangidwe a hardware a Quartus II file kusungidwa mu CFM1 ndi CFM2.(1) • The koyamba ntchito fano yodzaza mu chipangizo.

1. Mumitundu iwiri yosinthira zithunzi, CFM1 ndi CFM2 zimaphatikizidwa kusungirako imodzi ya CFM.

File Dzina app_image_2	Kufotokozera Quartus II hardware design file zomwe zimalowa m'malo app_image_2 panthawi yokweza makina akutali.
Remote_system_ upgrade.c	Nambala ya pulogalamu ya Nios II yomwe imagwira ntchito ngati woyang'anira pakupanga makina okweza akutali.
Remote Terminal.exe	• Zotheka file ndi GUI. • Imagwira ntchito ngati malo opangira alendo kuti azitha kulumikizana ndi zida zachitukuko za MAX 10 FPGA. • Kutumiza deta yamapulogalamu kudzera mu UART. • Khodi yochokera kwa terminal iyi ikuphatikizidwa.

Gulu 3: Mphunzitsi Files Kuphatikizidwa mu Reference Design

Mutha kugwiritsa ntchito izi master files pakupanga kwachidziwitso popanda kupanga mapangidwe files.

File Dzina   factory_application1.pof factory_application1.rpd	Kufotokozera Pulogalamu ya Quartus II file chomwe chili ndi chithunzi cha fakitale ndi mawonekedwe 1, kuti apangidwe kukhala CFM0 ndi CFM1 & CFM2 motsatana poyambiratage.
factory_application2.pof factory_application2.rpd	• Mapulogalamu a Quartus II file zomwe zimakhala ndi chithunzi cha fakitale ndi chithunzi cha ntchito 2. • Chithunzi cha pulogalamu 2 chidzachotsedwa pambuyo pake kuti chilowe m'malo mwa chithunzi 1 pakusintha makina akutali, otchedwa application_ image_2.rpd pansipa.
application_image_1.rpd	Quartus II yaiwisi mapulogalamu a data file zomwe zili ndi chithunzi cha pulogalamu 1 yokha.
application_image_2.rpd	Quartus II yaiwisi mapulogalamu a data file yomwe ili ndi chithunzi cha pulogalamu 2 yokha.
Nios_application.pof	• Kukonza mapulogalamu file yomwe ili ndi pulogalamu ya Nios II processor application .hex file kokha. • Kuti ikonzedwe kukhala kung'anima kwa QSPI yakunja.
pfl.sof	• Quartus II .sof zomwe zili ndi PFL. • Yakonzedwa mu QSPI flash pa MAX 10 FPGA Development kit.

Reference Design Functional Description

Nios II Gen2 purosesa

• Purosesa ya Nios II Gen2 pamapangidwe amawu ili ndi ntchito zotsatirazi:
• Katswiri wa basi yemwe amayang'anira ntchito zonse zolumikizirana ndi Altera On-Chip Flash IP core kuphatikiza kuwerenga, kulemba, ndi kufufuta.
• Amapereka ma aligorivimu mu pulogalamu kuti alandire pulogalamu yotsatsira kuchokera pakompyuta yolandila ndikuyambitsa kukonzanso kudzera pa Dual Configuration IP core.
• Muyenera kukhazikitsanso vekitala ya purosesa moyenerera. Izi ndikuwonetsetsa kuti purosesa imagwiritsa ntchito nambala yoyenera kuchokera ku UFM kapena kung'anima kwa QSPI.
• Zindikirani: Ngati nambala yofunsira ya Nios II ndi yayikulu, Intel ikulimbikitsa kuti musunge khodi ya pulogalamuyo mu flash ya QSPI yakunja. M'mapangidwe awa, vesi lokhazikitsiranso likulozera ku flash ya QSPI yakunja komwe code ya Nios II imasungidwa.

Zambiri Zogwirizana

• Maphunziro a Nios II Gen2 Hardware Development
• Amapereka zambiri zakupanga Nios II Gen2 purosesa.

Altera On-Chip Flash IP Core

• Altera On-Chip Flash IP core imagwira ntchito ngati mawonekedwe a purosesa ya Nios II kuti iwerenge, kulemba kapena kufufuta ntchito ku CFM ndi UFM. Altera On-Chip Flash IP core imakupatsani mwayi wofikira, kufufuta ndikusintha CFM ndi njira yatsopano yosinthira. Altera On-Chip Flash IP parameter mkonzi amawonetsa maadiresi omwe adakonzedweratu pagawo lililonse la kukumbukira.

Zambiri Zogwirizana

• Altera On-Chip Flash IP Core
• Amapereka zambiri za Altera On-Chip Flash IP Core.

Altera Dual Configuration IP Core

• Mutha kugwiritsa ntchito Altera Dual Configuration IP pachimake kuti mupeze cholumikizira chakutali pazida za MAX 10 FPGA. Altera Dual Configuration IP core imakulolani kuti muyambitse kukonzanso chithunzi chatsopano chikatsitsidwa.

Zambiri Zogwirizana

• Altera Dual Configuration IP Core
• Amapereka zambiri za Altera Dual Configuration IP Core

Kusintha UART IP Core

• Choyambira cha UART IP chimalola kulumikizana kwa mitsinje yamtundu wa serial pakati pa makina ophatikizidwa mu MAX 10 FPGA ndi chida chakunja. Monga mbuye wa Avalon-MM, purosesa ya Nios II imalumikizana ndi UART IP core, yomwe ndi kapolo wa Avalon-MM. Kuyankhulana uku kumachitika powerenga ndi kulemba zowongolera ndi zolembera za data.
• Pachimake chimagwiritsa ntchito nthawi ya protocol ya RS-232 ndipo imapereka izi:
• kusintha kwa baud, kufanana, kuyimitsa, ndi ma data bits
• zowongolera zowongolera za RTS/CTS

Zambiri Zogwirizana

• Mtengo wa UART Core
• Amapereka zambiri za UART Core.

Generic Quad SPI Controller IP Core

• Generic Quad SPI Controller IP core imagwira ntchito ngati mawonekedwe pakati pa MAX 10 FPGA, kuwala kwakunja ndi kung'anima kwa QSPI. Pakatikati imapereka mwayi wofikira kuwunikira kwa QSPI kudzera pakuwerenga, kulemba ndi kufufuta ntchito.
  Ntchito ya Nios II ikakula ndi malangizo ambiri, fayilo ya file kukula kwa hex file opangidwa kuchokera ku Nios II ntchito idzakhala yokulirapo. Kupitilira malire a kukula kwake, UFM sikhala ndi malo okwanira kusunga hex yofunsira file. Kuti muthane ndi izi, mutha kugwiritsa ntchito kuwala kwakunja kwa QSPI komwe kumapezeka pa MAX 10 FPGA Development kit kusunga hex ya application. file.

Nios II EDS Software Application Design

• Kapangidwe kazowunikira kumaphatikizapo nambala yogwiritsira ntchito pulogalamu ya Nios II yomwe imayang'anira kamangidwe kadongosolo kakutali. Nambala yogwiritsira ntchito pulogalamu ya Nios II imayankhidwa kumalo osungira alendo kudzera mu UART popereka malangizo enieni.

Kusintha Zithunzi Zapulogalamu Patali

• Mutatha kufalitsa pulogalamu yaying'ono file pogwiritsa ntchito Remote Terminal, pulogalamu ya Nios II idapangidwa kuti muchite izi:

1. Khazikitsani Register ya Altera On-Chip Flash IP core Control Register kuti musateteze gawo la CFM1 & 2.
2. Chitani ntchito yochotsa gawo pa CFM1 ndi CFM2. Mapulogalamuwa amasankha kaundula wa Altera On-Chip Flash IP core kuwonetsetsa kuti kufafanizidwa kwatha.
3. Landirani ma byte 4 a bit stream nthawi imodzi kuchokera ku stdin. Zowonjezera ndi zotuluka zingagwiritsidwe ntchito kulandira deta molunjika kuchokera ku malo osungira ndikusindikiza zotulukapo. Mitundu ya njira zolowera ndi zotuluka zitha kukhazikitsidwa kudzera mu BSP Editor mu chida cha Nios II Eclipse Build.
4. Imabweza kuyitanitsa pang'ono pa baiti iliyonse.
   • Zindikirani: Chifukwa cha kasinthidwe ka Altera On-Chip Flash IP Core, byte iliyonse ya data iyenera kusinthidwa musanalembe mu CFM.
5. Yambani kulemba ma byte anayi a data nthawi imodzi mu CFM4 ndi CFM1. Izi zikupitilira mpaka kumapeto kwa pulogalamu yotsitsa pang'ono.
6. Imavotera mbiri ya Altera On-Chip Flash IP kuti iwonetsetse kuti ntchito yolemba ikugwira bwino. Imauza uthenga wosonyeza kuti kutumiza kwatha.
   • Zindikirani: Ntchito yolemba ikalephera, terminal imayimitsa njira yotumizira ndikutulutsa uthenga wolakwika.
7. Imakhazikitsa Control Register kuti itetezenso CFM1 ndi CFM2 kuti mupewe kulemba kosafunikira.

Zambiri Zogwirizana

• pof Generation kudzera pa Convert Programming Files pa
• Amapereka chidziwitso chopanga rpd files pakusintha mapulogalamu files.

Kuyambitsa Kukonzanso Kutali

• Mukasankha kuyambitsanso kukonzanso koyambitsanso pa Remote Terminal, pulogalamu ya Nios II ichita izi:

1. Landirani lamulo kuchokera kumayendedwe okhazikika.
2. Yambitsani kukonzanso ndi ntchito ziwiri zotsatirazi:

• Lembani 0x03 ku adilesi yochotsera 0x01 mu Dual Configuration IP pachimake. Opareshoni iyi imachotsa pini yakuthupi ya CONFIG_SEL ndikuyika Chithunzi 1 ngati chithunzi chotsatira chosinthira boot.
• Lembani 0x01 ku adilesi yochotsera 0x00 mu Dual Configuration IP pachimake. Opareshoniyi imayambitsa kukonzanso ku chithunzi cha pulogalamu mu CFM1 ndi CFM2

Reference Design Walkthrough

Kupanga Mapulogalamu Files

• Muyenera kupanga mapulogalamu otsatirawa files musanagwiritse ntchito kukweza kwakutali pa MAX 10 FPGA Development kit:

Kwa QSPI Programming:

• sof - kugwiritsa ntchito pfl.sof ikuphatikizidwa muzojambula kapena mukhoza kusankha kupanga .sof yosiyana yomwe ili ndi mapangidwe anu a PFL
• pof - kasinthidwe file opangidwa kuchokera ku .hex ndikusinthidwa mu QSPI flash.
• Za Remote System Upgrade:
• pof - kasinthidwe file opangidwa kuchokera ku .sof ndipo amapangidwa mu kung'anima kwamkati.
• rpd - ili data ya kung'anima kwamkati komwe kumaphatikizapo zoikamo za ICB, CFM0, CFM1 ndi UFM.
• mapu-amagwira adilesi ya gawo lililonse lokumbukira la zoikamo za ICB, CFM0, CFM1 ndi UFM.

Kupanga files kwa QSPI Programming

Kupanga .pof file pa pulogalamu ya QSPI, chitani izi:

1. Pangani Nios II Project ndikupanga HEX file.
   • Zindikirani: Onani AN730: Njira Zoyambira za Nios II processor mu MAX 10 zida kuti mudziwe zambiri zomanga pulojekiti ya Nios II ndikupanga HEX file.
2. Pa File menyu, dinani Convert Programming Files.
3. Pansi Pulogalamu ya Output file, sankhani Programmer Object File (.pof) mu Programming file lembani mndandanda.
4. Pamndandanda wa Mode, sankhani 1-bit Passive seri.
5. Pamndandanda wa zida zosinthira, sankhani CFI_512Mb.
6. Mu File dzina bokosi, tchulani file dzina la pulogalamuyo file mukufuna kupanga.
7. Mukulowetsa files kutembenuza mndandanda, chotsani Zosankha ndi mzere wa data wa SOF. Dinani Onjezani Hex Data ndipo bokosi la dialog la Add Hex Data likuwonekera. Mu Add Hex Data bokosi, kusankha Mtheradi adiresi ndi kuika .hex file zopangidwa kuchokera ku Nios II EDS Build Tools.
8. Zikhazikiko zonse zikakhazikitsidwa, dinani Pangani kuti mupange mapulogalamu ofananira file.

Zambiri Zogwirizana

AN730: Njira Zoyambira za Nios II mu MAX 10 FPGA Zida
Kupanga files kwa Remote System Mokweza

Kupanga .pof, .map ndi .rpd files pakukweza kwakutali, chitani izi:

1. Bwezerani Factory_image, application_image_1 ndi application_image_2, ndikuphatikiza mapangidwe onse atatu.
2. Pangani awiri .pof filezafotokozedwa patebulo ili:
   • Zindikirani: Onani .po Generation through Convert Programming Files kwa masitepe pakupanga .pof files.
3. Tsegulani app2.rpd pogwiritsa ntchito mkonzi uliwonse wa hex.
4. Mu hex editor, sankhani chipika cha data cha binary potengera chiyambi ndi mapeto potengera .map file. Kuyamba ndi kutsiriza kwa chipangizo cha 10M50 ndi 0x12000 ndi 0xB9FFF motsatira. Lembani chipikachi kukhala chatsopano file ndi kusunga mu .rpd ina file. .rpd yatsopanoyi file ili ndi chithunzi cha pulogalamu 2 yokha.

pof Generation kudzera pa Convert Programming Files

Kutembenuza .sof files ku .pof files, tsatirani izi:

1. Pa File menyu, dinani Convert Programming Files.
2. Pansi Pulogalamu ya Output file, sankhani Programmer Object File (.pof) mu Programming file lembani mndandanda.
3. M'ndandanda wa Mawonekedwe, sankhani Kukonzekera Kwamkati.
4. Mu File dzina bokosi, tchulani file dzina la pulogalamuyo file mukufuna kupanga.
5. Kuti mupange Memory Map File (.map), yatsani Mapu a Memory Memory File (Pangani zotuluka zokha_file.mapu). Mapu a .map ali ndi adilesi ya CFM ndi UFM yokhala ndi makonda a ICB omwe mumakhazikitsa njira ya Option/Boot Info.
6.  Kuti mupange Raw Programming Data (.rpd), yatsani Pangani config data RPD (Generate output_file_auto.rpd).
   Mothandizidwa ndi Memory Map File, mutha kuzindikira mosavuta deta ya chipika chilichonse chogwira ntchito mu .rpd file. Muthanso kuchotsa zidziwitso zowunikira pazida zopangira mapulogalamu ena kapena kusintha masinthidwe kapena deta ya ogwiritsa ntchito kudzera pa Altera On-Chip Flash IP.
7. The .sof ikhoza kuwonjezeredwa kudzera mu Input files kutembenuza mndandanda ndipo mukhoza kuwonjezera kwa awiri .sof files.
   • Pazofuna zokwezera zakutali, mutha kusunga tsamba loyambirira 0 mu .pof, ndikusintha tsamba 1 ndi .sof yatsopano. file. Kuti muchite izi, muyenera kuwonjezera .pof file mu tsamba 0, ndiye
     add .sof page, kenaka yikani latsopano .sof file ku
8. Zikhazikiko zonse zikakhazikitsidwa, dinani Pangani kuti mupange mapulogalamu ofananira file.

Kusintha kwa mtengo wa QSPI

Kuti mukonze khodi ya Nios II mu QSPI flash, chitani izi:

1. Pa MAX 10 FPGA Development Kit, sinthani MAX10_BYPASSn kukhala 0 kuti mulambalale chida cha VTAP (MAX II).
2. Lumikizani Chingwe Chotsitsa cha Intel FPGA (kale USB Blaster) ku JTAG mutu.
3. Pazenera la Programmer, dinani Kukhazikitsa kwa Hardware ndikusankha USB Blaster.
4. Pa mndandanda wa Mode, sankhani JTAG.
5. Dinani batani la Auto Detect pagawo lakumanzere.
6. Sankhani chipangizo kuti akonze, ndipo dinani Add File.
7. Sankhani pfl.sof.
8. Dinani Start kuyambitsa mapulogalamu.
9. Kukonzekera kukachita bwino, popanda kuzimitsa bolodi, dinani batani la Auto Detect kumanzere kumanzere kachiwiri. Mudzawona kung'anima kwa QSPI_512Mb kuwonekera pazenera la mapulogalamu.
10. Sankhani chipangizo cha QSPI, ndikudina Add File.
11. Sankhani .pof file zopangidwa kale kuchokera ku .hex file.
12. Dinani Start kuti muyambe kukonza flash ya QSPI.

Kukonza FPGA ndi Chithunzi Choyambirira pogwiritsa ntchito JTAG

Muyenera kukhazikitsa app1.pof mu FPGA ngati chithunzi choyambirira cha chipangizocho. Kuti mutsegule app1.pof mu FPGA, chitani izi:

1. Pazenera la Programmer, dinani Kukhazikitsa kwa Hardware ndikusankha USB Blaster.
2. Pa mndandanda wa Mode, sankhani JTAG.
3. Dinani batani la Auto Detect pagawo lakumanzere.
4. Sankhani chipangizo kuti akonze, ndipo dinani Add File.
5. Sankhani app1.pof.
6. Dinani Start kuyambitsa mapulogalamu.

Kusintha Zithunzi ndi Kuyambitsa Kusinthanso pogwiritsa ntchito UART

Kuti mukonze zida zanu zachitukuko za MAX10 FPGA, chitani izi:

1. Zindikirani: Musanayambe, onetsetsani zotsatirazi:
   • pini ya CONFIG_SEL pa bolodi yakhazikitsidwa ku 0
   • doko la UART la board yanu lilumikizidwa ndi kompyuta yanu
   • Tsegulani Remote Terminal.exe ndipo mawonekedwe a Remote Terminal amatsegula.
2. Dinani Zikhazikiko ndi seri doko zoikamo zenera adzaoneka.
3. Khazikitsani magawo a terminal yakutali kuti agwirizane ndi zosintha za UART zosankhidwa mu Quartus II UART IP core. Mukamaliza kukhazikitsa, dinani Chabwino.
4. Dinani batani la nCONFIG pa zida zachitukuko kapena kiyi-mu 1 mubokosi la Tumizani, ndikugunda Lowani.
   • Mndandanda wa zosankha zogwirira ntchito udzawonekera pa terminal, monga momwe zilili pansipa:
   • Zindikirani: Kuti musankhe opareshoni, lowetsani nambala yomwe ili m'bokosi la Send text, ndiyeno dinani Enter.
5. Kuti musinthe chithunzi cha pulogalamu 1 ndi chithunzi cha pulogalamu 2, sankhani opareshoni 2. Mudzauzidwa kuti muyike adilesi yoyambira ndi yomaliza ya CFM1 ndi CFM2.
   • Zindikirani: Adilesi yowonetsedwa pamapu file imaphatikizapo zoikamo za ICB, CFM ndi UFM koma Altera On-Chip
   • Flash IP imatha kupeza CFM ndi UFM kokha. Chifukwa chake, pali ma adilesi osinthira pakati pa adilesi yomwe ili pamapu file ndi Altera On-Chip Flash IP parameter zenera.
6. Tsegulani adilesi kutengera adilesi yomwe yafotokozedwa ndi zenera la Altera On-Chip Flash IP.
   • Kufufuta kudzayamba zokha mukalowetsa adilesi yomaliza.
7. Mukafufuta bwino, mudzauzidwa kuti mulowetse mapulogalamu a .rpd file za ntchito chithunzi 2.
   • Kuti mukweze chithunzi, dinani SendFile batani, ndiyeno sankhani .rpd yomwe ili ndi chithunzi cha pulogalamu 2 yokha ndikudina Tsegulani.
   • Zindikirani: Kupatulapo chithunzi cha pulogalamu 2, mutha kugwiritsa ntchito chithunzi chilichonse chatsopano chomwe mukufuna kusintha mu chipangizocho.
   • Zosintha zidzayamba mwachindunji ndipo mutha kuyang'anira momwe zikuyendera kudzera pa terminal. Menyu ya opareshoni ipangitsa kuti Zachitika ndipo mutha kusankha ntchito ina.
8. Kuti muyambitse kukonzanso, sankhani ntchito 4. Mutha kuwona mawonekedwe a LED omwe akuwonetsa chithunzi chosiyana chomwe chakwezedwa mu chipangizocho.

Chithunzi	Mawonekedwe a LED (Yokhazikika Yotsika)
Factory Image	01010
Chithunzi cha Ntchito 1	10101
Chithunzi cha Ntchito 2	01110

Document Revision History

Tsiku	Baibulo	Zosintha
February 2017	2017.02.21	Adasinthidwa kukhala Intel.
Juni 2015	2015.06.15	Kutulutsidwa koyamba.

Zolemba / Zothandizira

Intel MAX 10 FPGA Zida Pa UART yokhala ndi Nios II processor [pdf] Buku Logwiritsa Ntchito MAX 10 FPGA Zida Pa UART yokhala ndi Nios II processor, MAX 10 FPGA Zida, Pa UART yokhala ndi Nios II processor, Over UART, Nios II processor UART, Nios II, processor UART

Maumboni

• Buku Logwiritsa Ntchito