Microsemi AC490 RTG4 FPGA: Gina Tsarin Tsarin Mi-V Mai sarrafawa

Tarihin Bita

Tarihin bita ya bayyana canje-canjen da aka aiwatar a cikin takaddar. Canje-canjen an jera su ta bita, farawa da mafi kyawun ɗaba'ar.

Bita 3.0

Mai zuwa shine taƙaitaccen canje-canjen da aka yi a cikin wannan bita.

• An sabunta takaddun don Libero SoC v2021.2.
• Sabunta Hoto na 1, shafi na 3 zuwa Hoto na 3, shafi na 5.
• Maye gurbin Hoto na 4, shafi na 5, Hoto na 5, shafi na 7, da Hoto na 18, shafi na 17.
• Table 2 da aka sabunta, shafi na 6 da Table 3, shafi na 7.
• Ƙara Shafi 1: Shirya Na'urar Ta Amfani da FlashPro Express, shafi na 14.
• Ƙara Rataye 3: Gudanar da Rubutun TCL, shafi na 20.
• An cire nassoshi zuwa lambobin sigar Libero.

Bita 2.0
Mai zuwa shine taƙaitaccen canje-canjen da aka yi a cikin wannan bita.

• Ƙarin bayani game da zaɓin tashar tashar COM a cikin Saita Hardware, shafi na 9.
• An sabunta yadda ake zaɓar tashar COM mai dacewa a cikin Gudun Demo, shafi na 11.

Bita 1.0
Buga na farko na takardar.

Gina Tsarin Tsarin Mulki na Mi-V

Microchip yana ba da Mi-V processor IP, 32-bit RISC-V processor da kayan aikin software don haɓaka ƙirar ƙirar RISC-V. RISC-V, daidaitaccen buɗaɗɗen Instruction Set Architecture (ISA) ƙarƙashin jagorancin Gidauniyar RISC-V, yana ba da fa'idodi da yawa, waɗanda suka haɗa da ba da damar buɗe tushen al'umma don gwadawa da haɓaka cores a cikin sauri fiye da ISAs da aka rufe.
RTG4® FPGAs suna goyan bayan Mi-V soft processor don gudanar da aikace-aikacen mai amfani. Wannan bayanin kula na aikace-aikacen yana bayyana yadda ake gina tsarin tsarin aikin Mi-V don aiwatar da aikace-aikacen mai amfani daga ƙirar masana'anta na RAM ko ƙwaƙwalwar DDR.

Bukatun ƙira
Tebu mai zuwa yana lissafin kayan aikin hardware da software don gudanar da demo.

Tebur 1 • Bukatun Zane

Software

• Libero® System-on-Chip (SoC)
• FlashPro Express
• SoftConsole

Lura: Koma zuwa readme.txt file bayar a cikin zane files don nau'ikan software da aka yi amfani da su tare da wannan ƙirar ƙira.

Lura: Labero SmartDesign da hotunan allo na daidaitawa da aka nuna a cikin wannan jagorar don dalilai ne kawai.
Bude ƙirar Libero don ganin sabbin abubuwan sabuntawa.

Abubuwan da ake bukata

Kafin ka fara:

1. Zazzage kuma shigar da Libero SoC (kamar yadda aka nuna a cikin website don wannan ƙira) akan PC mai masauki daga wuri mai zuwa: https://www.microsemi.com/product-directory/design-resources/1750-libero-soc
2. Don ƙirar demo files download link: http://soc.microsemi.com/download/rsc/?f=rtg4_ac490_df

Bayanin Zane

Girman RTG4 μPROM shine 57 KB. Ana iya adana aikace-aikacen mai amfani waɗanda ba su wuce girman μPROM ba a cikin μPROM kuma a aiwatar da su daga manyan ƙwaƙwalwar SRAM na ciki (LSRAM). Aikace-aikacen mai amfani waɗanda suka wuce girman μPROM dole ne a adana su a cikin ƙwaƙwalwar ajiyar waje mara mara ƙarfi. A wannan yanayin, ana buƙatar bootloader da ke aiwatarwa daga μPROM don fara tunanin SRAM na ciki ko na waje tare da aikace-aikacen da aka yi niyya daga ƙwaƙwalwar mara mara ƙarfi.
Tsarin tunani yana nuna ikon bootloader don kwafin aikace-aikacen manufa (na girman 7 KB) daga filasha SPI zuwa ƙwaƙwalwar DDR, da aiwatarwa daga ƙwaƙwalwar DDR. Ana aiwatar da bootloader daga ƙwaƙwalwar ciki. Sashen lambar yana cikin μPROM, kuma sashin bayanan yana cikin Large SRAM (LSRAM) na ciki.

Lura: Don ƙarin bayani game da yadda ake gina aikin Mi-V bootloader Libero da yadda ake gina aikin SoftConsole, koma zuwa TU0775: PolarFire FPGA: Gina Koyarwar Tsarin Tsarin Mi-V
Hoto na 1 yana nuna zane-zanen toshe matakin matakin sama.

Hoto 1 • Hoton Toshe Babban Matsayi

Kamar yadda aka nuna a cikin Hoto 1, abubuwan da ke gaba sun bayyana yadda tsarin ke gudana:

• Mai sarrafa Mi-V yana aiwatar da bootloader daga μPROM da LSRAMs da aka keɓe. Bootloader yana hulɗa tare da GUI ta hanyar toshe CoreUARTapb kuma yana jiran umarni.
• Lokacin da aka karɓi umarnin shirin filasha na SPI daga GUI, bootloader yana shirya filasha SPI tare da aikace-aikacen manufa da aka karɓa daga GUI.
• Lokacin da aka karɓi umarnin taya daga GUI, bootloader yana kwafin lambar aikace-aikacen daga filasha SPI zuwa DDR sannan kuma ya aiwatar da shi daga DDR.

Tsarin agogo
Akwai yankunan agogo biyu (40 MHz da 20 MHz) a cikin ƙira. An haɗa oscillator na kan-motsin kristal 50 MHz zuwa toshe PF_CCC wanda ke haifar da agogo 40 MHz da 20 MHz. Agogon tsarin 40 MHz yana tafiyar da cikakken tsarin aikin Mi-V banda μPROM. Agogon 20 MHz yana tafiyar da RTG4 μPROM da RTG4 μPROM APB interface. RTG4 μPROM yana goyan bayan mitar agogo har zuwa 30 MHz. An saita DDR_FIC don haɗin bas na AHB, wanda ke aiki a 40 MHz. Ƙwaƙwalwar DDR tana aiki a 320 MHz.
Hoto na 2 yana nuna tsarin agogo.

Hoto 2 • Tsarin rufewa

Sake saitin Tsarin
POWER_ON_RESET_N da siginonin LOCK suna ANDed, kuma ana amfani da siginar fitarwa (INIT_RESET_N) don sake saita toshewar RTG4FDDRC_INIT. Bayan an fitar da sake saitin FDDR, mai sarrafa FDDR zai fara farawa, sannan aka tabbatar da siginar INIT_DONE. Ana amfani da siginar INIT_DONE don sake saita na'ura mai sarrafa ta Mi-V, kayan aiki, da sauran tubalan da ke cikin ƙira.

Hoto 3 • Sake saitin Tsarin

Aiwatar Hardware
Hoto 4 yana nuna ƙirar Libero na ƙirar ƙira ta Mi-V.

Hoto 4 • SmartDesign Module

Lura: Hoton hoto na Libero SmartDesign da aka nuna a cikin wannan bayanin kula na aikace-aikacen don dalilai ne kawai. Bude aikin Libero don ganin sabbin abubuwan sabuntawa da nau'ikan IP.

Tubalan IP
Hoto 2 lissafta tubalan IP ɗin da aka yi amfani da su a cikin ƙirar ƙirar ƙirar mi-V da aikin su.

Tebur 2 • Tubalan IP1

Ana samun duk jagororin mai amfani da IP da littattafan hannu daga Libero SoC -> Catalog.

RTG4 μPROM yana adana har zuwa 10,400 kalmomi 36-bit (bits 374,400 na bayanai). Yana goyan bayan ayyukan karantawa kawai yayin aikin na'urar ta al'ada bayan an tsara na'urar. Babban abin sarrafawa MIV_RV32_C0 ya ƙunshi rukunin ɗauko umarni, bututun aiwatarwa, da tsarin ƙwaƙwalwar ajiya. Tsarin ƙwaƙwalwar na'ura na MIV_RV32_C0 ya haɗa da cache koyarwa da cache bayanai. Babban MIV_RV32_C0 ya haɗa da musaya na AHB na waje guda biyu-madaidaicin mashin bas ɗin AHB memori (MEM) da kuma AHB Memory Mapped I/O (MMIO) master interface. Mai sarrafa cache yana amfani da mahallin AHB MEM don cika umarni da cache ɗin bayanai. Ana amfani da mahallin AHB MMIO don samun damar da ba a ɓoye ba zuwa abubuwan da ke gefen I/O.

Taswirorin ƙwaƙwalwar ajiyar mahallin AHB MMIO da haɗin MEM sune 0x60000000 zuwa 0X6FFFFFFFF da 0x80000000 zuwa 0x8FFFFFFFF, bi da bi. Adireshin vector na sake saitin mai sarrafawa yana daidaitawa. Sake saitin MIV_RV32_C0 sigina ce mai ƙarancin aiki, wacce dole ne a yanke ta a daidaita tare da agogon tsarin ta hanyar sake saiti na aiki tare.

Mai sarrafa MIV_RV32_C0 yana samun dama ga ƙwaƙwalwar aiwatar da aikace-aikacen ta amfani da mahallin AHB MEM. An tsara misalin bas ɗin CoreAHBlite_C0_0 don samar da ramukan bayi 16, kowane girman 1 MB. Ƙwaƙwalwar RTG μPROM, da tubalan RTG4FDDRC ​​an haɗa su zuwa wannan bas. Ana amfani da μPROM don adana aikace-aikacen bootloader.

Mai sarrafa MIV_RV32_C0 yana jagorantar mu'amalar bayanai tsakanin adireshi 0x60000000 da 0x6FFFFFFFF zuwa MMIO interface. An haɗa haɗin haɗin MMIO zuwa bas ɗin CoreAHBlite_C1_0 don sadarwa tare da abubuwan da ke da alaƙa da ramukan bayi. An tsara misalin bas ɗin CoreAHBlite_C1_0 don samar da ramukan bayi 16, kowane girman 256 MB. Abubuwan UART, CoreSPI, da CoreGPIO an haɗa su zuwa bas ɗin CoreAHBlite_C1_0 ta gadar CoreAHBTOAPB3 da bas ɗin CoreAPB3.

Taswirar ƙwaƙwalwa
Tebur na 3 ya jera taswirar ƙwaƙwalwar ajiya na memories da na gefe.

Tebur na 3 • Taswirar ƙwaƙwalwa

Aiwatar da Software

Tsarin tunani files sun haɗa da filin aiki na SoftConsole wanda ya ƙunshi ayyukan software masu zuwa:

• Bootloader
• Aikace-aikacen Target

Bootloader
Ana tsara aikace-aikacen bootloader akan μPROM yayin shirye-shiryen na'urar. Bootloader yana aiwatar da ayyuka masu zuwa:

• Shirya SPI Flash tare da aikace-aikacen manufa.
• Kwafi aikace-aikacen manufa daga SPI Flash zuwa ƙwaƙwalwar DDR3.
• Canza aiwatar da shirin zuwa aikace-aikacen manufa da ake samu a ƙwaƙwalwar DDR3.
  Dole ne a aiwatar da aikace-aikacen bootloader daga μPROM tare da LSRAM azaman tari. Don haka, an saita adiresoshin ROM da RAM a cikin rubutun mahaɗin zuwa adireshin farawa na μPROM da LSRAMs da aka keɓe, bi da bi. Ana aiwatar da sashin lambar daga ROM kuma ana aiwatar da sashin bayanai daga RAM kamar yadda aka nuna a hoto 5.

Hoto 5 • Bootloader Linker Script

Rubutun mahaɗin (microsemi-riscv-ram_rom.ld) yana samuwa a wurin
SoftConsole_Project\mivrv32im-bootloader babban fayil na ƙira files.

Aikace-aikacen Target
Aikace-aikacen da aka yi niyya yana lumshe hasken LEDs 1, 2, 3, da 4 kuma yana buga saƙonnin UART. Dole ne a aiwatar da aikace-aikacen da aka yi niyya daga ƙwaƙwalwar DDR3. Don haka, an saita lambar da sassan tari a cikin rubutun mahaɗin zuwa adireshin farawa na ƙwaƙwalwar DDR3 kamar yadda aka nuna a hoto na 6.

Hoto na 6 • Rubutun mahaɗar da ake nema

Rubutun mahaɗin (microsemi-riscv-ram.ld) yana samuwa a babban fayil ɗin aikace-aikacen SoftConsole_Project\miv-rv32imddr files.

Saita Hardware

Matakai masu zuwa suna bayyana yadda ake saita kayan aikin:

1. Tabbatar cewa an kashe allo ta amfani da maɓalli na SW6.
2. Haɗa masu tsalle a kan kayan haɓakawa na RTG4, kamar yadda aka nuna a tebur mai zuwa:
   Tebur 4 • Masu tsalle-tsalle

   Jumper	Pin Daga	Pin Zuwa	Sharhi
   J11, J17, J19, J23, J26, J21, J32, da J27	1	2	Default
   J16	2	3	Default
   J33	1	2	Default
   	3	4

3. Haɗa PC mai masaukin zuwa mai haɗin J47 ta amfani da kebul na USB.
4. Tabbatar cewa ana gano direbobin gadar USB zuwa UART ta atomatik. Ana iya tabbatar da wannan a cikin mai sarrafa na'ura na PC mai masaukin baki.
5. Kamar yadda aka nuna a cikin Hoto 7, kayan tashar tashar jiragen ruwa na COM13 sun nuna cewa an haɗa shi da USB Serial Converter C. Don haka, an zaɓi COM13 a cikin wannan tsohon.ample. Lambar tashar tashar COM takamaiman tsari ce.
   Hoto 7 • Manajan Na'ura
   Lura: Idan ba a shigar da direbobin gada na USB zuwa UART ba, zazzagewa kuma shigar da direbobi daga www.microsemi.com//documents/CDM_2.08.24_WHQL_Certified.zip.
6. Haɗa wutar lantarki zuwa mai haɗin J9 kuma kunna wutan wutar lantarki, SW6.

Hoto 8 • Kit ɗin Ci Gaban RTG4

Gudun Demo

Wannan babin yana bayyana matakai don tsara na'urar RTG4 tare da ƙirar tunani, tsara SPI Flash tare da aikace-aikacen manufa, da kuma ƙaddamar da aikace-aikacen manufa daga ƙwaƙwalwar DDR ta amfani da Mi-V Bootloader GUI.

Gudanar da demo ya ƙunshi matakai masu zuwa:

1. Shirya na'urar RTG4, shafi na 11
2. Gudun Mi-V Bootloader, shafi na 11

Shirya na'urar RTG4
Ana iya tsara na'urar RTG4 ta amfani da FlashPro Express ko Libero SOC.

• Don tsara Kit ɗin Rarraba RTG4 tare da aikin file an bayar a matsayin wani ɓangare na zane files ta amfani da FlashPro Express software, koma zuwa shafi na 1: Shirya na'urar Amfani da FlashPro Express, shafi na 14.
• Don tsara na'urar ta amfani da Libero SoC, koma zuwa shafi na 2: Shirya na'urar Amfani da Libero SoC, shafi na 17.

Gudun Mi-V Bootloader
Bayan nasarar kammala shirye-shirye, bi waɗannan matakan:

1. Shigar da saitin.exe file samuwa a zane mai zuwa files wuri.
   <$Download_Directory>\rtg4_ac490_df\GUI_InstallerMi-V Bootloader_Installer_V1.4
2. Bi mayen shigarwa don shigar da Bootloader GUI aikace-aikacen.
   Hoto 9 yana nuna RTG4 Mi-V Bootloader GUI.
   Hoto 9 • Mi-V Bootloader GUI
3. Zaɓi tashar tashar COM da aka haɗa zuwa USB Serial Converter C kamar yadda aka nuna a hoto 7.
4. Danna maɓallin haɗi. Bayan haɗin da aka yi nasara, mai nuna ja yana juya Green kamar yadda aka nuna a hoto na 10.
   Hoto 10 • Haɗa tashar tashar COM
5. Danna maɓallin Import kuma zaɓi aikace-aikacen da aka yi niyya file (.bin). Bayan shigo da, hanyar da file Ana nunawa akan GUI kamar yadda aka nuna a Hoto 11.
   <$Download_Directory>\rtg4_ac490_df\Source_files
   Hoto 11 • Shigo da Aikace-aikacen Target File
6. Kamar yadda aka nuna a Hoto 11, danna Shirin SPI Flash zaɓi don tsara aikace-aikacen da aka yi niyya akan SPI Flash. Ana nuna pop-up bayan an tsara SPI Flash kamar yadda aka nuna a hoto na 12. Danna Ok.
   Hoto 12 • SPI Flash Shirye-shiryen
7. Zaɓi zaɓin Fara Boot don kwafin aikace-aikacen daga SPI Flash zuwa ƙwaƙwalwar DDR3 kuma fara aiwatar da aikace-aikacen daga ƙwaƙwalwar DDR3. Bayan nasarar ƙaddamar da aikace-aikacen da aka yi niyya daga ƙwaƙwalwar DDR3, aikace-aikacen yana buga saƙonnin UART kuma yana lumshe idanu mai amfani da LED1, 2, 3, da 4 kamar yadda aka nuna a hoto 13.
   Hoto 13 • Aiwatar da Aikace-aikace Daga DDR
8. Aikace-aikacen yana gudana daga ƙwaƙwalwar DDR3 kuma wannan yana ƙare demo. Rufe Mi-V Bootloader GUI.

Shirya Na'urar Ta Amfani da FlashPro Express

Wannan sashe yana bayyana yadda ake tsara na'urar RTG4 tare da aikin shirye-shirye file Amfani da FlashPro Express.

Don tsara na'urar, yi matakai masu zuwa:

1. Tabbatar cewa saitunan jumper a kan allo sun kasance daidai da waɗanda aka jera a cikin Table 3 na UG0617:
   Jagorar Mai Amfani da Kit ɗin Ci gaban RTG4.
2. Zabi, za a iya saita jumper J32 don haɗa fil 2-3 lokacin amfani da FlashPro4, FlashPro5, ko FlashPro6 na waje maimakon saitin tsalle don amfani da FlashPro5 da aka saka.
   Lura: Maɓallin wutar lantarki, SW6 dole ne a kashe shi yayin yin haɗin haɗin tsalle.
3. Haɗa kebul ɗin samar da wutar lantarki zuwa mai haɗin J9 akan allo.
4. Power ON da wutar lantarki sauya SW6.
5. Idan kuna amfani da FlashPro5 da aka saka, haɗa kebul na USB zuwa mai haɗa J47 da PC mai masauki.
   A madadin, idan kuna amfani da na'ura mai tsarawa ta waje, haɗa kebul na ribbon zuwa JTAG header J22 kuma haɗa mai shirye-shirye zuwa PC mai masauki.
6. A kan PC mai masaukin baki, ƙaddamar da software na FlashPro Express.
7. Danna Sabo ko zaɓi Sabon Ayyukan Ayyuka daga FlashPro Express Ayuba daga menu na Project don ƙirƙirar sabon aikin aiki, kamar yadda aka nuna a cikin adadi mai zuwa.
   Hoto 14 • FlashPro Express Ayyukan Aiki
8. Shigar da waɗannan a cikin Sabon Ayyukan Ayyuka daga FlashPro Express Akwatin maganganu:
   • Ayyukan shirye-shirye file: Danna Browse, kuma kewaya zuwa wurin da .aikin file yana samuwa kuma zaɓi file. Tsohuwar wurin shine: \rtg4_ac490_df\Programming_Ayyuka
   • Wurin aikin aikin FlashPro Express: Danna Bincika kuma kewaya zuwa wurin aikin FlashPro Express da ake so.
     Hoto 15 • Sabon Aikin Aiki daga FlashPro Express Ayuba
9. Danna Ok. Shirye-shiryen da ake buƙata file an zaɓi kuma a shirye don tsarawa a cikin na'urar.
10. Tagan FlashPro Express yana bayyana kamar yadda aka nuna a adadi mai zuwa. Tabbatar da cewa lambar mai shirye-shirye ta bayyana a cikin filin Programmer. Idan ba haka ba, tabbatar da haɗin allon kuma danna Refresh/Rescan Programmers.
    Hoto 16 • Shirya Na'urar
11. Danna RUN. Lokacin da aka tsara na'urar cikin nasara, ana nuna matsayin RUN PASSED kamar yadda aka nuna a adadi mai zuwa.
    Hoto 17 • FlashPro Express — GUDU WUCE
12. Rufe FlashPro Express ko danna Fita a cikin Project tab.

Shirya Na'urar Ta Amfani da Libero SoC

Tsarin tunani files sun haɗa da tsarin tsarin aikin Mi-V wanda aka ƙirƙira ta amfani da Libero SoC. Ana iya tsara na'urar RTG4 ta amfani da Libero SoC. An gina aikin Libero SoC gaba ɗaya kuma yana gudana daga Synthesis, Wuri da Hanya, Tabbatar da Lokaci, Ƙirƙirar Bayanai na FPGA, Sabunta Abubuwan Ƙwaƙwalwar Ƙwaƙwalwar μPROM, Tsarin Bitstream, Shirye-shiryen FPGA.

Ana nuna kwararar ƙirar Libero a cikin adadi mai zuwa.

Hoto 18 • Zane-zane na Labero

Don tsara na'urar RTG4, dole ne a buɗe tsarin tsarin aikin Mi-V a cikin Libero SoC kuma dole ne a sake aiwatar da matakai masu zuwa:

1. Sabunta Abubuwan Ƙwaƙwalwar Ƙwaƙwalwar uPROM: A wannan matakin, μPROM an tsara shi tare da aikace-aikacen bootloader.
2. Bitstream Generation: A cikin wannan mataki, da Ayuba file An ƙirƙira don na'urar RTG4.
3. Shirye-shiryen FPGA: A wannan mataki, ana tsara na'urar RTG4 ta amfani da Ayuba file.

Bi waɗannan matakan:

1. Daga Zane-zane na Labero, zaɓi Sabunta abun ciki na ƙwaƙwalwar ajiya na uPROM.
2. Ƙirƙiri abokin ciniki ta amfani da zaɓin Ƙara.
3. Zaɓi abokin ciniki sannan zaɓi zaɓin Gyara.
4. Zaɓi Abun ciki daga file sannan ka zabi zabin Browse kamar yadda aka nuna a hoto na 19.
   Hoto 19 • Shirya Abokin Adana Bayanai
5. Kewaya zuwa zane mai zuwa files wurin kuma zaɓi miv-rv32im-bootloader.hex file kamar yadda aka nuna a Hoto 20. <$Download_Directory>\rtg4_ac490_df
   • Saita File Buga azaman Intel-Hex (*.hex).
   • Zaɓi Yi amfani da hanyar dangi daga kundin tsarin aiki.
   • Danna Ok.
     Hoto 20 • Shigo da ƙwaƙwalwar ajiya File
6. Danna Ok.
   An sabunta abun ciki na μPROM.
7. Danna Ƙirƙirar Bitstream sau biyu kamar yadda aka nuna a hoto 21.
   Hoto 21 • Ƙirƙirar Bitstream
8. Danna Run PROGRAM Action sau biyu don tsara na'urar kamar yadda aka nuna a hoto 21.
   An tsara na'urar RTG4. Duba Gudun Demo, shafi na 11.

Gudanar da Rubutun TCL

Ana ba da rubutun TCL a cikin ƙira files babban fayil a ƙarƙashin directory TCL_Scripts. Idan an buƙata, za a iya sake fitar da kwararar ƙira daga Aiwatar da Zane har zuwa ƙarni na aiki file.

Don gudanar da TCL, bi matakan da ke ƙasa:

1. Kaddamar da software na Libero.
2. Zaɓi Project > aiwatar da Rubutun….
3. Danna Bincika kuma zaɓi script.tcl daga kundin adireshin TCL_Script da aka zazzage.
4. Danna Run.

Bayan nasarar aiwatar da rubutun TCL, an ƙirƙiri aikin Libero a cikin kundin adireshin TCL_Script.
Don ƙarin bayani game da rubutun TCL, koma zuwa rtg4_ac490_df/TCL_Scripts/readme.txt.
Koma zuwa Libro® SoC TCL Jagoran Magana don ƙarin cikakkun bayanai kan umarnin TCL. Tuntuɓar
Taimakon fasaha don kowane tambayoyin da aka fuskanta lokacin gudanar da rubutun TCL.

Microsemi baya bayar da garanti, wakilci, ko garanti game da bayanin da ke ƙunshe a ciki ko dacewa da samfuransa da sabis ɗin sa don kowane dalili na musamman, haka nan Microsemi baya ɗaukar wani alhaki duk abin da ya taso daga aikace-aikacen ko amfani da kowane samfur ko kewaye. Kayayyakin da aka siyar a ƙarƙashinsa da duk wasu samfuran da Microsemi ke siyarwa sun kasance ƙarƙashin ƙayyadaddun gwaji kuma bai kamata a yi amfani da su tare da kayan aiki masu mahimmanci ko aikace-aikace ba. An yi imanin duk wani ƙayyadaddun ƙayyadaddun aiki na abin dogaro ne amma ba a tabbatar da su ba, kuma mai siye dole ne ya gudanar da kammala duk ayyuka da sauran gwajin samfuran, shi kaɗai kuma tare da, ko shigar da su, kowane samfuran ƙarshe. Mai siye ba zai dogara da kowane bayanai da ƙayyadaddun ayyuka ko sigogi da Microsemi ya bayar ba. Alhakin Mai siye ne don ƙayyade dacewa da kowane samfur da kansa kuma don gwadawa da tabbatar da iri ɗaya. Bayanin da Microsemi ya bayar a nan an bayar da shi "kamar yadda yake, inda yake" kuma tare da duk kuskure, kuma duk haɗarin da ke tattare da irin wannan bayanin gaba ɗaya yana tare da mai siye. Microsemi baya ba, a bayyane ko a fakaice, ga kowace ƙungiya kowane haƙƙin haƙƙin mallaka, lasisi, ko kowane haƙƙin IP, ko dangane da irin wannan bayanin da kansa ko wani abu da irin wannan bayanin ya bayyana. Bayanin da aka bayar a cikin wannan takaddun mallakar Microsemi ne, kuma Microsemi yana da haƙƙin yin kowane canje-canje ga bayanin da ke cikin wannan takaddar ko zuwa kowane samfuri da sabis a kowane lokaci ba tare da sanarwa ba.

Game da Microsemi
Microsemi, wani kamfani na gaba ɗaya mallakar Microchip Technology Inc. (Nasdaq: MCHP), yana ba da cikakkiyar fayil na semiconductor da tsarin mafita don sararin samaniya & tsaro, sadarwa, cibiyar bayanai da kasuwannin masana'antu. Samfuran sun haɗa da babban aiki da radiyo-taurin analog gauran siginar hadedde, FPGAs, SoCs da ASICs; kayayyakin sarrafa wutar lantarki; lokaci da na'urorin aiki tare da daidaitattun hanyoyin magance lokaci, saita ƙa'idodin duniya don lokaci; na'urorin sarrafa murya; RF mafita; sassa masu hankali; Ma'ajiyar kasuwanci da hanyoyin sadarwa, fasahar tsaro da scalable anti-tampsamfurori; Hanyoyin Ethernet; Power-over-Ethernet ICs da midspans; kazalika da al'ada ƙira iyawa da kuma ayyuka. Ƙara koyo a www.microsemi.com.

Microsemi Headquarter
Ɗaya daga cikin Enterprise, Aliso Viejo,
CA 92656 Amurka
A cikin Amurka: +1 800-713-4113
A wajen Amurka: +1 949-380-6100
Talla: +1 949-380-6136
Fax: +1 949-215-4996
Imel: sales.support@microsemi.com
www.microsemi.com

©2021 Microsemi, gabaɗaya mallakar reshen Microchip Technology Inc. Duk haƙƙin mallaka. Microsemi da tambarin Microsemi alamun kasuwanci ne masu rijista na Kamfanin Microsemi. Duk sauran alamun kasuwanci da alamun sabis mallakin masu su ne

Takardu / Albarkatu

Microsemi AC490 RTG4 FPGA: Gina Tsarin Tsarin Mi-V Mai sarrafawa [pdf] Jagorar mai amfani AC490 RTG4 FPGA Gina Mi-V Subsystem Subsystem, AC490 RTG4, FPGA Gina Mi-V Mai sarrafawa, Mi-V Subsystem

Magana

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