intel Chip ID FPGA IP Cores

Each supported Intel® FPGA has a unique 64-bit chip ID. Chip ID Intel FPGA IP cores allow you to read out this chip ID for device identification.

Related Information

• Introduction to Intel FPGA IP Cores
  • Provides general information about all Intel FPGA IP cores, including parameterizing, generating, upgrading, and simulating IP cores.
• Generating a Combined Simulator Setup Script
  • Create simulation scripts that do not require manual updates for software or IP version upgrades.

Device Support

IP Cores	Supported Devices
Chip ID Intel Stratix® 10 FPGA IP core	Intel Stratix 10
Unique Chip ID Intel Arria® 10 FPGA IP core	Intel Arria 10
Unique Chip ID Intel Cyclone® 10 GX FPGA IP core	Intel Cyclone 10 GX
Unique Chip ID Intel MAX® 10 FPGA IP	Intel MAX 10
Unique Chip ID Intel FPGA IP core	Stratix V Arria V Cyclone V

Related Information

• Unique Chip ID Intel MAX 10 FPGA IP Core

Chip ID Intel Stratix 10 FPGA IP Core

• This section describes the Chip ID Intel Stratix 10 FPGA IP core.

Functional Description

The data_valid signal starts low in the initial state where no data is being read from the device. After feeding a high-to-low pulse to the readid input port, the Chip ID Intel Stratix 10 FPGA IP reads the unique chip ID. After reading, the IP core asserts the data_valid signal to indicate that the unique chip ID value at the output port is ready for retrieval. The operation repeats only when you reset the IP core. The chip_id[63:0] output port holds the value of the unique chip ID until you reconfigure the device or reset the IP core.

Note: You cannot simulate the Chip ID IP core because the IP core receives the response on chip ID data from SDM. To validate this IP core, Intel recommends that you perform hardware evaluation.

Ports

Figure 1: Chip ID Intel Stratix 10 FPGA IP Core Ports

Table 2: Chip ID Intel Stratix 10 FPGA IP Core Ports Description

Port	I/O	Size (Bit)	Description
clkin	Input	1	Feeds clock signal to the chip ID block. The maximum supported frequency is equivalent to your system clock.
reset	Input	1	Synchronous reset that resets the IP core. To reset the IP core, assert the reset signal high for at least 10 clkin cycles.
data_valid	Output	1	Indicates that the unique chip ID is ready for retrieval. If the signal is low, the IP core is in initial state or in progress to load data from a fuse ID. After the IP core asserts the signal, the data is ready for retrieval at the chip_id[63..0] output port.
chip_id	Output	64	Indicates the unique chip ID according to its respective fuse ID location. The data is only valid after the IP core asserts the data_valid signal. The value at power-up resets to 0. The chip_id [63:0]output port holds the value of the unique chip ID until you reconfigure the device or reset the IP core.
readid	Input	1	The readid signal is used to read the ID value from the device. Every time the signal change value from 1 to 0, the IP core triggers the read ID operation. You must drive the signal to 0 when unused. To start the read ID operation, drive the signal high for at least 3 clock cycles, then pull it low. The IP core starts reading the value of the chip ID.

Accessing Chip ID Intel Stratix 10 FPGA IP through Signal Tap

When you toggle the readid signal, the Chip ID Intel Stratix 10 FPGA IP core starts reading the chip ID from the Intel Stratix 10 device. When the chip ID is ready, the Chip ID Intel Stratix 10 FPGA IP core asserts the data_valid signal and ends the JTAG access.

Note: Allow a delay equivalent to tCD2UM after full chip configuration before attempting to read the unique chip ID. Refer the respective device datasheet for tCD2UM value.

Resetting the Chip ID Intel Stratix 10 FPGA IP Core

To reset the IP core, you must assert the reset signal for at least ten clock cycles.

Note

1. For Intel Stratix 10 devices, do not reset the IP core until at least tCD2UM after full chip initialization. Refer the respective device datasheet for tCD2UM value.
2. For IP core instantiation guidelines, you must refer to the Intel Stratix 10 Reset Release IP section in the Intel Stratix 10 Configuration User Guide.

Related Information

Intel Stratix 10 Configuration User Guide

• Provides more information about Intel Stratix 10 Reset Release IP.

Chip ID Intel FPGA IP Cores

This section describes the following IP cores

• Unique Chip ID Intel Arria 10 FPGA IP core
• Unique Chip ID Intel Cyclone 10 GX FPGA IP core
• Unique Chip ID Intel FPGA IP core

Functional Description

The data_valid signal starts low in the initial state where no data is being read from the device. After feeding a clock signal to the clkin input port, the Chip ID Intel FPGA IP core reads the unique chip ID. After reading, the IP core asserts the data_valid signal to indicate that the unique chip ID value at the output port is ready for retrieval. The operation repeats only when you reset the IP core. The chip_id[63:0] output port holds the value of the unique chip ID until you reconfigure the device or reset the IP core.

Note: The Intel Chip ID IP core does not have simulation model files. To validate this IP core, Intel recommends that you perform hardware evaluation.

Figure 2: Chip ID Intel FPGA IP Core Ports

Table 3: Chip ID Intel FPGA IP Core Ports Description

Port	I/O	Size (Bit)	Description
clkin	Input	1	Feeds clock signal to the chip ID block. The maximum supported frequencies are as follows: •    For Intel Arria 10 and Intel Cyclone 10 GX: 30 MHz. •    For Intel MAX 10, Stratix V, Arria V and Cyclone V: 100 MHz.
reset	Input	1	Synchronous reset that resets the IP core. To reset the IP core, assert the reset signal high for at least 10 clkin cycles(1). The chip_id [63:0]output port holds the value of the unique chip ID until you reconfigure the device or reset the IP core.
data_valid	Output	1	Indicates that the unique chip ID is ready for retrieval. If the signal is low, the IP core is in initial state or in progress to load data from a fuse ID. After the IP core asserts the signal, the data is ready for retrieval at the chip_id[63..0] output port.
chip_id	Output	64	Indicates the unique chip ID according to its respective fuse ID location. The data is only valid after the IP core asserts the data_valid signal. The value at power-up resets to 0.

Accessing Unique Chip ID Intel Arria 10 FPGA IP and Unique Chip ID Intel Cyclone 10 GX FPGA IP through Signal Tap

Note: The Intel Arria 10 and Intel Cyclone 10 GX chip ID is inaccessible if you have other systems or IP cores accessing the JTAG simultaneously. For example, the Signal Tap II Logic Analyzer, Transceiver Toolkit, in-system signals or probes, and the SmartVID Controller IP core.

When you toggle the reset signal, the Unique Chip ID Intel Arria 10 FPGA IP and Unique Chip ID Intel Cyclone 10 GX FPGA IP cores start reading the chip ID from theIntel Arria 10 or Intel Cyclone 10 GX device. When the chip ID is ready, the Unique Chip ID Intel Arria 10 FPGA IP and Unique Chip ID Intel Cyclone 10 GX FPGA IP cores assert the data_valid signal and ends the JTAG access.

Note: Allow a delay equivalent to tCD2UM after full chip configuration before attempting to read the unique chip ID. Refer the respective device datasheet for tCD2UM value.

Resetting the Chip ID Intel FPGA IP Core

To reset the IP core, you must assert the reset signal for at least ten clock cycles. After you deassert the reset signal, the IP core rereads the unique chip ID from the fuse ID block. The IP core asserts the data_valid signal after completing the operation.

Note: For Intel Arria 10, Intel Cyclone 10 GX, Intel MAX 10, Stratix V, Arria V, and Cyclone V devices, do not reset the IP core until at least tCD2UM after full chip initialization. Refer the respective device datasheet for tCD2UM value.

Chip ID Intel FPGA IP Cores User Guide Archives

If an IP core version is not listed, the user guide for the previous IP core version applies.

IP Core Version	User Guide
18.1	Chip ID Intel FPGA IP Cores User Guide
18.0	Chip ID Intel FPGA IP Cores User Guide

Document Revision History for the Chip ID Intel FPGA IP Cores User Guide

Document Version	Intel Quartus® Prime Version	Changes
2022.09.26	20.3	Removed Project Management Best Practices link. Updated Functional Description in Chip ID Intel Stratix 10 FPGA IP Core. Updated Functional Description in Chip ID Intel FPGA IP Cores.
2020.10.05	20.3	Updated the description of the clkin and resetports in Table: Chip ID Intel FPGA IP Core Ports Description to include Intel MAX 10 details. Updated the Resetting the Chip ID Intel FPGA IP Core section to include support for the Intel MAX 10 device.
2019.05.17	19.1	Updated the Resetting the Chip ID Intel Stratix 10 FPGA IP Core topic to add a second note regarding IP core instantiation guidelines.
2019.02.19	18.1	Added support for the Intel MAX 10 devices in the IP Cores and the Supported Devices table.
2018.12.24	18.1	Added the Chip ID Intel FPGA IP Cores User Guide Archives section.  Restructured the document to provide more details on the respective supported devices.
2018.06.08	18.0	Updated the readid port description. Updated the reset port description.
2018.05.07	18.0	Added readid port for Chip ID Intel Stratix 10 FPGA IP IP core.

 

Date	Version	Changes
December 2017	2017.12.11	Updated document title from Altera Unique Chip ID IP Core User Guide. Added Device Support section.  Combined and added information from Altera Arria 10 Unique Chip ID IP Core User Guide and Stratix 10 Unique Chip ID IP Core User Guide. Rebranded to Intel. Updated Functional Description. Added Intel Cyclone 10 GX device support.
May 2016	2016.05.02	Removed standard IP core information and added link to Quartus Prime Handbook. Updated note about Arria 10 device support.
September, 2014	2014.09.02	•    Updated document title to reflect new name of “Altera Unique Chip ID” IP core.

Date	Version	Changes
August, 2014	2014.08.18	Updated parameterization steps for legacy parameter editor. Added note that this IP core does not support Arria 10 designs.
June, 2014	2014.06.30	Replaced MegaWizard Plug-In Manager information with IP Catalog. Added standard information about upgrading IP cores. Added standard installation and licensing information. Removed outdated device support level information. IP core device support is now available in IP Catalog and parameter editor.
September, 2013	2013.09.20	Updated to reword “Acquiring the chip ID of an FPGA device” to “Acquiring the unique chip ID of an FPGA device”
May, 2013	1.0	Initial release.

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Documents / Resources

intel Chip ID FPGA IP Cores [pdf] User Guide Chip ID FPGA IP Cores, Chip ID, FPGA IP Cores, IP Cores

References

• User Manual