Intel Interlaken 2nd Generation Agilex 7 FPGA IP Design Example

Ulwazi Lomkhiqizo

I-Interlaken (2nd Generation) FPGA IP core iyisici se-Intel Agilex 7 FPGA. Ihlinzeka ngebhentshi lokuhlola lokulingisa kanye ne-ex ye-hardware designample esekela ukuhlanganiswa nokuhlolwa kwehadiwe. Umklamo exampi-le iyatholakala futhi ngesici se-Interlaken Look-aside. I-IP core isekela imodi ye-NRZ ne-PAM4 yamadivayisi e-E-tile futhi ikhiqiza i-design exampi-les yazo zonke izinhlanganisela ezisekelwayo zenani lemizila namazinga wedatha.

Izingxenyekazi zekhompuyutha nezidingo zeSoftware
I-Interlaken (2nd Generation) IP core design example idinga i-Intel Agilex 7 F-Series Transceiver-SoC Development Kit. Sicela ubheke Umhlahlandlela Womsebenzisi wekhithi yokuthuthukisa ukuze uthole ulwazi olwengeziwe.

Ukwakheka Kwemibhalo
I-Interlaken ekhiqiziwe (yesizukulwane sesibili) exampi-le design ifaka phakathi izinkomba ezilandelayo:

• exampi-le_design: Iqukethe okuyinhloko files ye-design example.
• ilk_uflex: Iqukethe files ihlobene nenketho yemodi ye-Interlaken Look-aside.
• ila_uflex: Iqukethe files ihlobene nenketho yemodi ye-Interlaken Look-aside (ekhiqizwa kuphela uma ikhethiwe).

Imiyalo yokusetshenziswa komkhiqizo

Ukusebenzisa i-Interlaken (2nd Generation) FPGA IP core design example, landela lezi zinyathelo:

1. Qinisekisa ukuthi une-Intel Agilex 7 F-Series Transceiver-SoC Development Kit.
2. Hlanganisa i-ex designampusebenzisa i-simulator.
3. Yenza ukulingisa okusebenzayo ukuze uqinisekise umklamo.
4. Khiqiza i-ex designampusebenzisa umhleli wepharamitha.
5. Hlanganisa i-ex designampusebenzisa i-Quartus Prime.
6. Yenza ukuhlolwa kwezingxenyekazi zekhompuyutha ukuze uqinisekise umklamo.

Qaphela: Inketho yemodi ye-Interlaken Look-aside iyatholakala ukuze uyikhethe kusihleli sepharamitha ye-IP. Uma kukhethiwe, kungeziwe files izokhiqizwa kumkhombandlela othi "ila_uflex".

Quick Start Guide

• I-Interlaken (2nd Generation) FPGA IP core inikeza ibhentshi lokuhlola lokulingisa kanye ne-ex yedizayini yehadiwe.ample esekela ukuhlanganiswa nokuhlolwa kwehadiwe.
• Uma udala i-ex designample, umhleli wepharamitha udala ngokuzenzakalelayo i filekudingekile ukulingisa, ukuhlanganisa, nokuhlola idizayini kuhadiwe.
• Umklamo exampI-le iyatholakala futhi ngesici se-Interlaken Look-aside.
• I-testbench kanye ne-design example isekela imodi ye-NRZ ne-PAM4 yamadivayisi we-E-tile.
• I-Interlaken (2nd Generation) FPGA IP core ikhiqiza i-design exampi-les yazo zonke izinhlanganisela ezisekelwayo zenani lemizila namazinga wedatha.

Umfanekiso 1. Izinyathelo Zokuthuthukisa Zomklamo Example

I-Interlaken (2nd Generation) IP core design example isekela izici ezilandelayo:

• I-TX yangaphakathi kuya kumodi ye-serial loopback ye-RX
• Yakha ngokuzenzakalelayo amaphakethe osayizi ongashintshi
• Amakhono okuhlola iphakethe ayisisekelo
• Ikhono lokusebenzisa Ikhonsoli Yesistimu ukuze usethe kabusha idizayini ngenjongo yokuhlola kabusha
• Ukushintsha kwe-PMA

Inkampani ye-Intel Wonke Amalungelo Agodliwe. I-Intel, ilogo ye-Intel, nezinye izimpawu ze-Intel yizimpawu zokuthengisa ze-Intel Corporation noma izinkampani ezingaphansi kwayo. I-Intel iqinisekisa ukusebenza kwe-FPGA yayo kanye nemikhiqizo yesemiconductor ekucacisweni kwamanje ngokuvumelana newaranti evamile ye-Intel, kodwa igodla ilungelo lokwenza izinguquko kunoma imiphi imikhiqizo namasevisi nganoma yisiphi isikhathi ngaphandle kwesaziso. I-Intel ayithathi mthwalo noma isikweletu esivele ngenxa yesicelo noma ukusetshenziswa kwanoma yiluphi ulwazi, umkhiqizo, noma isevisi echazwe lapha ngaphandle kwalapho okuvunyelwene ngakho ngokubhaliwe yi-Intel. Amakhasimende e-Intel ayelulekwa ukuthi athole inguqulo yakamuva yokucaciswa kwedivayisi ngaphambi kokuthembela kunoma yiluphi ulwazi olushicilelwe nangaphambi kokufaka ama-oda emikhiqizo noma amasevisi. *Amanye amagama namabhrendi angafunwa njengempahla yabanye.

Umfanekiso 2. Umdwebo Webhulokhi Wezinga eliphezulu We-Interlaken (Isizukulwane Sesibili) Umklamo Example

Ulwazi Oluhlobene

• I-Interlaken (2nd Generation) FPGA IP User Guide
• I-Interlaken (2nd Generation) Intel FPGA IP Release Notes

I-Hardware neSoftware

Izingxenyekazi zekhompuyutha nezidingo zeSoftware
Ukuhlola i-example design, sebenzisa ihadiwe nesoftware elandelayo:

• Isofthiwe ye-Intel® Quartus® Prime Pro Edition
• Ikhonsoli Yesistimu
• Izilingisi ezisekelwayo:
  • Siemens* EDA ModelSim* SE noma QuestaSim*
  • Ama-synopsy* VCS*
  • I-cadence* Xcelium*
• I-Intel Agilex® 7 F-Series Transceiver-SoC Development Kit (AGFB014R24A2E2V)

Ulwazi Oluhlobene
Intel Agilex 7 F-Series Transceiver-SoC Development Kit Umhlahlandlela Womsebenzisi
Ukwakheka Kwemibhalo
I-Interlaken (2nd Generation) IP core design example file uhla lwemibhalo luqukethe okulandelayo okwenziwe files ye-design example.

Umfanekiso 3. Ukwakheka Kwemibhalo Ye-Interlaken Ekhiqizwayo (Isizukulwane Sesibili) Example Design

Ukucushwa kwehadiwe, ukulingisa, nokuhlola files atholakala kuample_installation_dir>/uflex_ilk_0_example_design.
Ithebula 1. I-Interlaken (2nd Generation) IP Core Hardware Design Example File Izincazelo Lezi files zikuample_installation_dir>/uflex_ilk_0_example_design/ example_design/quartus directory.

File Amagama	Incazelo
example_design.qpf	Iphrojekthi ye-Intel Quartus Prime file.
example_design.qsf	Izilungiselelo zephrojekthi ye-Intel Quartus Prime file
example_design.sdc jtag_timing_template.sdc	I-Synopsys Design Constraint file. Ungakopisha futhi ulungisele umklamo wakho.
sysconsole_testbench.tcl	Okuyinhloko file ukuze ufinyelele Ikhonsoli Yesistimu

Ithebula 2. I-Interlaken (2nd Generation) IP Core Testbench File Incazelo
Lokhu file ikuample_installation_dir>/uflex_ilk_0_example_design/ example_design/rtl directory.

File Igama	Incazelo
top_tb.sv	I-testbench yezinga eliphezulu file.

Ithebula 3. I-Interlaken (2nd Generation) IP Core Testbench Scripts
Lezi files zikuample_installation_dir>/uflex_ilk_0_example_design/ example_design/testbench directory.

File Igama	Incazelo
vcstest.sh	Iskripthi se-VCS sokuqalisa ibhentshi le-test.
vlog_pro.do	Iskripthi se-ModelSim SE noma i-QuestaSim sokuqalisa ibhentshi le-test.
xcelium.sh	Iskripthi se-Xcelium sokuqalisa ibhentshi lokuhlola.

I-Hardware Design Example Components

• I-exampi-le design ixhuma amawashi ereferensi wesistimu kanye ne-PLL kanye nezingxenye zokuklama ezidingekayo. I-exampi-le design ilungisa i-IP core kumodi ye-loopback yangaphakathi futhi ikhiqize amaphakethe ku-IP core TX yokudlulisa idatha yomsebenzisi. I-IP core ithumela lawa maphakethe kumzila we-loopback wangaphakathi nge-transceiver.
• Ngemuva kokuthi umamukeli oyinhloko we-IP ethola amaphakethe endleleni ye-loopback, icubungula ifayela
• Amaphakethe e-Interlaken futhi awathumele kusixhumi esibonakalayo sokudlulisa idatha somsebenzisi we-RX. I-exampi-le design ihlola ukuthi amaphakethe atholiwe futhi adluliselwe afanayo.
• I-hardware example design ihlanganisa ama-PLL angaphandle. Ungakwazi ukuhlola umbhalo ocacile files kwe view sample code esebenzisa indlela eyodwa engenzeka yokuxhuma ama-PLL angaphandle ku-Interlaken (2nd Generation) FPGA IP.
• I-Interlaken (2nd Generation) ye-hardware design example ihlanganisa izingxenye ezilandelayo:
  • I-Interlaken (2nd Generation) FPGA IP
  • I-Packet Generator kanye ne-Packet Checker
  • JTAG isilawuli esixhumana ne-System Console. Uxhumana ne-logic yeklayenti nge-System Console.

Umfanekiso 4. I-Interlaken (2nd Generation) Hardware Design Example High Level Block Diagram for E-tile NRZ Mode Variations

I-Interlaken (2nd Generation) ye-hardware design example eqondise ukuhluka kwemodi ye-E-tile PAM4 idinga iwashi elengeziwe mac_clkin elenziwa yi-IO PLL. Le PLL kufanele isebenzise iwashi lesithenjwa elifanayo elishayela i-pll_ref_clk.
Umfanekiso 5. I-Interlaken (2nd Generation) Hardware Design Example High Level Block Diagram for E-tile PAM4 Mode Variations

Ngokuhlukahluka kwemodi ye-E-tile PAM4, uma unika amandla okuthi Londoloza amashaneli e-transceiver angasetshenzisiwe kupharamitha ye-PAM4, imbobo yewashi yesithenjwa eyengeziwe iyengezwa (pll_ref_clk [1]). Lesi simboli kufanele sishayelwe ngefrikhwensi efanayo njengoba kuchazwe kusihleli sepharamitha ye-IP (imvamisa yewashi lesithenjwa yamashaneli agciniwe). I-Gcina amashaneli e-transceiver angasetshenzisiwe ye-PAM4 uyazikhethela. Iphinikhodi nezingqinamba ezihlobene ezinikezwe leli washi zibonakala ku-QSF uma ukhetha i-Intel Stratix® 10 noma ikhithi yokuthuthukisa ye-Intel Agilex 7 yokukhiqiza idizayini.
Qaphela: Okokuklama exampngokulingisa, ibhentshi lokuhlola lihlala lichaza imvamisa efanayo ye-pll_ref_clk[0] kanye ne-pll_ref_clk[1].
Ulwazi Oluhlobene
Intel Agilex 7 F-Series Transceiver-SoC Development Kit Umhlahlandlela Womsebenzisi

Ikhiqiza Umklamo
Umfanekiso 6. Inqubo

Landela lezi zinyathelo ukuze ukhiqize i-hardware example design kanye ne-testbench:

1. Kuhlelo lwe-Intel Quartus Prime Pro Edition, chofoza File ➤ Iseluleki Sephrojekthi Esisha sokudala iphrojekthi entsha ye-Intel Quartus Prime, noma chofoza File ➤ Vula Iphrojekthi ukuze uvule iphrojekthi ekhona ye-Intel Quartus Prime. Iwizadi ikutshela ukuthi ucacise idivayisi.
2. Cacisa umndeni wedivayisi ye-Intel Agilex 7 bese ukhetha idivayisi yomklamo wakho.
3. Kukhathalogi ye-IP, thola bese uchofoza kabili i-Interlaken (2nd Generation) Intel FPGA IP. Iwindi elisha le-IP elihlukile liyavela.
4. Cacisa igama lezinga eliphezulu ngokuhlukahluka kwakho kwe-IP yangokwezifiso. Umhleli wepharamitha ugcina izilungiselelo zokuhlukahluka kwe-IP ku-a file okuthiwa .ip.
5. Chofoza okuthi KULUNGILE. Umhleli wepharamitha uyavela.
   Umfanekiso 7. Example Design Tab ku-Interlaken (2nd Generation) Intel FPGA IP Parameter Editor
6. Kuthebhu ye-IP, cacisa imingcele yokuhluka kwakho okubalulekile kwe-IP.
7. Kuthebhu ye-PMA Adaptation, cacisa imingcele yokujwayela ye-PMA uma uhlela ukusebenzisa ukulungiswa kwe-PMA kokuhluka kwedivayisi yakho ye-E-tile. Lesi sinyathelo singokuzithandela:
   • Khetha okuthi Vumela inketho yokulayisha ethambile ye-IP.
   • Qaphela: Kufanele unike amandla inketho Yephoyinti Yokuqeda Iphutha Le-PHY Yomdabu (NPDME) kuthebhu ye-IP uma ukuzivumelanisa ne-PMA kunikwe amandla.
   • Khetha i-PMA adaptation preset for PMA adaptation Khetha ipharamitha.
   • Chofoza i-PMA Adaptation Preload ukuze ulayishe amapharamitha wokuzijwayeza okuqala nokuqhubekayo.
   • Cacisa inombolo yokucushwa kwe-PMA okuzosekelwa lapho ukulungiselelwa okuningi kwe-PMA kunikwe amandla kusetshenziswa Inombolo yepharamitha yokumisa ye-PMA.
   • Khetha ukuthi yikuphi ukucushwa kwe-PMA ozokulayisha noma ukukugcina usebenzisa Khetha ukucushwa kwe-PMA ozokulayisha noma ukukugcina.
   • Chofoza Layisha ukulungisa kusuka ekucushweni okukhethiwe kwe-PMA ukuze ulayishe izilungiselelo ezikhethiwe zokucushwa kwe-PMA.
   • Ukuze uthole ulwazi olwengeziwe mayelana nemingcele yokujwayela ye-PMA, bheka i-E-tile
     Transceiver PHY Umhlahlandlela Womsebenzisi.
8. Ku-Example Design ithebhu, khetha inketho yokulingisa ukuze ukhiqize ibhentshi lokuhlola, bese ukhetha inketho ye-Synthesis ukuze ukhiqize i-hardware ex.ampumklamo.
   • Qaphela: Kufanele ukhethe okungenani eyodwa yezinketho Zokulingisa noma Zokuhlanganiswa okukhiqiza i-Example Design Files.
9. Ngefomethi ye-HDL Ekhiqiziwe, khetha i-Verilog noma i-VHDL.
10. Kukhithi Yokuthuthukiswa Kwethagethi khetha inketho efanelekile.
    • Qaphela: Inketho ye-Intel Agilex 7 F-Series Transceiver SoC Development Kit itholakala kuphela uma iphrojekthi yakho icacisa igama ledivayisi ye-Intel Agilex 7 eqala ngo-AGFA012 noma i-AGFA014. Uma ukhetha inketho Yekhithi Yokuthuthukisa, imisebenzi yephinikhodi isethwa ngokwengxenye yedivayisi ye-Intel Agilex 7 Development Kit engu-AGFB014R24A2E2V futhi ingase ihluke kudivayisi yakho oyikhethile. Uma uhlose ukuhlola idizayini ku-hardware ku-PCB ehlukile, khetha inketho ethi Akukho futhi wenze iphinikhodi elifanele ku-.qsf file.
11. Chofoza okuthi Khiqiza Isibample Design. Khetha ExampIwindi le-Design Directory liyavela.
12. Uma ufuna ukushintsha i-design example mkhombandlela noma igama elivela kokumisiwe okubonisiwe (uflex_ilk_0_example_design), phequlula endleleni entsha bese uthayipha umklamo omusha exampigama lesikhombi.
13. Chofoza okuthi KULUNGILE.

Ulwazi Oluhlobene

• Intel Agilex 7 F-Series Transceiver-SoC Development Kit Umhlahlandlela Womsebenzisi
• I-E-tile Transceiver PHY Umhlahlandlela Womsebenzisi

Ukulingisa i-Design Example Testbench
Bheka ku-Interlaken (2nd Generation) Hardware Design Example High Level Block ye-E-tile NRZ Mode Variations kanye ne-Interlaken (2nd Generation) Hardware Design Example High Level Block ye-E-tile PAM4 Mode Ukuhlukahluka kwemidwebo yebhulokhi yebhentshi lokulingisa.
Umfanekiso 8. Inqubo

Landela lezi zinyathelo ukuze ulingise i-testbench:

1. Emyalweni womyalo, shintshela kumkhombandlela wokulingisa we-testbench. Inkomba ithiample_installation_dir>/example_design/ testbench yamadivayisi we-Intel Agilex 7.
2. Qalisa iskripthi sokulingisa sesifanisi esisekelwayo ozikhethele sona. Umbhalo uhlanganisa futhi uqhube ibhentshi lokuhlola kusifanisi. Iskripthi sakho kufanele sihlole ukuthi izibalo ze-SOP ne-EOP ziyafana ngemva kokuqedwa kokulinganisa. Bheka ithebula Izinyathelo Zokuqalisa Ukulingisa.

Ithebula 4. Izinyathelo Zokuqalisa Ukulingisa

Isifanisi	Iziyalezo
ModelSim SE noma QuestaSim	Emugqeni womyalo, thayipha -do vlog_pro.do Uma ukhetha ukulingisa ngaphandle kokuletha i-ModelSim GUI, thayipha i-vsim -c -do vlog_pro.do
I-VCS	Emugqeni womyalo, thayipha okuthi sh vcstest.sh
I-Xcelium	Emugqeni womyalo, thayipha okuthi sh xcelium.sh

Hlaziya imiphumela. Ukulingisa okuphumelelayo kuthumela futhi kwamukele amaphakethe, futhi kubonisa "Ukuhlola KUPHASIWE".
Ibhentshi lokuhlola le-ex designample uqeda imisebenzi elandelayo:

• Iqinisekisa i-Interlaken (2nd Generation) Intel FPGA IP.
• Iphrinta isimo se-PHY.
• Ihlola ukuvumelanisa kwe-metaframe (SYNC_LOCK) nemingcele yegama (vimba) (WORD_LOCK).
• Ilinda imizila ngayinye ukuthi ikhiywe futhi iqondaniswe.
• Iqala ukudlulisa amaphakethe.
• Ihlola izibalo zephakethe:
  • CRC24 amaphutha
  • Ama-SOP
  • EOPs

Okulandelayo sampokukhiphayo kubonisa ukuhlolwa okuphumelelayo kokulingisa okwenziwa kumodi ye-Interlaken:

Qaphela: I-Interlaken design exampI-le simulation testbench ithumela amaphakethe ayi-100 futhi ithola amaphakethe ayi-100. Okulandelayo sampokukhiphayo kubonisa ukuhlolwa okuphumelelayo kokulingisa okwenziwa kumodi ye-Interlaken Look-aside:

Qaphela: Inani lamaphakethe (ama-SOP nama-EOP) liyahlukahluka ngomzila ngamunye ku-Interlaken Lookaside design example simulation sample okukhiphayo.
Ulwazi Oluhlobene
I-Hardware Design Example Izingxenye ekhasini 6

Ukuhlanganisa kanye nokulungiselela i-Design Exampku-Hardware
Umfanekiso 9. Inqubo

Ukuhlanganisa nokusebenzisa ukuhlolwa kokubonisa ku-hardware example design, landela lezi zinyathelo:

1. Qinisekisa i-hardware exampi-design generation iqedile.
2. Kuhlelo lwe-Intel Quartus Prime Pro Edition, vula iphrojekthi ye-Intel Quartus Primeample_installation_dir>/example_design/quartus/ example_design.qpf>.
3. Kumenyu Yokucubungula, chofoza Qala Ukuhlanganisa.
4. Ngemva kokuhlanganiswa ngempumelelo, i-.sof file iyatholakala ohlwini lwakho lwemibhalo olushilo. Landela lezi zinyathelo ukuze uhlele i-hardware exampLe design kudivayisi ye-Intel Agilex 7:
   • a. Xhuma i-Intel Agilex 7 F-Series Transceiver-SoC Development Kit kukhompuyutha engusokhaya.
   • b. Yethula uhlelo lokusebenza lokulawula iwashi, oluyingxenye yekhithi yokuthuthukisa, bese usetha amafrikhwensi amasha e-design ex.ample. Ngezansi isethingi yefrikhwensi kuhlelo Lokulawula Iwashi:
   • • I-Si5338 (U37), CLK1- 100 MHz
   • • I-Si5338 (U36), CLK2- 153.6 MHz
   • • Si549 (Y2), OKUPHUMILE- Misa inani le-pll_ref_clk(1) ngokwesidingo sakho somklamo.
   • c. Kumenyu yamathuluzi, chofoza uMhleli.
   • d. Ku-Programmer, chofoza Ukusethwa Kwezingxenyekazi zekhompuyutha.
   • e. Khetha idivayisi yokuhlela.
   • f. Khetha bese wengeza i-Intel Agilex 7 F-Series Transceiver-SoC Development Kit lapho iseshini yakho ye-Intel Quartus Prime ingaxhumeka kuyo.
   • g. Qinisekisa ukuthi Imodi isethwe ku-JTAG.
   • h. Khetha idivayisi ye-Intel Agilex 7 bese uchofoza Engeza idivayisi. I-Programmer ibonisa idayagramu yebhlokhi yokuxhumana phakathi kwamadivayisi ebhodini lakho.
   • i. Emgqeni ne-.sof yakho, hlola ibhokisi le-.sof.
   • j. Thikha ibhokisi kokuthi Uhlelo/Lungisa ikholomu.
   • k. Chofoza Qala.

Ulwazi Oluhlobene

• Izinhlelo ze-Intel FPGA Amadivayisi ekhasini 0
• Ukuhlaziya nokulungisa amadizayini nge-System Console
• Intel Agilex 7 F-Series Transceiver-SoC Development Kit Umhlahlandlela Womsebenzisi

Ihlola i-Hardware Design Example
Ngemva kokuhlanganisa i-Interlaken (2nd Generation) Intel FPGA IP core design exampfuthi ulungiselele idivayisi yakho, ungasebenzisa Ikhonsoli Yesistimu ukuze uhlele umongo we-IP kanye namarejista awo ayinhloko we-PHY IP ashumekiwe.

Landela lezi zinyathelo ukuze uveze Ikhonsoli Yesistimu futhi uhlole i-ex yedizayini yehadiweample:

1. Kuhlelo lwe-Intel Quartus Prime Pro Edition, kumenyu ethi Amathuluzi, chofoza Amathuluzi Okulungisa Amaphutha Esistimu ➤ Ikhonsoli Yesistimu.
2. Shintsha ku-ample_installation_dir>isibample_design/hwtest directory.
3. Ukuze uvule uxhumano ku-JTAG master, thayipha umyalo olandelayo: umthombo sysconsole_testbench.tcl
4. Ungavula imodi ye-serial loopback ye-serial nge-ex yomklamo elandelayoampngiyala:
   • a. izibalo: Iphrinta imininingwane yesimo esijwayelekile.
   • b. sys_reset: Isetha kabusha isistimu.
   • c. i-loop_on: Ivula i-loopback ye-serial yangaphakathi.
   • d. gijima_isbample_design: Isebenzisa i-ex designample.
   • Qaphela: Kufanele usebenzise umyalo we-loop_on ngaphambi kwe-run_exampumyalo we_design. I-run_exampI-le_design isebenzisa imiyalo elandelayo ngokulandelana: sys_reset->stat->gen_on->stat->gen_off.
   • Qaphela: Uma ukhetha okuthi Vumela i-adaptation load soft option, the run_exampumyalo we-le_design wenza ukulinganisa kokuqala kokujwayela ohlangothini lwe-RX ngokusebenzisa umyalo we-run_load_PMA_configuration.
5. Ungavala imodi ye-serial loopback yangaphakathi nge-ex yomklamo elandelayoampumyalo othi:
   • a. i-loop_off: Ivala i-loopback ye-serial yangaphakathi.
6. Ungakwazi ukuhlela i-IP core nge-ex yedizayini eyengeziwe elandelayoampngiyala:
   • a. gen_on: Inika amandla ijeneretha yephakethe.
   • b. gen_off: Ikhubaza ijeneretha yephakethe.
   • c. run_test_loop: Iqalisa ukuhlolwa kwe izikhathi zokuhlukahluka kwe-E-tile NRZ kanye ne-PAM4.
   • d. clear_err: Isula zonke izingcezu zamaphutha anamathelayo.
   • e. setha_imodi_yokuhlola : Isetha ukuhlolwa ukuze kuqalise ngemodi ethile.
   • f. get_test_mode: Iphrinta imodi yokuhlola yamanje.
   • g. set_burst_size : Isetha usayizi wokuqhuma ngamabhayithi.
   • h. get_burst_size: Imininingwane kasayizi wokuphrinta.

Ukuhlola okuyimpumelelo kuphrinta umlayezo HW_TEST:PASS. Ngezansi imibandela yokuphasa yokuqaliswa kokuhlolwa:

• Awekho amaphutha e-CRC32, CRC24, nesihloli.
• Ama-SOP adlulisiwe kanye nama-EOP kufanele afane nowamukelwe.

Okulandelayo sampi-le output ibonisa ukuhlolwa okuphumelelayo okwenziwa kumodi ye-Interlaken:

Ukuhlolwa okuphumelelayo kuphrinta HW_TEST : Umlayezo we-PASS. Ngezansi imibandela yokuphasa yokuqaliswa kokuhlolwa:

• Awekho amaphutha e-CRC32, CRC24, nesihloli.
• Ama-SOP adlulisiwe kanye nama-EOP kufanele afane nowamukelwe.

Okulandelayo sampi-le okukhiphayo ibonisa ukuhlolwa okuphumelelayo kumodi ye-Interlaken Lookaside:

I-Design Example Incazelo

Umklamo exampI-le ibonisa ukusebenza kwe-Interlaken IP core.

Ulwazi Oluhlobene
I-Interlaken (2nd Generation) FPGA IP User Guide

I-Design Example Behaviour
Ukuze uhlole idizayini kuhadiwe, thayipha imiyalo elandelayo kukhonsoli Yesistimu::

1. Umthombo wokusethwa file:
   • % umthomboample>uflex_ilk_0_example_design/example_design/hwtest/ sysconsole_testbench.tcl
2. Yenza ukuhlolwa:
   • % run_example_design
3. I-Interlaken (2nd Generation) ye-hardware design example uqedela izinyathelo ezilandelayo:
   • a. Isetha kabusha i-IP ye-Interlaken (yesizukulwane sesibili).
   • b. Ilungiselela i-Interlaken (2nd Generation) IP kumodi ye-loopback yangaphakathi.
   • c. Ithumela uchungechunge lwamaphakethe e-Interlaken anedatha echazwe kusengaphambili ekulayishweni okukhokhelwayo kusixhumi esibonakalayo sokudlulisa idatha somsebenzisi we-TX somongo we-IP.
   • d. Ihlola amaphakethe atholiwe bese ibika isimo. Isihloli sephakethe esifakwe kumklamo we-hardware exampI-le inikeza amakhono alandelayo okuhlola iphakethe:
     • Ihlola ukuthi ukulandelana kwephakethe elidlulisiwe kulungile.
     • Ihlola ukuthi idatha etholiwe ifana namanani alindelekile ngokuqinisekisa ukuthi izibalo zokuqala zephakethe (SOP) kanye nokuphela kwephakethe (EOP) ziqondana ngenkathi idatha idluliswa futhi yamukelwa.

Izimpawu Zokuxhumana
Ithebula 5. I-Design Example Interface Signals

Igama Lembobo	Isiqondiso	Ububanzi (Amabhithi)	Incazelo
mgmt_clk	Okokufaka	1	Okokufaka kwewashi lesistimu. Imvamisa yewashi kufanele ibe ngu-100 MHz.
pll_ref_clk / pll_ref_clk[1:0](2)	Okokufaka	1/2	Iwashi lereferensi ye-Transceiver. Ishayela i-RX CDR PLL.
waqhubeka...

Igama Lembobo	Isiqondiso	Ububanzi (Amabhithi)	Incazelo
			pll_ref_clk[1] itholakala kuphela uma unika amandla Londoloza okungasetshenzisiwe Qaphela: Amashaneli e-transceiver we-PAM4 ipharamitha ekuhlukeni kwe-IP yemodi ye-E-tile PAM4.
rx_pin	Okokufaka	Inombolo yemizila	Isamukeli sedatha yephinikhodi ye-SERDES.
tx_pin	Okukhiphayo	Inombolo yemizila	Dlulisa iphinikhodi yedatha ye-SERDES.
rx_pin_n	Okokufaka	Inombolo yemizila	Isamukeli sedatha yephinikhodi ye-SERDES. Le siginali itholakala kuphela ezinhlobonhlobo zedivayisi yemodi ye-E-tile PAM4.
tx_pin_n	Okukhiphayo	Inombolo yemizila	Dlulisa iphinikhodi yedatha ye-SERDES. Le siginali itholakala kuphela ezinhlobonhlobo zedivayisi yemodi ye-E-tile PAM4.
mac_clk_pll_ref	Okokufaka	1	Lesi siginali kufanele ishayelwe i-PLL futhi kufanele isebenzise umthombo wewashi ofanayo oshayela i-pll_ref_clk. Le siginali itholakala kuphela ezinhlobonhlobo zedivayisi yemodi ye-E-tile PAM4.
usr_pb_reset_n	Okokufaka	1	Ukuhlelwa kabusha kwesistimu.

Ulwazi Oluhlobene
Izimpawu Zokuxhumana

Bhalisa imephu
Qaphela: • Umklamo ExampIkheli lerejista liqala ngo-0x20** kuyilapho ikheli lerejista eliyinhloko le-Interlaken IP liqala ngo-0x10**.

• Ikhodi yokufinyelela: RO—Funda Kuphela, kanye ne-RW—Funda/Bhala.
• Ikhonsoli yesistimu ifunda umklamo example irejista futhi ibike isimo sokuhlola esikrinini.

Ithebula 6. I-Design Example Bhalisa imephu ye-Interlaken Design Example

I-Offset	Igama	Ukufinyelela	Incazelo
8h00	Igodliwe
8h01	Igodliwe
8h02	Ukusethwa kabusha kwesistimu ye-PLL	RO	Amabhithi alandelayo abonisa isicelo sokusetha kabusha uhlelo lwe-PLL futhi unike amandla inani: • Ibhithi [0] – sys_pll_rst_req • Ibhithi [1] – sys_pll_rst_en
8h03	Umzila we-RX uqondaniswe	RO	Ibonisa ukuqondanisa komzila we-RX.
8h04	IZWI likhiyiwe	RO	[NUM_LANES–1:0] – Ukuhlonza imingcele yegama (vimba).
waqhubeka...

Uma unika amandla okuthi Londoloza amashaneli e-transceiver angasetshenzisiwe kupharamitha ye-PAM4, imbobo yewashi yesithenjwa eyengeziwe iyengezwa ukuze kulondolozwe umzila wezigqila we-PAM4 ongasetshenzisiwe.

I-Offset	Igama	Ukufinyelela	Incazelo
8h05	Ukuvumelanisa kukhiyiwe	RO	[NUM_LANES–1:0] – Ukuvumelanisa i-Metaframe.
8'h06 - 8'h09	Isibalo samaphutha se-CRC32	RO	Ibonisa inani lamaphutha e-CRC32.
8h0a	Isibalo samaphutha se-CRC24	RO	Ibonisa inani lamaphutha e-CRC24.
8h0b	Isignali yokuchichima/Ukugeleza ngaphansi	RO	Amabhithi alandelayo abonisa: • I-Bit [3] – isignali ye-TX egelezayo • I-Bit [2] – isignali yokuchichima ye-TX • Ibhithi [1] – Isignali yokuchichima ye-RX
8h0c	Isibalo se-SOP	RO	Ibonisa inombolo ye-SOP.
8h0D	Ukubala kwe-EOP	RO	Ibonisa inombolo ye-EOP
8h0e	Isibalo samaphutha	RO	Ibonisa inombolo yamaphutha alandelayo: • Ukulahleka kwendlela • Igama lokulawula elingekho emthethweni • Iphethini yokufaka uzimele engekho emthethweni • I-SOP noma inkomba ye-EOP ayikho
8h0f	send_data_mm_clk	RW	Bhala oku-1 kuye kubhithi [0] ukuze unike amandla isignali yokukhiqiza.
8h10	Iphutha lokuhlola		Ibonisa iphutha lokuhlola. (Iphutha ledatha ye-SOP, iphutha lenombolo yesiteshi, kanye nephutha ledatha ye-PLD)
8h11	Ilokhi yesistimu ye-PLL	RO	I-Bit [0] ibonisa inkomba yokukhiya i-PLL.
8h14	Inani le-TX SOP	RO	Ibonisa inombolo ye-SOP ekhiqizwe ijeneretha yephakethe.
8h15	Inani eliphakeme kakhulu lama-TX EOP	RO	Ibonisa inombolo ye-EOP ekhiqizwe ijeneretha yephakethe.
8h16	Iphakethe eliqhubekayo	RW	Bhala 1 kuya kubhithi [0] ukuze unike amandla iphakethe eliqhubekayo.
8h39	Isibalo samaphutha e-ECC	RO	Ibonisa inombolo yamaphutha e-ECC.
8h40	I-ECC ilungise inani lamaphutha	RO	Ibonisa inombolo yamaphutha e-ECC alungisiwe.

I-Design Example Bhalisa imephu ye-Interlaken Bheka eceleni Yomklamo Example
Sebenzisa le mephu yerejista lapho udala i-ex designample nge-Vula ipharamitha yemodi ye-Interlaken Look-aside evuliwe.

I-Offset	Igama	Ukufinyelela	Incazelo
8h00	Igodliwe
8h01	Setha kabusha isibali	RO	Bhala 1 kuya kubhithi [0] ukuze usule i-TX ne-RX counter bit elinganayo.
8h02	Ukusethwa kabusha kwesistimu ye-PLL	RO	Amabhithi alandelayo abonisa isicelo sokusetha kabusha uhlelo lwe-PLL futhi unike amandla inani: • Ibhithi [0] – sys_pll_rst_req • Ibhithi [1] – sys_pll_rst_en
8h03	Umzila we-RX uqondaniswe	RO	Ibonisa ukuqondanisa komzila we-RX.
8h04	IZWI likhiyiwe	RO	[NUM_LANES–1:0] – Ukuhlonza imingcele yegama (vimba).
8h05	Ukuvumelanisa kukhiyiwe	RO	[NUM_LANES–1:0] – Ukuvumelanisa i-Metaframe.
8'h06 - 8'h09	Isibalo samaphutha se-CRC32	RO	Ibonisa inani lamaphutha e-CRC32.
8h0a	Isibalo samaphutha se-CRC24	RO	Ibonisa inani lamaphutha e-CRC24.
waqhubeka...

I-Offset	Igama	Ukufinyelela	Incazelo
8h0b	Igodliwe
8h0c	Isibalo se-SOP	RO	Ibonisa inombolo ye-SOP.
8h0D	Ukubala kwe-EOP	RO	Ibonisa inombolo ye-EOP
8h0e	Isibalo samaphutha	RO	Ibonisa inombolo yamaphutha alandelayo: • Ukulahleka kwendlela • Igama lokulawula elingekho emthethweni • Iphethini yokufaka uzimele engekho emthethweni • I-SOP noma inkomba ye-EOP ayikho
8h0f	send_data_mm_clk	RW	Bhala oku-1 kuye kubhithi [0] ukuze unike amandla isignali yokukhiqiza.
8h10	Iphutha lokuhlola	RO	Ibonisa iphutha lokuhlola. (Iphutha ledatha ye-SOP, iphutha lenombolo yesiteshi, kanye nephutha ledatha ye-PLD)
8h11	Ilokhi yesistimu ye-PLL	RO	I-Bit [0] ibonisa inkomba yokukhiya i-PLL.
8h13	Ukubambezeleka kwesibalo	RO	Ikhombisa inombolo yokubambezeleka.
8h14	Inani le-TX SOP	RO	Ibonisa inombolo ye-SOP ekhiqizwe ijeneretha yephakethe.
8h15	Inani eliphakeme kakhulu lama-TX EOP	RO	Ibonisa inombolo ye-EOP ekhiqizwe ijeneretha yephakethe.
8h16	Iphakethe eliqhubekayo	RO	Bhala 1 kuya kubhithi [0] ukuze unike amandla iphakethe eliqhubekayo.
8h17	Ikhawunta ye-TX ne-RX iyalingana	RW	Ikhombisa ukuthi i-TX ne-RX counter ziyalingana.
8h23	Nika amandla ukubambezeleka	WO	Bhala oku-1 kuye kubhithi [0] ukuze unike amandla ukukala kokubambezeleka.
8h24	Ukubambezeleka kulungile	RO	Ikhombisa ukuthi ukukala ukubambezeleka kulungile.

I-Interlaken (2nd Generation) Intel Agilex 7 FPGA IP Design Example Izingobo zomlando zomhlahlandlela womsebenzisi

• Ukuze uthole izinguqulo zakamuva nezidlule zalo mhlahlandlela womsebenzisi, bheka i-Interlaken (2nd
• Generation) Intel Agilex 7 FPGA IP Design Example Umhlahlandlela Womsebenzisi inguqulo ye-HTML. Khetha inguqulo bese uchofoza Landa. Uma i-IP noma inguqulo yesofthiwe ingekho ohlwini, inkomba yomsebenzisi ye-IP yangaphambilini noma inguqulo yesofthiwe iyasebenza.
• Izinguqulo ze-IP ziyefana nezinguqulo zesofthiwe ye-Intel Quartus Prime Design Suite kufika ku-v19.1. Kusukela ku-Intel Quartus Prime Design Suite software version 19.2 noma kamuva, ama-IP cores anohlelo olusha lwenguqulo ye-IP.

Umlando Wokubuyekezwa Kombhalo we-Interlaken (2nd Generation) Intel Agilex 7 FPGA IP Design Example Umhlahlandlela Womsebenzisi

Inguqulo Yedokhumenti	Inguqulo ye-Intel Quartus Prime	Inguqulo ye-IP	Izinguquko
2023.06.26	23.2	21.1.1	• Kwengezwe usekelo lwe-VHDL lokuhlanganiswa nemodeli yokulingisa. • Kubuyekezwe igama lomndeni lomkhiqizo ku-“Intel Agilex 7”.
2022.08.03	21.3	20.0.1	Kulungiswe idivayisi ye-OPN ye-Intel Agilex F-Series Transceiver-SoC Development Kit.
2021.10.04	21.3	20.0.1	• Ukwesekwa okwengeziwe kwe-QuestaSim simulator. • Ukwesekwa okususiwe kwe-NCSim simulator.
2021.02.24	20.4	20.0.1	• Ulwazi olungeziwe mayelana nokugcina isiteshi sokudlulisa ulwazi esingasetshenzisiwe se-PAM4 esigabeni: I-Hardware Design Example Components. • Kwengezwe incazelo yesignali ye-pll_ref_clk[1] esigabeni: Izimpawu Zokuxhumana.
2020.12.14	20.4	20.0.0	• Kubuyekeziwe sample hardware yokuhlola okukhiphayo kwemodi ye-Interlaken kanye nemodi ye-Interlaken Look-aside esigabeni Ihlola i-Hardware Design Example. • Imephu yerejista ebuyekeziwe ye-Interlaken Look-aside design example esigabeni Bhalisa imephu. • Kwengezwe indlela yokuphasa yokuhlolwa kwezingxenyekazi zekhompuyutha ngempumelelo esigabeni Ihlola i-Hardware Design Example.
2020.10.16	20.2	19.3.0	Umyalo olungisiwe wokuqalisa ukulinganiswa kokujwayela kokuqala ohlangothini lwe-RX ngaphakathi Ihlola i-Hardware Design Example ingxenye.
2020.06.22	20.2	19.3.0	• Umklamo exampi-le iyatholakala ngemodi ye-Interlaken Look- eceleni. • Ukuhlolwa kwezingxenyekazi zekhompuyutha ze-design example iyatholakala ngokuhlukahluka kwedivayisi ye-Intel Agilex. • Kwengezwe Umfanekiso: Umdwebo Webhulokhi Osezingeni eliphezulu we-Interlaken (Isizukulwane Sesibili) Umklamo Example. • Kubuyekezwe izigaba ezilandelayo: —   Izingxenyekazi zekhompuyutha nezidingo zeSoftware —   Ukwakheka Kwemibhalo • Kulungiswe izibalo ezilandelayo ukuze kufakwe isibuyekezo esihlobene ne-Interlaken Look-aside: —   Umfanekiso: I-Interlaken (2nd Generation) Hardware Design Example High Level Block Diagram for E- tile NRZ Mode Variations —   Umfanekiso: I-Interlaken (2nd Generation) Hardware Design Example High Level Block Diagram for E- tile PAM4 Mode Variations • Kubuyekeziwe Umfanekiso: IP Parameter Editor.
waqhubeka...

Inguqulo Yedokhumenti	Inguqulo ye-Intel Quartus Prime	Inguqulo ye-IP	Izinguquko
			• Ulwazi olungeziwe mayelana nezilungiselelo zefrikhwensi ohlelweni lokulawula iwashi esigabeni Ukuhlanganisa kanye nokulungiselela i-Design Exampku-Hardware. • Kwengezwe imiphumela yokuhlola yokubheka eceleni kwe-Interlaken ezigabeni ezilandelayo: —   Ukulingisa i-Design Example Testbench —   Ihlola i-Hardware Design Example • Kwengezwe amasignali amasha alandelayo ku Izimpawu Zokuxhumana ingxenye: - mgmt_clk — rx_pin_n — tx_pin_n - mac_clk_pll_ref • Kwengezwe imephu yerejista ye-Interlaken Look-aside design example in ingxenye: Bhalisa imephu.
2019.09.30	19.3	19.2.1	Kukhishwe i-clk100. I-mgmt_clk isebenza njengewashi eliyireferensi ku-IO PLL kulokhu okulandelayo: •    Umfanekiso: I-Interlaken (2nd Generation) Hardware Design Example High Level Block Diagram for E-tile NRZ Mode Variations. •    Umfanekiso: I-Interlaken (2nd Generation) Hardware Design Example High Level Block Diagram for E-tile PAM4 Mode Variations.
2019.07.01	19.2	19.2	Ukukhishwa kokuqala.

I-Interlaken (2nd Generation) Intel Agilex® 7 FPGA IP Design Example Umhlahlandlela Womsebenzisi

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Intel Interlaken 2nd Generation Agilex 7 FPGA IP Design Example [pdf] Umhlahlandlela Womsebenzisi I-Interlaken 2nd Generation Agilex 7 FPGA IP Design Example, Interlaken, 2nd Generation Agilex 7 FPGA IP Design Example, FPGA IP Design Example, IP Design Example, Design Example

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