Intel Interlaken 2nd Generation Agilex 7 FPGA IP Dhizaini Example

Product Information

Iyo Interlaken (2nd Generation) FPGA IP musimboti chinhu cheIntel Agilex 7 FPGA. Inopa simulation testbench uye hardware dhizaini example iyo inotsigira kuunganidza uye kuyedza hardware. Iyo yakagadzirwa example inowanikwawo kune iyo Interlaken Tarisa-padivi chimiro. Iyo IP musimboti inotsigira NRZ uye PAM4 modhi yeE-tile zvishandiso uye inogadzira dhizaini examples kune ese anotsigirwa musanganiswa wenhamba yenzira uye data data.

Hardware uye Software Zvinodiwa
Iyo Interlaken (2nd Generation) IP musimboti dhizaini example inoda iyo Intel Agilex 7 F-Series Transceiver-SoC Development Kit. Ndokumbira utarise kuBhuku reMushandisi weti yekuvandudza kuti uwane rumwe ruzivo.

Directory Structure
Iyo yakagadzirwa Interlaken (2nd Generation) example dhizaini inosanganisira anotevera madhairekitori:

• example_design: Rine chikuru files yekugadzira example.
• ilk_uflex: Contains files inoenderana neiyo Interlaken Tarisa-padivi modhi sarudzo.
• ila_uflex: Contains files ine hukama neiyo Interlaken Tarisa-padivi modhi sarudzo (inogadzirwa chete kana yasarudzwa).

Mirayiridzo Yekushandiswa Kwechigadzirwa

Kushandisa iyo Interlaken (2nd Generation) FPGA IP musimboti dhizaini example, tevera matanho aya:

1. Ita shuwa kuti une Intel Agilex 7 F-Series Transceiver-SoC Development Kit.
2. Gadzira iyo dhizaini exampndinoshandisa simulator.
3. Ita simulation inoshanda kuti uone dhizaini.
4. Gadzira iyo dhizaini exampuye kushandisa parameter editor.
5. Gadzira iyo dhizaini exampuye kushandisa Quartus Prime.
6. Ita bvunzo yehardware kusimbisa dhizaini.

Cherechedza: Iyo Interlaken Tarisa-padivi modhi sarudzo inowanikwa yekusarudza muIP parameter mupepeti. Kana zvasarudzwa, kuwedzera files ichagadzirwa mu "ila_uflex" dhairekitori.

Quick Start Guide

• Iyo Interlaken (2nd Generation) FPGA IP musimboti inopa simulation testbench uye hardware dhizaini ex.ample iyo inotsigira kuunganidza uye kuyedza hardware.
• Paunogadzira iyo dhizaini example, iyo parameter editor inogadzira iyo fileinodiwa kutevedzera, kuunganidza, uye kuyedza dhizaini muhardware.
• Iyo yakagadzirwa example inowanikwawo yeInterlaken Tarisa-padivi chimiro.
• Iyo testbench uye dhizaini example inotsigira NRZ uye PAM4 modhi yeE-tile zvishandiso.
• Iyo Interlaken (2nd Generation) FPGA IP musimboti inogadzira dhizaini examples kune ese anotsigirwa musanganiswa wenhamba yenzira uye data data.

Mufananidzo 1. Matanho Ekuvandudza eDesign Example

Iyo Interlaken (2nd Generation) IP musimboti dhizaini example inotsigira zvinotevera maficha:

• Yemukati TX kuenda kuRX serial loopback modhi
• Inogadzira otomatiki mapeji akagadziriswa saizi
• Basic packet yekutarisa kugona
• Kugona kushandisa System Console kuseta zvakare dhizaini yekuyedzazve chinangwa
• PMA kugadzirisa

Intel Corporation. Kodzero dzese dzakachengetwa. Intel, iyo Intel logo, uye mamwe maIntel mamaki zviratidzo zveIntel Corporation kana vatsigiri vayo. Intel inobvumidza kuita kwayo FPGA uye semiconductor zvigadzirwa kune zvazvino zvirevo zvinoenderana neIntel's standard waranti, asi inochengetera kodzero yekuita shanduko kune chero zvigadzirwa nemasevhisi chero nguva pasina chiziviso. Intel haitore mutoro kana mutoro unobva mukushandisa kana kushandiswa kwechero ruzivo, chigadzirwa, kana sevhisi inotsanangurwa pano kunze kwekunge yakabvumiranwa nekunyora neIntel. Vatengi veIntel vanorairwa kuti vawane yazvino vhezheni yezvakatemwa zvemudziyo vasati vavimba nechero ruzivo rwakaburitswa uye vasati vaisa maodha ezvigadzirwa kana masevhisi. *Mamwe mazita nemhando zvinogona kunzi ndezvevamwe.

Mufananidzo 2. Yepamusoro-mwero Block Dhizaini yeInterlaken (2nd Generation) Dhizaini Example

Related Information

• Interlaken (2nd Generation) FPGA IP User Guide
• Interlaken (2nd Generation) Intel FPGA IP Release Notes

Hardware uye Software

Hardware uye Software Zvinodiwa
Kuedza example dhizaini, shandisa zvinotevera Hardware uye software:

• Intel® Quartus® Prime Pro Edition software
• System Console
• Inotsigirwa simulators:
  • Siemens* EDA ModelSim* SE kana QuestaSim*
  • Synopsy* VCS*
  • Cadence* Xcelium*
• Intel Agilex® 7 F-Series Transceiver-SoC Development Kit (AGFB014R24A2E2V)

Related Information
Intel Agilex 7 F-Series Transceiver-SoC Development Kit User Guide
Directory Structure
Iyo Interlaken (2nd Generation) IP musimboti dhizaini example file madhairekitori ane zvinotevera kugadzirwa files yekugadzira example.

Mufananidzo 3. Dhairekitori Maumbirwo eiyo Yakagadzirwa Interlaken (Chizvarwa chechipiri) Example Dhizaini

Iyo hardware kumisikidzwa, simulation, uye bvunzo files dziri muample_installation_dir>/uflex_ilk_0_example_design.
Tafura 1. Interlaken (2nd Generation) IP Core Hardware Dhizaini Example File Tsananguro Idzi files vari muample_installation_dir>/uflex_ilk_0_example_design/ example_design/quartus directory.

File Mazita	Tsanangudzo
example_design.qpf	Intel Quartus Prime chirongwa file.
example_design.qsf	Intel Quartus Prime purojekiti marongero file
example_design.sdc jtag_timing_template.sdc	Synopsys Dhizaini Constraint file. Iwe unogona kukopa uye kugadzirisa kune yako dhizaini.
sysconsole_testbench.tcl	Main file yekuwana System Console

Tafura 2. Interlaken (2nd Generation) IP Core Testbench File Tsanangudzo
Izvi file iri muample_installation_dir>/uflex_ilk_0_example_design/ example_design/rtl directory.

File Zita	Tsanangudzo
top_tb.sv	Top-level testbench file.

Tafura 3. Interlaken (2nd Generation) IP Core Testbench Scripts
Izvi files vari muample_installation_dir>/uflex_ilk_0_example_design/ example_design/testbench directory.

File Zita	Tsanangudzo
vcstest.sh	Iyo VCS script yekumhanyisa testbench.
vlog_pro.do	Iyo ModelSim SE kana QuestaSim script yekumhanyisa testbench.
xcelium.sh	Iyo Xcelium script yekumhanyisa testbench.

Hardware Dhizaini Example Components

• The example dhizaini inobatanidza sisitimu uye PLL referensi wachi uye inodiwa dhizaini zvikamu. The example dhizaini inogadzirisa iyo IP musimboti mune yemukati loopback modhi uye inogadzira mapaketi paIP musimboti TX mushandisi data data interface. Iyo IP musimboti inotumira aya mapaketi pane yemukati loopback nzira kuburikidza neiyo transceiver.
• Mushure meiyo IP yepakati inogamuchira inogamuchira mapaketi paiyo loopback nzira, inogadzirisa iyo
• Interlaken mapaketi uye oaendesa paRX mushandisi data data interface. The example dhizaini inotarisa kuti mapaketi akagamuchirwa uye akatapurirana mechi.
• Hardware example dhizaini inosanganisira ekunze PLLs. Unogona kuongorora chinyorwa chakajeka files kuti view sample kodhi inoshandisa imwe nzira inogoneka yekubatanidza ekunze PLLs kune Interlaken (2nd Generation) FPGA IP.
• Iyo Interlaken (2nd Generation) hardware dhizaini example inosanganisira zvinotevera zvikamu:
  • Interlaken (2nd Generation) FPGA IP
  • Packet jenareta uye Packet Checker
  • JTAG controller inotaurirana neSystem Console. Iwe unotaurirana nemutengi logic kuburikidza neSystem Console.

Mufananidzo 4. Interlaken (2nd Generation) Hardware Dhizaini Example High Level Block Digiramu yeE-tile NRZ Mode Kusiyana

Iyo Interlaken (2nd Generation) hardware dhizaini exampiyo inonangana neE-tile PAM4 modhi kusiyanisa inoda imwe wachi mac_clkin inogadzirwa neIO PLL. Iyi PLL inofanirwa kushandisa imwechete referensi wachi inotyaira iyo pll_ref_clk.
Mufananidzo 5. Interlaken (2nd Generation) Hardware Dhizaini Example High Level Block Digiramu yeE-tile PAM4 Mode Kusiyana

Kune E-tile PAM4 modhi kusiyanisa, kana iwe uchigonesa Chengetedza isina kushandiswa transceiver chiteshi chePAM4 parameter, imwe referensi wachi yewachi inowedzerwa (pll_ref_clk [1]). Ichi chiteshi chinofanirwa kufambiswa panguva imwechete sekutsanangurwa muIP parameter mupepeti (Reference wachi frequency yematanho akachengetedzwa). Iyo Chengetedza isina kushandiswa transceiver nzira yePAM4 inosarudzika. Pini uye zvipingamupinyi zvine hukama zvakapihwa wachi iyi zvinoonekwa muQSF paunosarudza Intel Stratix® 10 kana Intel Agilex 7 yekuvandudza kit yekugadzira dhizaini.
Cherechedza: For design example simulation, testbench inogara ichitsanangura yakafanana frequency ye pll_ref_clk[0] uye pll_ref_clk[1].
Related Information
Intel Agilex 7 F-Series Transceiver-SoC Development Kit User Guide

Kugadzira Dhizaini
Mufananidzo 6. Maitiro

Tevedza nhanho idzi kugadzira iyo hardware example dhizaini uye testbench:

1. MuIntel Quartus Prime Pro Edition software, tinya File ➤ New Project Wizard kugadzira Intel Quartus Prime purojekiti itsva, kana kudzvanya File ➤ Vhura Project kuvhura iripo Intel Quartus Prime project. Iyo wizard inokukurudzira kuti utaure mudziyo.
2. Rondedzera mudziyo mhuri Intel Agilex 7 uye sarudza mudziyo dhizaini yako.
3. Muiyo IP Catalog, tsvaga uye tinya kaviri Interlaken (2nd Generation) Intel FPGA IP. The New IP Variant hwindo rinoonekwa.
4. Taura zita repamusoro-soro kune yako tsika IP musiyano. Iyo parameter mupepeti inochengetedza iyo IP kusiyanisa marongero mune a file zita .ip.
5. Dzvanya OK. Iyo parameter editor inooneka.
   Mufananidzo 7. Exampuye Dhizaini Tab muInterlaken (2nd Generation) Intel FPGA IP Parameter Mharidzo
6. PaI IP tab, tsanangura maparamita eiyo IP yako musimboti musiyano.
7. Pa PMA Adaptation tab, tsanangura iyo PMA inogadziriswa paramita kana ukaronga kushandisa PMA kuchinjika kune yako E-tile mudziyo musiyano. Danho iri nderokusarudza:
   • Sarudza Bvumira gadziriso yakapfava IP sarudzo.
   • Cherechedza: Iwe unofanirwa kugonesa Inogonesa Native PHY Debug Master Endpoint (NPDME) sarudzo pane iyo IP tebhu kana PMA inogadziriswa inogoneswa.
   • Sarudza PMA yakagadziridzwa preset yePMA inogadziriswa Sarudza parameter.
   • Dzvanya PMA Adaptation Preload kurodha yekutanga uye inoenderera inogadziriswa paramita.
   • Taura huwandu hwePMA zvigadziriso zvekutsigira kana akawanda PMA magadzirirwo akagoneswa uchishandisa Nhamba yePMA kumisikidza parameter.
   • Sarudza iyo PMA gadziriso yekuisa kana kuchengeta uchishandisa Sarudza PMA gadziriso yekuisa kana kuchengeta.
   • Dzvanya Load adaptation kubva yakasarudzwa PMA kumisikidza kurodha yakasarudzwa PMA yekumisikidza marongero.
   • Kuti uwane rumwe ruzivo nezve PMA inogadziriswa paramita, tarisa iyo E-tile
     Transceiver PHY User Guide.
8. Pamusoro peExample Dhizaini tab, sarudza iyo Simulation sarudzo yekugadzira iyo testbench, uye sarudza iyo Synthesis sarudzo yekugadzira iyo hardware ex.ample design.
   • Cherechedza: Iwe unofanirwa kusarudza imwechete yeSimulation kana Synthesis sarudzo dzinogadzira iyo Example Dhizaini Files.
9. Kune Yakagadzirwa HDL Format, sarudza Verilog kana VHDL.
10. YeTarget Development Kit sarudza yakakodzera sarudzo.
    • Cherechedza: Iyo Intel Agilex 7 F-Series Transceiver SoC Development Kit sarudzo inongowanikwa kana chirongwa chako chatsanangura Intel Agilex 7 zita remudziyo kutanga ne AGFA012 kana AGFA014. Paunosarudza iyo Yekuvandudza Kit sarudzo, iyo pini migove inoiswa zvinoenderana neIntel Agilex 7 Development Kit mudziyo chikamu nhamba AGFB014R24A2E2V uye inogona kusiyana kubva kune chako chakasarudzwa. Kana uchida kuyedza dhizaini pahardware pane imwe PCB, sarudza iyo Hapana uye ita mapini akakodzera mu .qsf file.
11. Dzvanya Gadzira Example Design. Sarudza Example Dhizaini Dhairekitori hwindo rinoonekwa.
12. Kana iwe uchida kugadzirisa iyo dhizaini example dhairekitori nzira kana zita kubva kune zvimiro zvakaratidzwa (uflex_ilk_0_example_design), tsvaga kunzira nyowani uye nyora iyo nyowani dhizaini example directory zita.
13. Dzvanya OK.

Related Information

• Intel Agilex 7 F-Series Transceiver-SoC Development Kit User Guide
• E-tile Transceiver PHY User Guide

Kutevedzera Dhizaini Example Testbench
Tarisa kune Interlaken (2nd Generation) Hardware Dhizaini Example High Level Block yeE-tile NRZ Mode Kusiyana uye Interlaken (2nd Generation) Hardware Design Ex.ample High Level Block yeE-tile PAM4 Mode Variations block diagrams ye simulation testbench.
Mufananidzo 8. Maitiro

Tevera matanho aya kutevedzera testbench:

1. Pakuraira kwekuraira, shandura kune testbench simulation dhairekitori. Dhairekitori iriample_installation_dir>/example_design/ testbench yeIntel Agilex 7 zvishandiso.
2. Mhanya iyo simulation script yeiyo inotsigirwa simulator yesarudzo yako. Iyo script inounganidza uye inomhanyisa testbench mune simulator. Chinyorwa chako chinofanira kutarisa kuti SOP neEOP inoverengera machisi mushure mekunge simulation yapera. Tarisa kune tafura Matanho ekumhanya Simulation.

Tafura 4. Matanho ekumhanya Simulation

Simulator	Mirayiridzo
ModelSim SE kana QuestaSim	Mumutsara wekuraira, nyora -do vlog_pro.do Kana ukasarudza kutevedzera pasina kuunza ModelSim GUI, nyora vsim -c -do vlog_pro.do
VCS	Mumutsara wekuraira, nyora sh vcstest.sh
Xcelium	Mumutsara wekuraira, nyora sh xcelium.sh

Ongorora zvabuda. Yekutevedzera yakabudirira inotumira uye inogamuchira mapaketi, uye inoratidza "Test PASSED".
Testbench yekugadzira example anopedza mabasa anotevera:

• Inosimbisa iyo Interlaken (2nd Generation) Intel FPGA IP.
• Inodhinda chimiro chePHY.
• Inotarisa metaframe synchronization (SYNC_LOCK) uye izwi (block) miganhu (WORD_LOCK).
• Inomirira kuti mikoto yega yega ivharwe uye ienderane.
• Inotanga kutumira mapaketi.
• Inotarisa packet statistics:
  • CRC24 kukanganisa
  • SOPs
  • EOPs

Inotevera sample kuburitsa inoratidza yakabudirira simulation bvunzo inomhanya muInterlaken modhi:

Cherechedza: Iyo Interlaken dhizaini example simulation testbench inotumira 100 mapaketi uye inogamuchira 100 mapaketi. Inotevera sample kuburitsa inoratidza yakabudirira simulation bvunzo inomhanya muInterlaken Tarisa-padivi modhi:

Cherechedza: Huwandu hwemapaketi (SOPs uye EOPs) inosiyana pamutsara muInterlaken Lookaside dhizaini ex.ample simulation sample output.
Related Information
Hardware Dhizaini Example Zvikamu zviri papeji 6

Kunyora uye Kugadzirisa Dhizaini Example mu Hardware
Mufananidzo 9. Maitiro

Kuunganidza uye kumhanyisa bvunzo yekuratidzira pane Hardware example design, tevera matanho aya:

1. Ita shuwa kuti hardware example design generation yapera.
2. MuIntel Quartus Prime Pro Edition software, vhura iyo Intel Quartus Prime purojekitiample_installation_dir>/example_design/quartus/ example_design.qpf>.
3. Pane iyo Processing menyu, tinya Start Compilation.
4. Mushure mekubudirira kuunganidza, a .sof file inowanikwa mudhairekitori rako rawakataura. Tevedza matanho aya kuronga hardware exampdhizaini paIntel Agilex 7 mudziyo:
   • a. Batanidza Intel Agilex 7 F-Series Transceiver-SoC Development Kit kune komputa inotambira.
   • b. Tangisa Clock Control application, inova chikamu cheti yekuvandudza, uye isa ma frequency matsva eiyo dhizaini ex.ample. Pazasi pane frequency kuseta muClock Control application:
   • • Si5338 (U37), CLK1- 100 MHz
   • • Si5338 (U36), CLK2- 153.6 MHz
   • • Si549 (Y2), OUT- Set kune kukosha kwe pll_ref_clk(1) maererano nezvinodiwa zvekugadzira.
   • c. PaZvishandiso menyu, tinya Programmer.
   • d. MuPurogiramu, tinya Hardware Setup.
   • e. Sarudza chigadzirwa chepurogiramu.
   • f. Sarudza uye wedzera iyo Intel Agilex 7 F-Series Transceiver-SoC Development Kit iyo yako Intel Quartus Prime chikamu inogona kubatana.
   • g. Ita shuwa kuti Mode yakaiswa kuna JTAG.
   • h. Sarudza iyo Intel Agilex 7 mudziyo uye tinya Wedzera Chishandiso. Iyo Programmer inoratidza dhizaini dhizaini yekubatana pakati pemidziyo iri pabhodhi rako.
   • i. Mumutsara ne .sof yako, tarisa bhokisi re .sof.
   • j. Tarisa bhokisi riri muPurogiramu/Gadzirisa column.
   • k. Click Start.

Related Information

• Kuronga Intel FPGA Zvishandiso pane peji 0
• Kuongorora uye Kugadzirisa Dhizaini neSystem Console
• Intel Agilex 7 F-Series Transceiver-SoC Development Kit User Guide

Kuedza iyo Hardware Dhizaini Example
Mushure mekunyora iyo Interlaken (2nd Generation) Intel FPGA IP musimboti dhizaini example uye gadzirisa mudziyo wako, unogona kushandisa iyo System Console kuronga iyo IP musimboti uye yakamisikidzwa Native PHY IP epakati marejista.

Tevedza nhanho idzi kuunza iyo System Console uye kuyedza iyo hardware dhizaini example:

1. MuIntel Quartus Prime Pro Edition software, pane Zvishandiso menyu, tinya System Debugging Zvishandiso ➤ System Console.
2. Shandura kuneample_installation_dir>example_design/hwtest dhairekitori.
3. Kuti uvhure chinongedzo kuJTAG tenzi, nyora murairo unotevera: source sysconsole_testbench.tcl
4. Iwe unogona kubatidza yemukati serial loopback modhi neinotevera dhizaini exampini ndinoraira:
   • a. stat: Inodhinda general status info.
   • b. sys_reset: Inogadzirisa zvakare sisitimu.
   • c. loop_on: Inobatidza yemukati serial loopback.
   • d. run_example_design: Inomhanyisa dhizaini example.
   • Cherechedza: Iwe unofanirwa kumhanya loop_on command usati wamhanya_example_design command. The run_example_design inoshandisa mirairo inotevera munhevedzano: sys_reset-> stat-> gen_on-> stat-> gen_off.
   • Cherechedza: Paunosarudza iyo Gonesa kugadzirisa kurodha yakapfava IP sarudzo, iyo run_example_design command inoita yekutanga kugadzirisa calibration paRX side nekumhanyisa run_load_PMA_configuration command.
5. Unogona kudzima yemukati serial loopback modhi neinotevera dhizaini example command:
   • a. loop_off: Inodzima yemukati serial loopback.
6. Iwe unogona kuronga iyo IP musimboti neinotevera yekuwedzera dhizaini exampini ndinoraira:
   • a. gen_on: Inogonesa jenareta yepakiti.
   • b. gen_off: Inodzima packet jenareta.
   • c. run_test_loop: Inomhanyisa bvunzo ye nguva dzeE-tile NRZ uye PAM4 mutsauko.
   • d. clear_err: Inodzima zvese zvinonamira kukanganisa mabits.
   • e. set_test_mode : Inomisa bvunzo kuti imhanye mune yakatarwa modhi.
   • f. get_test_mode: Inodhinda iyo yazvino bvunzo modhi.
   • g. set_burst_size : Inoisa kuputika saizi mumabhaiti.
   • h. get_burst_size: Inodhinda kuputika saizi ruzivo.

Muedzo wakabudirira unodhinda HW_TEST:PASS meseji. Pazasi pane nzira dzekupasa dzebvunzo kumhanya:

• Hapana zvikanganiso zve CRC32, CRC24, uye cheki.
• Akatumirwa maSOP uye EOPs anofanirwa kuenderana neakagamuchirwa.

Inotevera sample kuburitsa inoratidza yakabudirira bvunzo inomhanya muInterlaken modhi:

Muedzo wakabudirira unodhinda HW_TEST : PASS meseji. Pazasi pane nzira dzekupasa dzebvunzo kumhanya:

• Hapana zvikanganiso zve CRC32, CRC24, uye cheki.
• Akatumirwa maSOP uye EOPs anofanirwa kuenderana neakagamuchirwa.

Inotevera sample kuburitsa inoratidza yakabudirira bvunzo inomhanya muInterlaken Lookaside mode:

Design Example Description

Iyo yakagadzirwa example inoratidza mashandiro eiyo Interlaken IP musimboti.

Related Information
Interlaken (2nd Generation) FPGA IP User Guide

Design Example Behavior
Kuti uedze dhizaini muhardware, nyora iyo inotevera mirairo muSystem Console:

1. Kunobva setup file:
   • % tsimeample>uflex_ilk_0_example_design/example_design/hwtest/ sysconsole_testbench.tcl
2. Isai bvunzo:
   • % run_example_design
3. Iyo Interlaken (2nd Generation) hardware dhizaini example anopedzisa nhanho dzinotevera:
   • a. Inogadzirisa zvakare iyo Interlaken (2nd Generation) IP.
   • b. Inogadzirisa iyo Interlaken (2nd Generation) IP mune yemukati loopback modhi.
   • c. Inotumira rwizi rweInterlaken mapaketi ane akafanotsanangurwa dhata mubhadharo kune TX mushandisi wekufambisa data weiyo IP musimboti.
   • d. Inotarisa mapaketi akagamuchirwa uye inoshuma mamiriro. Iyo packet cheki inosanganisirwa mune hardware dhizaini example inopa anotevera ekutanga pakiti yekutarisa kugona:
     • Inotarisa kuti kutevedzana kwepaketi yekutumira kwakarurama.
     • Inotarisa kuti data rakagamuchirwa rinoenderana nemitengo inotarisirwa nekuona kutanga kwepakiti (SOP) uye kupera kwepakiti (EOP) kuverenga kunoenderana apo data iri kufambiswa nekugamuchirwa.

Interface Signals
Tafura 5. Design Example Interface Signals

Port Name	Direction	Upamhi (Bits)	Tsanangudzo
mgmt_clk	Input	1	Kuiswa kwewachi yehurongwa. Wachi frequency inofanira kuva 100 MHz.
pll_ref_clk / pll_ref_clk[1:0](2)	Input	1/2	Transceiver reference wachi. Inotyaira iyo RX CDR PLL.
akaenderera…

Port Name	Direction	Upamhi (Bits)	Tsanangudzo
			pll_ref_clk[1] inongowanikwa kana wagonesa Chengetedza zvisina kushandiswa Cherechedza: transceiver nzira dzePAM4 parameter muE-tile PAM4 mode IP kusiyana.
rx_pin	Input	Nhamba yenzira	Receiver SERDES data pin.
tx_pin	Output	Nhamba yenzira	Tumira SERDES data pin.
rx_pin_n	Input	Nhamba yenzira	Receiver SERDES data pin. Ichi chiratidzo chinongowanikwa muE-tile PAM4 modhi mudziyo musiyano.
tx_pin_n	Output	Nhamba yenzira	Tumira SERDES data pin. Ichi chiratidzo chinongowanikwa muE-tile PAM4 modhi mudziyo musiyano.
mac_clk_pll_ref	Input	1	Iyi siginecha inofanirwa kufambiswa nePLL uye inofanirwa kushandisa imwechete wachi sosi inotyaira iyo pll_ref_clk. Ichi chiratidzo chinongowanikwa muE-tile PAM4 modhi mudziyo musiyano.
usr_pb_reset_n	Input	1	Reset System.

Related Information
Interface Signals

Register Mepu
Cherechedza: • Dhizaini Exampkero yerejista inotanga na 0x20** nepo Interlaken IP kero yerejisita inotanga na0x10**.

• Kodhi yekupinda: RO—Kuverenga Chete, uye RW—Kuverenga/Kunyora.
• System console inoverenga dhizaini example inonyoresa uye inoshuma mamiriro ebvunzo pachiratidziri.

Tafura 6. Design Exampuye Kunyoresa Mepu yeInterlaken Dhizaini Example

Offset	Zita	Access	Tsanangudzo
8'h00	Reserved
8'h01	Reserved
8'h02	System PLL reset	RO	Kutevera mabits kunoratidza system PLL reset chikumbiro uye kugonesa kukosha: • Bit [0] – sys_pll_rst_req • Bit [1] – sys_pll_rst_en
8'h03	RX nzira yakarongeka	RO	Inoratidza kurongeka kweRX.
8'h04	WORD rakakiyiwa	RO	[NUM_LANES–1:0] – Kuzivikanwa kwemiganhu yeIzwi (block).
akaenderera…

Kana iwe uchigonesa Chengetedza isina kushandiswa transceiver chiteshi chePAM4 paramende, imwe yekuwedzera referensi wachi inowedzerwa kuchengetedza isina kushandiswa PAM4 muranda chiteshi.

Offset	Zita	Access	Tsanangudzo
8'h05	Kubatanidza kwakavharwa	RO	[NUM_LANES–1:0] – Kuwiriranisa kweMetaframe.
8'h06 – 8'h09	CRC32 kukanganisa kuverenga	RO	Inoratidza CRC32 kukanganisa kuverenga.
8'h0A	CRC24 kukanganisa kuverenga	RO	Inoratidza CRC24 kukanganisa kuverenga.
8'h0B	Kufashukira/Kuyerera kwechiratidzo	RO	Mabhii anotevera anoratidza: • Bit [3] - TX underflow signal • Bit [2] - TX chivharo chekufashukira • Bit [1] - RX kufashukira chiratidzo
8'h0C	SOP kuverenga	RO	Inoratidza nhamba yeSOP.
8'h0D	EOP kuverenga	RO	Inoratidza nhamba yeEOP
8'h0E	Kuverengera kukanganisa	RO	Inoratidza nhamba yezvikanganiso zvinotevera: • Kurasika kwenzira • Shoko rekutonga zvisiri pamutemo • Patani yekuumba isiri pamutemo • SOP kana EOP chiratidzo chisipo
8'h0F	send_data_mm_clk	RW	Nyora 1 kubhiti [0] kugonesa chiratidzo chejenareta.
8'h10	Checker kukanganisa		Inoratidza kukanganisa kwecheki. (SOP data kukanganisa, Channel nhamba kukanganisa, uye PLD data kukanganisa)
8'h11	System PLL kukiya	RO	Bit [0] inoratidza PLL yekuvhara chiratidzo.
8'h14	TX SOP kuverenga	RO	Inoratidza nhamba yeSOP inogadzirwa nejenareta yepakiti.
8'h15	TX EOP kuverenga	RO	Inoratidza nhamba yeEOP inogadzirwa nejenareta yepakiti.
8'h16	Continuous packet	RW	Nyora 1 kusvika kubhiti [0] kugonesa iyo inoenderera packet.
8'h39	ECC kukanganisa kuverenga	RO	Inoratidza nhamba yeECC zvikanganiso.
8'h40	ECC yakagadzirisa kukanganisa kuverenga	RO	Inoratidza nhamba yakagadziriswa ECC zvikanganiso.

Design Exampuye Nyoresa Mepu yeInterlaken Tarisa-padivi Dhizaini Example
Shandisa iyi mepu yerejista paunogadzira dhizaini example ine Gonesa Interlaken Tarisa-padivi modhi paramende yakabatidzwa.

Offset	Zita	Access	Tsanangudzo
8'h00	Reserved
8'h01	Counter reset	RO	Nyora 1 kubhiti [0] kujekesa TX uye RX counter yakaenzana bit.
8'h02	System PLL reset	RO	Kutevera mabits kunoratidza system PLL reset chikumbiro uye kugonesa kukosha: • Bit [0] – sys_pll_rst_req • Bit [1] – sys_pll_rst_en
8'h03	RX nzira yakarongeka	RO	Inoratidza kurongeka kweRX.
8'h04	WORD rakakiyiwa	RO	[NUM_LANES–1:0] – Kuzivikanwa kwemiganhu yeIzwi (block).
8'h05	Kubatanidza kwakavharwa	RO	[NUM_LANES–1:0] – Kuwiriranisa kweMetaframe.
8'h06 – 8'h09	CRC32 kukanganisa kuverenga	RO	Inoratidza CRC32 kukanganisa kuverenga.
8'h0A	CRC24 kukanganisa kuverenga	RO	Inoratidza CRC24 kukanganisa kuverenga.
akaenderera…

Offset	Zita	Access	Tsanangudzo
8'h0B	Reserved
8'h0C	SOP kuverenga	RO	Inoratidza nhamba yeSOP.
8'h0D	EOP kuverenga	RO	Inoratidza nhamba yeEOP
8'h0E	Kuverengera kukanganisa	RO	Inoratidza nhamba yezvikanganiso zvinotevera: • Kurasika kwenzira • Shoko rekutonga zvisiri pamutemo • Patani yekuumba isiri pamutemo • SOP kana EOP chiratidzo chisipo
8'h0F	send_data_mm_clk	RW	Nyora 1 kubhiti [0] kugonesa chiratidzo chejenareta.
8'h10	Checker kukanganisa	RO	Inoratidza kukanganisa kwecheki. (SOP data kukanganisa, Channel nhamba kukanganisa, uye PLD data kukanganisa)
8'h11	System PLL kukiya	RO	Bit [0] inoratidza PLL yekuvhara chiratidzo.
8'h13	Latency count	RO	Inoratidza nhamba ye latency.
8'h14	TX SOP kuverenga	RO	Inoratidza nhamba yeSOP inogadzirwa nejenareta yepakiti.
8'h15	TX EOP kuverenga	RO	Inoratidza nhamba yeEOP inogadzirwa nejenareta yepakiti.
8'h16	Continuous packet	RO	Nyora 1 kusvika kubhiti [0] kugonesa iyo inoenderera packet.
8'h17	TX uye RX counter yakaenzana	RW	Inoratidza TX uye RX counter zvakaenzana.
8'h23	Vhura latency	WO	Nyora 1 kusvika kubhiti [0] kugonesa kuyerwa kwekunonoka.
8'h24	Latency yakagadzirira	RO	Inoratidza latency kuyerwa kwagadzirira.

Interlaken (2nd Generation) Intel Agilex 7 FPGA IP Dhizaini Example User Guide Archives

• Kune ichangoburwa uye yapfuura vhezheni yegwaro remushandisi, tarisa iyo Interlaken (2nd
• Chizvarwa) Intel Agilex 7 FPGA IP Dhizaini Example User Guide HTML shanduro. Sarudza shanduro wobva wadzvanya Dhawunirodha. Kana IP kana software vhezheni isina kunyorwa, gwaro remushandisi rekare IP kana software shanduro inoshanda.
• IP shanduro dzakafanana neIntel Quartus Prime Design Suite software shanduro kusvika v19.1. Kubva kuIntel Quartus Prime Design Suite software vhezheni 19.2 kana gare gare, IP cores ine itsva IP shanduro chirongwa.

Gwaro Revision Nhoroondo yeInterlaken (2nd Generation) Intel Agilex 7 FPGA IP Dhizaini Ex.ample User Guide

Document Version	Intel Quartus Prime Version	IP Version	Kuchinja
2023.06.26	23.2	21.1.1	• Yakawedzerwa VHDL tsigiro ye synthesis uye simulation modhi. • Yakagadziridzwa zita remhuri yechigadzirwa ku "Intel Agilex 7".
2022.08.03	21.3	20.0.1	Yakagadzirisa mudziyo OPN weIntel Agilex F-Series Transceiver-SoC Development Kit.
2021.10.04	21.3	20.0.1	• Yakawedzera rutsigiro rweQuestaSim simulator. • Yakabviswa tsigiro yeNCSim simulator.
2021.02.24	20.4	20.0.1	• Ruzivo rwakawedzerwa pamusoro pekuchengetedza chiteshi chetransceiver chisina kushandiswa chePAM4 muchikamu: Hardware Dhizaini Example Components. • Yakawedzera pll_ref_clk[1] tsananguro yechiratidzo muchikamu: Interface Signals.
2020.12.14	20.4	20.0.0	• Yakavandudzwa pample hardware bvunzo yakabuda yeInterlaken modhi uye Interlaken Tarisa-padivi modhi muchikamu Kuedza iyo Hardware Dhizaini Example. • Mepu yekunyoresa yakagadziridzwa yeInterlaken Tarisa-padivi dhizaini example muchikamu Register Mepu. • Yakawedzera nzira yekupasa yeyakabudirira hardware test inomhanya muchikamu Kuedza iyo Hardware Dhizaini Example.
2020.10.16	20.2	19.3.0	Yakagadziriswa rairo yekumhanyisa yekutanga kugadzirisa calibration paRX side mukati Kuedza iyo Hardware Dhizaini Example chikamu.
2020.06.22	20.2	19.3.0	• Magadzirirwo example inowanikwa yeInterlaken Tarisa- parutivi modhi. • Hardware kuongororwa kweiyo dhizaini example inowanikwa kune Intel Agilex mudziyo musiyano. • Yakawedzerwa Mufananidzo: Yepamusoro-nhanho Block Dhiagiramu yeInterlaken (2nd Generation) Dhizaini Example. • Zvikamu zvinovandudzwa: —   Hardware uye Software Zvinodiwa —   Directory Structure • Yakagadziridza nhamba dzinotevera kuti dzisanganisire Interlaken Look-aside ine chekuita nekuvandudzwa: —   Mufananidzo: Interlaken (2nd Generation) Hardware Dhizaini Example High Level Block Digiramu yeE- tile NRZ Mode Kusiyana —   Mufananidzo: Interlaken (2nd Generation) Hardware Dhizaini Example High Level Block Digiramu yeE- tile PAM4 Mode Kusiyana • Updated Mufananidzo: IP Parameter Editor.
akaenderera…

Document Version	Intel Quartus Prime Version	IP Version	Kuchinja
			• Yakawedzerwa ruzivo pamusoro pema frequency marongero muchirongwa chekudzora wachi muchikamu Kunyora uye Kugadzirisa Dhizaini Example mu Hardware. • Yakawedzera bvunzo yekubuda kweiyo Interlaken Tarisa- parutivi muzvikamu zvinotevera: —   Kutevedzera Dhizaini Example Testbench —   Kuedza iyo Hardware Dhizaini Example • Yakawedzerwa inotevera masaini matsva mukati Interface Signals chikamu: — mgmt_clk — rx_pin_n — tx_pin_n — mac_clk_pll_ref • Yakawedzera mepu yerejista yeInterlaken Tarisa-padivi dhizaini example mu chikamu: Nyora Mepu.
2019.09.30	19.3	19.2.1	Yakabviswa clk100. Iyo mgmt_clk inoshanda sereferensi wachi kuIO PLL mune zvinotevera: •    Mufananidzo: Interlaken (2nd Generation) Hardware Dhizaini Example High Level Block Digiramu yeE-tile NRZ Mode Kusiyana. •    Mufananidzo: Interlaken (2nd Generation) Hardware Dhizaini Example High Level Block Digiramu yeE-tile PAM4 Mode Kusiyana.
2019.07.01	19.2	19.2	Kusunungurwa kwekutanga.

Interlaken (2nd Generation) Intel Agilex® 7 FPGA IP Dhizaini Example User Guide

Zvinyorwa / Zvishandiso

Intel Interlaken 2nd Generation Agilex 7 FPGA IP Dhizaini Example [pdf] Bhuku reMushandisi Interlaken 2nd Generation Agilex 7 FPGA IP Dhizaini Example, Interlaken, 2nd Generation Agilex 7 FPGA IP Dhizaini Example, FPGA IP Dhizaini Example, IP Dhizaini Example, Dhizaini Example

References

• User Manual