Intel Interlaken 2nd Generation Agilex 7 FPGA IP Design Example

Ozi ngwaahịa

Interlaken (2nd Generation) FPGA IP isi bụ akụkụ nke Intel Agilex 7 FPGA. Ọ na-enye simulation testbench na ngwaike imewe example nke na-akwado mkpokọta na nyocha ngwaike. Imewe example dịkwa maka njirimara Interlaken Look-side. Isi IP na-akwado ọnọdụ NRZ na PAM4 maka ngwaọrụ E-tile ma na-emepụta examples maka nchikota niile akwadoro nke ọnụọgụ ụzọ na ọnụego data.

Achọrọ ngwaike na ngwanrọ
Interlaken (2nd Generation) IP isi imewe example chọrọ Intel Agilex 7 F-Series Transceiver-SoC Development Kit. Biko rụtụ aka na ntuziaka onye ọrụ nke ngwa mmepe maka ozi ndị ọzọ.

Ọdịdị ndekọ
Interlaken (2nd Generation) emepụtara example Design gụnyere akwụkwọ ndekọ aha ndị a:

• example_design: Nwere isi files maka imewe example.
• ilk_uflex: Nwere filemetụtara nhọrọ ọnọdụ Interlaken Look-side.
• ila_uflex: Nwere files metụtara nhọrọ ọnọdụ Interlaken Look-side (emepụtara naanị mgbe ahọpụtara).

Ntuziaka ojiji ngwaahịa

Iji jiri Interlaken (2nd Generation) FPGA IP core design example, soro usoro ndị a:

1. Gbaa mbọ hụ na ị nwere Intel Agilex 7 F-Series Transceiver-SoC Development Kit.
2. Chịkọta imewe exampiji simulator.
3. Mee simulation arụ ọrụ iji nyochaa imewe ahụ.
4. Mepụta imewe example iji parameter editọ.
5. Chịkọta imewe exampna-eji Quartus Prime.
6. Mee nnwale ngwaike iji kwado imewe ahụ.

Mara: Nhọrọ ọnọdụ-n'akụkụ Interlaken dị maka nhọrọ na nchịkọta nhọrọ paramita IP. Ọ bụrụ na ahọpụtara, gbakwụnye fileA ga-emepụta s na ndekọ "ila_uflex".

Ntuziaka mmalite ngwa ngwa

• Interlaken (2nd Generation) FPGA IP core na-enye testbench simulation na ihe nrụpụta ngwaike ex.ample nke na-akwado mkpokọta na nyocha ngwaike.
• Mgbe ị na-emepụta imewe example, paramita nchịkọta akụkọ na-akpaghị aka na-emepụta filedị mkpa iji megharịa, chịkọta, na nwalee imewe na ngwaike.
• Imewe example dịkwa maka atụmatụ Interlaken Look-side.
• The testbench na imewe example na-akwado ọnọdụ NRZ na PAM4 maka ngwaọrụ E-tile.
• Interlaken (2nd Generation) FPGA IP isi na-ewepụta imewe examples maka nchikota niile akwadoro nke ọnụọgụ ụzọ na ọnụego data.

Onyonyo 1. Nzọụkwụ mmepe maka imewe Example

Interlaken (2nd Generation) IP isi imewe example na-akwado atụmatụ ndị a:

• Ụdị TX dị n'ime ruo RX serial loopback mode
• Na-ewepụta ngwugwu nha nha na-akpaghị aka
• Ikike ịlele ngwugwu bụ isi
• Ikike iji Sistemu Console iji tọgharịa imewe maka ebumnuche nnwale ọzọ
• Mgbanwe PMA

Ụlọ ọrụ Intel. Ikike niile echekwabara. Intel, akara Intel, na akara Intel ndị ọzọ bụ ụghalaahịa nke Intel Corporation ma ọ bụ ndị enyemaka ya. Intel nyere ikike ịrụ ọrụ nke FPGA na ngwaahịa semiconductor na nkọwapụta ugbu a dịka akwụkwọ ikike ọkọlọtọ Intel siri dị, mana nwere ikike ịme mgbanwe na ngwaahịa na ọrụ ọ bụla n'oge ọ bụla na-enweghị ọkwa. Intel anaghị ewere ọrụ ọ bụla ma ọ bụ ụgwọ sitere na ngwa ma ọ bụ iji ozi ọ bụla, ngwaahịa ma ọ bụ ọrụ akọwara n'ime ebe a belụsọ dị ka Intel kwetara na ederede. A dụrụ ndị ahịa Intel ọdụ ka ha nweta ụdị nkọwa ngwaọrụ kachasị ọhụrụ tupu ha adabere na ozi ọ bụla ebipụtara yana tupu ịnye iwu maka ngwaahịa ma ọ bụ ọrụ. * Enwere ike ịzọrọ aha na akara ndị ọzọ dị ka ihe onwunwe nke ndị ọzọ.

Onyonyo 2. Eserese ngọngọ dị elu maka Interlaken (ọgbọ nke abụọ) imewe Example

Ozi metụtara

• Interlaken (ọgbọ nke abụọ) Ntuziaka onye ọrụ IP FPGA
• Interlaken (ọgbọ nke abụọ) Intel FPGA IP ndetu mwepụta

Akụrụngwa na ngwanrọ

Achọrọ ngwaike na ngwanrọ
Iji nwalee exampiji chepụta, jiri ngwaike na ngwanrọ ndị a:

• Intel® Quartus® Prime Pro Edition software
• Sistemụ njikwa
• Ndị simulator akwadoro:
  • Siemens* EDA ModelSim* SE ma ọ bụ QuestaSim*
  • Synopsys* VCS*
  • Cadence* Xcelium*
• Intel Agilex® 7 F-Series Transceiver-SoC Development Kit (AGFB014R24A2E2V)

Ozi metụtara
Intel Agilex 7 F-Series Transceiver-SoC Development Kit Guide User
Ọdịdị ndekọ
Interlaken (2nd Generation) IP isi imewe example file akwụkwọ ndekọ aha nwere ihe ndị a emepụtara files maka imewe example.

Onyonyo 3. Nhazi ndekọ aha nke emepụtara Interlaken (ọgbọ nke abụọ) Ọpụample Design

Nhazi ngwaike, ịme anwansị, na nnwale files dị naample_installation_dir>/uflex_ilk_0_example_design.
Tebụl 1. Interlaken (ọgbọ nke abụọ) IP Core Hardware Design Example File Nkọwa Ndị a files nọ naample_installation_dir>/uflex_ilk_0_example_design/ example_design/quartus ndekọ.

File Aha	Nkọwa
example_design.qpf	Intel Quartus Prime oru ngo file.
example_design.qsf	Ntọala ọrụ Intel Quartus Prime file
example_design.sdc jtag_timing_template.sdc	Synopsys imewe mmachi file. Ị nwere ike idetuo ma gbanwee maka imewe nke gị.
sysconsole_testbench.tcl	Isi file maka ịnweta Sistemu Console

Tebụl 2. Interlaken (ọgbọ nke abụọ) IP Core Testbench File Nkọwa
Nke a file dị n'imeample_installation_dir>/uflex_ilk_0_example_design/ example_design/rtl ndekọ.

File Aha	Nkọwa
top_tb.sv	testbench dị elu file.

Tebụl 3. Interlaken (ọgbọ nke abụọ) IP Core Testbench Scripts
Ndị a files nọ naample_installation_dir>/uflex_ilk_0_example_design/ example_design/ testbench ndekọ.

File Aha	Nkọwa
vcstest.sh	Edemede VCS iji mee testbench.
vlog_pro.do	Edemede ModelSim SE ma ọ bụ QuestaSim iji mee testbench.
xcelium.sh	Edemede Xcelium iji mee testbench.

Nhazi ngwaike Exampna akụrụngwa

• The example imewe ejikọta usoro na PLL ntụaka clocks na chọrọ imewe components. The example imewe configures IP isi na esịtidem loopback mode na site na ngwugwu na IP isi TX onye ọrụ data nnyefe interface. Isi IP na-eziga ngwugwu ndị a na ụzọ loopback dị n'ime site na transceiver.
• Mgbe IP isi nnata natachara ngwugwu na ụzọ loopback, ọ na-eme ihe
• Ngwunye Interlaken ma na-ebufe ha na ntinye data onye ọrụ RX. The example imewe elele na ngwugwu natara na bufere egwuregwu.
• Akụrụngwa example imewe na-agụnye mpụga PLLs. Ị nwere ike nyochaa ederede doro anya files na view sampkoodu nke na-arụ otu ụzọ enwere ike iji jikọọ PLLs mpụga na Interlaken (2nd Generation) FPGA IP.
• Interlaken (2nd Generation) ngwaike imewe example gụnyere ihe ndị a:
  • Interlaken (ọgbọ nke abụọ) FPGA IP
  • Ngwunye Generator na ihe nlele ngwugwu
  • JTAG njikwa na-ekwurịta okwu na System Console. Ị na-ekwurịta okwu na mgbagha onye ahịa site na Sistemu Console.

Onyonyo 4. Interlaken (ọgbọ nke abụọ) Ihe nrụpụta ngwaike Example Eserese ngọngọ High Ọkwa maka E-tile NRZ ụdịdị iche iche

Interlaken (2nd Generation) ngwaike imewe exampnke ahụ lekwasịrị anya ụdịdị ụdị E-tile PAM4 chọrọ mgbakwunye mac_clkin elekere nke IO PLL na-ebute. PLL a ga-ejirịrị otu elekere ntụaka na-ebugharị pll_ref_clk.
Onyonyo 5. Interlaken (ọgbọ nke abụọ) Ihe nrụpụta ngwaike Example Eserese Block High Ọkwa maka E-tile PAM4 ụdịdị dị iche iche

Maka mgbanwe ụdị E-tile PAM4, mgbe ị na-eme ka ọwa transceiver Chekwaa ejighi ya maka paramita PAM4, a na-agbakwunye ọdụ ụgbọ mmiri elekere (pll_ref_clk [1]). A ga-ebugharị ọdụ ụgbọ mmiri a n'otu oge ka akọwara ya na nchịkọta nhọrọ paramita IP (Ugboro elekere maka ọwa echekwara). Chekwa ọwa transceiver ejighi ya maka PAM4 bụ nhọrọ. A na-ahụ pin na ihe mgbochi ndị metụtara ya na elekere a na QSF mgbe ịhọrọ Intel Stratix® 10 ma ọ bụ ngwa mmepe Intel Agilex 7 maka ọgbọ imewe.
Mara: Maka imewe exampna simulation, testbench na-akọwakarị otu ugboro maka pll_ref_clk[0] na pll_ref_clk[1].
Ozi metụtara
Intel Agilex 7 F-Series Transceiver-SoC Development Kit Guide User

Ịmepụta Nhazi
Onyonyo 6. Usoro

Soro usoro ndị a ka ịmepụta ngwaike example design na testbench:

1. Na ngwanrọ Intel Quartus Prime Pro Edition, pịa File ➤ Ọkachamara Project ọhụrụ iji mepụta ọrụ Intel Quartus Prime ọhụrụ, ma ọ bụ pịa File ➤ Mepee Project ka imepe ọrụ Intel Quartus Prime dị ugbu a. Ọkachamara na-akpali gị ezipụta ngwaọrụ.
2. Ezipụta ezinụlọ ngwaọrụ Intel Agilex 7 wee họrọ ngwaọrụ maka imewe gị.
3. Na katalọgụ IP, chọta ma pịa Interlaken (2nd Generation) Intel FPGA IP ugboro abụọ. Window IP dị iche iche ga-egosi.
4. Ezipụta aha ọkwa dị elu maka IP omenala gị iche. Onye ndezi paramita na-echekwa ntọala IP dị iche na a file aha ya .ip.
5. Pịa OK. Ihe ndezi paramita na-egosi.
   Onyonyo 7. Exampma chepụta Tab na Interlaken (2nd Generation) Intel FPGA IP Parameter Editor
6. Na taabụ IP, ezipụta paramita maka mgbanwe isi IP gị.
7. Na PMA Adaptation tab, ezipụta usoro mmegharị PMA ma ọ bụrụ na ị na-eme atụmatụ iji mmegharị PMA maka ọdịiche ngwaọrụ E-tile gị. Nzọụkwụ a bụ nhọrọ:
   • Họrọ Kwado mmeghari ibu dị nro nhọrọ IP.
   • Mara: Ị ga-emerịrị ka nhọrọ Kwado Native PHY Debug Master Endpoint (NPDME) na taabụ IP mgbe agbanyere ngbanwe PMA.
   • Họrọ ntọala ngbanwe PMA maka mmegharị PMA Họrọ oke.
   • Pịa Preload PMA Adaptation iji buo paramita mgbanwe nke mbụ na nke na-aga n'ihu.
   • Kọwaa ọnụ ọgụgụ nke nhazi PMA iji kwado mgbe ọtụtụ nhazi PMA na-enyere aka site na iji Ọnụọgụ nhazi nhazi PMA.
   • Họrọ nhazi PMA nke ị ga-ebu ma ọ bụ chekwaa site na iji Họrọ PMA nhazi iji buo ma ọ bụ chekwaa.
   • Pịa Load mmegharị site na nhazi PMA ahọpụtara iji buo ntọala nhazi PMA ahọpụtara.
   • Maka ozi ndị ọzọ gbasara paramita ngbanwe PMA, rụtụ aka na E-tile
     Ntuziaka onye ọrụ Transceiver PHY.
8. Na ExampLe Design tab, họrọ nhọrọ Simulation iji mepụta testbench, wee họrọ nhọrọ Synthesis iji mepụta ngwaike ex.ampimewe.
   • Mara: Ị ga-ahọrọ ma ọ dịkarịa ala otu n'ime nhọrọ Simulation ma ọ bụ Synthesis na-emepụta Example Design Files.
9. Maka usoro HDL emepụtara, họrọ Verilog ma ọ bụ VHDL.
10. Maka ngwa mmepe Target họrọ nhọrọ kwesịrị ekwesị.
    • Mara: Nhọrọ Intel Agilex 7 F-Series Transceiver SoC Development Kit dị naanị mgbe ọrụ gị na-akọwa aha ngwaọrụ Intel Agilex 7 malite na AGFA012 ma ọ bụ AGFA014. Mgbe ịhọrọ nhọrọ ngwa ngwa mmepe, a na-edozi ọrụ ntụtụ dị ka akụkụ ngwaọrụ Intel Agilex 7 Development Kit nọmba AGFB014R24A2E2V ma nwee ike ịdị iche na ngwaọrụ ahọpụtara. Ọ bụrụ na ị bu n'obi ịnwale imewe na ngwaike na PCB dị iche, họrọ Ọ dịghị nhọrọ wee mee pin ọrụ kwesịrị ekwesị na .qsf file.
11. Pịa n'ịwa Example Design. Họrọ Example Imepụta windo ndekọ na-egosi.
12. Ọ bụrụ na ị chọrọ ịgbanwe imewe exampụzọ ndekọ aha ma ọ bụ aha sitere na ndabara egosiri (uflex_ilk_0_example_design), chọgharịa n'ụzọ ọhụrụ wee pịnye ihe ọhụrụ ahụ example ndekọ aha.
13. Pịa OK.

Ozi metụtara

• Intel Agilex 7 F-Series Transceiver-SoC Development Kit Guide User
• Ntuziaka onye ọrụ E-tile Transceiver PHY

Ịmepụta atụmatụ Exampna Testbench
Rụtụ aka na Interlaken (ọgbọ nke abụọ) Nhazi ngwaike Example High Level Block for E-tile NRZ Mode Variance and Interlaken (2nd Generation) Hardware Design Ex.ample High Level Block for E-tile PAM4 Mode Variations igbochi eserese nke simulation testbench.
Onyonyo 8. Usoro

Soro usoro ndị a ka ịmee testbench:

1. Na ngwa ngwa iwu, gbanwee gaa na ndekọ ndekọ simulation testbench. Akwụkwọ ndekọ aha bụample_installation_dir>/ example_design/ testbench maka ngwaọrụ Intel Agilex 7.
2. Gbaa script simulation maka simulator akwadoro nke nhọrọ gị. Edemede a na-achịkọta ma na-agba testbench na simulator. Edemede gị kwesịrị ịlele na ọnụ ọgụgụ SOP na EOP dakọtara mgbe ịmechara simulation. Rụtụ aka na tebụl Nzọụkwụ iji mee Simulation.

Tebụl 4. Nzọụkwụ iji mee Simulation

Simulator	Ntuziaka
ModelSim SE ma ọ bụ QuestaSim	N'ahịrị iwu, pịnye -do vlog_pro.do Ọ bụrụ na-amasị gị ịme simulate na-ebuliteghị ModelSim GUI, pịnye vsim -c -do vlog_pro.do
VCS	N'ahịrị iwu, pịnye sh vcstest.sh
Xcelium	N'ahịrị iwu, pịnye sh xcelium.sh

Nyochaa nsonaazụ ya. Simulation na-aga nke ọma na-eziga ma nata ngwugwu, ma gosipụta “Nnwale gafere”.
The testbench maka imewe example rụchaa ọrụ ndị a:

• Na-ebute Interlaken (ọgbọ nke abụọ) Intel FPGA IP.
• Na-ebipụta ọkwa PHY.
• Na-enyocha mmekọrịta metaframe (SYNC_LOCK) na oke okwu (mgbochi) (WORD_LOCK).
• Na-eche ka akpọchie ma kwekọọ n'ụzọ ọ bụla.
• Na-amalite izisa ngwugwu.
• Nyochaa ọnụ ọgụgụ ngwugwu:
  • Njehie CRC24
  • SOPs
  • EOPs

Ndị na-esonụ sampIhe nrụpụta na-egosi nnwale ịme anwansị na-aga nke ọma na ọnọdụ Interlaken:

Mara: Interlaken imewe example simulation testbench na-eziga ngwugwu 100 wee nata 100 ngwugwu. Ndị na-esonụ sampIhe nrụpụta na-egosi nnwale ịme anwansị na-aga nke ọma na ọnọdụ nlele-akụkụ Interlaken:

Mara: Ọnụọgụ nke ngwugwu (SOPs na EOPs) dịgasị iche n'ụzọ ọ bụla na Interlaken Lookside design ex.ample simulation sample mmepụta.
Ozi metụtara
Nhazi ngwaike ExampIhe ndị dị na ibe 6

Ịchịkọta na Hazie Nhazi Exampna Hardware
Onyonyo 9. Usoro

Iji chịkọta ma mee nnwale ngosi na ngwaike exampka imewe, soro usoro ndị a:

1. Gbaa mbọ hụ na ngwaike example imewe ọgbọ zuru ezu.
2. Na ngwanrọ Intel Quartus Prime Pro Edition, mepee ọrụ Intel Quartus Primeample_installation_dir>/ example_design/quartus/ example_design.qpf>.
3. Na nhazi menu, pịa Malite Nchịkọta.
4. Mgbe nchịkọta nke ọma gasịrị, .sof file dị na ndekọ aha gị akọwapụtara. Soro usoro ndị a ka mmemme ngwaike example imewe na Intel Agilex 7 ngwaọrụ:
   • a. Jikọọ Intel Agilex 7 F-Series Transceiver-SoC Development Kit na kọmputa nnabata.
   • b. Mepee ngwa njikwa elekere, nke bụ akụkụ nke ngwa mmepe, ma tọọ ugboro ọhụrụ maka imewe ex.ample. N'okpuru bụ ntọala ugboro ugboro na ngwa njikwa elekere:
   • • Si5338 (U37), CLK1- 100 MHz
   • • Si5338 (U36), CLK2- 153.6 MHz
   • • Si549 (Y2), OUT- Tọọ uru nke pll_ref_clk(1) maka imewe gị chọrọ.
   • c. Na Ngwaọrụ menu, pịa Programmer.
   • d. Na Programmer, pịa Hardware Mbido.
   • e. Họrọ ngwaọrụ mmemme.
   • f. Họrọ ma tinye Intel Agilex 7 F-Series Transceiver-SoC Development Kit nke oge Intel Quartus Prime gị nwere ike jikọọ.
   • g. Gbaa mbọ hụ na edobere ọnọdụ na JTAG.
   • h. Họrọ ngwaọrụ Intel Agilex 7 wee pịa Tinye Ngwaọrụ. Onye mmemme na-egosiputa eserese mgbochi nke njikọ dị n'etiti ngwaọrụ dị na bọọdụ gị.
   • i. N'ahịrị na .sof gị, lelee igbe maka .sof.
   • j. Lelee igbe dị na kọlụm Mmemme/Hazie.
   • k. Pịa Malite.

Ozi metụtara

• Ịmepụta ngwa Intel FPGA na ibe 0
• Iji Sistemụ Console nyochaa na imegharị atụmatụ
• Intel Agilex 7 F-Series Transceiver-SoC Development Kit Guide User

Nnwale ihe nrụpụta ngwaike Example
Mgbe ị chịkọtara Interlaken (2nd Generation) Intel FPGA IP core design exampma hazie ngwaọrụ gị, ị nwere ike iji Sistemu Console iji hazie IP core yana ndebanye aha Native PHY IP agbakwunyere ya.

Soro usoro ndị a ka ibulite Sistemụ Console wee nwalee nhazi ngwaike exampLe:

1. Na sọftụwia Intel Quartus Prime Pro Edition, na menu Ngwaọrụ, pịa Ngwaọrụ Debugging System ➤ System Console.
2. Gbanwee naample_installation_dir>example_design/ hwest ndekọ.
3. Imepe njikọ na JTAG nna ukwu, pịnye iwu a: isi iyi sysconsole_testbench.tcl
4. Ị nwere ike gbanye mode serial loopback nke dị n'ime site na iji ụdị ihe aample iwu:
   • a. stat: Na-ebipụta ozi ọnọdụ izugbe.
   • b. sys_reset: Tọgharịa sistemụ ahụ.
   • c. loop_on: Na-agbanye n'ime serial loopback.
   • d. ọsọ_example_design: Na-agba ọsọ imewe example.
   • Mara: Ị ga-agba ọsọ loop_on iwu tupu run_exampiwu le_design. The run_example_design na-agba iwu ndị a n'usoro: sys_reset->stat->gen_on->stat->gen_off.
   • Mara: Mgbe ị họrọ Kwado mmezi ibu dị nro nhọrọ IP, run_example_design iwu na-arụ nhazi nhazi mbụ n'akụkụ RX site n'ịgba ọsọ ọsọ_load_PMA_configuration.
5. Ị nwere ike gbanyụọ mode serial loopback nke dị n'ime site na iji ụdị ihe aample iwu:
   • a. loop_off: Gbanyụọ loopback nke ime.
6. Ị nwere ike hazie IP core na ndị a agbakwunyere imewe example iwu:
   • a. gen_on: Na-akwado generator ngwugwu.
   • b. gen_off: Gbanyụọ generator ngwugwu.
   • c. run_test_loop: Na-agba ule maka oge maka E-tile NRZ na PAM4 iche.
   • d. clear_err: Na-ekpochapụ mpe mpe mpe mpe mpe mpe akwa.
   • e. set_test_mode : Na-edozi ule ka ọ na-agba ọsọ na ọnọdụ akọwapụtara.
   • f. get_test_mode: Na-ebipụta ụdị ule dị ugbu a.
   • g. set_burst_size : Tọọ nha gbawara na bytes.
   • h. get_burst_size: Na-ebipụta ozi nha nha.

Nnwale na-aga nke ọma na-ebipụta ozi HW_TEST:PASS. N'okpuru bụ njirisi ngafe maka ọsọ ule:

• Enweghị mperi maka CRC32, CRC24 na checker.
• SOPs na EOP ndị a na-ebufe kwesịrị dakọtara na ndị natara.

Ndị na-esonụ sampmmepụta ihe na-egosi ọsọ ule na-aga nke ọma na ọnọdụ Interlaken:

Nnwale na-aga nke ọma na-ebipụta HW_TEST: ozi PASS. N'okpuru bụ njirisi ngafe maka ọsọ ule:

• Enweghị mperi maka CRC32, CRC24 na checker.
• SOPs na EOP ndị a na-ebufe kwesịrị dakọtara na ndị natara.

Ndị na-esonụ sampmmepụta ihe na-egosi ọsọ ule na-aga nke ọma na ọnọdụ Interlaken Lookside:

Imepụta Example Nkọwa

Imewe example na-egosiputa arụmọrụ nke Interlaken IP isi.

Ozi metụtara
Interlaken (ọgbọ nke abụọ) Ntuziaka onye ọrụ IP FPGA

Imepụta Example Omume
Iji nwalee imewe na ngwaike, pịnye iwu ndị a na Sistemụ Console ::

1. Isi mmalite ntọala file:
   • % isi iyiample>uflex_ilk_0_example_design/example_design/hwtest/ sysconsole_testbench.tcl
2. Gbaa ule:
   • % run_example_design
3. Interlaken (2nd Generation) ngwaike imewe example mezue usoro ndị a:
   • a. Tụgharịa Interlaken (ọgbọ nke abụọ) IP.
   • b. Na-ahazi Interlaken (ọgbọ nke abụọ) IP na ọnọdụ loopback dị n'ime.
   • c. Na-eziga iyi nke ngwugwu Interlaken nwere data akọwapụtagoro n'ime ụgwọ a na-akwụ ya na ntinye data onye ọrụ TX nke isi IP.
   • d. Na-enyocha ngwungwu anatara wee kọọ ọkwa. Ihe nlele ngwugwu gụnyere na ngwaike imewe example na-enye ikike ịlele ngwugwu ndị a:
     • Na-enyocha na usoro ngwugwu ebufere bụ eziokwu.
     • Na-enyocha na data enwetara dabara n'ụkpụrụ ndị a tụrụ anya ya site n'ịhụ na mmalite nke ngwugwu (SOP) na njedebe nke ngwugwu (EOP) na-ejikọta ọnụ mgbe a na-ebufe ma nata data.

Ihe nrịbama ihu
Tebụl 5. Imepụta Exampna akara ngosi interface

Aha Port	Ntuziaka	Obosara (Bits)	Nkọwa
mgmt_clk	Ntinye	1	Ntinye elekere sistemụ. Ugboro elekere ga-abụrịrị 100 MHz.
pl_ref_clk / pll_ref_clk[1:0] (2)	Ntinye	1/2	Elekere ntụgharị ntụgharị. Na-anya RX CDR PLL.
gara n'ihu…

Aha Port	Ntuziaka	Obosara (Bits)	Nkọwa
			pll_ref_clk[1] dị naanị mgbe ị nyeere Chekwaa ejighi ya Mara: ọwa transceiver maka PAM4 oke na E-tile PAM4 ụdịdị IP dị iche iche.
rx_pin	Ntinye	Ọnụọgụ nke ụzọ	PIN nnata SErdES.
tx_pin	Mpụta	Ọnụọgụ nke ụzọ	Nyefee PIN data SErdES.
rx_pin_n	Ntinye	Ọnụọgụ nke ụzọ	PIN nnata SErdES. Mgbama a dị naanị na ụdịdị ngwaọrụ E-tile PAM4.
tx_pin_n	Mpụta	Ọnụọgụ nke ụzọ	Nyefee PIN data SErdES. Mgbama a dị naanị na ụdịdị ngwaọrụ E-tile PAM4.
mac_clk_pll_ref	Ntinye	1	PLL ga-eburịrị mgbaama a ma ga-ejikwa otu isi mmalite elekere na-ebugharị pll_ref_clk. Mgbama a dị naanị na ụdịdị ngwaọrụ E-tile PAM4.
usr_pb_reset_n	Ntinye	1	Ntọgharị usoro.

Ozi metụtara
Ihe nrịbama ihu

Deba aha map
Mara: • Imepụta Example Register Adreesị na-amalite na 0x20** mgbe interlaken IP isi aha adreesị na-amalite na 0x10**.

• Koodu nnweta: RO—Nanị na-agụ, yana RW—Gụọ/Dee.
• Sistemụ njikwa na-agụ imewe example aha na-akọ ule ọnọdụ na ihuenyo.

Tebụl 6. Imepụta Example Deba aha Map maka Interlaken Design Example

Akwụsịghị	Aha	Nweta	Nkọwa
8'h00	Echekwara
8'h01	Echekwara
8'h02	Ntọgharị PLL Sistemu	RO	bits ndị a na-egosi arịrịọ nrụpụta PLL sistemu wee mee ka uru dị: • Bit [0] - sys_pll_rst_req • Bit [1] - sys_pll_rst_en
8'h03	Ahịrị RX kwadoro	RO	Na-egosi nhazi n'ụzọ RX.
8'h04	akpọchiri okwu	RO	[NUM_LANES–1:0] – Okwu (mgbochi) njirimara oke.
gara n'ihu…

Mgbe ị nyere aka Chekwaa ọwa transceiver ejighi ya maka paramita PAM4, a na-agbakwunye ọdụ ụgbọ mmiri elekere iji chekwaa ọwa ohu PAM4 na-ejighị ya.

Akwụsịghị	Aha	Nweta	Nkọwa
8'h05	Mmekọrịta akpọchiri	RO	[NUM_LANES–1:0] – Metaframe gakọrịta.
8 'h06 - 8'h09	Ọnụọgụ njehie CRC32	RO	Na-egosi ọnụọgụ njehie CRC32.
8'h0A	Ọnụọgụ njehie CRC24	RO	Na-egosi ọnụọgụ njehie CRC24.
8'h0B	Ngosipụta oke/Ngosipụta n'okpuru	RO	Ihe ndị na-esonụ na-egosi: • Bit [3] - TX mgbama n'okpuru • Bit [2] - TX mgbama njupụta • Bit [1] - mgbama njupụta RX
8'h0C	Ọnụọgụ SOP	RO	Na-egosi ọnụọgụ SOP.
8h0d	Ọnụọgụ EOP	RO	Na-egosi ọnụ ọgụgụ nke EOP
8'h0E	Ọnụọgụ mperi	RO	Na-egosi ọnụọgụ mperi ndị a: • Ọnwụ nke nhazi okporo ụzọ • Okwu njikwa iwu na-akwadoghị • Usoro nhazi nke ezighi ezi • Ihe ngosi SOP ma ọ bụ EOP efu
8'h0F	zipu_data_mm_clk	RW	Dee 1 na bit [0] iji mee ka mgbama generator nwee ike.
8'h10	Njehie nyocha		Na-egosi mperi nyocha. (Njehie data SOP, njehie nọmba ọwa, yana njehie data PLD)
8'h11	Mkpọchi PLL Sistemu	RO	Bit [0] na-egosi egosi mkpọchi PLL.
8'h14	Ọnụọgụ TX SOP	RO	Na-egosi ọnụọgụ SOP nke ihe na-emepụta ngwugwu mebere.
8'h15	Ọnụ ego TX EOP	RO	Na-egosi ọnụọgụ nke EOP nke ihe na-emepụta ngwugwu mepụtara.
8'h16	ngwugwu na-aga n'ihu	RW	Dee 1 na bit [0] iji mee ka ngwugwu ahụ na-aga n'ihu.
8'h39	Ọnụọgụ njehie ECC	RO	Na-egosi ọnụọgụ mperi ECC.
8'h40	ECC deziri ọnụọgụ njehie	RO	Na-egosi ọnụọgụ mperi ECC emeziri.

Imepụta Example Deba aha Map maka Interlaken anya-akụkụ imewe Example
Jiri map ndekọ aha a mgbe ị na-emepụta ihe ngosi exampGbanwuo paramita ọnọdụ anya-akụkụ Interlaken.

Akwụsịghị	Aha	Nweta	Nkọwa
8'h00	Echekwara
8'h01	Ntọgharị counter	RO	Dee 1 ka ọ bụrụ bit [0] iji kpochapụ TX na RX counter hà nhata.
8'h02	Ntọgharị PLL Sistemu	RO	bits ndị a na-egosi arịrịọ nrụpụta PLL sistemu wee mee ka uru dị: • Bit [0] - sys_pll_rst_req • Bit [1] - sys_pll_rst_en
8'h03	Ahịrị RX kwadoro	RO	Na-egosi nhazi n'ụzọ RX.
8'h04	akpọchiri okwu	RO	[NUM_LANES–1:0] – Okwu (mgbochi) njirimara oke.
8'h05	Mmekọrịta akpọchiri	RO	[NUM_LANES–1:0] – Metaframe gakọrịta.
8 'h06 - 8'h09	Ọnụọgụ njehie CRC32	RO	Na-egosi ọnụọgụ njehie CRC32.
8'h0A	Ọnụọgụ njehie CRC24	RO	Na-egosi ọnụọgụ njehie CRC24.
gara n'ihu…

Akwụsịghị	Aha	Nweta	Nkọwa
8'h0B	Echekwara
8'h0C	Ọnụọgụ SOP	RO	Na-egosi ọnụọgụ SOP.
8h0d	Ọnụọgụ EOP	RO	Na-egosi ọnụ ọgụgụ nke EOP
8'h0E	Ọnụọgụ mperi	RO	Na-egosi ọnụọgụ mperi ndị a: • Ọnwụ nke nhazi okporo ụzọ • Okwu njikwa iwu na-akwadoghị • Usoro nhazi nke ezighi ezi • Ihe ngosi SOP ma ọ bụ EOP efu
8'h0F	zipu_data_mm_clk	RW	Dee 1 na bit [0] iji mee ka mgbama generator nwee ike.
8'h10	Njehie nyocha	RO	Na-egosi mperi nyocha. (Njehie data SOP, njehie nọmba ọwa, yana njehie data PLD)
8'h11	Mkpọchi PLL Sistemu	RO	Bit [0] na-egosi egosi mkpọchi PLL.
8'h13	Ọnụọgụ latency	RO	Na-egosi ọnụ ọgụgụ nke latency.
8'h14	Ọnụọgụ TX SOP	RO	Na-egosi ọnụọgụ SOP nke ihe na-emepụta ngwugwu mebere.
8'h15	Ọnụ ego TX EOP	RO	Na-egosi ọnụọgụ nke EOP nke ihe na-emepụta ngwugwu mepụtara.
8'h16	ngwugwu na-aga n'ihu	RO	Dee 1 na bit [0] iji mee ka ngwugwu ahụ na-aga n'ihu.
8'h17	TX na RX counter hà nhata	RW	Na-egosi TX na counter RX hà nhata.
8'h23	Kwado latency	WO	Dee 1 ka ọ̀tụ̀tụ̀ [0] iji mee ka ọ̀tụ̀tụ̀ latency nwee ike.
8'h24	adịla njikere	RO	Na-egosi njiri latency adịla njikere.

Interlaken (ọgbọ nke abụọ) Intel Agilex 2 FPGA IP Design ExampEbe nchekwa ihe ntuziaka onye ọrụ

• Maka ụdị ọhụrụ na nke gara aga nke ntuziaka onye ọrụ a, rụtụ aka na Interlaken (2nd
• Ọgbọ) Intel Agilex 7 FPGA IP Design Example User Guide HTML version. Họrọ ụdị na pịa Download. Ọ bụrụ na edepụtaghị ụdị IP ma ọ bụ sọftụwia, ntuziaka onye ọrụ maka ụdị IP gara aga ma ọ bụ ụdị ngwanrọ na-emetụta.
• Ụdị IP bụ otu ụdị sọftụwia Intel Quartus Prime Design Suite ruo v19.1. Site na ụdị sọftụwia Intel Quartus Prime Design Suite 19.2 ma ọ bụ karịa, IP cores nwere atụmatụ mbipụta IP ọhụrụ.

Akụkọ ndozigharị akwụkwọ maka Interlaken (ọgbọ nke abụọ) Intel Agilex 2 FPGA IP Design Example ntuziaka onye ọrụ

Ụdị akwụkwọ	Intel Quartus Prime Version	Ụdị IP	Mgbanwe
2023.06.26	23.2	21.1.1	• agbakwunyere nkwado VHDL maka nhazi na ụdị ịme anwansị. • Aha ezinụlọ ngwaahịa emelitere ka ọ bụrụ "Intel Agilex 7".
2022.08.03	21.3	20.0.1	Emeziri ngwaọrụ OPN maka Intel Agilex F-Series Transceiver-SoC Development Kit.
2021.10.04	21.3	20.0.1	• nkwado agbakwunyere maka simulator QuestaSim. • nkwado ewepụrụ maka simulator NCsim.
2021.02.24	20.4	20.0.1	• agbakwunyere ozi gbasara ichekwa ọwa transceiver ejighi ya maka PAM4 na ngalaba: Nhazi ngwaike Exampna akụrụngwa. • Agbakwunyere nkọwa mgbaàmà pll_ref_clk[1] na ngalaba: Ihe nrịbama ihu.
2020.12.14	20.4	20.0.0	• emelitere sampMmepụta nnwale ngwaike maka ọnọdụ Interlaken yana ọnọdụ anya-akụkụ Interlaken na ngalaba Nnwale ihe nrụpụta ngwaike Example. • Maapụ ndebanye aha emelitere maka imewe anya-akụkụ Interlaken example na ngalaba Deba aha map. • Agbakwunyere njirisi ngafe maka nnwale ngwaike na-aga nke ọma na ngalaba Nnwale ihe nrụpụta ngwaike Example.
2020.10.16	20.2	19.3.0	Iwu emeziri iji mee mgbanwe mgbanwe izizi n'akụkụ RX n'ime Nnwale ihe nrụpụta ngwaike Example ngalaba.
2020.06.22	20.2	19.3.0	• Nhazi example dị maka Interlaken Look-side mode. • Nnwale ngwaike nke imewe example dị maka Intel Agilex ngwaọrụ iche. • agbakwunyere Ọgụgụ: Eserese ngọngọ dị elu maka Interlaken (ọgbọ nke abụọ) Nhazi Ọpụample. • Emelitere ngalaba ndị a: —   Achọrọ ngwaike na ngwanrọ —   Ọdịdị ndekọ • Haziri ọnụ ọgụgụ ndị a ka ịgụnye mmelite metụtara anya-akụkụ Interlaken: —   Ihe onyonyo: Interlaken (ọgbọ nke abụọ) Nhazi ngwaike Example Eserese Block High Ọkwa maka E-tile NRZ Ụdịdị dị iche iche —   Ihe onyonyo: Interlaken (ọgbọ nke abụọ) Nhazi ngwaike Example Eserese Block High Ọkwa maka E-tile PAM4 ụdịdị dị iche iche • emelitere Ọgụgụ: IP Parameter Editor.
gara n'ihu…

Ụdị akwụkwọ	Intel Quartus Prime Version	Ụdị IP	Mgbanwe
			• agbakwunyere ozi gbasara ntọala ugboro na ngwa njikwa elekere na ngalaba Ịchịkọta na Hazie Nhazi Exampna Hardware. • Mgbakwunye ọsọ ule agbakwunyere maka Interlaken Look n'akụkụ na ngalaba ndị a: —   Ịmepụta atụmatụ Exampna Testbench —   Nnwale ihe nrụpụta ngwaike Example • Agbakwunyere na-eso akara ngosi ọhụrụ Ihe nrịbama ihu ngalaba: - mgmt_clk - rx_pin_n - tx_pin_n - mac_clk_pll_ref • Maapụ ndebanye aha agbakwunyere maka imewe anya-akụkụ Interlaken example in ngalaba: Deba aha Map.
2019.09.30	19.3	19.2.1	Ewepụrụ clk100. The mgmt_clk na-eje ozi dị ka elekere ntụaka na IO PLL na ndị a: •    Ihe onyonyo: Interlaken (ọgbọ nke abụọ) Nhazi ngwaike Example Eserese ngọngọ High Ọkwa maka E-tile NRZ ụdịdị iche iche. •    Ihe onyonyo: Interlaken (ọgbọ nke abụọ) Nhazi ngwaike Example Eserese Block High Ọkwa maka E-tile PAM4 ụdịdị dị iche iche.
2019.07.01	19.2	19.2	Ntọhapụ mbụ.

Interlaken (ọgbọ nke abụọ) Intel Agilex® 2 FPGA IP Design Example ntuziaka onye ọrụ

Akwụkwọ / akụrụngwa

Intel Interlaken 2nd Generation Agilex 7 FPGA IP Design Example [pdf] Ntuziaka onye ọrụ Interlaken 2nd Generation Agilex 7 FPGA IP Design Example, Interlaken, Ọgbọ nke abụọ Agilex 2 FPGA IP Design Example, FPGA IP Design Example, IP Design Example, Imepụta Example

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