Litaba pata
1 Intel Interlaken 2nd Generation Agilex 7 FPGA IP Design Example
2 Tlhahisoleseding ya Sehlahiswa
3 Litaelo tsa Tšebeliso ea Sehlahisoa
4 Tataiso ea ho Qala ka Potlako
5 Hardware le Software
6 Lintlha Tse Amanang
7 Moqapi Example Tlhaloso
8 Litokomane / Lisebelisoa
8.1 Litšupiso

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Intel Interlaken 2nd Generation Agilex 7 FPGA IP Design Example

Intel-Interlaken-2nd-Generation-Agilex-7-FPGA-IP-Design-Example-sehlahisoa

Tlhahisoleseding ya Sehlahiswa

Interlaken (2nd Generation) FPGA IP ea mantlha ke karolo ea Intel Agilex 7 FPGA. E fana ka ketsiso testbench le hardware moralo example e tšehetsang ho bokella le ho hlahloba hardware. Moqapi example e fumaneha hape bakeng sa karolo ea Interlaken Look-aside. IP core e ts'ehetsa mokhoa oa NRZ le PAM4 bakeng sa lisebelisoa tsa E-tile mme e hlahisa moralo oa examples bakeng sa metsoako eohle e tšehetsoeng ea palo ea litselana le litefiso tsa data.

Litlhoko tsa Hardware le Software
Interlaken (2nd Generation) IP core design example hloka Intel Agilex 7 F-Series Transceiver-SoC Development Kit. Ka kopo sheba Bukana ea Mosebelisi ea lisebelisoa tsa nts'etsopele ho fumana lintlha tse ling.

Sebopeho sa Directory
Interlaken (Moloko oa Bobeli) e hlahisitsoeng example design e kenyelletsa li-directory tse latelang:

  • example_design: E na le sehlooho files bakeng sa moralo example.
  • ilk_uflex: E na le files e amanang le khetho ea mokhoa oa Interlaken Look-aside.
  • ila_uflex: E na le files e amanang le khetho ea mokhoa oa Interlaken Look-aside (e hlahisoang feela ha e khethiloe).

Litaelo tsa Tšebeliso ea Sehlahisoa

Ho sebelisa Interlaken (2nd Generation) FPGA IP core design example, latela mehato ena:

  1. Netefatsa hore o na le Intel Agilex 7 F-Series Transceiver-SoC Development Kit.
  2. Kopanya moralo exampKe sebelisa simulator.
  3. Etsa papiso e sebetsang ho netefatsa moralo.
  4. Hlahisa sebopeho sa mohlalaample sebelisa parameter editor.
  5. Kopanya moralo example sebelisa Quartus Prime.
  6. Etsa tlhahlobo ea hardware ho netefatsa moralo.

Hlokomela: Khetho ea mokhoa oa Interlaken Look-aside e fumaneha bakeng sa khetho ho mohlophisi oa paramethara ea IP. Haeba e khethiloe, eketsa files e tla hlahisoa bukeng ea "ila_uflex".

Tataiso ea ho Qala ka Potlako

  • Interlaken (2nd Generation) FPGA IP core e fana ka teko ea ketsiso le moralo oa lisebelisoa tsa khale.ample e tšehetsang ho bokella le ho hlahloba hardware.
  • Ha o hlahisa moqapi example, mohlophisi oa parameter o iketsetsa faele ea files bohlokoa ho etsisa, ho bokella, le ho leka moralo ho hardware.
  • Moqapi example e fumaneha hape bakeng sa karolo ea Interlaken Look-aside.
  • The testbench le moralo example e ts'ehetsa mokhoa oa NRZ le PAM4 bakeng sa lisebelisoa tsa E-tile.
  • Interlaken (2nd Generation) FPGA IP mantlha e hlahisa moralo oa examples bakeng sa metsoako eohle e tšehetsoeng ea palo ea litselana le litefiso tsa data.

Setšoantšo sa 1. Mehato ea Ntlafatso ea Moqapi ExampleIntel-Interlaken-2nd-Generation-Agilex-7-FPGA-IP-Design-Example-fig-1 (1)

Interlaken (2nd Generation) IP core design example e tšehetsa likarolo tse latelang:

  • Ka hare TX ho RX serial loopback mode
  • E iketsetsa lipakete tsa boholo bo tsitsitseng
  • Bokhoni ba ho hlahloba pakete ea mantlha
  • Bokhoni ba ho sebelisa System Console ho hlophisa moralo bocha molemong oa ho etsa liteko hape
  • Phetoho ea PMA

Intel Corporation. Litokelo tsohle li sirelelitsoe. Intel, logo ea Intel, le matšoao a mang a Intel ke matšoao a khoebo a Intel Corporation kapa lithuso tsa eona. Intel e tiisa ts'ebetso ea FPGA ea eona le lihlahisoa tsa semiconductor ho latela litlhaloso tsa hajoale ho latela waranti e tloaelehileng ea Intel, empa e na le tokelo ea ho etsa liphetoho ho lihlahisoa le lits'ebeletso life kapa life ka nako efe kapa efe ntle le tsebiso. Intel ha e nke boikarabello kapa boikarabello bo hlahang ka lebaka la kopo kapa ts'ebeliso ea tlhahisoleseling efe kapa efe, sehlahisoa, kapa ts'ebeletso e hlalositsoeng mona ntle le ha ho lumellane ka ho hlaka ka lengolo ke Intel. Bareki ba Intel ba eletsoa ho fumana mofuta oa morao-rao oa litlhaloso tsa sesebelisoa pele ba itšetleha ka tlhahisoleseling efe kapa efe e phatlalalitsoeng le pele ba kenya liodara tsa lihlahisoa kapa lits'ebeletso. *Mabitso a mang le mabitso a mang a ka nkoa e le thepa ea ba bang.

Setšoantšo sa 2. Setšoantšo sa Block Block sa boemo bo phahameng bakeng sa Interlaken (Moloko oa Bobeli) Moqapi Example

Lintlha Tse Amanang

  • Interlaken (Moloko oa Bobeli) FPGA IP User Guide
  • Interlaken (Moloko oa 2) Lintlha tsa Phallo tsa Intel FPGA IP

Hardware le Software

Litlhoko tsa Hardware le Software
Ho leka example design, sebelisa hardware le software tse latelang:

  • Software ea Intel® Quartus® Prime Pro Edition
  • Console ea tsamaiso
  • Li-simulator tse tšehetsoeng:
    • Siemens* EDA ModelSim* SE kapa QuestaSim*
    • Synopsy* VCS*
    • Cadence* Xcelium*
  • Intel Agilex® 7 F-Series Transceiver-SoC Development Kit (AGFB014R24A2E2V)

Lintlha Tse Amanang
Intel Agilex 7 F-Series Transceiver-SoC Development Kit User Guide
Sebopeho sa Directory
Interlaken (2nd Generation) IP core design example file li-directory li na le tse latelang tse hlahisitsoeng files bakeng sa moralo example.

Setšoantšo sa 3. Sebopeho sa Mananeo a Hlahisang Interlaken (Moloko oa Bobeli) Example DesignIntel-Interlaken-2nd-Generation-Agilex-7-FPGA-IP-Design-Example-fig-1 (3)

Tlhophiso ea hardware, ketsiso, le teko files li fumaneha hoample_installation_dir>/uflex_ilk_0_example_design.
Lethathamo la 1. Interlaken (Moloko oa Bobeli) IP Core Hardware Design Example File Litlhaloso Tsena files li hoample_installation_dir>/uflex_ilk_0_example_design/ mohlalaample_design/quartus directory.

File Mabitso Tlhaloso
example_design.qpf Morero oa mantlha oa Intel Quartus file.
example_design.qsf Litlhophiso tsa projeke ea Intel Quartus Prime file
example_design.sdc jtag_timing_template.sdc Synopsys Design Constraint file. U ka kopitsa le ho fetola moralo oa hau.
sysconsole_testbench.tcl Ka sehloohong file bakeng sa ho fihlella System Console

Lethathamo la 2. Interlaken (Moloko oa 2) IP Core Testbench File Tlhaloso
Sena file e ka har'aample_installation_dir>/uflex_ilk_0_example_design/ mohlalaample_design/rtl directory.

File Lebitso Tlhaloso
top_tb.sv Testbench ea boemo bo holimo file.

Lethathamo la 3. Interlaken (Moloko oa 2) IP Core Testbench Scripts
Tsena files li hoample_installation_dir>/uflex_ilk_0_example_design/ mohlalaample_design/testbench directory.

File Lebitso Tlhaloso
vcstest.sh Mongolo oa VCS ho tsamaisa testbench.
vlog_pro.do Sengoloa sa ModelSim SE kapa QuestaSim ho tsamaisa testbench.
xcelium.sh Sengoloa sa Xcelium ho tsamaisa testbench.

Moqapi oa lisebelisoa tsa thepa Example Likarolo

  • Example design e hokahanya lioache tsa litšupiso tsa sistimi le PLL le likarolo tse hlokahalang tsa moralo. Example design e hlophisa mantlha ea IP ka har'a mokhoa oa ka hare oa loopback mme e hlahisa lipakete ho sebopeho sa phetiso ea data ea mosebelisi ea IP core TX. IP core e romela lipakete tsena tseleng e ka hare ea loopback ka transceiver.
  • Kamora hore moamoheli oa mantlha oa IP a fumane lipakete tseleng ea loopback, e sebetsa
  • Lipakete tsa Interlaken ebe li li fetisetsa ho sebopeho sa phetiso ea data ea basebelisi ba RX. Example design e lekola hore na lipakete li amohetse le ho fetisoa li ts'oana.
  • The hardware example moralo o kenyelletsa li-PLL tsa kantle. U ka hlahloba mongolo o hlakileng files ho view sample khoutu e sebelisang mokhoa o le mong o ka khonehang oa ho hokahanya li-PLL tsa kantle ho Interlaken (2nd Generation) FPGA IP.
  • Moralo oa hardware oa Interlaken (2nd Generation) example kenyeletsa likarolo tse latelang:
    • Interlaken (Moloko oa Bobeli) FPGA IP
    • Pakete jenereithara le Pakete Checker
    • JTAG molaoli ea buisanang le System Console. U buisana le logic ea bareki ka System Console.

Setšoantšo sa 4. Interlaken (Moloko oa Bobeli) Moqapi oa Hardware Example Setšoantšo sa Thibelo ea Boemo bo Phahameng bakeng sa Phapang ea Mokhoa oa E-tile NRZIntel-Interlaken-2nd-Generation-Agilex-7-FPGA-IP-Design-Example-fig-1 (4)

Moralo oa hardware oa Interlaken (2nd Generation) exampLe hore e shebane le mefuta ea E-tile PAM4 e hloka oache e eketsehileng mac_clkin eo IO PLL e e hlahisang. PLL ena e tlameha ho sebelisa oache e ts'oanang e tsamaisang pll_ref_clk.
Setšoantšo sa 5. Interlaken (Moloko oa Bobeli) Moqapi oa Hardware Example Setšoantšo se Phahameng sa Block Block bakeng sa E-tile PAM4 Mode VariationsIntel-Interlaken-2nd-Generation-Agilex-7-FPGA-IP-Design-Example-fig-1 (5)

Bakeng sa mefuta e fapaneng ea mokhoa oa E-tile PAM4, ha o nolofalletsa Boloka liteishene tsa transceiver tse sa sebelisoeng bakeng sa parameter ea PAM4, ho eketsoa sebaka se eketsehileng sa oache (pll_ref_clk [1]). Boema-kepe bona bo tlameha ho tsamaisoa ka makhetlo a tšoanang le a hlalositsoeng ho IP parameter editor (Reference clock frequency bakeng sa likanale tse bolokiloeng). The Sireletsa likanale tsa transceiver tse sa sebelisoeng bakeng sa PAM4 ke boikhethelo. Pini le litšitiso tse amanang le tsona tse abetsoeng oache ena li bonahala ho QSF ha u khetha Intel Stratix® 10 kapa Intel Agilex 7 kit ea ntlafatso bakeng sa tlhahiso ea moralo.
Hlokomela: Bakeng sa moralo example simulation, testbench e lula e hlalosa makhetlo a tšoanang bakeng sa pll_ref_clk[0] le pll_ref_clk[1].
Lintlha Tse Amanang
Intel Agilex 7 F-Series Transceiver-SoC Development Kit User Guide

Ho Hlahisa Moralo
Setšoantšo sa 6. TsamaisoIntel-Interlaken-2nd-Generation-Agilex-7-FPGA-IP-Design-Example-fig-1 (6)

Latela mehato ena ho hlahisa hardware example moralo le testbench:

  1. Ho software ea Intel Quartus Prime Pro Edition, tobetsa File ➤ Project Wizard e Ncha ho theha projeke e ncha ea Intel Quartus Prime, kapa tobetsa File ➤ Open Project ho bula morero o teng oa Intel Quartus Prime. Wizate e o kopa hore o hlalose sesebediswa.
  2. Hlalosa lelapa la sesebelisoa Intel Agilex 7 'me u khethe sesebelisoa bakeng sa moralo oa hau.
  3. Ho IP Catalog, fumana le ho penya habeli Interlaken (2nd Generation) Intel FPGA IP. Ho hlaha fensetere e ncha ea IP Variant.
  4. Hlalosa lebitso la boemo bo holimo bakeng sa phapang ea hau ea IP e tloaelehileng. Mohlophisi oa paramethara o boloka litlhophiso tsa phapang ea IP ho a file bitsetsoe .ip.
  5. Tobetsa OK. Mohlophisi oa parameter oa hlaha.
    Setšoantšo sa 7. Example Design Tab ho Interlaken (Moloko oa Bobeli) Intel FPGA IP Parameter EditorIntel-Interlaken-2nd-Generation-Agilex-7-FPGA-IP-Design-Example-fig-1 (7)
  6. Ho tab ea IP, hlakisa li-parameter tsa IP ea hau ea mantlha.
  7. Ho thebo ea PMA Adaptation, hlakisa maemo a ho ikamahanya le maemo a PMA haeba u rera ho sebelisa phetoho ea PMA bakeng sa mefuta ea hau ea lisebelisoa tsa E-tile. Mohato ona ke oa boikhethelo:
    • Khetha Numella ho ikamahanya le maemo a bonolo a IP khetho.
    • Hlokomela: O tlameha ho nolofalletsa khetho ea Enable Native PHY Debug Master Endpoint (NPDME) ho tab ea IP ha ho feto-fetoha ha PMA ho nolofalitsoe.
    • Khetha setaele se seng sa PMA bakeng sa ho ikamahanya le maemo a PMA Khetha parametha.
    • Tobetsa PMA Adaptation Preload ho kenya li-parameter tsa pele le tse tsoelang pele tsa ho ikamahanya le maemo.
    • Hlalosa palo ea litlhophiso tsa PMA ho tšehetsa ha litlhophiso tse ngata tsa PMA li nolofalitsoe ho sebelisoa Palo ea paramethara ea tlhophiso ea PMA.
    • Kgetha hore na o tla kenya kapa o boloke tlhophiso efe ya PMA ka ho sebedisa Kgetha tlhophiso ya PMA ho kenya kapa ho e boloka.
    • Tobetsa Load adaptation ho tsoa ho tlhophiso ea PMA e khethiloeng ho kenya litlhophiso tse khethiloeng tsa PMA.
    • Bakeng sa tlhaiso-leseling e batsi mabapi le liparamente tsa ho ikamahanya le PMA, sheba ho E-tile
      Tataiso ea mosebelisi ea Transceiver PHY.
  8. Ho Example Design tab, khetha khetho ea Simulation ho hlahisa testbench, 'me u khethe khetho ea Synthesis ho hlahisa thepa ea khale.ampmoralo.
    • Hlokomela: U tlameha ho khetha bonyane khetho e le 'ngoe ea Simulation kapa Synthesis e hlahisang Example Design Files.
  9. Bakeng sa Foromo e Hlahisitsoeng ea HDL, khetha Verilog kapa VHDL.
  10. Bakeng sa Target Development Kit khetha khetho e nepahetseng.
    • Hlokomela: Khetho ea Intel Agilex 7 F-Series Transceiver SoC Development Kit e fumaneha feela ha morero oa hau o hlalosa lebitso la sesebelisoa sa Intel Agilex 7 ho qala ka AGFA012 kapa AGFA014. Ha o khetha khetho ea Development Kit, likabelo tsa phini li behiloe ho latela nomoro ea sesebelisoa sa Intel Agilex 7 Development Kit AGFB014R24A2E2V mme e ka fapana le sesebelisoa seo u se khethileng. Haeba u ikemiselitse ho leka moralo ho hardware ho PCB e fapaneng, khetha khetho ea None 'me u etse likabelo tse nepahetseng ho .qsf file.
  11. Tobetsa Hlahisa Example Design. The Khetha Exampho hlaha fensetere ea Design Directory.
  12. Haeba u batla ho fetola moralo examptsela ea directory kapa lebitso ho tsoa ho li-defaults tse bontšitsoeng (uflex_ilk_0_example_design), sheba tsela e ncha ebe u thaepa sebopeho se secha sa example lebitso la directory.
  13. Tobetsa OK.

Lintlha Tse Amanang

  • Intel Agilex 7 F-Series Transceiver-SoC Development Kit User Guide
  • E-tile Transceiver PHY User Guide

Ho Etsisa Moralo Example Testbench
Sheba ho Interlaken (Moloko oa Bobeli) Moqapi oa Hardware Example Block Level Level bakeng sa E-tile NRZ Mode Variations and Interlaken (2nd Generation) Hardware Design Ex.ample High Level Block bakeng sa E-tile PAM4 Mode Variations block diagrams tsa simulation testbench.
Setšoantšo sa 8. TsamaisoIntel-Interlaken-2nd-Generation-Agilex-7-FPGA-IP-Design-Example-fig-1 (8)

Latela mehato ena ho etsisa testbench:

  1. Ka potlako ea taelo, fetola ho directory ea simulation ea testbench. Lethathamo keample_installation_dir>/example_design/ testbench bakeng sa lisebelisoa tsa Intel Agilex 7.
  2. Matha sengoloa sa ketsiso bakeng sa simulator e tšehelitsoeng eo u e khethileng. Script e bokella le ho tsamaisa testbench ho simulator. Sengoliloeng sa hau se lokela ho lekola hore SOP le EOP li bapana ka mor'a hore papiso e felile. Sheba tafoleng Mehato ea ho Matha Ketsiso.

Lethathamo la 4. Mehato ea ho Matha Ketsiso

Moetsisi Litaelo
ModelSim SE kapa QuestaSim Moleng oa taelo, thaepa -do vlog_pro.do

Haeba u khetha ho etsisa ntle le ho hlahisa ModelSim GUI, thaepa vsim -c -do vlog_pro.do
VCS Moleng oa taelo, thaepa sh vcstest.sh
Xcelium Moleng oa taelo, thaepa sh xcelium.sh

Sekaseka liphetho. Ketsiso e atlehileng e romella le ho amohela lipakete, 'me e bonts'a "Test PASSED".
The testbench bakeng sa moralo example phetha mesebetsi e latelang:

  • Instatiates Interlaken (Moloko oa Bobeli) Intel FPGA IP.
  • E hatisa boemo ba PHY.
  • E hlahloba khokahano ea metaframe (SYNC_LOCK) le meeli ea lentsoe (thibelo) (WORD_LOCK).
  • E emetse hore litselana ka bomong li notleloe le ho lokisoa.
  • E qala ho tsamaisa lipakete.
  • E hlahloba lipalo-palo tsa liphutheloana:
    • CRC24 liphoso
    • SOPs
    • EOPs

Tse latelang sample sephetho se bonts'a tlhahlobo e atlehileng ea papiso e etsoang ka mokhoa oa Interlaken:Intel-Interlaken-2nd-Generation-Agilex-7-FPGA-IP-Design-Example-fig-1 (9)Intel-Interlaken-2nd-Generation-Agilex-7-FPGA-IP-Design-Example-fig-1 (10)

Hlokomela: Moqapi oa Interlaken example simulation testbench e romella lipakete tse 100 mme e amohela lipakete tse 100. Tse latelang sample sephetho se bonts'a tlhahlobo e atlehileng ea ketsiso e etsoang ka mokhoa oa Interlaken Look-aside:Intel-Interlaken-2nd-Generation-Agilex-7-FPGA-IP-Design-Example-fig-1 (11)

Hlokomela: Palo ea lipakete (SOPs le EOPs) e fapana ka lane ho Interlaken Lookaside design ex.ample ketsiso sample tlhahiso.
Lintlha Tse Amanang
Moqapi oa lisebelisoa tsa thepa Example Likarolo leqepheng la 6

Ho Kopanya le ho Hlophisa Moralo Example ho Hardware
Setšoantšo sa 9. TsamaisoIntel-Interlaken-2nd-Generation-Agilex-7-FPGA-IP-Design-Example-fig-1 (12)

Ho bokella le ho etsa tlhahlobo ea pontšo ho hardware example design, latela mehato ena:

  1. Netefatsa hore hardware example tlhahiso ea moralo e felile.
  2. Ho software ea Intel Quartus Prime Pro Edition, bula morero oa Intel Quartus Primeample_installation_dir>/example_design/quartus/ example_design.qpf>.
  3. Ho menu ea Processing, tobetsa Start Compilation.
  4. Ka mor'a ho bokella ka katleho, a .sof file e fumaneha bukeng ea hau e boletsoeng. Latela mehato ena ho etsa lenaneo la hardware example moralo ho sesebelisoa sa Intel Agilex 7:
    • a. Hokela Intel Agilex 7 F-Series Transceiver-SoC Development Kit khomphuteng ea moamoheli.
    • b. Qala ts'ebeliso ea Clock Control, e leng karolo ea lisebelisoa tsa nts'etsopele, 'me u behe maqhubu a macha bakeng sa moqapi oa khale.ample. Ka tlase ke litlhophiso tsa khafetsa ts'ebelisong ea Clock Control:
    • • Si5338 (U37), CLK1- 100 MHz
    • • Si5338 (U36), CLK2- 153.6 MHz
    • • Si549 (Y2), OUT- Beha boleng ba pll_ref_clk(1) ho latela tlhoko ea moralo oa hau.
    • c. Ho Tools menu, tobetsa Programmer.
    • d. Ho "Programmer", tobetsa "Hardware Setup".
    • e. Khetha sesebelisoa sa ho etsa mananeo.
    • f. Khetha 'me u kenye Intel Agilex 7 F-Series Transceiver-SoC Development Kit eo karolo ea hau ea Intel Quartus Prime e ka hokelang ho eona.
    • g. Netefatsa hore Mode e setetsoe ho JTAG.
    • h. Khetha sesebelisoa sa Intel Agilex 7 ebe o tobetsa Eketsa Sesebelisoa. Lenaneo le bonts'a setšoantšo sa li-block tsa likhokahano lipakeng tsa lisebelisoa tse botong ea hau.
    • ke. Moleng le .sof ea hau, hlahloba lebokose la .sof.
    • j. Tshwaya lebokoso mo kholomong ya Lenaneo/Configure.
    • k. Tobetsa Qala.

Lintlha Tse Amanang

  • Lisebelisoa tsa Intel FPGA tsa mananeo leqepheng la 0
  • Ho sekaseka le ho lokisa meralo ka System Console
  • Intel Agilex 7 F-Series Transceiver-SoC Development Kit User Guide

Ho Lekola Moetso oa Hardware Example
Kamora hore o bokelle Interlaken (2nd Generation) Intel FPGA IP core design example ho lokisa sesebelisoa sa hau, u ka sebelisa System Console ho hlophisa motheo oa IP le lirejistara tsa eona tsa mantlha tsa Native PHY IP.

Latela mehato ena ho hlahisa Console ea Sisteme le ho leka moralo oa lisebelisoa tsa khaleampLe:

  1. Ho software ea Intel Quartus Prime Pro Edition, ho Tools menu, tobetsa Lisebelisoa tsa Tsamaiso ea Tsamaiso ➤ System Console.
  2. Fetola ho eaample_installation_dir>mohlalaample_design/ hwtest directory.
  3. Ho bula khokahano ho JTAG monghali, ngola taelo e latelang: mohloli sysconsole_testbench.tcl
  4. O ka bulela serial loopback mode ka moetso o latelangample litaelo:
    • a. stat: E hatisa lintlha tse akaretsang tsa boemo.
    • b. sys_reset: E tsosolosa tsamaiso.
    • c. loop_on: E bulela serial loopback e ka hare.
    • d. run_example_design: E tsamaisa sebopeho sa mohlalaample.
    • Hlokomela: U tlameha ho tsamaisa taelo ea loop_on pele run_examptaelo ea le_design. The run_example_design e tsamaisa litaelo tse latelang ka tatellano: sys_reset->stat->gen_on->stat->gen_off.
    • Hlokomela: Ha o khetha Enable adaptation load soft IP khetho, run_examptaelo ea le_design e etsa tekanyo ea pele ea ho ikamahanya le maemo ka lehlakoreng la RX ka ho sebelisa taelo ea run_load_PMA_configuration.
  5. O ka tima mokhoa oa ka hare oa serial loopback ka moralo o latelang oa mohlalaample command:
    • a. loop_off: E tima loopback ea ka hare ea serial.
  6. U ka hlophisa mantlha ea IP ka moralo o latelang oa mohlalaample litaelo:
    • a. gen_on: E nolofalletsa jenereithara ea pakete.
    • b. gen_off: E thibela jenereithara ea pakete.
    • c. run_test_loop: E etsa tlhahlobo bakeng sa linako tse fapaneng tsa E-tile NRZ le PAM4.
    • d. clear_err: E hlakola likarolo tsohle tsa liphoso tse khomarelang.
    • e. set_test_mode : E theha tlhahlobo hore e sebetse ka mokhoa o itseng.
    • f. get_test_mode: E hatisa mokhoa oa hajoale oa teko.
    • g. set_burst_size : E beha boholo ba ho phatloha ka li-byte.
    • h. get_burst_size: E hatisa lintlha tsa boholo bo phatlohileng.

Teko e atlehileng e hatisa HW_TEST:PASS molaetsa. Ka tlase ke mekhoa ea ho feta bakeng sa ho etsa tlhahlobo:

  • Ha ho liphoso tsa CRC32, CRC24, le checker.
  • Li-SOP tse fetisoang le li-EOP li lokela ho tsamaisana le tse amoheloang.

Tse latelang sample sephetho se bonts'a tlhahlobo e atlehileng e etsoang ka mokhoa oa Interlaken:Intel-Interlaken-2nd-Generation-Agilex-7-FPGA-IP-Design-Example-fig-1 (13)

Teko e atlehileng e hatisitse HW_TEST : Molaetsa oa PASS. Ka tlase ke mekhoa ea ho feta bakeng sa ho etsa tlhahlobo:

  • Ha ho liphoso tsa CRC32, CRC24, le checker.
  • Li-SOP tse fetisoang le li-EOP li lokela ho tsamaisana le tse amoheloang.

Tse latelang sample sephetho se bonts'a tlhahlobo e atlehileng e etsoang ka mokhoa oa Interlaken Lookaside:Intel-Interlaken-2nd-Generation-Agilex-7-FPGA-IP-Design-Example-fig-1 (14)Intel-Interlaken-2nd-Generation-Agilex-7-FPGA-IP-Design-Example-fig-1 (15)

Moqapi Example Tlhaloso

Moqapi example e bonts'a ts'ebetso ea mantlha ea IP ea Interlaken.

Lintlha Tse Amanang
Interlaken (Moloko oa Bobeli) FPGA IP User Guide

Moqapi Example Boitšoaro
Ho leka moralo ho Hardware, thaepa litaelo tse latelang ho System Console:

  1. Mohloli oa setup file:
    • % mohloliample>uflex_ilk_0_example_design/example_design/hwtest/ sysconsole_testbench.tcl
  2. Etsa tlhahlobo:
    • % run_example_design
  3. Moralo oa hardware oa Interlaken (2nd Generation) example phetha mehato e latelang:
    • a. E tsosolosa IP ea Interlaken (Moloko oa Bobeli).
    • b. E lokisa Interlaken (Moloko oa Bobeli) IP ka mokhoa oa ka hare oa loopback.
    • c. E romella liphutheloana tse ngata tsa Interlaken tse nang le data e boletsoeng esale pele e lefelloang ho sebopeho sa phetisetso ea data ea mosebelisi ea TX ea mantlha ea IP.
    • d. E hlahloba lipakete tse amohetsoeng ebe e tlaleha boemo. Sehlahlobi sa pakete se kenyellelitsoeng ho sebopeho sa hardware exampLe e fana ka lintlha tse latelang tsa ho hlahloba liphutheloana:
      • E hlahloba hore na tatellano ea pakete e fetisoang e nepahetse.
      • Lekola hore na data e amohetsweng e tsamaellana le boleng bo lebeletsweng ka ho netefatsa hore palo ya ho qala pakete (SOP) le ya pheletso ya pakete (EOP) e tsamaellana ha data e ntse e romelwa le ho amohelwa.

Lipontšo tsa Interface
Lethathamo la 5. Moqapi Example Lipontšo tsa Interface

Lebitso la Port Tataiso Bophara (Bits) Tlhaloso
 

mgmt_clk

  

Kenyeletso

  

1

 Ho kenya oache ea sistimi. Maqhubu a oache a tlameha ho ba 100 MHz.
pll_ref_clk /

pll_ref_clk[1:0](2)

  

Kenyeletso

  

1/2

 Oache ea litšupiso ea transceiver. E tsamaisa RX CDR PLL.
e tsoela pele…
Lebitso la Port Tataiso Bophara (Bits) Tlhaloso
      pll_ref_clk[1] e fumaneha feela ha o butse Boloka e sa sebelisoe

Hlokomela: likanale tsa transceiver tsa PAM4 parameter ka E-tile PAM4 mode IP mefuta e fapaneng.
rx_pin Kenyeletso Palo ea litselana Receiver SERDES phini ea data.
tx_pin Sephetho Palo ea litselana Fetisetsa PIN ea data ea SERDES.
 

rx_pin_n

  

Kenyeletso

  

Palo ea litselana

 Receiver SERDES phini ea data.

Letšoao lena le fumaneha feela ka mefuta ea lisebelisoa tsa mokhoa oa E-tile PAM4.
 

tx_pin_n

  

Sephetho

  

Palo ea litselana

 Fetisetsa PIN ea data ea SERDES.

Letšoao lena le fumaneha feela ka mefuta ea lisebelisoa tsa mokhoa oa E-tile PAM4.
 

 

mac_clk_pll_ref

  

 

Kenyeletso

  

 

1

 Letšoao lena le tlameha ho tsamaisoa ke PLL 'me le tlameha ho sebelisa mohloli o tšoanang oa oache o tsamaisang pll_ref_clk.

Letšoao lena le fumaneha feela ka mefuta ea lisebelisoa tsa mokhoa oa E-tile PAM4.
usr_pb_reset_n Kenyeletso 1 Sesebelisoa sa reset.

Lintlha Tse Amanang
Lipontšo tsa Interface

Ngolisa 'mapa
Hlokomela: • Moralo ExampAterese ea register e qala ka 0x20** ha aterese ea mantlha ea IP ea Interlaken e qala ka 0x10**.

  • Khouto ea ho kena: RO—Bala Feela, le RW—Bala/Ngola.
  • System console e bala sebopeho sa exampe ngolisa le ho tlaleha boemo ba teko skrineng.

Lethathamo la 6. Moqapi Example Ngoliso 'mapa oa Interlaken Design Example

Offset Lebitso Phihlello Tlhaloso
8h00 Reserved
8h01 Reserved
 

 

8h02

  

 

Sistimi ea PLL e nchafalitsoe

  

 

RO

 Li-bits tse latelang li bonts'a kopo ea ho seta bocha PLL le ho nolofalletsa boleng:

• Bit [0] – sys_pll_rst_req

• Bit [1] – sys_pll_rst_en
8h03 RX lane e tsamaellana RO E bonts'a tlhophiso ea tsela ea RX.
 

8h04

  

LENTSOE notletsoe

  

RO

 [NUM_LANES–1:0] – Tlhaloso ea meeli ea Lentsoe (thibelo).
e tsoela pele…

Ha o nolofalletsa Boloka liteishene tsa transceiver tse sa sebelisoeng bakeng sa paramethara ea PAM4, boema-kepe bo eketsehileng ba litšupiso bo eketsoa ho boloka mocha oa makhoba oa PAM4 o sa sebelisoeng.

Offset Lebitso Phihlello Tlhaloso
8h05 Khokahano e notletsoe RO [NUM_LANES–1:0] – Khokahano ea Metaframe.
8'h06 - 8'h09 CRC32 palo ea liphoso RO E bontša palo ea liphoso tsa CRC32.
8h0A CRC24 palo ea liphoso RO E bontša palo ea liphoso tsa CRC24.
 

 

8h0b

  

 

Lets'oao la ho phalla / Tlaaseha

  

 

RO

 Lintlha tse latelang li bontša:

• Bit [3] - TX lets'oao la phallo e tlase

• Bit [2] - Letšoao la ho phalla la TX

• Bit [1] - Letšoao la ho phalla la RX
8h0C palo ea SOP RO E bontša palo ea SOP.
8'h0D palo ea EOP RO E bontša palo ea EOP
 

 

8h0E

  

 

Palo ea liphoso

  

 

RO

 E bontša palo ea liphoso tse latelang:

• Ho lahleheloa ke tsela ea tsela

• Lentsoe la taolo e seng molaong

• Paterone e seng molaong ea ho etsa liforeimi

• SOP kapa EOP sesupa se sieo
8'h0F send_data_mm_clk RW Ngola 1 ho bit [0] ho nolofalletsa lets'oao la jenereithara.
 

8h10

  

Phoso ea ho hlahloba

   E bontša phoso ea ho hlahloba. (Phoso ea data ea SOP, phoso ea nomoro ea Channel, le phoso ea data ea PLD)
8h11 Sistimi PLL senotlolo RO Bit [0] e supa sesupo sa senotlolo sa PLL.
 

8h14

  

TX SOP palo

  

RO

 E bontša palo ea SOP e hlahisoang ke jenereithara ea pakete.
 

8h15

  

TX EOP palo

  

RO

 E bontša palo ea EOP e hlahisoang ke jenereithara ea pakete.
8h16 Phakete e tsoelang pele RW Ngola ho tloha ho 1 ho isa ho [0] ho nolofalletsa pakete e tsoelang pele.
8h39 ECC palo ea liphoso RO E bontša palo ea liphoso tsa ECC.
8h40 ECC e lokisitse palo ea liphoso RO E bontša palo ea liphoso tse lokisitsoeng tsa ECC.

Moqapi Example Ngolisa 'mapa oa Interlaken Sheba-kathoko Design Example
Sebelisa 'mapa ona oa rejisetara ha u etsa moralo oa example ka Enable Interlaken Look-aside mode parameter e butswe.

Offset Lebitso Phihlello Tlhaloso
8h00 Reserved
8h01 Counter reset RO Ngola 1 to bit [0] ho hlakola TX le RX counter biti e lekanang.
 

 

8h02

  

 

Sistimi ea PLL e nchafalitsoe

  

 

RO

 Li-bits tse latelang li bonts'a kopo ea ho seta bocha PLL le ho nolofalletsa boleng:

• Bit [0] – sys_pll_rst_req

• Bit [1] – sys_pll_rst_en
8h03 RX lane e tsamaellana RO E bonts'a tlhophiso ea tsela ea RX.
 

8h04

  

LENTSOE notletsoe

  

RO

 [NUM_LANES–1:0] – Tlhaloso ea meeli ea Lentsoe (thibelo).
8h05 Khokahano e notletsoe RO [NUM_LANES–1:0] – Khokahano ea Metaframe.
8'h06 - 8'h09 CRC32 palo ea liphoso RO E bontša palo ea liphoso tsa CRC32.
8h0A CRC24 palo ea liphoso RO E bontša palo ea liphoso tsa CRC24.
e tsoela pele…
Offset Lebitso Phihlello Tlhaloso
8h0b Reserved
8h0C palo ea SOP RO E bontša palo ea SOP.
8'h0D palo ea EOP RO E bontša palo ea EOP
 

 

8h0E

  

 

Palo ea liphoso

  

 

RO

 E bontša palo ea liphoso tse latelang:

• Ho lahleheloa ke tsela ea tsela

• Lentsoe la taolo e seng molaong

• Paterone e seng molaong ea ho etsa liforeimi

• SOP kapa EOP sesupa se sieo
8'h0F send_data_mm_clk RW Ngola 1 ho bit [0] ho nolofalletsa lets'oao la jenereithara.
 

8h10

  

Phoso ea ho hlahloba

  

RO

 E bontša phoso ea ho hlahloba. (Phoso ea data ea SOP, phoso ea nomoro ea Channel, le phoso ea data ea PLD)
8h11 Sistimi PLL senotlolo RO Bit [0] e supa sesupo sa senotlolo sa PLL.
8h13 Palo ea morao RO E bontša palo ea latency.
 

8h14

  

TX SOP palo

  

RO

 E bontša palo ea SOP e hlahisoang ke jenereithara ea pakete.
 

8h15

  

TX EOP palo

  

RO

 E bontša palo ea EOP e hlahisoang ke jenereithara ea pakete.
8h16 Phakete e tsoelang pele RO Ngola ho tloha ho 1 ho isa ho [0] ho nolofalletsa pakete e tsoelang pele.
8h17 TX le RX counter li lekana RW E bontša hore TX le RX counter lia lekana.
8h23 Numella latency WO Ngola 1 ho isa ho biti [0] ho nolofalletsa tekanyo ea latency.
8h24 Latency loketse RO E bontša hore latency methatso e se e loketse.

Interlaken (Moloko oa Bobeli) Intel Agilex 2 FPGA IP Design Example User Guide Archives

  • Bakeng sa liphetolelo tsa morao-rao le tse fetileng tsa bukana ena ea basebelisi, sheba Interlaken (2nd
  • Moloko) Intel Agilex 7 FPGA IP Design Example Buka ea Mosebelisi HTML version. Khetha mofuta ebe o tobetsa Download. Haeba IP kapa mofuta oa software o sa thathamisoa, ho sebetsa tataiso ea mosebelisi bakeng sa IP e fetileng kapa mofuta oa software.
  • Liphetolelo tsa IP li tšoana le mefuta ea software ea Intel Quartus Prime Design Suite ho fihla ho v19.1. Ho tsoa ho Intel Quartus Prime Design Suite software version 19.2 kapa hamorao, li-cores tsa IP li na le morero o mocha oa phetolelo ea IP.

Nalane ea Tokomane ea Tokomane bakeng sa Interlaken (Moloko oa Bobeli) Intel Agilex 2 FPGA IP Design Example Bukana ea Mosebelisi

Tokomane Version Intel Quartus Prime Version IP Version Liphetoho
2023.06.26 23.2 21.1.1 • Ts'ehetso ea VHDL e ekelitsoeng bakeng sa motsoako le mohlala oa ketsiso.

• Ho ntlafatsa lebitso la lelapa la sehlahisoa ho "Intel Agilex 7".
2022.08.03 21.3 20.0.1 E lokisitse sesebelisoa sa OPN bakeng sa Intel Agilex F-Series Transceiver-SoC Development Kit.
2021.10.04 21.3 20.0.1 • Tšehetso e ekelitsoeng bakeng sa simulator ea QuestaSim.

• Tšehetso e tlositsoeng bakeng sa simulator ea NCSim.
2021.02.24 20.4 20.0.1 • Lintlha tse ling mabapi le ho boloka mocha oa transceiver o sa sebelisoang bakeng sa PAM4 karolong: Moqapi oa lisebelisoa tsa thepa Example Likarolo.

• E kentse tlhaloso ea lets'oao la pll_ref_clk[1] karolong: Lipontšo tsa Interface.
2020.12.14 20.4 20.0.0 • E ntlafalitsoeng kample hardware test output for Interlaken mode le Interlaken Look-aside mode karolong Ho Lekola Moetso oa Hardware Example.

• 'Mapa o ntlafalitsoeng oa ngoliso bakeng sa moralo oa Interlaken Look-aside example karolong Ngolisa 'mapa.

• E kentse mokhoa oa ho feta bakeng sa teko ea hardware e atlehileng e etsoang karolong Ho Lekola Moetso oa Hardware Example.
2020.10.16 20.2 19.3.0 Taelo e lokisitsoeng ea ho tsamaisa mokhoa oa pele oa ho ikamahanya le maemo ka lehlakoreng la RX ho Ho Lekola Moetso oa Hardware Example karolo.
2020.06.22 20.2 19.3.0 • Moqapi mohlalaample e fumaneha bakeng sa mokhoa oa Interlaken Look-side.

• Ho hlahloba lisebelisoa tsa sebopeho sa example e fumaneha bakeng sa mefuta e fapaneng ea lisebelisoa tsa Intel Agilex.

• E kentsoe Setšoantšo: Setšoantšo se Phahameng sa Block Diagram bakeng sa Interlaken (Moloko oa 2) Moqapi Example.

• Likarolo tse latelang li ntlafalitsoe:

—   Litlhoko tsa Hardware le Software

—   Sebopeho sa Directory

• E fetotse lipalo tse latelang ho kenyelletsa lintlha tse amanang le Interlaken Look-aside:

—   Setšoantšo: Interlaken (2nd Generation) Hardware Design Example Setšoantšo sa Thibelo ea Boemo bo Phahameng bakeng sa Phapang ea Mokhoa oa E- tile NRZ

—   Setšoantšo: Interlaken (2nd Generation) Hardware Design Example Setšoantšo sa Block Level e Phahameng bakeng sa E- tile PAM4 Mode Variations

• E ntlafalitsoe Setšoantšo: IP Parameter Editor.
e tsoela pele…
Tokomane Version Intel Quartus Prime Version IP Version Liphetoho
      • Tlhahisoleseding e ekeditsweng mabapi le di-setting tsa maqhubu a tshebediso ya taolo ya watjhe karolong Ho Kopanya le ho Hlophisa Moralo Example ho Hardware.

• Liphetho tsa liteko tse kentsoeng bakeng sa Interlaken Look- kathoko likarolong tse latelang:

—   Ho Etsisa Moralo Example Testbench

—   Ho Lekola Moetso oa Hardware Example

• E kentse ho latela matshwao a matjha ho Lipontšo tsa Interface

karolo:

— mgmt_clk

— rx_pin_n

— tx_pin_n

— mac_clk_pll_ref

• Ekelitsoe 'mapa oa ngoliso bakeng sa moralo oa Interlaken Look-aside example ka karolo: Ngolisa 'mapa.
2019.09.30 19.3 19.2.1 E tlositsoe clk100. The mgmt_clk e sebetsa e le oache ea litšupiso ho IO PLL ka tse latelang:

•    Setšoantšo: Interlaken (2nd Generation) Hardware Design Example Setšoantšo sa Thibelo ea Boemo bo Phahameng bakeng sa Phapang ea Mokhoa oa E-tile NRZ.

•    Setšoantšo: Interlaken (2nd Generation) Hardware Design Example Setšoantšo se Phahameng sa Block Block bakeng sa E-tile PAM4 Mode Variations.
2019.07.01 19.2 19.2 Tokollo ea pele.

Interlaken (Moloko oa Bobeli) Intel Agilex® 2 FPGA IP Design Example Bukana ea Mosebelisi

Litokomane / Lisebelisoa

Intel Interlaken 2nd Generation Agilex 7 FPGA IP Design Example [pdf] Bukana ea Mosebelisi
Interlaken 2nd Generation Agilex 7 FPGA IP Design Example, Interlaken, 2nd Generation Agilex 7 FPGA IP Design Example, FPGA IP Design Example, IP Design Example, Moqapi Example

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