Cov ntsiab lus zais
1 Intel Interlaken 2nd Generation Agilex 7 FPGA IP Tsim Example
2 Cov ntaub ntawv khoom
3 Cov lus qhia siv khoom
4 Phau Ntawv Qhia Pib Ceev
5 Hardware thiab Software
6 Cov ntaub ntawv ntsig txog
7 Tsim Examplus piav qhia
8 Cov ntaub ntawv / Cov ntaub ntawv
8.1 Cov ntaub ntawv

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Intel Interlaken 2nd Generation Agilex 7 FPGA IP Tsim Example

Intel-Interlaken-2nd-Generation-Agilex-7-FPGA-IP-Design-Example-product

Cov ntaub ntawv khoom

Interlaken (2nd Generation) FPGA IP core yog ib qho ntawm Intel Agilex 7 FPGA. Nws muab lub simulation testbench thiab kho vajtse tsim example uas txhawb kev muab tso ua ke thiab kev sim kho vajtse. Design example kuj muaj rau Interlaken Look-aside feature. Cov tub ntxhais IP txhawb nqa NRZ thiab PAM4 hom rau E-tile li thiab tsim qauv tsim examples rau txhua qhov kev txhawb nqa ua ke ntawm cov kab thiab cov ntaub ntawv tus nqi.

Hardware thiab Software Requirements
Lub Interlaken (2nd Generation) IP core tsim example xav tau Intel Agilex 7 F-Series Transceiver-SoC Development Kit. Thov xa mus rau Tus Neeg Siv Qhia ntawm cov khoom siv txhim kho kom paub ntau ntxiv.

Directory Structure
Lub generated Interlaken (2nd Generation) example design suav nrog cov npe hauv qab no:

  • example_design: Muaj lub ntsiab files rau tus tsim example.
  • ilk_uflex: Muaj files ntsig txog Interlaken Look-aside hom kev xaiv.
  • ila_uflex: Muaj files ntsig txog Interlaken Look-aside hom kev xaiv (tsim tsuas yog thaum xaiv).

Cov lus qhia siv khoom

Txhawm rau siv Interlaken (2nd Generation) FPGA IP core tsim example, ua raws li cov kauj ruam no:

  1. Xyuas kom koj muaj Intel Agilex 7 F-Series Transceiver-SoC Development Kit.
  2. Compile tus tsim exampsiv lub simulator.
  3. Ua haujlwm simulation los xyuas qhov tsim.
  4. Tsim tus tsim example siv parameter editor.
  5. Compile tus tsim exampsiv Quartus Prime.
  6. Ua qhov kev sim kho vajtse kom paub tseeb tias tus qauv tsim.

Nco tseg: Interlaken Look-aside hom kev xaiv muaj rau xaiv hauv IP parameter editor. Yog xaiv, ntxiv files yuav raug tsim nyob rau hauv "ila_uflex" directory.

Phau Ntawv Qhia Pib Ceev

  • Lub Interlaken (2nd Generation) FPGA IP core muab lub simulation testbench thiab kho vajtse tsim example uas txhawb kev muab tso ua ke thiab kev sim kho vajtse.
  • Thaum koj tsim tus tsim example, parameter editor cia li tsim cov files yuav tsum simulate, compile, thiab sim tus tsim nyob rau hauv hardware.
  • Design example kuj muaj rau Interlaken Look-aside feature.
  • The testbench thiab design example txhawb NRZ thiab PAM4 hom rau E-tile li.
  • Lub Interlaken (2nd Generation) FPGA IP core generates tsim examples rau txhua qhov kev txhawb nqa ua ke ntawm cov kab thiab cov ntaub ntawv tus nqi.

Daim duab 1. Cov kauj ruam txhim kho rau Kev Tsim ExampleIntel-Interlaken-2nd-Generation-Agilex-7-FPGA-IP-Design-Example-fig-1 (1)

Lub Interlaken (2nd Generation) IP core tsim example txhawb cov yam ntxwv hauv qab no:

  • Internal TX to RX serial loopback mode
  • Tsis siv neeg tsim cov pob ntawv loj tas li
  • Basic packet checking peev xwm
  • Muaj peev xwm siv System Console los pib dua tus qauv tsim rau rov sim dua lub hom phiaj
  • Kev hloov pauv ntawm PMA

Intel Corporation. Txhua txoj cai. Intel, Intel logo, thiab lwm yam Intel cov cim yog cov cim lag luam ntawm Intel Corporation lossis nws cov koom haum. Intel lav kev ua tau zoo ntawm nws cov FPGA thiab cov khoom lag luam semiconductor rau cov kev qhia tshwj xeeb tam sim no raws li Intel tus qauv kev lees paub, tab sis muaj txoj cai los hloov cov khoom thiab cov kev pabcuam txhua lub sijhawm yam tsis muaj ntawv ceeb toom. Intel xav tias tsis muaj lub luag haujlwm lossis kev lav phib xaub uas tshwm sim los ntawm daim ntawv thov lossis siv cov ntaub ntawv, cov khoom lag luam, lossis cov kev pabcuam uas tau piav qhia hauv no tshwj tsis yog raws li tau pom zoo hauv kev sau ntawv los ntawm Intel. Intel cov neeg siv khoom tau qhia kom tau txais qhov tseeb version ntawm cov cuab yeej tshwj xeeb ua ntej tso siab rau cov ntaub ntawv tshaj tawm thiab ua ntej muab xaj rau cov khoom lossis cov kev pabcuam. * Lwm lub npe thiab hom yuav raug lees paub raws li cov cuab yeej ntawm lwm tus.

Daim duab 2. High-level Block Diagram for Interlaken (2nd Generation) Tsim Example

Cov ntaub ntawv ntsig txog

  • Interlaken (2nd Generation) FPGA IP Tus Neeg Siv Qhia
  • Interlaken (2nd Generation) Intel FPGA IP Tso Lus Sau

Hardware thiab Software

Hardware thiab Software Requirements
Mus kuaj tus example tsim, siv hardware thiab software hauv qab no:

  • Intel® Quartus® Prime Pro Edition software
  • System Console
  • Txhawb nqa simulators:
    • Siemens* EDA ModelSim* SE or QuestaSim*
    • Synopsys* VCS*
    • Cadence * Xcelium *
  • Intel Agilex® 7 F-Series Transceiver-SoC Development Kit (AGFB014R24A2E2V)

Cov ntaub ntawv ntsig txog
Intel Agilex 7 F-Series Transceiver-SoC Kev Tsim Kho Cov Khoom Siv Qhia
Directory Structure
Lub Interlaken (2nd Generation) IP core tsim example file directory muaj cov nram qab no generated files rau tus tsim example.

Daim duab 3. Directory Structure ntawm Generated Interlaken (2nd Generation) ExamptsimIntel-Interlaken-2nd-Generation-Agilex-7-FPGA-IP-Design-Example-fig-1 (3)

Kho vajtse configuration, simulation, thiab kuaj files yog nyob rau hauvample_installation_dir>/uflex_ilk_0_example_design.
Table 1. Interlaken (2nd Generation) IP Core Hardware Design Example File Cov lus piav qhia Cov files yog inample_installation_dir>/uflex_ilk_0_example_design/example_design/quartus directory.

File Cov npe Kev piav qhia
example_design.qpf Qhov project Intel Quartus Prime file.
example_design.qsf Intel Quartus Prime qhov project nqis file
example_design.sdc jtag_timeing_template.sdc Synopsys Design Constraint file. Koj tuaj yeem luam thiab hloov kho rau koj tus kheej tsim.
sysconsole_testbench.tcl Main file rau kev nkag mus rau System Console

Table 2. Interlaken (2nd Generation) IP Core Testbench File Kev piav qhia
Qhov no file yog nyob rau hauvample_installation_dir>/uflex_ilk_0_example_design/example_design/rtl directory.

File Lub npe Kev piav qhia
top_tb.sv Sab saum toj-theem testbench file.

Table 3. Interlaken (2nd Generation) IP Core Testbench Scripts
Cov no files yog inample_installation_dir>/uflex_ilk_0_example_design/example_design/testbench directory.

File Lub npe Kev piav qhia
vcstest.sh ua VCS tsab ntawv los khiav lub testbench.
vlog_pro.do ModelSim SE los yog QuestaSim tsab ntawv los khiav lub testbench.
xcelium.sh Xcelium tsab ntawv los khiav lub testbench.

Hardware Design Exampcov Components

  • Cov example tsim txuas qhov system thiab PLL siv moos thiab cov khoom tsim tsim. Cov example tsim configures tus IP core nyob rau hauv internal loopback hom thiab generates packets ntawm tus IP core TX cov neeg siv cov ntaub ntawv hloov lwm lub tsev interface. IP tub ntxhais xa cov pob ntawv no rau ntawm txoj hauv kev rov qab los ntawm lub transceiver.
  • Tom qab tus IP core receiver tau txais cov pob ntawv ntawm txoj kev rov qab, nws ua cov txheej txheem
  • Interlaken pob ntawv thiab xa lawv ntawm RX tus neeg siv cov ntaub ntawv hloov chaw. Cov example tsim kuaj xyuas tias cov pob ntawv tau txais thiab kis sib tw.
  • Hardware example tsim suav nrog PLLs sab nraud. Koj tuaj yeem tshuaj xyuas cov ntawv ntshiab files rau view sample code uas siv ib txoj hauv kev los txuas cov PLLs sab nraud rau Interlaken (2nd Generation) FPGA IP.
  • Lub Interlaken (2nd Generation) kho vajtse tsim example suav nrog cov hauv qab no:
    • Interlaken (2nd Generation) FPGA IP
    • Packet Generator thiab Packet Checker
    • JTAG controller uas sib txuas lus nrog System Console. Koj sib txuas lus nrog tus neeg siv khoom logic los ntawm System Console.

Daim duab 4. Interlaken (2nd Generation) Kho vajtse Tsim Example High Level Block Diagram for E-tile NRZ Mode VariationsIntel-Interlaken-2nd-Generation-Agilex-7-FPGA-IP-Design-Example-fig-1 (4)

Lub Interlaken (2nd Generation) kho vajtse tsim example uas lub hom phiaj E-tile PAM4 kev hloov pauv yuav tsum muaj lub moos ntxiv mac_clkin uas IO PLL tsim. PLL no yuav tsum siv tib lub moos siv uas tsav lub pll_ref_clk.
Daim duab 5. Interlaken (2nd Generation) Kho vajtse Tsim Example High Level Block Diagram rau E-tile PAM4 Hom VariationsIntel-Interlaken-2nd-Generation-Agilex-7-FPGA-IP-Design-Example-fig-1 (5)

Rau E-tile PAM4 hom variations, thaum koj pab kom txuag tsis tau siv transceiver raws rau PAM4 parameter, ib qho ntxiv siv moos chaw nres nkoj ntxiv (pll_ref_clk [1]). Qhov chaw nres nkoj no yuav tsum tau tsav ntawm tib zaus raws li tau hais tseg hauv IP parameter editor (Riv sijhawm moos zaus rau cov channel khaws cia). Lub Txuag tsis siv cov transceiver raws rau PAM4 yog xaiv tau. Tus pin thiab lwm yam kev txwv uas tau muab rau lub moos no yog pom hauv QSF thaum koj xaiv Intel Stratix® 10 lossis Intel Agilex 7 cov khoom siv txhim kho rau kev tsim tsim.
Nco tseg: Rau tsim example simulation, lub testbench ib txwm txhais tib zaus rau pll_ref_clk[0] thiab pll_ref_clk[1].
Cov ntaub ntawv ntsig txog
Intel Agilex 7 F-Series Transceiver-SoC Kev Tsim Kho Cov Khoom Siv Qhia

Tsim tus Tsim
Daim duab 6. Txheej txheemIntel-Interlaken-2nd-Generation-Agilex-7-FPGA-IP-Design-Example-fig-1 (6)

Ua raws li cov kauj ruam no los tsim kho hardware example design thiab testbench:

  1. Hauv Intel Quartus Prime Pro Edition software, nyem File ➤ New Project Wizard los tsim ib txoj haujlwm tshiab Intel Quartus Prime, lossis nyem File ➤ Qhib Project qhib qhov project Intel Quartus Prime uas twb muaj lawm. Tus wizard qhia koj kom qhia meej lub cuab yeej.
  2. Qhia cov cuab yeej cuab tam tsev neeg Intel Agilex 7 thiab xaiv cov cuab yeej rau koj tsim.
  3. Hauv IP Catalog, nrhiav thiab nyem ob npaug rau Interlaken (2nd Generation) Intel FPGA IP. Lub qhov rais tshiab IP Variant tshwm.
  4. Qhia lub npe saum toj kawg nkaus rau koj tus IP kev hloov pauv. Tus parameter editor txuag tus IP variation nqis hauv a file npe .ip ib.
  5. Nyem OK. Cov parameter editor tshwm.
    Daim duab 7. Example Tsim Tab hauv Interlaken (2nd Generation) Intel FPGA IP Parameter EditorIntel-Interlaken-2nd-Generation-Agilex-7-FPGA-IP-Design-Example-fig-1 (7)
  6. Ntawm tus IP tab, qhia qhov tsis muaj rau koj tus IP qhov hloov pauv.
  7. Ntawm PMA Adaptation tab, qhia cov PMA adaptation tsis yog tias koj npaj yuav siv PMA hloov kho rau koj cov khoom siv E-tile variations. Cov kauj ruam no yog xaiv tau:
    • Xaiv Pab kom yoog tau yooj yim thauj khoom IP xaiv.
    • Nco tseg: Koj yuav tsum ua kom Native PHY Debug Master Endpoint (NPDME) kev xaiv ntawm IP tab thaum PMA hloov pauv tau qhib.
    • Xaiv ib PMA adaptation preset rau PMA adaptation Xaiv parameter.
    • Nyem PMA Adaptation Preload kom thauj khoom pib thiab tsis tu ncua hloov pauv.
    • Qhia tus naj npawb ntawm PMA configurations los txhawb thaum ntau PMA configurations enabled siv Number of PMA configuration parameter.
    • Xaiv qhov PMA configuration rau thauj lossis khaws cia siv Xaiv PMA teeb tsa los thauj lossis khaws cia.
    • Nyem Load adaptation los ntawm xaiv PMA configuration mus thauj cov xaiv PMA configuration chaw.
    • Yog xav paub ntxiv txog PMA adaptation parameters, xa mus rau E-tile
      Transceiver PHY Phau Ntawv Qhia.
  8. Hauv Example Tsim tab, xaiv qhov kev xaiv Simulation los tsim cov testbench, thiab xaiv qhov kev xaiv Synthesis los tsim cov khoom kho vajtse example design.
    • Nco tseg: Koj yuav tsum xaiv yam tsawg kawg yog ib qho ntawm Simulation lossis Synthesis xaiv tsim kom muaj Examptsim Files.
  9. Rau Generated HDL hom, xaiv Verilog lossis VHDL.
  10. Rau Cov Khoom Siv Lub Hom Phiaj Xaiv qhov kev xaiv tsim nyog.
    • Nco tseg: Qhov kev xaiv Intel Agilex 7 F-Series Transceiver SoC Development Kit tsuas yog muaj thaum koj qhov project qhia Intel Agilex 7 ntaus ntawv npe pib nrog AGFA012 lossis AGFA014. Thaum koj xaiv qhov kev xaiv Cov Khoom Siv Tsim Kho, cov haujlwm tus pin tau teeb tsa raws li Intel Agilex 7 Cov Khoom Siv Txhim Kho Cov Khoom Siv Khoom Siv Ib feem ntawm AGFB014R24A2E2V thiab yuav txawv ntawm koj lub cuab yeej xaiv. Yog tias koj npaj siab yuav sim tus qauv tsim ntawm kho vajtse ntawm PCB sib txawv, xaiv qhov tsis muaj kev xaiv thiab ua tus pin tsim nyog hauv .qsf file.
  11. Nyem Tsim Example Design. Xaiv Example Design Directory window tshwm.
  12. Yog tias koj xav hloov kho tus tsim example directory path or name from the defaults displayed (uflex_ilk_0_example_design), xauj rau txoj hauv kev tshiab thiab ntaus tus qauv tshiab exampnpe directory.
  13. Nyem OK.

Cov ntaub ntawv ntsig txog

  • Intel Agilex 7 F-Series Transceiver-SoC Kev Tsim Kho Cov Khoom Siv Qhia
  • E-tile Transceiver PHY Phau Ntawv Qhia

Simulating Design Exampua Testbench
Xa mus rau Interlaken (2nd Generation) Hardware Design Example High Level Block rau E-tile NRZ Hom Variations thiab Interlaken (2nd Generation) Hardware Design Example High Level Block rau E-tile PAM4 Hom Variations thaiv daim duab ntawm lub simulation testbench.
Daim duab 8. Txheej txheemIntel-Interlaken-2nd-Generation-Agilex-7-FPGA-IP-Design-Example-fig-1 (8)

Ua raws li cov kauj ruam no los simulate lub testbench:

  1. Ntawm qhov kev hais kom ua, hloov mus rau testbench simulation directory. Phau ntawv yogample_installation_dir>/example_design/testbench rau Intel Agilex 7 li.
  2. Khiav cov ntawv simulation rau qhov kev txhawb nqa simulator ntawm koj xaiv. Cov ntawv sau ua ke thiab khiav lub testbench hauv lub simulator. Koj tsab ntawv yuav tsum kuaj xyuas tias SOP thiab EOP suav qhov sib tw tom qab simulation tiav. Xa mus rau lub rooj Cov kauj ruam los khiav Simulation.

Table 4. Cov kauj ruam los khiav Simulation

Simulator Cov lus qhia
ModelSim SE or QuestaSim Hauv kab hais kom ua, ntaus -do vlog_pro.do

Yog tias koj xav simulate yam tsis tau nqa ModelSim GUI, ntaus vsim -c -do vlog_pro.do
VCS Hauv kab hais kom ua, ntaus sh vcstest.sh
Xcelium Hauv kab hais kom ua, ntaus sh xcelium.sh

Txheeb xyuas cov txiaj ntsig. Kev simulation ua tiav xa thiab tau txais pob ntawv, thiab qhia tias "Test PASSED".
Testbench rau tus tsim example ua tiav cov haujlwm hauv qab no:

  • Instantiates lub Interlaken (2nd Generation) Intel FPGA IP.
  • Luam tawm PHY xwm txheej.
  • Tshawb xyuas metaframe synchronization (SYNC_LOCK) thiab lo lus (block) ciam teb (WORD_LOCK).
  • Tos rau tus kheej txoj kab yuav raug kaw thiab ua kom haum.
  • Pib kis pob ntawv.
  • Tshawb xyuas pob ntawv txheeb cais:
    • CRC24 yuam kev
    • SOPs
    • EOPs

Cov nram qab no sample cov zis qhia txog qhov kev simulation ua tau zoo khiav hauv Interlaken hom:Intel-Interlaken-2nd-Generation-Agilex-7-FPGA-IP-Design-Example-fig-1 (9)Intel-Interlaken-2nd-Generation-Agilex-7-FPGA-IP-Design-Example-fig-1 (10)

Nco tseg: Interlaken tsim example simulation testbench xa 100 pob ntawv thiab tau txais 100 pob ntawv. Cov nram qab no sample cov zis qhia txog qhov kev simulation ua tau zoo khiav hauv Interlaken Look-aside hom:Intel-Interlaken-2nd-Generation-Agilex-7-FPGA-IP-Design-Example-fig-1 (11)

Nco tseg: Tus naj npawb ntawm pob ntawv (SOPs thiab EOPs) txawv ntawm ib txoj kab hauv Interlaken Lookaside tsim example simulation sample output.
Cov ntaub ntawv ntsig txog
Hardware Design Example Cheebtsam ntawm nplooj 6

Compiling thiab Configuring Design Examphauv Hardware
Daim duab 9. Txheej txheemIntel-Interlaken-2nd-Generation-Agilex-7-FPGA-IP-Design-Example-fig-1 (12)

Txhawm rau sau thiab khiav qhov kev sim ua qauv qhia ntawm lub hardware example design, ua raws li cov kauj ruam no:

  1. Xyuas kom hardware example tsim tiam ua tiav.
  2. Hauv Intel Quartus Prime Pro Edition software, qhib Intel Quartus Prime projectample_installation_dir>/example_design/quartus/ example_design.qpf>.
  3. Nyob rau hauv cov ntawv qhia zaub mov, nyem Start Compilation.
  4. Tom qab kev ua tiav tiav, a .sof file muaj nyob rau hauv koj daim ntawv teev npe. Ua raws li cov kauj ruam no rau kev pab cuam hardware example tsim ntawm Intel Agilex 7 ntaus ntawv:
    • ib. Txuas Intel Agilex 7 F-Series Transceiver-SoC Development Kit rau lub khoos phis tawj.
    • b. Tua tawm daim ntawv thov Clock Control, uas yog ib feem ntawm cov khoom siv txhim kho, thiab teeb tsa cov zaus tshiab rau tus tsim example. Hauv qab no yog qhov kev teeb tsa zaus hauv daim ntawv thov Clock Control:
    • • Si5338 (U37), CLK1- 100 MHz
    • • Si5338 (U36), CLK2- 153.6 MHz
    • • Si549 (Y2), OUT- Teem rau tus nqi ntawm pll_ref_clk(1) raws li qhov koj xav tau tsim.
    • c. Hauv cov cuab yeej ntawv qhia zaub mov, nyem Programmer.
    • d. Hauv Programmer, nyem Hardware Setup.
    • e. Xaiv ib lub programming ntaus ntawv.
    • f. Xaiv thiab ntxiv Intel Agilex 7 F-Series Transceiver-SoC Development Kit uas koj lub Intel Quartus Prime kev sib tham tuaj yeem txuas tau.
    • g. Xyuas kom meej tias hom yog teem rau JTAG.
    • h. Xaiv Intel Agilex 7 ntaus ntawv thiab nyem Ntxiv Ntaus. Tus Programmer qhia ib daim duab thaiv ntawm kev sib txuas ntawm cov khoom siv ntawm koj lub rooj tsavxwm.
    • i. Hauv kab nrog koj .sof, kos lub thawv rau .sof.
    • j. Kos lub npov nyob rau hauv Program/Configure kem.
    • k. Nyem Pib.

Cov ntaub ntawv ntsig txog

  • Programming Intel FPGA Devices ntawm nplooj ntawv 0
  • Txheeb xyuas thiab Debugging Designs nrog System Console
  • Intel Agilex 7 F-Series Transceiver-SoC Kev Tsim Kho Cov Khoom Siv Qhia

Testing Hardware Design Example
Tom qab koj suav nrog Interlaken (2nd Generation) Intel FPGA IP core tsim example thiab teeb tsa koj lub cuab yeej, koj tuaj yeem siv System Console los ua qhov kev pab cuam IP core thiab nws cov Native PHY IP core registers.

Ua raws li cov kauj ruam no coj mus rau System Console thiab sim kho vajtse tsim example:

  1. Hauv Intel Quartus Prime Pro Edition software, ntawm cov cuab yeej ntawv qhia zaub mov, nyem System Debugging Tools ➤ System Console.
  2. Hloov mus rauample_installation_dir>example_design/ hwtest directory.
  3. Txhawm rau qhib kev sib txuas rau JTAG tswv, ntaus cov lus txib nram qab no: qhov chaw sysconsole_testbench.tcl
  4. Koj tuaj yeem tig rau sab hauv serial loopback hom nrog cov qauv hauv qab no examplus txib:
    • a. stat: Sau cov ntaub ntawv xwm txheej dav dav.
    • b. sys_reset: Rov pib dua qhov system.
    • c. loop_on: Tig rau sab hauv serial loopback.
    • d. run_example_design: Khiav tus tsim example.
    • Nco tseg: Koj yuav tsum khiav loop_on hais kom ua ua ntej run_example_design lus. The run_example_design khiav cov lus txib hauv qab no hauv ib ntu: sys_reset->stat-> gen_on-> stat-> gen_off.
    • Nco tseg: Thaum koj xaiv Enable adaptation load soft IP xaiv, run_example_design hais kom ua ua qhov kev hloov pauv thawj zaug ntawm RX sab los ntawm kev khiav cov lus txib run_load_PMA_configuration.
  5. Koj tuaj yeem tua lub serial loopback hom nrog cov qauv hauv qab no examplus command:
    • ib. loop_off: Tig tawm sab hauv serial loopback.
  6. Koj tuaj yeem ua tus txheej txheem IP core nrog rau cov qauv hauv qab no ntxiv examplus txib:
    • ib. gen_on: Enables packet generator.
    • b. gen_off: Disables packet generator.
    • c. run_test_loop: Khiav qhov kev xeem rau lub sij hawm rau E-tile NRZ thiab PAM4 variations.
    • d. clear_err: Clears tag nrho cov nplaum yuam kev me ntsis.
    • e. set_test_mode : Teeb tsa kev xeem kom khiav hauv ib hom tshwj xeeb.
    • f. get_test_mode: Sau hom kev sim tam sim no.
    • g. set_burst_size : Teem tawg loj hauv bytes.
    • h. get_burst_size: Sau cov ntaub ntawv tawg loj.

Qhov kev xeem ua tiav luam tawm HW_TEST:PASS lus. Hauv qab no yog cov txheej txheem dhau mus rau kev xeem khiav:

  • Tsis muaj qhov yuam kev rau CRC32, CRC24, thiab checker.
  • Kev xa tawm SOPs thiab EOPs yuav tsum sib phim nrog tau txais.

Cov nram qab no sample cov zis qhia txog qhov kev sim ua tiav hauv Interlaken hom:Intel-Interlaken-2nd-Generation-Agilex-7-FPGA-IP-Design-Example-fig-1 (13)

Qhov kev xeem ua tiav luam tawm HW_TEST : PASS lus. Hauv qab no yog cov txheej txheem dhau mus rau kev xeem khiav:

  • Tsis muaj qhov yuam kev rau CRC32, CRC24, thiab checker.
  • Kev xa tawm SOPs thiab EOPs yuav tsum sib phim nrog tau txais.

Cov nram qab no sample cov zis qhia txog qhov kev sim ua tiav hauv Interlaken Lookaside hom:Intel-Interlaken-2nd-Generation-Agilex-7-FPGA-IP-Design-Example-fig-1 (14)Intel-Interlaken-2nd-Generation-Agilex-7-FPGA-IP-Design-Example-fig-1 (15)

Tsim Examplus piav qhia

Design example qhia txog kev ua haujlwm ntawm Interlaken IP core.

Cov ntaub ntawv ntsig txog
Interlaken (2nd Generation) FPGA IP Tus Neeg Siv Qhia

Tsim Example Behavior
Txhawm rau kuaj tus qauv tsim hauv kho vajtse, ntaus cov lus txib hauv qab no hauv System Console::

  1. Tau qhov kev teeb tsa file:
    • % qhov chawample>uflex_ilk_0_example_design/example_design/hwtest/ sysconsole_testbench.tcl
  2. Khiav qhov kev xeem:
    • % run_example_design
  3. Lub Interlaken (2nd Generation) kho vajtse tsim example ua kom tiav cov kauj ruam hauv qab no:
    • a. Rov pib dua Interlaken (2nd Generation) IP.
    • b. Configures Interlaken (2nd Generation) IP nyob rau hauv hom loopback.
    • c. Xa cov kwj ntawm Interlaken pob ntawv nrog cov ntaub ntawv teev tseg ua ntej hauv kev them nyiaj rau TX tus neeg siv cov ntaub ntawv hloov chaw ntawm IP core.
    • d. Xyuas cov pob ntawv tau txais thiab qhia txog xwm txheej. Cov pob ntawv checker suav nrog hauv kev tsim kho vajtse example muab cov peev txheej hauv qab no kuaj pob ntawv:
      • Txheeb xyuas tias cov pob ntawv sib kis tau raug lawm.
      • Txheeb xyuas tias cov ntaub ntawv tau txais sib phim cov txiaj ntsig xav tau los ntawm kev ua kom ntseeg tau tias ob qho tib si pib ntawm pob ntawv (SOP) thiab qhov kawg ntawm pob ntawv (EOP) suav nrog thaum cov ntaub ntawv raug xa mus thiab tau txais.

Interface Signals
Table 5. Tsim Example Interface Signals

Chaw nres nkoj npe Kev taw qhia Dav (ntsis) Kev piav qhia
 

mgmt_clk

  

Tswv yim

  

1

 System moos input. Lub moos zaus yuav tsum yog 100 MHz.
pll_ref_clk /

npl_ref_clk[1:0](2)

  

Tswv yim

  

1/2

 Transceiver siv moos. Tsav RX CDR PLL.
txuas ntxiv…
Chaw nres nkoj npe Kev taw qhia Dav (ntsis) Kev piav qhia
      pll_ref_clk[1] tsuas yog muaj thaum koj qhib Khaws cia tsis siv

Nco tseg: Transceiver channel rau PAM4 parameter hauv E-tile PAM4 hom IP variations.
rx_pin Tswv yim Tus lej ntawm txoj kab Tus neeg txais SERDES cov ntaub ntawv tus pin.
tx_pin Tso zis Tus lej ntawm txoj kab Hloov SERDES cov ntaub ntawv tus pin.
 

rx_pin_n

  

Tswv yim

  

Tus lej ntawm txoj kab

 Tus neeg txais SERDES cov ntaub ntawv tus pin.

Cov teeb liab no tsuas yog muaj nyob rau hauv E-tile PAM4 hom ntaus ntawv hloov pauv.
 

tx_pin_n

  

Tso zis

  

Tus lej ntawm txoj kab

 Hloov SERDES cov ntaub ntawv tus pin.

Cov teeb liab no tsuas yog muaj nyob rau hauv E-tile PAM4 hom ntaus ntawv hloov pauv.
 

 

mac_clk_pl_ref

  

 

Tswv yim

  

 

1

 Cov teeb liab no yuav tsum tau tsav los ntawm PLL thiab yuav tsum siv tib lub moos uas tsav lub pll_ref_clk.

Cov teeb liab no tsuas yog muaj nyob rau hauv E-tile PAM4 hom ntaus ntawv hloov pauv.
usr_pb_reset_n Tswv yim 1 Qhov system pib dua.

Cov ntaub ntawv ntsig txog
Interface Signals

Sau npe daim ntawv qhia
Nco tseg: • Tsim Example sau npe chaw nyob pib nrog 0x20** thaum Interlaken IP core register chaw nyob pib nrog 0x10**.

  • Nkag mus rau code: RO—Nyeem nkaus xwb, thiab RW—Nyeem/Sau.
  • System console nyeem tus tsim example sau npe thiab tshaj tawm cov xwm txheej xeem ntawm qhov screen.

Table 6. Tsim Example Register Map for Interlaken Design Example

Offset Lub npe Nkag mus Kev piav qhia
8h00 ua Khaws tseg
8h01 ua Khaws tseg
 

 

8h02 ua

  

 

System PLL rov pib dua

  

 

RO

 Cov khoom nram qab no qhia txog qhov system PLL rov pib thov thiab pab tus nqi:

• Bit [0] – sys_pll_rst_req

• ntsis [1] – sys_pll_rst_en
8h03 ua RX txoj kab aligned RO Qhia txog RX txoj kab sib dhos.
 

8h04 ua

  

Lo lus xauv

  

RO

 [NUM_LANES–1:0] – Lo lus (block) ciam teb kev txheeb xyuas.
txuas ntxiv…

Thaum koj tso cai rau khaws cia tsis siv cov transceiver raws rau PAM4 parameter, ib qho ntxiv siv moos chaw nres nkoj ntxiv los khaws cov PAM4 qhev channel tsis siv.

Offset Lub npe Nkag mus Kev piav qhia
8h05 ua Sync xauv RO [NUM_LANES–1:0] – Metaframe synchronization.
8-06 Nws CRC32 yuam kev suav RO Qhia txog CRC32 yuam kev suav.
8h0 ua CRC24 yuam kev suav RO Qhia txog CRC24 yuam kev suav.
 

 

8h0 ib

  

 

Overflow / Underflow teeb liab

  

 

RO

 Cov nram qab no qhia tias:

• Ntsis [3] – TX underflow signal

• Ntsis [2] – TX overflow signal

• Ntsis [1] – RX overflow teeb liab
8h0c ua SOP suav RO Qhia tus naj npawb ntawm SOP.
8h0d ua EOP suav RO Qhia tus naj npawb ntawm EOP
 

 

8 h0e

  

 

yuam kev suav

  

 

RO

 Qhia tus lej ntawm qhov yuam kev hauv qab no:

• Poob txoj kab sib dhos

• Lo lus tswj tsis raug cai

• Tsis raug cai framing qauv

• Qhov taw qhia SOP lossis EOP ploj lawm
8h0f ua xa_data_mm_clk RW Sau 1 mus rau me ntsis [0] los pab kom lub tshuab hluav taws xob teeb liab.
 

8h10 ua

  

Checker yuam kev

   Qhia tus checker yuam kev. (SOP cov ntaub ntawv yuam kev, Channel tus lej yuam kev, thiab PLD cov ntaub ntawv yuam kev)
8h11 ua System PLL xauv RO Bit [0] qhia PLL ntsuas phoo.
 

8h14 ua

  

TX SOP count

  

RO

 Qhia txog tus naj npawb ntawm SOP tsim los ntawm pob ntawv tshuab hluav taws xob.
 

8h15 ua

  

TX EOP count

  

RO

 Qhia txog tus naj npawb ntawm EOP tsim los ntawm pob khoom siv hluav taws xob.
8h16 ua Pob ntawv txuas ntxiv RW Sau 1 mus rau me ntsis [0] kom pab tau cov pob ntawv txuas ntxiv.
8h39 ua ECC yuam kev suav RO Qhia tus lej ntawm ECC yuam kev.
8h40 ua ECC kho qhov yuam kev suav RO Qhia txog tus lej ntawm kev kho ECC qhov yuam kev.

Tsim Example Register Map for Interlaken Look-aside Design Example
Siv daim ntawv teev npe no thaum koj tsim tus tsim example nrog Enable Interlaken Look-aside mode parameter qhib.

Offset Lub npe Nkag mus Kev piav qhia
8h00 ua Khaws tseg
8h01 ua Rov pib dua RO Sau 1 rau ntsis [0] kom tshem TX thiab RX txee sib npaug me ntsis.
 

 

8h02 ua

  

 

System PLL rov pib dua

  

 

RO

 Cov khoom nram qab no qhia txog qhov system PLL rov pib thov thiab pab tus nqi:

• Bit [0] – sys_pll_rst_req

• ntsis [1] – sys_pll_rst_en
8h03 ua RX txoj kab aligned RO Qhia txog RX txoj kab sib dhos.
 

8h04 ua

  

Lo lus xauv

  

RO

 [NUM_LANES–1:0] – Lo lus (block) ciam teb kev txheeb xyuas.
8h05 ua Sync xauv RO [NUM_LANES–1:0] – Metaframe synchronization.
8-06 Nws CRC32 yuam kev suav RO Qhia txog CRC32 yuam kev suav.
8h0 ua CRC24 yuam kev suav RO Qhia txog CRC24 yuam kev suav.
txuas ntxiv…
Offset Lub npe Nkag mus Kev piav qhia
8h0 ib Khaws tseg
8h0c ua SOP suav RO Qhia tus naj npawb ntawm SOP.
8h0d ua EOP suav RO Qhia tus naj npawb ntawm EOP
 

 

8 h0e

  

 

yuam kev suav

  

 

RO

 Qhia tus lej ntawm qhov yuam kev hauv qab no:

• Poob txoj kab sib dhos

• Lo lus tswj tsis raug cai

• Tsis raug cai framing qauv

• Qhov taw qhia SOP lossis EOP ploj lawm
8h0f ua xa_data_mm_clk RW Sau 1 mus rau me ntsis [0] los pab kom lub tshuab hluav taws xob teeb liab.
 

8h10 ua

  

Checker yuam kev

  

RO

 Qhia tus checker yuam kev. (SOP cov ntaub ntawv yuam kev, Channel tus lej yuam kev, thiab PLD cov ntaub ntawv yuam kev)
8h11 ua System PLL xauv RO Bit [0] qhia PLL ntsuas phoo.
8h13 ua Latency suav RO Qhia tus naj npawb ntawm latency.
 

8h14 ua

  

TX SOP count

  

RO

 Qhia txog tus naj npawb ntawm SOP tsim los ntawm pob ntawv tshuab hluav taws xob.
 

8h15 ua

  

TX EOP count

  

RO

 Qhia txog tus naj npawb ntawm EOP tsim los ntawm pob khoom siv hluav taws xob.
8h16 ua Pob ntawv txuas ntxiv RO Sau 1 mus rau me ntsis [0] kom pab tau cov pob ntawv txuas ntxiv.
8h17 ua TX and RX counter equal RW Qhia tias TX thiab RX txee yog sib npaug.
8h23 ua Pab kom latency WO Sau 1 mus rau me ntsis [0] los pab ntsuas latency.
8h24 ua Latency npaj RO Qhia tias kev ntsuas latency npaj txhij.

Interlaken (2nd Generation) Intel Agilex 7 FPGA IP Tsim Example User Guide Archives

  • Rau qhov tseeb thiab yav dhau los versions ntawm no tus neeg siv phau ntawv qhia, xa mus rau Interlaken (2nd
  • Generation) Intel Agilex 7 FPGA IP Tsim Example User Guide HTML version. Xaiv lub version thiab nyem Download. Yog tias tus IP lossis software version tsis tau teev tseg, cov lus qhia siv rau tus IP yav dhau los lossis software version siv.
  • IP versions yog tib yam li Intel Quartus Prime Design Suite software versions mus txog v19.1. Los ntawm Intel Quartus Prime Design Suite software version 19.2 lossis tom qab ntawd, IP cores muaj cov txheej txheem tshiab IP versioning.

Cov Ntaub Ntawv Hloov Kho Keeb Kwm rau Interlaken (2nd Generation) Intel Agilex 7 FPGA IP Tsim Example User Guide

Cov ntaub ntawv Version Intel Quartus Prime Version IP Version Hloov
2023.06.26 23.2 21.1.1 • Ntxiv VHDL kev txhawb nqa rau kev sib txuas thiab simulation qauv.

• Hloov kho cov khoom npe tsev neeg rau "Intel Agilex 7".
2022.08.03 21.3 20.0.1 Kho cov cuab yeej OPN rau Intel Agilex F-Series Transceiver-SoC Development Kit.
2021.10.04 21.3 20.0.1 • Ntxiv kev txhawb nqa rau QuestaSim simulator.

• Tshem tawm kev txhawb nqa rau NCSim simulator.
2021.02.24 20.4 20.0.1 • Ntxiv cov ntaub ntawv hais txog kev khaws cia tsis siv cov transceiver channel rau PAM4 hauv ntu: Hardware Design Exampcov Components.

• Ntxiv cov pll_ref_clk[1] cov lus piav qhia hauv ntu: Interface Signals.
2020.12.14 20.4 20.0.0 • Hloov kho sample hardware test output for Interlaken mode thiab Interlaken Look-aside mode in section Testing Hardware Design Example.

• Hloov kho daim ntawv teev npe rau Interlaken Look-aside design examplwm in section Sau npe daim ntawv qhia.

• Ntxiv cov txheej txheem dhau mus rau qhov kev sim kho vajtse ua tiav hauv ntu Testing Hardware Design Example.
2020.10.16 20.2 19.3.0 Kho cov lus txib kom khiav qhov pib hloov kho calibration ntawm RX sab hauv Testing Hardware Design Example ntu.
2020.06.22 20.2 19.3.0 • Tus tsim example yog muaj rau Interlaken Look-aside hom.

• Kev sim kho vajtse ntawm tus tsim example yog muaj rau Intel Agilex ntaus ntawv variations.

• Ntxiv Daim duab: High-level Block Diagram for Interlaken (2nd Generation) Design Example.

• Hloov kho cov ntu hauv qab no:

—   Hardware thiab Software Requirements

—   Directory Structure

• Hloov kho cov duab hauv qab no kom suav nrog Interlaken Look-aside hloov tshiab:

—   Daim duab: Interlaken (2nd Generation) Hardware Design Example High Level Block Diagram for E-tile NRZ Mode Variations

—   Daim duab: Interlaken (2nd Generation) Hardware Design Example High Level Block Diagram for E-tile PAM4 Hom Variations

• Hloov tshiab Daim duab: IP Parameter Editor.
txuas ntxiv…
Cov ntaub ntawv Version Intel Quartus Prime Version IP Version Hloov
      • Ntxiv cov ntaub ntawv hais txog kev teeb tsa zaus hauv daim ntawv thov tswj lub moos hauv ntu Compiling thiab Configuring Design Examphauv Hardware.

• Ntxiv cov kev xeem khiav tawm rau Interlaken Saib- ib sab hauv cov ntu hauv qab no:

—   Simulating Design Exampua Testbench

—   Testing Hardware Design Example

• Ntxiv cov cim tshiab hauv qab no Interface Signals

ntu:

— mgmt_clk

- rx_pin_n

- tx_pin_n

— mac_clk_pll_ref

• Ntxiv daim ntawv teev npe rau Interlaken Look-aside design example in seem: Sau npe daim ntawv qhia.
2019.09.30 19.3 19.2.1 Tshem tawm clk100. Lub mgmt_clk ua haujlwm raws li lub sijhawm siv rau IO PLL hauv qab no:

•    Daim duab: Interlaken (2nd Generation) Hardware Design Example High Level Block Diagram for E-tile NRZ Mode Variations.

•    Daim duab: Interlaken (2nd Generation) Hardware Design Example High Level Block Diagram rau E-tile PAM4 Hom Variations.
2019.07.01 19.2 19.2 Kev tso tawm thawj zaug.

Interlaken (2nd Generation) Intel Agilex® 7 FPGA IP Tsim Example User Guide

Cov ntaub ntawv / Cov ntaub ntawv

Intel Interlaken 2nd Generation Agilex 7 FPGA IP Tsim Example [ua pdf] Cov neeg siv phau ntawv qhia
Interlaken 2nd Generation Agilex 7 FPGA IP Tsim Example, Interlaken, 2nd Generation Agilex 7 FPGA IP Design Example, FPGA IP Design Example, IP Design Example, Design Example

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