Intel Interlaken 2nd Generation Agilex 7 FPGA IP Design Example

Ulwazi lweMveliso

I-Interlaken (i-2nd Generation) i-FPGA IP core yinkalo ye-Intel Agilex 7 FPGA. Inika i-testbench yokulinganisa kunye noyilo lwe-hardware example exhasa ukuhlanganiswa kunye novavanyo lwehardware. Uyilo example ikwafumaneka kwi-Interlaken Look-aside feature. I-IP engundoqo isekela i-NRZ kunye ne-PAM4 imodi ye-E-tile izixhobo kwaye ivelise i-design exampiles kuyo yonke indibaniselwano exhaswayo yenani leendlela kunye namazinga edatha.

IiMfuno zeHardware kunye neSoftware
I-Interlaken (2nd Generation) IP core design example ifuna i-Intel Agilex 7 F-Series Transceiver-SoC Development Kit. Nceda ujonge kwiSikhokelo soMsebenzisi sekhithi yophuhliso ngolwazi oluthe vetshe.

Ulwakhiwo lukavimba weefayili
I-Interlaken eyenziweyo (isiZukulwana sesi-2) example uyilo luquka abalawuli balandelayo:

• exampuyilo: Iqulethe eyona nto iphambili files yoyilo example.
• ilk_uflex: Iqulathe files enxulumene ne-Interlaken Jonga- ecaleni indlela ukhetho.
• ila_uflex: Iqulathe files enxulumene ne-Interlaken Jonga-ecaleni indlela ukhetho (yenziwe kuphela xa ikhethiwe).

Imiyalelo yokusetyenziswa kwemveliso

Ukusebenzisa i-Interlaken (2nd Generation) FPGA IP core design exampLe, landela la manyathelo:

1. Qinisekisa ukuba unayo i-Intel Agilex 7 F-Series Transceiver-SoC Development Kit.
2. Qokelela uyilo exampusebenzisa i-simulator.
3. Yenza ukulinganisa okusebenzayo ukuqinisekisa uyilo.
4. Veza uyilo example usebenzisa umhleli weparameter.
5. Qokelela uyilo example usebenzisa iQuartus Prime.
6. Yenza uvavanyo lwe-hardware ukuqinisekisa ukuyila.

Phawula: I-Interlaken Jonga-ecaleni imowudi ukhetho luyafumaneka ukuze ukhethe kumhleli weparamitha ye-IP. Ukuba ikhethiwe, yongeza files iya kwenziwa kwi-"ila_uflex" directory.

Isikhokelo sokuQalisa ngokukhawuleza

• I Interlaken (2nd Generation) FPGA IP core ibonelela testbench yokulinganisa kunye noyilo hardware example exhasa ukuhlanganiswa kunye novavanyo lwehardware.
• Xa uvelisa uyilo exampLe, umhleli weparameter yenza ngokuzenzekelayo i files iyimfuneko ukulinganisa, ukuqulunqa, kunye nokuvavanya uyilo kwihardware.
• Uyilo example iyafumaneka kwi-Interlaken Jonga-ecaleni isici.
• I-testbench kunye noyilo example ixhasa imowudi ye-NRZ kunye ne-PAM4 yezixhobo ze-E-tile.
• I Interlaken (2nd Generation) FPGA IP core ivelisa uyilo exampiles kuyo yonke indibaniselwano exhaswayo yenani leendlela kunye namazinga edatha.

Umzobo 1. Amanyathelo oPhuhliso kuYilo Example

I-Interlaken (2nd Generation) IP core design example ixhasa ezi mpawu zilandelayo:

• I-TX yangaphakathi ukuya kwimowudi yeserial loopback ye-RX
• Yenza iipakethi zobungakanani obuzinzileyo ngokuzenzekelayo
• Ipakethe esisiseko yokujonga amandla
• Ukukwazi ukusebenzisa iSystem Console ukusetha kwakhona uyilo ngenjongo yokuvavanya kwakhona
• Ukulungelelaniswa kwe-PMA

Intel Corporation. Onke Amalungelo Agciniwe. I-Intel, ilogo ye-Intel, kunye nezinye iimpawu ze-Intel ziimpawu zorhwebo ze-Intel Corporation okanye iinkampani eziphantsi kwayo. I-Intel iqinisekisa ukusebenza kweFPGA yayo kunye neemveliso zesemiconductor kwiinkcukacha zangoku ngokuhambelana newaranti esemgangathweni ye-Intel, kodwa inelungelo lokwenza utshintsho kuzo naziphi na iimveliso kunye neenkonzo nangaliphi na ixesha ngaphandle kwesaziso. I-Intel ayithathi xanduva okanye ityala elivela kwisicelo okanye ukusetyenziswa kwalo naluphi na ulwazi, imveliso, okanye inkonzo echazwe apha ngaphandle kokuba kuvunyelwene ngokubhaliweyo yi-Intel. Abathengi be-Intel bayacetyiswa ukuba bafumane inguqulelo yamva nje yeenkcazo zesixhobo ngaphambi kokuba baxhomekeke kulo naluphi na ulwazi olupapashiweyo naphambi kokubeka iiodolo zeemveliso okanye iinkonzo. *Amanye amagama kunye neempawu zingabangwa njengempahla yabanye.

Umzobo 2. Umzobo weBhloko okwinqanaba eliphezulu le-Interlaken (isizukulwana sesi-2) uyilo Example

Ulwazi olunxulumeneyo

• Interlaken (2nd Generation) FPGA IP User Guide
• Interlaken (2nd Generation) Intel FPGA IP amanqaku okuKhupha

Hardware kunye neSoftware

IiMfuno zeHardware kunye neSoftware
Ukuvavanya i-example uyilo, sebenzisa ihardware elandelayo kunye nesoftware:

• Intel® Quartus® Prime Pro Edition software
• Inkqubo yeConsole
• Izilingisi ezixhaswayo:
  • Siemens* EDA ModelSim* SE okanye QuestaSim*
  • Isishwankathelo* VCS*
  • Cadence* Xcelium*
• I-Intel Agilex® 7 F-Series Transceiver-SoC Development Kit (AGFB014R24A2E2V)

Ulwazi olunxulumeneyo
I-Intel Agilex 7 F-Series Transceiver-SoC Development Kit IsiKhokelo soMsebenzisi
Ulwakhiwo lukavimba weefayili
I-Interlaken (2nd Generation) IP core design example file abalawuli baqulathe oku kulandelayo kwenziwe files yoyilo example.

Umzobo 3. Ubume boluhlu lwe-Interlaken eVelisiwe (isiZukulwana sesi-2) Eksample Design

Ubumbeko lwehardware, ukulinganisa, kunye novavanyo files zibekwe kwiample_installation_dir>/uflex_ilk_0_example_design.
Uluhlu loku-1. I-Interlaken (isizukulwana se-2) IP Core Hardware Design Example File Iingcaciso Ezi files kwiample_installation_dir>/uflex_ilk_0_example_design/ umzample_design/quartus directory.

File Amagama	Inkcazo
example_design.qpf	Iprojekthi ye-Intel Quartus Prime file.
example_design.qsf	Intel Quartus Prime useto lweprojekthi file
example_design.sdc jtag_timing_template.sdc	Isinyanzelo soYilo lwe-Synopsys file. Ungakopa kwaye ulungise uyilo lwakho.
sysconsole_testbench.tcl	Engundoqo file yokufikelela kwiNkqubo yeConsole

Uluhlu loku-2. Interlaken (2nd Generation) IP Core Testbench File Inkcazo
Oku file ikuample_installation_dir>/uflex_ilk_0_example_design/ umzample_design/rtl ulawulo.

File Igama	Inkcazo
phezulu_tb.sv	Inqanaba eliphezulu testbench file.

Uluhlu loku-3. Interlaken (2nd Generation) IP Core Testbench Scripts
Ezi files kwiample_installation_dir>/uflex_ilk_0_example_design/ umzample_design/testbench directory.

File Igama	Inkcazo
vcstest.sh	Iskripthi seVCS sokusebenzisa i-testbench.
vlog_pro.do	I-ModelSim SE okanye i-QuestaSim iskripthi sokusebenzisa i-testbench.
xcelium.sh	Iskripthi se-Xcelium sokusebenzisa i-testbench.

Uyilo lwezixhobo zekhompyutha Eksample Components

• Exampi-design le idibanisa inkqubo kunye neewotshi zereferensi ze-PLL kunye nezinto ezifunekayo zoyilo. Example uyilo iqwalasela i-IP engundoqo kwimowudi ye-loopback yangaphakathi kwaye ivelise iipakethi kwi-IP engundoqo ye-TX yokudlulisa idatha yomsebenzisi. Undoqo we-IP uthumela ezi pakethi kwindlela yangaphakathi ye-loopback nge-transceiver.
• Emva kokuba umamkeli ongundoqo we-IP efumana iipakethi kwindlela ye-loopback, iqhuba i
• Iipakethi ze-Interlaken kwaye uzidlulisele kwi-RX yomsebenzisi wokudlulisa idatha. Exampi-design ijonga ukuba iipakethi zifunyenwe kwaye zigqithisiwe zihambelana.
• I-hardware example uyilo lubandakanya ii-PLL zangaphandle. Unokuhlolisisa isicatshulwa esicacileyo files ukuya view sample khowudi eyenza enye indlela enokwenzeka yokudibanisa ii-PLL zangaphandle kwi-Interlaken (i-2nd Generation) FPGA IP.
• I-Interlaken (yeSizukulwana sesi-2) uyilo lwehardware example iquka la malungu alandelayo:
  • Interlaken (2nd Generation) FPGA IP
  • I-Packet Generator kunye nePacket Checker
  • JTAG umlawuli onxibelelana neNkqubo yeConsole. Unxibelelana nengqiqo yomxhasi ngeNkqubo yeConsole.

Umzobo 4. I-Interlaken (isiZukulwana sesi-2) UYilo lweHardware Example Umzobo weBhlohlo ekwiNqanaba eliPhakamileyo yeeNguqulelo zeNdlela ye-E-tile ye-NRZ

I-Interlaken (yeSizukulwana sesi-2) uyilo lwehardware example ejolise kwi-E-tile PAM4 imo yenguqu ifuna iwotshi eyongezelelweyo mac_clkin eyenziwa yi-IO PLL. Le PLL kufuneka isebenzise iwotshi yereferensi efanayo eqhuba i-pll_ref_clk.
Umzobo 5. I-Interlaken (isiZukulwana sesi-2) UYilo lweHardware Example Idayagram yeBhlokhi yeNqanaba eliPhezulu le-E-tile PAM4 yeMode yeeNguqulelo

Kumahluko emowudi ye-E-tile PAM4, xa uvumela i Gcina amajelo etransceiver angasetyenziswanga ukwenzela PAM4 iparamitha, izibuko elongezelelweyo lewotshi yereferensi iyongezwa (pll_ref_clk [1]). Eli zibuko kufuneka liqhutywe ngamaxesha afanayo njengoko kuchaziweyo kumhleli weparameter ye-IP (Iwashi yoReferensi yekloko yamajelo agciniweyo). I-Gcina iitshaneli ze-transceiver ezingasetyenziswanga ze-PAM4 zikhethwa. I-pin kunye nemiqobo ehambelana nayo eyabelwe le wotshi ibonakala kwi-QSF xa ukhetha i-Intel Stratix® 10 okanye i-Intel Agilex 7 ikiti yokuphuhlisa i-design generation.
Phawula: Kuyilo exampkunye nokulinganisa, i-testbench ihlala ichaza i-frequency efanayo ye-pll_ref_clk[0] kunye ne-pll_ref_clk[1].
Ulwazi olunxulumeneyo
I-Intel Agilex 7 F-Series Transceiver-SoC Development Kit IsiKhokelo soMsebenzisi

Ukuvelisa uYilo
Umzobo 6. Inkqubo

Landela la manyathelo ukwenza i-hardware exampuyilo kunye ne-testbench:

1. Kwisoftware ye-Intel Quartus Prime Pro Edition, cofa File ➤ IWizard yeProjekthi Entsha ukwenza iprojekthi entsha ye-Intel Quartus Prime, okanye ucofe File ➤ Vula iProjekthi yokuvula iprojekthi esele ikho ye-Intel Quartus Prime. Iwizard ikwenza ukuba uchaze isixhobo.
2. Cacisa usapho lwesixhobo se-Intel Agilex 7 kwaye ukhethe isixhobo soyilo lwakho.
3. KwiKhathalogi ye-IP, fumana kwaye ucofe kabini i-Interlaken (isizukulwana sesibini) Intel FPGA IP. Iwindow eNtsha eyahlukileyo ye-IP iyavela.
4. Chaza igama lomgangatho ophezulu ukwenzela ukwahluka kwe-IP yakho. Umhleli weparameter ugcina useto loguqulo lwe IP kwi file igama .ip.
5. Cofa u-Kulungile. Umhleli weparameter uyavela.
   Umzobo 7. Example Tab yoYilo kwi-Interlaken (2nd Generation) Intel FPGA IP Parameter Editor
6. Kwi-IP ithebhu, khankanya iiparamitha zokwahluka kondoqo we-IP yakho.
7. Kwi-PMA Uhlengahlengiso isithuba, khankanya iiparamitha zohlengahlengiso lwe-PMA ukuba uceba ukusebenzisa uhlengahlengiso lwe-PMA kutshintsho lwesixhobo sakho se-E-tile. Eli nyathelo linokuzikhethela:
   • Khetha Vula uhlengahlengiso lomthwalo othambileyo ukhetho lwe-IP.
   • Phawula: Kufuneka uvule iNdlela yokuPhepha eyiNtloko ye-PHY ye-Debug (NPDME) kwi-IP tab xa uhlengahlengiso lwe-PMA luvuliwe.
   • Khetha ulungelelwaniso lwePMA olusetwe kwangaphambili lwePMA ulungelelwaniso Khetha iparamitha.
   • Cofa i-PMA Adaptation Preload ukuze ulayishe iparameters yokuqala kunye neqhubekayo yokulungelelanisa.
   • Chaza inani lolungelelwaniso lwe-PMA ukuxhasa xa ulungelelwaniso oluninzi lwe-PMA luvuliwe kusetyenziswa Inani leparamitha yoqwalaselo lwe-PMA.
   • Khetha ukuba loluphi uqwalaselo lwe-PMA oza kululayisha okanye ulugcine usebenzisa Khetha ubumbeko lwe-PMA ukulayisha okanye ukulugcina.
   • Cofa Layisha uhlengahlengiso kuqwalaselo olukhethiweyo lwe-PMA ukulayisha useto olukhethiweyo loqwalaselo lwe-PMA.
   • Ngolwazi oluthe kratya malunga neeparamitha zohlengahlengiso lwe-PMA, bhekisa kwi-E-tile
     Transceiver PHY User Guide.
8. KwiEksample Yila isithuba, khetha i Ufaniso ukhetho ukuvelisa ibhentshi yovavanyo, kwaye khetha i Udibaniso ukhetho ukuvelisa i hardware ex.ampuyilo.
   • Phawula: Kufuneka ukhethe nokuba nye kwiinketho zokulinganisa okanye uHlanganiso oluvelisa iExample Design Files.
9. KwiFomathi yeHDL eVeliswe, khetha iVerilog okanye iVHDL.
10. KwiKhithi yoPhuhliso ekujoliswe kuyo khetha ukhetho olufanelekileyo.
    • Phawula: I-Intel Agilex 7 F-Series Transceiver SoC Development Kit ukhetho lufumaneka kuphela xa iprojekthi yakho ichaza igama lesixhobo se-Intel Agilex 7 ukuqala nge-AGFA012 okanye i-AGFA014. Xa ukhetha ukhetho lweKit yoPhuhliso, izabelo ze-pin zisetwa ngokwe-Intel Agilex 7 Development Kit device number number AGFB014R24A2E2V kwaye inokwahluka kwisixhobo sakho esikhethiweyo. Ukuba ujonge ukuvavanya uyilo kwihardware kwiPCB eyahlukileyo, khetha i Akukho nanye kwaye wenze i assignment ezifanelekileyo kwi .qsf file.
11. Cofa uVelisa Example Design. Khetha Eksample Dizayini kavimba weefayili iwindow iyavela.
12. Ukuba ufuna ukulungisa uyilo example ndlela yolawulo okanye igama ukusuka kokungagqibekanga okubonisiwe (uflex_ilk_0_example_design), khangela kwindlela entsha kwaye uchwetheze uyilo olutsha exampigama lolawulo.
13. Cofa u-Kulungile.

Ulwazi olunxulumeneyo

• I-Intel Agilex 7 F-Series Transceiver-SoC Development Kit IsiKhokelo soMsebenzisi
• I-E-tile Transceiver ye-PHY yeSikhokelo soMsebenzisi

Ukulinganisa i-Design Example Testbench
Jonga kwi-Interlaken (iSizukulwana se-2) Uyilo lweHardware Example Ibhloko ekwiNqanaba eliPhezulu le-E-tile yeNRZ yokwahluka kweMowudi kunye ne-Interlaken (isizukulwana sesi-2) i-Hardware Design Ex.ample Ibhloko yeNqanaba eliPhezulu le-E-tile PAM4 Iindlela ezahlukeneyo zemizobo yebhloko ye-testbench yokulinganisa.
Umzobo 8. Inkqubo

Landela la manyathelo ukulinganisa i-testbench:

1. Kwi-prompt yomyalelo, tshintshela kwi-testbench simulation directory. Uluhlu luyiample_installation_dir>/example_design/ testbench yeIntel Agilex 7 izixhobo.
2. Sebenzisa iskripthi sokulinganisa kwi-simulator exhaswayo oyikhethileyo. Iskripthi siqulunqa kwaye siqhuba i-testbench kwi-simulator. Iskripthi sakho kufuneka sijonge ukuba i-SOP kunye ne-EOP ibala umdlalo emva kokuba ukulinganisa kugqityiwe. Jonga kwitheyibhile Amanyathelo okuqhuba ukulinganisa.

Uluhlu loku-4. Amanyathelo okuqhuba ukulinganisa

Isifanisi	Imiyalelo
ModelSim SE okanye QuestaSim	Kumgca womyalelo, chwetheza -do vlog_pro.do Ukuba ukhetha ukulinganisa ngaphandle kokuzisa i-ModelSim GUI, chwetheza i-vsim -c -do vlog_pro.do
VCS	Kumgca womyalelo, chwetheza sh vcstest.sh
Xcelium	Kumgca womyalelo, chwetheza sh xcelium.sh

Hlalutya iziphumo. Ukulinganisa okuphumelelayo kuthumela kwaye kufumane iipakethi, kwaye kubonisa "Uvavanyo LUPASIWE".
I-testbench yoyilo exampugqiba le misebenzi ilandelayo:

• Iqinisekisa i-Interlaken (isizukulwana sesibini) Intel FPGA IP.
• Iprinta ubume be-PHY.
• Ijonga ungqamaniso lwemetaframe (SYNC_LOCK) kunye negama (ibhloko) imida (WORD_LOCK).
• Ilinda ukuba iindlela ezizimeleyo zitshixiwe kwaye zilungelelaniswe.
• Iqala ukuthumela iipakethi.
• Ijonga iinkcukacha zepakethi:
  • CRC24 iimpazamo
  • Ii-SOPs
  • EOPs

Oku kulandelayo sample mveliso ibonisa uvavanyo oluyimpumelelo lokulinganisa oluqhutywa kwimowudi ye-Interlaken:

Phawula: Uyilo lwe Interlaken example testbench yokulinganisa ithumela iipakethi ezili-100 kwaye ifumana iipakethi ezili-100. Oku kulandelayo sample mveliso ibonisa uvavanyo oluyimpumelelo lokulinganisa oluqhutywa kwimowudi ye-Interlaken Jonga ecaleni:

Phawula: Inani leepakethi (ii-SOPs kunye nee-EOPs) ziyahluka ngomzila kwi-Interlaken Lookaside design example yokulinganisa sample imveliso.
Ulwazi olunxulumeneyo
Uyilo lwezixhobo zekhompyutha Eksample Amacandelo akwiphepha 6

Ukuqulunqa kunye nokuqwalasela i-Design Example kwi-Hardware
Umzobo 9. Inkqubo

Ukuqokelela kunye nokuqhuba uvavanyo lokubonisa kwi-hardware exampkuyilo, landela la manyathelo:

1. Qinisekisa i-hardware example mveliso yoyilo igqityiwe.
2. Kwisoftware ye-Intel Quartus Prime Pro Edition, vula iprojekthi ye-Intel Quartus Primeample_installation_dir>/example_design/quartus/ example_design.qpf>.
3. Kwi-Processing menu, cofa Qala ukuHlanganisa.
4. Emva kokuhlanganiswa ngempumelelo, i.sof file iyafumaneka kulawulo lwakho olukhankanyiweyo. Landela la manyathelo ukucwangcisa ihardware exampuyilo kwisixhobo se-Intel Agilex 7:
   • a. Qhagamshela i-Intel Agilex 7 F-Series Transceiver-SoC Development Kit kwi-host computer.
   • b. Qalisa isicelo soLawulo lweClock, eyinxalenye yekhithi yophuhliso, kwaye ucwangcise izakhelo ezintsha zoyilo ex.ample. Apha ngezantsi luseto lwamaxesha ngamaxesha kwisicelo soLawulo lwewotshi:
   • • Si5338 (U37), CLK1- 100 MHz
   • • Si5338 (U36), CLK2- 153.6 MHz
   • • Si549 (Y2), OUT- Misela ixabiso le pll_ref_clk(1) ngokwemfuno yakho yoyilo.
   • c. Kwimenyu yeZixhobo, cofa uMlungisi.
   • d. KuMdwelisi weNkqubo, cofa uSeto lweHardware.
   • e. Khetha isixhobo sokucwangcisa.
   • f. Khetha kwaye wongeze i-Intel Agilex 7 F-Series Transceiver-SoC Development Kit apho iseshoni yakho ye-Intel Quartus Prime inokuxhuma khona.
   • g. Qinisekisa ukuba iMowudi isetelwe ku-JTAG.
   • h. Khetha isixhobo se-Intel Agilex 7 kwaye ucofe Yongeza isixhobo. I-Programmer ibonisa umzobo webhloko woqhagamshelwano phakathi kwezixhobo ebhodini yakho.
   • i. Kumqolo neyakho .sof, khangela ibhokisi ye .sof.
   • j. Khangela ibhokisi kwiNkqubo/Qwalasela ikholam.
   • k. Cofa uQalisa.

Ulwazi olunxulumeneyo

• Ukucwangcisa Intel FPGA Devices kwiphepha 0
• Ukuhlalutya kunye noYilo lwe-Debugging nge-System Console
• I-Intel Agilex 7 F-Series Transceiver-SoC Development Kit IsiKhokelo soMsebenzisi

Ukuvavanya i-Hardware Design Example
Emva kokuba uqokelele Interlaken (2nd Generation) Intel FPGA IP core uyilo example kwaye uqwalasele isixhobo sakho, ungasebenzisa iSixokelelwano seKhonsoli ukwenza inkqubo ye-IP engundoqo kunye neerejista ezizinzisiweyo zeNative PHY IP.

Landela la manyathelo ukuzisa iNkqubo yeConsole kwaye uvavanye uyilo lwehardware example:

1. Kwisoftware ye-Intel Quartus Prime Pro Edition, kwimenyu yeZixhobo, cofa iSixokelelwano sokuLungisa izixhobo ➤ Ikhonsoli yeNkqubo.
2. Tshintshela kwiample_installation_dir>example_design/ hwtest directory.
3. Ukuvula umdibaniso kuJTAG inkosi, chwetheza lo myalelo ulandelayo: umthombo sysconsole_testbench.tcl
4. Ungavula imowudi yangaphakathi yesiriyali loopback ngoyilo lulandelayo example miyalelo:
   • a. izibalo: Ishicilela ulwazi lwemo jikelele.
   • b. sys_reset: Seta kwakhona inkqubo.
   • c. i-loop_on: Ivula i-loop yangaphakathi yesiriyali.
   • d. run_example_design: Iqhuba uyilo example.
   • Phawula: Kufuneka uqhube loop_on umyalelo phambi kokuba run_example_design umyalelo. I run_exampi-le_design yenza le miyalelo ilandelayo ngolandelelwano: sys_reset->stat->gen_on->stat->gen_off.
   • Phawula: Xa ukhetha i Yenza ulungelelwaniso lomthwalo othambileyo ukhetho lwe-IP, i run_exampUmyalelo we-le_design wenza ulungelelwaniso lokuqala kwicala le-RX ngokuqhuba umyalelo we-run_load_PMA_configuration.
5. Ungacima imowudi yangaphakathi yothotho lweloopback ngoyilo lulandelayo example command:
   • a. loop_off: Cima iluphu yangaphakathi yesiriyali.
6. Uyakwazi ukuprograma i-IP core ngolu hlobo lulandelayo loyilo olongezelelweyo example miyalelo:
   • a. gen_on: Yenza ipakethe generator.
   • b. gen_off: Ivala ipakethe generator.
   • c. run_test_loop: Iqhuba uvavanyo lwe amaxesha e-E-tile NRZ kunye nokwahluka kwePAM4.
   • d. clear_err: Icoca zonke iimpazamo ezincangathi.
   • e. set_test_mode : Icwangcisa uvavanyo ukuze isebenze kwimowudi ethile.
   • f. get_test_mode: Shicilela imo yovavanyo lwangoku.
   • g. set_burst_size : Iseta ubungakanani bokugqabhuka kwiibhayithi.
   • h. get_burst_size: Ushicilelo lobungakanani bolwazi.

Uvavanyo oluphumeleleyo luprinta HW_TEST:PASS umyalezo. Apha ngezantsi yimilinganiselo yokupasa yovavanyo:

• Akukho zimpazamo ze-CRC32, CRC24, kunye ne-checker.
• Ii-SOP ezithunyelwayo kunye nee-EOPs kufuneka zihambelane nezifunyenweyo.

Oku kulandelayo sample mveliso ibonisa uvavanyo oluyimpumelelo kwimowudi ye-Interlaken:

Ushicilelo lovavanyo oluyimpumelelo HW_TEST : Umyalezo wePASS. Apha ngezantsi yimilinganiselo yokupasa yovavanyo:

• Akukho zimpazamo ze-CRC32, CRC24, kunye ne-checker.
• Ii-SOP ezithunyelwayo kunye nee-EOPs kufuneka zihambelane nezifunyenweyo.

Oku kulandelayo sample mveliso ibonisa uvavanyo oluyimpumelelo kwimowudi ye-Interlaken Lookaside:

Uyilo Eksample Inkcazo

Uyilo example ibonisa ukusebenza kwe-Interlaken IP core.

Ulwazi olunxulumeneyo
Interlaken (2nd Generation) FPGA IP User Guide

Uyilo Eksample Behaviour
Ukuvavanya uyilo kwihardware, chwetheza le miyalelo ilandelayo kwiSistim Console::

1. Umthombo wokuseta file:
   • % umthomboample>uflex_ilk_0_example_design/example_design/hwtest/ sysconsole_testbench.tcl
2. Yenza uvavanyo:
   • % run_example_design
3. I-Interlaken (yeSizukulwana sesi-2) uyilo lwehardware example igqibezela la manyathelo alandelayo:
   • a. Iseta kwakhona i-Interlaken (yeSizukulwana sesi-2) IP.
   • b. Iqwalasela i-Interlaken (yeSizukulwana sesi-2) IP kwimowudi yangaphakathi yokubuyisela umva.
   • c. Ithumela uthotho lweepakethi ze-Interlaken ezinedatha echazwe kwangaphambili kumthwalo wokuhlawula kwi-TX yomsebenzisi wokudluliselwa kwedatha ye-IP engundoqo.
   • d. Ijonga iipakethi ezifunyenweyo kwaye ichaze ubume. Umkhangeli wepakethi uqukwe kuyilo lwehardware example ibonelela ngezakhono zokujonga ipakethi esisiseko:
     • Ijonga ukuba ulandelelwano lwepakethi egqithisiweyo ichanekile.
     • Ijonga ukuba idatha efunyenweyo ihambelana namaxabiso alindelekileyo ngokuqinisekisa zombini ukuqala kwepakethi (SOP) kunye nokuphela kwepakethi (EOP) ukubala ukulungelelaniswa ngelixa idatha ihanjiswa kwaye ifunyanwa.

Iimpawu zokunxibelelana
Uluhlu loku-5. Uyilo Eksample Iimpawu zoNxibelelwano

Igama lePort	Isalathiso	Ububanzi (Amasuntswana)	Inkcazo
mgmt_clk	Igalelo	1	Ungeniso lwewotshi yenkqubo. Amaxesha ewotshi kufuneka abe yi-100 MHz.
pll_ref_clk / pll_ref_clk[1:0](2)	Igalelo	1/2	Iwotshi yereferensi yeTransceiver. Iqhuba i-RX CDR PLL.
iqhubekile...

Igama lePort	Isalathiso	Ububanzi (Amasuntswana)	Inkcazo
			pll_ref_clk[1] ifumaneka kuphela xa uvula Gcina ezingasetyenziswanga Phawula: Iitshaneli ze-transceiver ze-PAM4 ipharamitha kwi-E-tile PAM4 imo ye-IP eyahlukileyo.
rx_pin	Igalelo	Inani leendlela	Umamkeli SEDES iphini yedatha.
tx_pin	Isiphumo	Inani leendlela	Thumela iphini yedatha yeSERDES.
rx_pin_n	Igalelo	Inani leendlela	Umamkeli SEDES iphini yedatha. Lo mqondiso ufumaneka kuphela kwimo ye-E-tile PAM4 eyahlukileyo yesixhobo.
tx_pin_n	Isiphumo	Inani leendlela	Thumela iphini yedatha yeSERDES. Lo mqondiso ufumaneka kuphela kwimo ye-E-tile PAM4 eyahlukileyo yesixhobo.
mac_clk_pll_ref	Igalelo	1	Lo mqondiso kufuneka uqhutywe yi-PLL kwaye kufuneka usebenzise umthombo ofanayo wewotshi eqhuba i-pll_ref_clk. Lo mqondiso ufumaneka kuphela kwimo ye-E-tile PAM4 eyahlukileyo yesixhobo.
usr_pb_reset_n	Igalelo	1	Ukusetha kwakhona inkqubo.

Ulwazi olunxulumeneyo
Iimpawu zokunxibelelana

Bhalisa imephu
Phawula: • Yila EksampIdilesi yerejista iqala ngo-0x20** ngelixa idilesi yerejista ye-Interlaken IP engundoqo iqala ngo-0x10**.

• Ikhowudi yokufikelela: RO—Funda Kuphela, kunye ne-RW—Funda/Bhala.
• Inkqubo console ifunda uyilo example iirejista kwaye ingxelo ubume uvavanyo kwisikrini.

Uluhlu loku-6. Uyilo Eksample Bhalisa imephu ye-Interlaken Design Example

Offset	Igama	Ukufikelela	Inkcazo
8'h00	Igciniwe
8'h01	Igciniwe
8'h02	Ukusetha kwakhona inkqubo ye-PLL	RO	Amasuntswana alandelayo abonisa inkqubo ye-PLL isicelo sokusetha ngokutsha kwaye wenze ixabiso: • Intwana [0] – sys_pll_rst_req • Intwana [1] – sys_pll_rst_en
8'h03	Indlela ye-RX ilungelelanisiwe	RO	Ibonisa ulungelelwaniso lwendlela ye-RX.
8'h04	WORD itshixiwe	RO	[NUM_LANES–1:0] – Igama (ibhloko) ukuchongwa kwemida.
iqhubekile...

Xa usenza Gcina amajelo ogqithiso angasetyenziswanga wePAM4 iparamitha, izibuko eyongezelelweyo yereferensi yewotshi yongezwa ukugcina itshaneli yekhoboka yePAM4 engasetyenziswanga.

Offset	Igama	Ukufikelela	Inkcazo
8'h05	Ungqamaniso lutshixiwe	RO	[NUM_LANES–1:0] – Ungqamaniso lweMetaframe.
8'h06 - 8'h09	CRC32 ubalo lwempazamo	RO	Ibonisa i-CRC32 count yempazamo.
8h0A	CRC24 ubalo lwempazamo	RO	Ibonisa i-CRC24 count yempazamo.
8h0b	Isiginali yokuphuphuma/Ngaphantsi	RO	Amasuntswana alandelayo abonisa: • Bit [3] – TX isiginali yokuqukuqela • Bit [2] – TX isignali yokuphuphuma • Bit [1] – RX isignali yokuphuphuma
8'h0C	Ubalo lwe-SOP	RO	Ibonisa inani le-SOP.
8'h0D	Ukubala kwe-EOP	RO	Ibonisa inani le-EOP
8'h0E	Ubalo lwempazamo	RO	Ibonisa inani leempazamo ezilandelayo: • Ukulahleka kolungelelwaniso lwendlela • Igama elilawulayo elingekho mthethweni • Ipateni yoyilo engekho mthethweni • I-SOP engekho okanye isalathisi se-EOP
8'h0F	send_data_mm_clk	RW	Bhala isi-1 kwibhithi [0] ukwenza isignali yomvelisi.
8'h10	Imposiso yomkhangeli		Ibonisa impazamo yomkhangeli. (Impazamo yedatha ye-SOP, impazamo yenombolo yesitishi, kunye nempazamo yedatha ye-PLD)
8'h11	Isitshixo sePLL yeNkqubo	RO	I-Bit [0] ibonisa isalathiso sokutshixa i-PLL.
8'h14	TX SOP ubalo	RO	Ibonisa inani le-SOP eveliswe yi-packet generator.
8'h15	TX EOP ukubala	RO	Ibonisa inani le-EOP eveliswe yi-packet generator.
8'h16	Ipakethi eqhubekayo	RW	Bhala i-1 ukuya kwibit [0] ukwenza ipakethi eqhubekayo.
8'h39	Ubalo lwemposiso ye-ECC	RO	Ibonisa inani leempazamo ze-ECC.
8'h40	I-ECC ilungise inani lemposiso	RO	Ibonisa inani leempazamo ezilungisiweyo ze-ECC.

Uyilo Eksample Bhalisa iMaphu ye-Interlaken Jonga-secaleni uyilo Example
Sebenzisa le mephu yokubhalisa xa uvelisa i-ex yoyiloample nge Yenza i-Interlaken Jonga-ecaleni iparameter ivuliwe.

Offset	Igama	Ukufikelela	Inkcazo
8'h00	Igciniwe
8'h01	Ukuseta kwakhona ikhawuntara	RO	Bhala i-1 ukuya kwibit [0] ukucima i-TX kunye ne-RX counter bit elinganayo.
8'h02	Ukusetha kwakhona inkqubo ye-PLL	RO	Amasuntswana alandelayo abonisa inkqubo ye-PLL isicelo sokusetha ngokutsha kwaye wenze ixabiso: • Intwana [0] – sys_pll_rst_req • Intwana [1] – sys_pll_rst_en
8'h03	Indlela ye-RX ilungelelanisiwe	RO	Ibonisa ulungelelwaniso lwendlela ye-RX.
8'h04	WORD itshixiwe	RO	[NUM_LANES–1:0] – Igama (ibhloko) ukuchongwa kwemida.
8'h05	Ungqamaniso lutshixiwe	RO	[NUM_LANES–1:0] – Ungqamaniso lweMetaframe.
8'h06 - 8'h09	CRC32 ubalo lwempazamo	RO	Ibonisa i-CRC32 count yempazamo.
8h0A	CRC24 ubalo lwempazamo	RO	Ibonisa i-CRC24 count yempazamo.
iqhubekile...

Offset	Igama	Ukufikelela	Inkcazo
8h0b	Igciniwe
8'h0C	Ubalo lwe-SOP	RO	Ibonisa inani le-SOP.
8'h0D	Ukubala kwe-EOP	RO	Ibonisa inani le-EOP
8'h0E	Ubalo lwempazamo	RO	Ibonisa inani leempazamo ezilandelayo: • Ukulahleka kolungelelwaniso lwendlela • Igama elilawulayo elingekho mthethweni • Ipateni yoyilo engekho mthethweni • I-SOP engekho okanye isalathisi se-EOP
8'h0F	send_data_mm_clk	RW	Bhala isi-1 kwibhithi [0] ukwenza isignali yomvelisi.
8'h10	Imposiso yomkhangeli	RO	Ibonisa impazamo yomkhangeli. (Impazamo yedatha ye-SOP, impazamo yenombolo yesitishi, kunye nempazamo yedatha ye-PLD)
8'h11	Isitshixo sePLL yeNkqubo	RO	I-Bit [0] ibonisa isalathiso sokutshixa i-PLL.
8'h13	Ubalo lokubambezeleka	RO	Ibonisa inani le-latency.
8'h14	TX SOP ubalo	RO	Ibonisa inani le-SOP eveliswe yi-packet generator.
8'h15	TX EOP ukubala	RO	Ibonisa inani le-EOP eveliswe yi-packet generator.
8'h16	Ipakethi eqhubekayo	RO	Bhala i-1 ukuya kwibit [0] ukwenza ipakethi eqhubekayo.
8'h17	I-TX kunye ne-RX counter iyalingana	RW	Ibonisa ukuba i-TX kunye ne-RX counter ziyalingana.
8'h23	Yenza ukubambezeleka	WO	Bhala isi-1 ukuya kwibhiti [0] ukuze uvumele umlinganiselo wokulibaziseka.
8'h24	I-latency ilungile	RO	Ibonisa umlinganiselo we-latency ulungile.

Interlaken (2nd Generation) Intel Agilex 7 FPGA IP Design Example ULondolozo lweeNkcukacha eziBalulekileyo

• Kwiinguqulelo zamva nje kunye nezidlulileyo zesi sikhokelo somsebenzisi, bhekisa kwi-Interlaken (2nd
• Isizukulwana) Intel Agilex 7 FPGA IP Design Example Isikhokelo somsebenzisi uguqulelo lweHTML. Khetha inguqulelo kwaye ucofe Khuphela. Ukuba i-IP okanye inguqulelo yesoftware ayidweliswanga, isikhokelo somsebenzisi se-IP yangaphambili okanye inguqulelo yesoftware siyasebenza.
• Iinguqulelo ze-IP ziyafana ne-Intel Quartus Prime Design Suite iinguqulelo zesoftware ukuya kuthi ga kwi-v19.1. Ukusuka kwi-Intel Quartus Prime Design Suite software version 19.2 okanye kamva, ii-IP cores zineskimu esitsha soguqulelo lwe-IP.

Uhlaziyo lweMbali yoXwebhu lwe-Interlaken (isizukulwana se-2) Intel Agilex 7 FPGA IP Design Example Isikhokelo somsebenzisi

Inguqulelo yoXwebhu	Intel Quartus Prime Version	IP Version	Iinguqu
2023.06.26	23.2	21.1.1	• Inkxaso eyongeziweyo yeVHDL yokudibanisa kunye nemodeli yokulinganisa. • Uhlaziyo lwegama losapho lwemveliso kwi-"Intel Agilex 7".
2022.08.03	21.3	20.0.1	Kulungiswe isixhobo se-OPN ye-Intel Agilex F-Series Transceiver-SoC Development Kit.
2021.10.04	21.3	20.0.1	• Inkxaso eyongeziweyo ye-QuestaSim simulator. • Isusiwe inkxaso ye-NCSim simulator.
2021.02.24	20.4	20.0.1	• Ulwazi olongeziweyo malunga nokugcina umjelo wogqithiso olungasetyenziswanga wePAM4 kwicandelo: Uyilo lwezixhobo zekhompyutha Eksample Components. • Yongeza inkcazo yomqondiso we-pll_ref_clk[1] kwicandelo: Iimpawu zokunxibelelana.
2020.12.14	20.4	20.0.0	• Uhlaziyoampimveliso yovavanyo lwehardware yemowudi ye-Interlaken kunye ne-Interlaken Jonga ecaleni kwendlela kwicandelo Ukuvavanya i-Hardware Design Example. • Imephu yerejista ehlaziyiweyo ye-Interlaken Look-side design example kwicandelo Bhalisa imephu. • Kongezwe indlela yokupasa yovavanyo lwehardware oluyimpumelelo kwicandelo Ukuvavanya i-Hardware Design Example.
2020.10.16	20.2	19.3.0	Umyalelo ochanekileyo wokuqhuba ulungelelwaniso lokuqala kwicala le-RX ngaphakathi Ukuvavanya i-Hardware Design Example icandelo.
2020.06.22	20.2	19.3.0	• Uyilo umzekeloample iyafumaneka kwi Interlaken Jonga-imowudi ecaleni. • Uvavanyo lwe-Hardware yoyilo example iyafumaneka kwiinguqulelo zesixhobo ze-Intel Agilex. • Ifakwe Umzobo: Umzobo weBhlokhi ekwinqanaba eliphezulu le-Interlaken (isizukulwana se-2) uyilo Example. • Hlaziya amacandelo alandelayo: —   IiMfuno zeHardware kunye neSoftware —   Ulwakhiwo lukavimba weefayili • Uhlengahlengiso lwamanani alandelayo ukuze abandakanye uhlaziyo olunxulumene ne-Interlaken Look-aside: —   Umzobo: I-Interlaken (isizukulwana se-2) Uyilo lweHardware Example ISazobe soMgangatho oPhezulu weBhloko ye-E- tile yeNRZ yokwahluka kweMowudi —   Umzobo: I-Interlaken (isizukulwana se-2) Uyilo lweHardware Example Umzobo weBhlohlo ekwiNqanaba eliPhezulu le-E- tile PAM4 IiNdlela eziNxulukileyo • Uhlaziywe Umzobo: IP Parameter Editor.
iqhubekile...

Inguqulelo yoXwebhu	Intel Quartus Prime Version	IP Version	Iinguqu
			• Ulwazi olongeziweyo malunga noseto lwamaza kwisixhobo solawulo lwewotshi kwicandelo Ukuqulunqa kunye nokuqwalasela i-Design Example kwi-Hardware. • Ukongeza iziphumo zovavanyo lwe-Interlaken Jonga ecaleni kula macandelo alandelayo: —   Ukulinganisa i-Design Example Testbench —   Ukuvavanya i-Hardware Design Example • Kongezwe imiqondiso emitsha elandelayo Iimpawu zokunxibelelana icandelo: — mgmt_clk — rx_pin_n — tx_pin_n — mac_clk_pll_ref • Kongezwe imephu yerejista yoyilo lwe-Interlaken Look-side design example kwi icandelo: Bhalisa imephu.
2019.09.30	19.3	19.2.1	Isusiwe i-clk100. I-mgmt_clk isebenza njengewotshi yereferensi kwi-IO PLL kwezi zilandelayo: •    Umzobo: I-Interlaken (isizukulwana se-2) Uyilo lweHardware Example Umzobo weBhlohlo ekwiNqanaba eliPhakamileyo yeeNguqulelo zeNdlela ye-E-tile ye-NRZ. •    Umzobo: I-Interlaken (isizukulwana se-2) Uyilo lweHardware Example Idayagram yeBhlokhi yeNqanaba eliPhezulu le-E-tile PAM4 yeMode yeeNguqulelo.
2019.07.01	19.2	19.2	Ukukhutshwa kokuqala.

Interlaken (2nd Generation) Intel Agilex® 7 FPGA IP Design Example Isikhokelo somsebenzisi

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Intel Interlaken 2nd Generation Agilex 7 FPGA IP Design Example [pdf] Isikhokelo somsebenzisi Interlaken 2nd Generation Agilex 7 FPGA IP Design Example, Interlaken, 2nd Generation Agilex 7 FPGA IP Design Example, FPGA IP Design Example, IP Design Example, Uyilo Eksample

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