DSP Builder kanggo Intel FPGAs
Informasi produk
Produk kasebut diarani DSP Builder kanggo Intel FPGAs. Iki minangka piranti lunak sing ngidini pangguna ngrancang lan ngetrapake algoritma pangolahan sinyal digital (DSP) ing Intel FPGA. Alat kasebut nyedhiyakake antarmuka grafis sing nggabungake karo alat MathWorks MATLAB lan Simulink, ngidini pangguna ngrancang sistem DSP nggunakake pendekatan diagram blok. Piranti kasebut nduweni versi sing beda-beda, kanthi versi paling anyar yaiku 22.4. Produk wis ngalami sawetara revisi, saben revisi ngenalake fitur anyar, koreksi bug, lan dandan. Tabel riwayat revisi nyedhiyakake ringkesan owah-owahan sing ditindakake ing saben versi. Produk kasebut duwe rong edisi blokset: blokset standar lan blokset lanjutan. Blokset standar kasedhiya kanggo Intel Quartus Prime Standard Edition, dene blokset maju kasedhiya kanggo Intel Quartus Prime Pro Edition lan Intel Quartus Prime Standard Edition. Produk kasebut nduweni syarat sistem sing kudu ditindakake kanggo instalasi lan panggunaan sing tepat. Sampeyan mbutuhake paling ora siji versi The MathWorks MATLAB lan alat Simulink, kanthi dhukungan kanggo versi 64-bit MATLAB. Versi piranti lunak Intel Quartus Prime kudu cocog karo versi DSP Builder kanggo Intel FPGA sing digunakake. Blokset canggih nggunakake jinis titik tetep Simulink kanggo kabeh operasi lan mbutuhake versi Simulink Fixed Point sing dilisensi. Intel uga nyaranake DSP System Toolbox lan Communications System Toolbox kanggo fungsi tambahan.
Pandhuan Panggunaan Produk
- Priksa manawa sampeyan duwe versi kompatibel MathWorks MATLAB lan alat Simulink sing diinstal ing workstation sampeyan. Alat kasebut mung ndhukung versi 64-bit MATLAB.
- Priksa manawa sampeyan duwe versi piranti lunak Intel Quartus Prime sing cocog. Versi kasebut kudu cocog karo versi DSP Builder kanggo Intel FPGA sing sampeyan gunakake.
- Bukak DSP Builder kanggo Intel FPGA lan bukak antarmuka grafis.
- Rancang sistem DSP sampeyan nggunakake pendekatan diagram blok sing diwenehake dening alat kasebut. Gunakake blok lan fitur sing kasedhiya kanggo nggawe algoritma sing dikarepake.
- Njupuk advantage saka jinis titik tetep Simulink kanggo kabeh operasi ing desain sampeyan. Priksa manawa sampeyan duwe lisensi sing dibutuhake kanggo Simulink Fixed Point.
- Yen sampeyan mbutuhake fungsi tambahan, coba gunakake DSP System Toolbox lan Communications System Toolbox, sing disaranake Intel.
- Sawise desain rampung, sampeyan bisa nggawe sing perlu files kanggo program Intel FPGA.
Kanthi tindakake pandhuan panggunaan iki, sampeyan bakal bisa ngrancang lan ngleksanakake algoritma DSP kanthi efektif ing Intel FPGA nggunakake DSP Builder kanggo Intel FPGA.
DSP Builder kanggo Cathetan Rilis Intel® FPGAs
Informasi sing gegandhengan
- Pangkalan Pengetahuan
- Instalasi lan Lisensi Software
salahe
Errata minangka cacat utawa kesalahan fungsional, sing bisa nyebabake prodhuk nyimpang saka spesifikasi sing diterbitake. Masalah dokumentasi kalebu kesalahan, deskripsi sing ora jelas, utawa ngilangi spesifikasi sing diterbitake utawa dokumen produk saiki.
Kanggo informasi lengkap babagan kesalahan lan versi sing kena pengaruh kesalahan, deleng kaca Pangkalan Pengetahuan ing Intel® websitus.
Informasi sing gegandhengan
Pangkalan Pengetahuan
DSP Builder kanggo Intel FPGAs Advanced Blockset Sajarah Revisi
| Versi | Tanggal | Katrangan |
| 22.4 | 2022.12.12 | Added Matrix Multiply Engine Design Example. |
| 22.3 | 2022.09.30 | • Kinerja sing luwih apik:
- DSP Builder saiki nggunakake blok FP DSP kanggo FP16 lan Bfloat16, dibunderake kanthi bener, Tambah, Sub or AddSub ing piranti Intel Agilex - Nyedhiyani akses menyang arsitektur DSP abot lan DSP cahya kanggo log eksponensial lan alami ing blok DSP Builder. - panggunaan logika FP FFT sing luwih apik kanggo rong format FP presisi ngisor: FP16 lan FP19. • Integrasi apik saka desain DSP Builder karo IP liyane ing Desainer Platform. - DSP Builder ora mbukak gulungan nanging nyimpen vektor sinyal kompleks (opsional) minangka entitas saluran tunggal. - Sampeyan uga bisa nemtokake peran khusus kanggo saluran kasebut. DSP Builder kanthi otomatis nemtokake macem-macem saluran kanthi jeneng unik kanthi prefixing antarmuka karo jeneng model DSP Builder. • Apik konfigurasi gawan saka FFT pamblokiran kanggo nyilikake kasalahan nalika ngganti paramèter FFT. • kasedhiya pilihan kanggo ngreset negara internal saka FIR pamblokiran sak reset anget. • Added perpustakaan sing ngemot pamblokiran Simulink sing DSP Builder designs support. |
| 22.2 | 2022.03.30 | Ngurangi jumlah iterasi internal ing CORDIC blok kanggo nyuda panggunaan sumber daya lan nambah akurasi. |
| terus… | ||
| Versi | Tanggal | Katrangan |
| 22.1 | 2022.06.30 | • Added latensi nglaporake menyang GPIO blok (padha karo latensi nglaporake ing Saluran IO
blok). • Added Sato back-to-back VFFT pemblokiran, sing ndhukung terus streaming data nalika ukuran FFT diganti tanpa kudu flush pipo FFT. • Dhukungan tambahan kanggo Intel Cyclone 10 LP, Intel MAX 10, Cyclone IV E + GX ing DSP Builder Advanced Pro. Sampeyan kudu ngumpulake RTL sing digawe karo edisi Intel Quartus Std. • Extended maca-akses kontrol mekanisme kanggo SharedMems pamblokiran • Apik DSP pemblokiran packing dening nindakake Tambah, Sub, lan Mux menyang dinamis AddSub pamblokiran |
| 21.4 | 2021.12.30 | Ditambahake AXI4StreamReceiver lan AXI4StreamTransmitter menyang Streaming perpustakaan |
| 21.3 | 2021.09.30 | • Added DFT Library karo DFT, ReorderBlock, lan ReorderAndRescale pamblokiran
• Added support kanggo piranti Cyclone V • Added advisory akses maca (RA) kontrol kanggo pamblokiran memori DSP Builder • Added simplified back-to-back FFT blockset • Kapabilitas ditambahake kanggo nginstal DSP Builder mandiri tanpa mbutuhake instalasi Intel Quartus Prime sing kompatibel karo versi |
| 21.1 | 2021.06.30 | • Ditambahake Mesin Negara Finite blok lan desain example.
• support Added kanggo versi MATLAB: R2020b |
| 20.1 | 2020.04.13 | Pamilih piranti dibusak ing Parameter piranti panel. |
| 2019.09.01 | Dhukungan tambahan kanggo piranti Intel Agilex®. | |
| 19.1 | 2019.04.01 | • Added support kanggo rong jinis floating-titik anyar float16_m7 (bfloat) lan float19_m10.
• Added fitur latensi gumantung. • Added FIFO buffer isi-tingkat Reporting. |
| 18.1 | 2018.09.17 | • Added ngimpor HDL.
• Added C ++ model piranti lunak. |
| 18.0 | 2018.05.08 | • Added support kanggo minimalake reset otomatis designs DSP Builder. Reset minimalake nemtokake set minimal saka ndhaftar ing desain sing mbutuhake reset, nalika nahan fungsi desain kang bener. Ngurangi jumlah ndhaptar sing direset DSP Builder bisa nambah kualitas asil, yaiku nyuda area lan nambah Fmax.
• Added support kanggo kothak dicokot menyang SharedMem pamblokiran. Kothak kasebut nyedhiyakake fungsi sing padha karo dhukungan lapangan bit sing ana ing RegField lan RegOut pamblokiran. • Ditambahake dhukungan beta kanggo ngimpor HDL, sing nggabungake desain sintesis VHDL utawa Verilog HDL menyang desain DSP Builder. Sampeyan banjur bisa cosimulate desain diimpor karo komponen DSP Builder Simulink. Impor HDL kalebu antarmuka panganggo minimal, nanging mbutuhake sawetara persiyapan manual. Kanggo nggunakake fitur iki, sampeyan mbutuhake lisensi kanggo alat MathWorks HDL Verifier. |
| 17.1 | 2017.11.06 | • Added super-sample NCO desain example.
• Dhukungan tambahan kanggo piranti Intel Cyclone® 10 lan Intel Stratix® 10. • kedadean dibusak saka Sinyal pamblokiran. • Dibusak pilihan WYSIWYG ing Info Sintesis pamblokiran. |
| 17.0 | 2017.05.05 | • Rebranded minangka Intel
• Ditinggalake Sinyal pamblokiran • Added Gaussian lan Random Number Generator desain examples • Added supers ukuran maneko rupoampmimpin FFT desain example • Ditambahake HibridVFFT pamblokiran • Ditambahake UmumVTwiddle lan UmumMultVTwiddle pamblokiran |
| 16.1 | 2016.11.10 | • Added 4-saluran 2-antena DUC lan DDC kanggo desain referensi LTE
• Added BFU_simple pemblokiran • Digawe Standard lan Pro edition. Pro ndhukung Arria 10 piranti; Standar ndhukung kabeh kulawarga liyane. • Deprecated ing Sinyal pamblokiran • fungsi Added kanggo nyetel setelan antarmuka Avalon-MM ing menu DSP Builder |
| terus… | ||
| Versi | Tanggal | Katrangan |
| 16.0 | 2016.05.02 | • perpustakaan direorganisasi
• Apik asil lempitan ing MAX 10 piranti • Added desain anyar examples: - Generator Nomer Acak Gaussian - DUC_4C4T4R lan DDC_4C4T4R LTE konversi digital munggah lan mudhun • Ditambahake strategi pruning FFT anyar: prune_to_widths() |
| 15.1 | 2015.11.11 | • Ditinggalake Run Quartus II lan Run Modelsim pamblokiran
• Added jam nyebrang support • Added reconfigurable FIR saringan • Antarmuka bus sing luwih apik: - Apik mriksa kesalahan lan nglaporake - Akurasi simulasi sing luwih apik - Apik implementasine logika budak bus - Apik nyebrang jam • Ngganti sawetara antarmuka Avalon-MM • Ditambahake blok anyar: — Njupuk Nilai — Fanout — ngaso — Vectorfanout • Added IIR: full-rate fixed-point lan IIR: full-rate floating-point demo • Added ngirim lan nampa desain referensi modem |
| 15.0 | Mèi 2015 | • Added support kanggo SystemVerilog output
• Added perpustakaan kenangan external • Ditambahake Memori njaba pamblokiran • Ditambahake anyar Allow nulis ing loro bandar parameter kanggo DualMem pamblokiran • Paramèter diganti ing AvalonMMSlaveSettings pamblokiran |
| 14.1 | Desember 2014 | • Added support kanggo Arria 10 pamblokiran hard-ngambang-titik
• Ditambahake BusStimulus lan BusStimulusFileReader pamblokiran kanggo memori-dipetake ndhaftar desain example. • Added pemblokiran AvalonMMSlaveSettings lan DSP Builder> Antarmuka Avalon> Abdi Avalon-MM pilihan menu • Dibusak paramèter bus saka Control lan pamblokiran Signal • Dibusak ex desain ing ngisor ikiamples: — Konverter Ruang Warna (Resource Sharing Folding) - Interpolasi Filter FIR karo Koefisien Nganyari - Filter FIR Primitif (Resource Sharing Folding) - Tunggal-Stage Filter IIR (Resource Sharing Folding) - Telu-stage Filter IIR (Resource Sharing Folding) • Added sistem-in-the-loop support • Ditambahake blok anyar: - Klasifikasi titik ngambang - Floating-point multiply nglumpukake - Nambahake fungsi hypotenuse menyang blok matematika • Added desain examples: - Konverter ruang warna - Komplek FIR - CORDIC saka Blok Primitif - Pengurangan faktor puncak - Lempitan FIR — Variabel Integer Rate Decimation Filter - Urut vektor - urutan lan iteratif |
| terus… | ||
| Versi | Tanggal | Katrangan |
| • Desain referensi sing ditambahake:
- Pengurangan faktor puncak - Direct RF karo Synthesizable Testbench - Filter Decimation Dinamis - Filter Decimation sing bisa dikonfigurasi maneh — Variabel Integer Rate Decimation Filter • Dibusak folder enggo bareng sumber • Dianyari folder ALU |
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| 14.0 | Juni 2014 | • Added support kanggo MAX 10 FPGAs.
• Dhukungan dibusak kanggo piranti Cyclone III lan Stratix III • Apik DSP Builder Run ModelSim opsi, sing saiki ngijini sampeyan kanggo mbukak ModelSim kanggo desain tingkat ndhuwur utawa submodules individu • Ngganti generasi HDL menyang direktori level piranti (ing direktori target RTL sing ditemtokake) tinimbang ing hierarki direktori • Added maca sinyal ing antarmuka bis • Added port cetha ing FIFO • 13 pamblokiran FFT ora digunakake • Added desain anyar examples: - Antarmuka Avalon-ST (Input lan Output FIFO Buffer) karo Backpressure - Antarmuka Avalon-ST (Output FIFO Buffer) karo Backpressure - Fungsi matematika titik tetep - ROOT kuadrat pecahan nggunakake CORDIC - Normalisasi - FFT paralel - FFT Floating-Point Paralel - ROOT kothak nggunakake CORDIC — FFT/iFFT sing bisa dialihake — FFT Titik Tetap Ukuran Variabel — FFT Titik Tetap Ukuran Variabel tanpa Blok BitReverseCoreC — Variabel-Size Fixed-Point iFFT — Variabel-Size Fixed-Point iFFT tanpa BitReverseCoreC Block — Variabel-Ukuran Floating-Titik FFT — FFT Floating-Point Ukuran Variabel tanpa Blok BitReverseCoreC — Variabel-Ukuran Floating-Point iFFT — Variabel-Ukuran Floating-Point iFFT tanpa BitReverseCoreC Block • Ditambahake blok anyar: - Anchored Tundha - Diaktifake Tundha Line - Aktifake Umpan Balik Tundha - FFT2P, FFT4P, FFT8P, FFT16P, FFT32P, lan FFT64P — FFT2X, FFT4X, FFT8X, FFT16X, FFT32X, lan FFT64X — FFT2, FFT4, VFFT2, lan VFFT4 - Umum Multitwiddle lan Umum Twiddle (GeneralMultiTwiddle, GeneralTwiddle) — Hibrida FFT (Hybrid_FFT) - Parallel Pipelined FFT (PFFT_Pipe) - Siap |
| 13.1 | November 2013 | • Mbusak dhukungan kanggo piranti ing ngisor iki:
- Arria GX - Siklon II - HardCopy II, HardCopy III, lan HardCopy IV - Stratix, Stratix II, Stratix GX, lan Stratix II GX • Apik aliran lempitan ALU • Added fungsi anyar kanggo pemblokiran Math. |
| terus… | ||
| Versi | Tanggal | Katrangan |
| • Added Simulink fi blok pilihan kanggo Const, DualMem, lan LUT pamblokiran
• Added desain anyar examples: - Variabel-tliti nyata-wektu FFT - Interpolasi Filter FIR kanthi koefisien nganyari - Beamformer wektu tundha • Ditambahake blok anyar: - Anchored Tundha - Polinomial - TwiddleAngle - TwiddleROM lan TwiddleROMF - VariableBitReverse — VFFT |
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| 13.0 | Mèi 2013 | • Pemblokiran piranti sing dianyari karo menu Pamilih Piranti anyar.
• Ditambahake blok ModelPrim anyar: - Konst Mult - Dibagi - MinMax - Negate - Produk skalar • Added sangang pamblokiran FFT anyar • Ditambahake sepuluh demonstrasi FFT anyar |
| 12.1 | November 2012 | • Added fitur lempitan ALU
• Added meningkat tliti opsi floating-titik • Nambahake blok ModelPrim anyar ing ngisor iki: - AddSub - AddSubFused - CmpCtrl — Matématika - Maksimum lan Minimal - MinMaxCtrl - Babak — Trig • Nambahake pamblokiran FFT anyar ing ngisor iki: - Deteksi Tepi (EdgeDetect) - Pulse Divider (PulseDivider) - Pengganda Pulsa (PulseMultiplier) — Bit-Reverse FFT kanthi Output Alami (FFT_BR_Natural) • Added ing ngisor iki FIR desain anyaramples: - Super-sampFilter FIR decimating - Super-sampFilter FIR pecahan • Added posisi, kacepetan, lan kontrol saiki kanggo motor AC (karo ALU lempitan) desain example |
Informasi sing gegandhengan
DSP Builder Advanced Blockset Handbook
Requirements Sistem
- DSP Builder kanggo Intel FPGAs terintegrasi karo alat MathWorks MATLAB lan Simulink lan piranti lunak Intel Quartus® Prime.
- Priksa manawa paling ora siji versi alat MathWorks MATLAB lan Simulink kasedhiya ing workstation sadurunge sampeyan nginstal DSP Builder kanggo Intel FPGAs. Sampeyan kudu nggunakake versi sing padha saka piranti lunak Intel Quartus Prime lan DSP Builder kanggo Intel FPGA. DSP Builder kanggo Intel FPGA mung ndhukung versi 64-bit MATLAB.
- Saka v18.0, DSP Builder kanggo Intel FPGAs pamblokiran majeng kasedhiya kanggo Intel Quartus Prime Pro Edition lan Intel Quartus Prime Standard Edition. DSP Builder kanggo blokset standar Intel FPGAs mung kasedhiya kanggo Intel Quartus Prime Standard Edition.
Tabel 2. DSP Builder kanggo Intel FPGAs MATLAB Dependensi
| Versi | Versi sing Didhukung MATLAB | ||
| DSP Builder Standard Blockset | DSP Builder Advanced Blockset | ||
| Intel Quartus Prime Standard Edition | Intel Quartus Prime Pro Edition | ||
| 22.4 | Ora kasedhiya | R2022a R2021b R2021a R2020b R2020a | |
| 22.3 | Ora kasedhiya | R2022a R2021b R2021a R2020b R2020a | |
| 22.1 | Ora kasedhiya | R2021b R2021a R2020b R2020a R2019b | |
| 21.3 | Ora kasedhiya | R2021a R2020b R2020a R2019b R2019a | |
| 21.1 | Ora kasedhiya | R2020b R2020a R2019b R2019a R2018b | |
| 20.1 | Ora kasedhiya | R2019b R2019a R2018b R2018a R2017b R2017a | |
| 19.3 | Ora kasedhiya | R2019a R2018b R2018a R2017b | |
| terus… | |||
| Versi | Versi sing Didhukung MATLAB | ||
| DSP Builder Standard Blockset | DSP Builder Advanced Blockset | ||
| Intel Quartus Prime Standard Edition | Intel Quartus Prime Pro Edition | ||
| R2017a R2016b | |||
| 19.1 | Ora didhukung | R2013a | R2018b R2018a R2017b R2017a R2016b |
| 18.1 | R2013a | R2013a | R2018a R2017b R2017a R2016b |
| 18.0 | R2013a | R2013a | R2017b R2017a R2016b R2016a R2015b |
| 17.1 | R2013a | R2013a | R2016a R2015b R2015a R2014b R2014a R2013b |
Cathetan:
DSP Builder kanggo blokset canggih Intel FPGA nggunakake jinis titik tetep Simulink kanggo kabeh operasi lan mbutuhake versi Simulink Fixed Point sing dilisensi. Intel uga nyaranake DSP System Toolbox lan Communications System Toolbox, sing sawetara desain examples nggunakake.
Informasi sing gegandhengan
Instalasi lan Lisensi Piranti Lunak Intel.
DSP Builder kanggo Cathetan Rilis Intel® FPGAs 9
Dokumen / Sumber Daya
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intel DSP Builder kanggo Intel FPGAs [pdf] Pandhuan pangguna DSP Builder kanggo Intel FPGAs, Builder kanggo Intel FPGAs, Intel FPGAs, FPGAs |