DSP Builder ya Intel FPGAs
Zambiri Zamalonda
Chogulitsacho chimatchedwa DSP Builder for Intel FPGAs. Ndi pulogalamu yamapulogalamu yomwe imalola ogwiritsa ntchito kupanga ndi kukhazikitsa ma algorithms a digito (DSP) pa Intel FPGAs. Chidachi chimapereka chithunzithunzi chojambula chomwe chimagwirizanitsa ndi The MathWorks MATLAB ndi chida cha Simulink, kulola ogwiritsa ntchito kupanga machitidwe a DSP pogwiritsa ntchito njira ya block block. Chidacho chili ndi mitundu yosiyanasiyana, pomwe mtundu waposachedwa ndi 22.4. Chogulitsacho chadutsamo zosinthidwa zingapo, ndikuwunikiridwa kulikonse kumabweretsa zatsopano, kukonza zolakwika, ndi kukonza. Tsamba lokonzanso mbiri yakale limapereka chidule cha zosintha zomwe zasinthidwa mu mtundu uliwonse. Chogulitsacho chili ndi mitundu iwiri ya blockset: blockset yokhazikika ndi blockset yapamwamba. Chotsekereza chokhazikika chikupezeka cha Intel Quartus Prime Standard Edition, pomwe blockset yapamwamba ikupezeka onse Intel Quartus Prime Pro Edition ndi Intel Quartus Prime Standard Edition. Chogulitsacho chili ndi zofunikira zamakina zomwe ziyenera kukwaniritsidwa kuti zikhazikike bwino ndikugwiritsa ntchito. Pamafunika mtundu umodzi wa The MathWorks MATLAB ndi chida cha Simulink, mothandizidwa ndi 64-bit mitundu ya MATLAB. Mtundu wa Intel Quartus Prime software uyenera kufanana ndi mtundu wa DSP Builder wa Intel FPGAs womwe ukugwiritsidwa ntchito. Chotchinga chapamwamba chimagwiritsa ntchito mitundu yokhazikika ya Simulink pazochita zonse ndipo imafuna mitundu yovomerezeka ya Simulink Fixed Point. Intel imalimbikitsanso DSP System Toolbox ndi Communications System Toolbox kuti zigwire ntchito zina.
Malangizo Ogwiritsira Ntchito Zogulitsa
- Onetsetsani kuti muli ndi mtundu wogwirizana wa The MathWorks MATLAB ndi chida cha Simulink chomwe chayikidwa pamalo anu antchito. Chidachi chimangothandizira mitundu ya 64-bit ya MATLAB.
- Onetsetsani kuti mwayika pulogalamu yoyenera ya Intel Quartus Prime. Mtunduwu uyenera kufanana ndi mtundu wa DSP Builder wa Intel FPGA womwe mukugwiritsa ntchito.
- Yambitsani DSP Builder ya Intel FPGAs ndikutsegula mawonekedwe azithunzi.
- Konzani dongosolo lanu la DSP pogwiritsa ntchito njira ya block diagram yoperekedwa ndi chida. Gwiritsani ntchito ma block ndi mawonekedwe omwe alipo kuti mupange algorithm yomwe mukufuna.
- Tengani advantage wa mitundu ya Simulink yokhazikika pamachitidwe onse omwe mwapanga. Onetsetsani kuti muli ndi zilolezo zofunika za Simulink Fixed Point.
- Ngati mukufuna zina zowonjezera, ganizirani kugwiritsa ntchito DSP System Toolbox ndi Communications System Toolbox, zomwe Intel amalimbikitsa.
- Mukamaliza kupanga, mutha kupanga zofunikira files popanga Intel FPGA.
Potsatira malangizowa, mudzatha kupanga ndi kukhazikitsa ma algorithms a DSP pa Intel FPGAs pogwiritsa ntchito DSP Builder ya Intel FPGAs.
DSP Builder for Intel® FPGAs Release Notes
Zambiri Zogwirizana
- Knowledge Base
- Kuyika Mapulogalamu ndi Kupereka Chilolezo
Zolakwitsa
Errata ndi zolakwika kapena zolakwika, zomwe zingapangitse kuti malonda apatukane ndi zomwe zasindikizidwa. Zolemba zikuphatikiza zolakwika, zofotokozera zosadziwika bwino, kapena zomwe zasiyidwa pazotsatira zomwe zasindikizidwa kapena zolemba zamalonda.
Kuti mumve zambiri za errata ndi mitundu yomwe yakhudzidwa ndi zolakwika, onani tsamba la Knowledge Base la Intel®. webmalo.
Zambiri Zogwirizana
Knowledge Base
DSP Builder for Intel FPGAs Advanced Blockset Revision History
| Baibulo | Tsiku | Kufotokozera |
| 22.4 | 2022.12.12 | Zowonjezera Matrix Multiply Engine Design Example. |
| 22.3 | 2022.09.30 | • Kuchita bwino:
- DSP Builder tsopano imagwiritsa ntchito chipika cha FP DSP cha FP16 ndi Bfloat16, chozunguliridwa bwino, Onjezani, Sub or AddSub pazida za Intel Agilex - Anapereka mwayi wofikira ku DSP yolemetsa komanso yopepuka ya DSP yolowera motsogola komanso zachilengedwe mu blockset ya DSP Builder. - kugwiritsa ntchito kwanzeru kwa FP FFT pamawonekedwe awiri otsika kwambiri a FP: FP16 ndi FP19. • Kuphatikizana bwino kwa mapangidwe a DSP Builder ndi IP ina mu Platform Designer. - DSP Builder samamasula koma amasunga ma vector a (mwasankha) ma siginecha ovuta ngati gawo limodzi. - Mutha kugawanso gawo lokhazikika panjira. DSP Builder imadzipatsa yokha makoswe angapo okhala ndi mayina apadera poyika mawonekedwe ake ndi dzina lachitsanzo la DSP Builder. • Kupititsa patsogolo kasinthidwe kachitidwe ka FFT midadada kuti muchepetse zolakwika posintha magawo a FFT. • Anapatsidwa mwayi bwererani dziko lamkati la MOYO block panthawi yobwezeretsanso kutentha. • Anawonjezera laibulale yomwe ili ndi midadada ya Simulink yomwe DSP Builder imapanga imathandizira. |
| 22.2 | 2022.03.30 | Kuchepetsa kubwereza kwamkati mkati CORDIC block kuti muchepetse kugwiritsa ntchito zida ndikuwonjezera kulondola. |
| anapitiriza… | ||
| Baibulo | Tsiku | Kufotokozera |
| 22.1 | 2022.06.30 | • Anawonjezera malipoti a latency ku GPIO block (zofanana ndi lipoti la latency pa Channel IO
ma block). • Anawonjezera wosakanizidwa kumbuyo-kumbuyo Chithunzi cha VFFT block, yomwe imathandizira kusuntha kosalekeza kwa data pomwe kukula kwa FFT kumasintha popanda kutulutsa payipi ya FFT. • Zowonjezera zothandizira Intel Cyclone 10 LP, Intel MAX 10, Cyclone IV E+GX mu DSP Builder Advanced Pro. Muyenera kupanga RTL yopangidwa ndi Intel Quartus Std edition. • Anawonjezera njira yowongolera zowerengera kuti SharedMems chipika • Kupititsa patsogolo kulongedza kwa block ya DSP posintha Onjezani, Sub,ndi Mux ku dynamic AddSub chipika |
| 21.4 | 2021.12.30 | Zowonjezedwa AXI4StreamReceiver ndi AXI4StreamTransmitter ku ku Kukhamukira laibulale |
| 21.3 | 2021.09.30 | • Anawonjezera DFT Library ndi DFT, ReorderBlock,ndi ReorderAndRescale midadada
• Zowonjezera zothandizira zida za Cyclone V • Kuwonjezedwa kwa upangiri wowerengera zowongolera (RA) ku midadada yokumbukira ya DSP Builder • Onjezani chosavuta cham'mbuyo cham'mbuyo cha FFT • Kuthekera kowonjezera kukhazikitsa DSP Builder standalone popanda kuyika Intel Quartus Prime yogwirizana ndi mtundu |
| 21.1 | 2021.06.30 | • Wowonjezera Finite State Machine block ndi design example.
• Zowonjezera zothandizira mtundu wa MATLAB: R2020b |
| 20.1 | 2020.04.13 | Chosankha chida chachotsedwa mkati Chipangizo Parameters gulu. |
| 2019.09.01 | Zowonjezera zothandizira zida za Intel Agilex®. | |
| 19.1 | 2019.04.01 | • Zowonjezera zothandizira mitundu iwiri yatsopano yoyandama ya float16_m7 (bfloat) ndi float19_m10.
• Anawonjezera amadalira latency Mbali. • Anawonjezera FIFO buffer kudzaza-level lipoti. |
| 18.1 | 2018.09.17 | • Anawonjezera kuitanitsa kwa HDL.
• Zowonjezera mapulogalamu a C ++. |
| 18.0 | 2018.05.08 | Thandizo lowonjezera pakuchepetsa kukonzanso zodziwikiratu za mapangidwe a DSP Builder. Kuchedwetsanso kuchepetsa kumatsimikizira zolembera zocheperako pamapangidwe omwe amafunikira kukonzanso, ndikusunga magwiridwe antchito olondola a mapangidwewo. Kuchepetsa chiwerengero cha kaundula omwe DSP Builder akhazikitsanso angapereke zotsatira zabwino monga kuchepetsedwa kwa malo ndi kuchuluka kwa Fmax.
• Anawonjezera thandizo kwa minda pang'ono kwa SharedMem chipika. Magawowa amapereka magwiridwe antchito ofanana ndi othandizira omwe alipo mu gawo la RegField ndi RegOut midadada. • Thandizo la beta lowonjezera la HDL loitanitsa kunja, lomwe limaphatikizapo ma VHDL kapena Verilog HDL opangidwa ndi mapangidwe a DSP Builder. Mutha kufananiza kapangidwe kake ndi zida za DSP Builder Simulink. Kulowetsa kwa HDL kumaphatikizapo mawonekedwe ocheperako, koma kumafuna kukhazikitsidwa kwapamanja. Kuti mugwiritse ntchito izi, mufunika chilolezo cha chida cha MathWorks HDL Verifier. |
| 17.1 | 2017.11.06 | • Anawonjezera super-sampndi NCO design example.
• Zowonjezera zothandizira pa zipangizo za Intel Cyclone® 10 ndi Intel Stratix® 10. • Kuchotsa zochitika za Zizindikiro chipika. • Zichotsedwa WYSIWYG njira pa SynthesisInfo chipika. |
| 17.0 | 2017.05.05 | • Adasinthidwanso kukhala Intel
• Adasiya ntchito Zizindikiro chipika • Anawonjezera Gaussian ndi Random Number Generator design examples • Anawonjezera variable-size supersampanatsogolera FFT mapangidwe example • Wowonjezera Mtengo wa HybridVFFT chipika • Wowonjezera GeneralVTwiddle ndi GeneralMultVTwiddle midadada |
| 16.1 | 2016.11.10 | • Anawonjezera 4-channel 2-antenna DUC ndi DDC kwa LTE reference design
• Anawonjezera BFU_simple block • Anapanga ma Standard ndi Pro editions. Pro imathandizira zida za Arria 10; Standard imathandizira mabanja ena onse. • Anasiya ntchito Zizindikiro chipika • Ntchito zowonjezeredwa zokhazikitsira mawonekedwe a Avalon-MM mu menyu ya DSP Builder |
| anapitiriza… | ||
| Baibulo | Tsiku | Kufotokozera |
| 16.0 | 2016.05.02 | • Kukonzanso malaibulale
• Zotsatira zopinda bwino pazida za MAX 10 • Anawonjezera mapangidwe atsopano exampzochepa: - Gaussian Random Number Generator - DUC_4C4T4R ndi DDC_4C4T4R LTE digito-mmwamba ndi pansi-kutembenuka • Tawonjeza njira yatsopano yodulira ya FFT: prune_to_widths() |
| 15.1 | 2015.11.11 | • Adasiya ntchito Thamangani Quartus II ndi Thamangani Modelsim midadada
• Anawonjezera wotchi kuwoloka thandizo • Onjezani zosefera za FIR zosinthikanso • Malo olumikizirana mabasi owongolera: -Kuwunika kolakwika ndi kupereka malipoti - Kuwongolera kulondola kayeseleledwe - Kupititsa patsogolo malingaliro a akapolo a basi - Kuwoloka koloko bwino • Anasintha malo ena a Avalon-MM • Adawonjeza midadada yatsopano: — Jambulani Makhalidwe — Fanout — Imani kaye — Vectorfanout • IIR Yowonjezera: malo okhazikika ndi IIR: ma demo oyandama • Anawonjezera kufalitsa ndi kulandira modemu zofotokozera kapangidwe |
| 15.0 | Meyi 2015 | • Anawonjezera thandizo kwa SystemVerilog linanena bungwe
• Anawonjezera kunja kukumbukira laibulale • Wowonjezera Memory Yakunja chipika • Wowonjezera watsopano Lolani kulemba pamadoko onse awiri parameter kwa DualMem chipika • Kusintha magawo kuyatsa AvalonMMslaveSettings chipika |
| 14.1 | Disembala 2014 | • Zowonjezera zothandizira midadada ya Arria 10 yolimba yoyandama
• Anawonjezera BusStimulus ndi BusStimulusFileOwerenga amatchinga ku ma regista omwe ali ndi mapu okumbukira kapangidwe kakaleample. • Anawonjezera AvalonMMSlaveSettings chipika ndi DSP Builder> Avalon Interfaces> Avalon-MM kapolo menyu njira • Kuchotsa magawo a mabasi ku Control and Signal blocks • Anachotsa chitsanzo chotsatirachiampzochepa: - Colour Space Converter (Kugawana Zothandizira) - Kutanthauzira FIR FIR ndi Kusintha Coefficients - Sefa Yoyamba Yoyambira (Kugawana Zogawana) — Mmodzi-StagE IIR Sefa (Kugawana Zogawana Zothandizira) - ZitatutagE IIR Sefa (Kugawana Zogawana Zothandizira) • Anawonjezera dongosolo-mu-kuzungulira thandizo • Adawonjeza midadada yatsopano: - Gulu loyandama - Kuchulukitsa kwa malo oyandama kumawunjika - Anawonjezera ntchito ya hypotenuse pa masamu block • Mapangidwe owonjezera exampzochepa: - Chosinthira danga lamtundu - MOYO Wovuta - CORDIC yochokera ku Primitive Blocks - Crest factor kuchepetsa - Kupinda MOTO - Zosefera Zosiyanasiyana za Integer Rate Decimation - Mtundu wa Vector - wotsatizana komanso wobwerezabwereza |
| anapitiriza… | ||
| Baibulo | Tsiku | Kufotokozera |
| • Mapangidwe owonjezera:
- Crest factor kuchepetsa - Direct RF yokhala ndi Synthesizable Testbench - Sefa ya Dynamic Decimation - Sefa yosinthiranso Decimation - Zosefera Zosiyanasiyana za Integer Rate Decimation • Chachotsedwa gwero kugawana chikwatu • Foda ya ALU yosinthidwa |
||
| 14.0 | Juni 2014 | • Zowonjezera zothandizira pa MAX 10 FPGAs.
• Kuchotsa kuthandizira kwa Cyclone III ndi Stratix III zipangizo • Zasinthidwa DSP Builder Run ModelSim kusankha, zomwe tsopano zimakupatsani mwayi woyendetsa ModelSim pamapangidwe apamwamba kapena ma submodule amunthu • Tinasintha kupanga HDL kukhala chikwatu cha mulingo wa chipangizo (pansi pa chikwatu chandandale cha RTL) m'malo mwa mndandanda wazinthu • Anawonjezera kuwerenga chizindikiro pa mawonekedwe basi • Anawonjezera doko lomveka bwino pa FIFO • Mabuloko 13 a FFT adachotsedwa • Anawonjezera mapangidwe atsopano exampzochepa: - Chiyankhulo cha Avalon-ST (Zolowetsa ndi Zotulutsa FIFO Buffer) yokhala ndi Kumbuyo - Chiyankhulo cha Avalon-ST (Chotulutsa FIFO Buffer) chokhala ndi Kumbuyo - Ntchito za masamu zokhazikika - Muzu wagawo lalikulu pogwiritsa ntchito CORDIC - Normalizer - Kufanana kwa FFT - Parallel Floating-Point FFT - Mizu yayikulu pogwiritsa ntchito CORDIC - Kusintha FFT/iFFT - Kusintha-Kukula Kokhazikika-Mfundo FFT - Kusinthana-Kukula Kwambiri Fixed-Point FFT popanda BitReverseCoreC Block - Kukula-Kukula Kokhazikika-Point iFFT - Kukula-Kukula Kokhazikika-Point iFFT yopanda BitReverseCoreC Block - Kukula-Kukula Koyandama-Point FFT - Kukula-Kukula Koyandama-Point FFT popanda BitReverseCoreC Block - Kukula-Kukula Koyandama-Point iFFT - Kukula-Kukula Kuyandama-Point iFFT yopanda BitReverseCoreC Block • Adawonjeza midadada yatsopano: - Kuchedwa kwa Anchored - Yathandizira Delay Line - Yathandizira Kuchedwa Kuyankha - FFT2P, FFT4P, FFT8P, FFT16P, FFT32P, ndi FFT64P - FFT2X, FFT4X, FFT8X, FFT16X, FFT32X, ndi FFT64X - FFT2, FFT4, VFFT2, ndi VFFT4 - General Multitwiddle ndi General Twiddle (GeneralMultiTwiddle, GeneralTwiddle) - Wophatikiza FFT (Hybrid_FFT) - Parallel Pipelined FFT (PFFT_Pipe) — Okonzeka |
| 13.1 | Novembala 2013 | • Chothandizira pazida zotsatirazi:
-Aria GX - Cyclone II - HardCopy II, HardCopy III, ndi HardCopy IV - Stratix, Stratix II, Stratix GX, ndi Stratix II GX • Kuyenda bwino kwa ALU kopinda • Anawonjezera ntchito zatsopano ku Math block. |
| anapitiriza… | ||
| Baibulo | Tsiku | Kufotokozera |
| • Anawonjezera njira ya Simulink fi block ku mabatani a Const, DualMem, ndi LUT
• Anawonjezera mapangidwe atsopano exampzochepa: - Zosintha-zolondola zenizeni zenizeni FFT - Kutanthauzira FIR FIR yokhala ndi ma coefficients osintha - Kuchedwetsa nthawi beamformer • Adawonjeza midadada yatsopano: - Kuchedwa kwa Anchored - Polynomial -TwiddleAngle - TwiddleROM ndi TwiddleROMF - VariableBitReverse - VFF |
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| 13.0 | Meyi 2013 | • Chida chosinthidwa chokhala ndi menyu Yatsopano Yosankha Chipangizo.
• Anawonjezera midadada yatsopano ya ModelPrim: - Const Mult - Gawani - MinMax - Negate - Scalar Product • Anawonjezera midadada isanu ndi inayi ya FFT • Anawonjezera ziwonetsero khumi zatsopano za FFT |
| 12.1 | Novembala 2012 | • Anawonjezera ALU kupinda mbali
• Anawonjezera kumatheka mwatsatanetsatane zoyandama-mfundo njira • Onjezani midadada yatsopano ya ModelPrim: - AddSub - AddSubFused - CmpCtrl - Masamu - Maximum ndi Minimum - MinMaxCtrl - Chizungulire - Mwachidule • Onjezani midadada ya FFT yatsopanoyi: - Edge Detect (EdgeDetect) - Pulse Divider (PulseDivider) - Pulse Multiplier (PulseMultiplier) - Bit-Reverse FFT yokhala ndi Natural Output (FFT_BR_Natural) • Anawonjezera mawonekedwe atsopano a FIR omwe kale analiampzochepa: - Supersampndi kuchepetsa FIR fyuluta - Supersampndi FIR FIR fyuluta • Anawonjezera udindo, liwiro, ndi ulamuliro panopa AC motors (ndi ALU kupinda) kapangidwe example |
Zambiri Zogwirizana
DSP Builder Advanced Blockset Handbook
Zofunikira pa System
- DSP Builder ya Intel FPGAs imaphatikizana ndi MathWorks MATLAB ndi zida za Simulink komanso pulogalamu ya Intel Quartus® Prime.
- Onetsetsani kuti mtundu umodzi wa The MathWorks MATLAB ndi chida cha Simulink chilipo pamalo anu antchito musanayike DSP Builder ya Intel FPGAs. Muyenera kugwiritsa ntchito mtundu womwewo wa Intel Quartus Prime software ndi DSP Builder ya Intel FPGAs. DSP Builder ya Intel FPGAs imangothandizira mitundu ya 64-bit ya MATLAB.
- Kuchokera ku v18.0, DSP Builder for Intel FPGAs advanced blockset ikupezeka kwa Intel Quartus Prime Pro Edition ndi Intel Quartus Prime Standard Edition. DSP Builder ya Intel FPGAs blockset yokhazikika imapezeka ku Intel Quartus Prime Standard Edition yokha.
Table 2. DSP Builder for Intel FPGAs MATLAB Dependencies
| Baibulo | Mitundu Yothandizira ya MATLAB | ||
| DSP Builder Standard Blockset | DSP Builder Advanced Blockset | ||
| Intel Quartus Prime Standard Edition | Intel Quartus Prime Pro Edition | ||
| 22.4 | Sakupezeka | R2022a R2021b R2021a R2020b R2020a | |
| 22.3 | Sakupezeka | R2022a R2021b R2021a R2020b R2020a | |
| 22.1 | Sakupezeka | R2021b R2021a R2020b R2020a R2019b | |
| 21.3 | Sakupezeka | R2021a R2020b R2020a R2019b R2019a | |
| 21.1 | Sakupezeka | R2020b R2020a R2019b R2019a R2018b | |
| 20.1 | Sakupezeka | R2019b R2019a R2018b R2018a R2017b R2017a | |
| 19.3 | Sakupezeka | R2019a R2018b R2018a R2017b | |
| anapitiriza… | |||
| Baibulo | Mitundu Yothandizira ya MATLAB | ||
| DSP Builder Standard Blockset | DSP Builder Advanced Blockset | ||
| Intel Quartus Prime Standard Edition | Intel Quartus Prime Pro Edition | ||
| R2017a R2016b | |||
| 19.1 | Osathandizidwa | R2013a | R2018b R2018a R2017b R2017a R2016b |
| 18.1 | R2013a | R2013a | R2018a R2017b R2017a R2016b |
| 18.0 | R2013a | R2013a | R2017b R2017a R2016b R2016a R2015b |
| 17.1 | R2013a | R2013a | R2016a R2015b R2015a R2014b R2014a R2013b |
Zindikirani:
DSP Builder for Intel FPGAs advanced blockset imagwiritsa ntchito mitundu yokhazikika ya Simulink pazochita zonse ndipo imafuna mitundu yovomerezeka ya Simulink Fixed Point. Intel imalimbikitsanso DSP System Toolbox ndi Communications System Toolbox, zomwe ena amapanga kaleamples ntchito.
Zambiri Zogwirizana
Intel Software Installation ndi Licensing.
DSP Builder for Intel® FPGAs Release Notes 9
Zolemba / Zothandizira
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Intel DSP Builder ya Intel FPGAs [pdf] Buku Logwiritsa Ntchito DSP Builder for Intel FPGAs, Builder for Intel FPGAs, Intel FPGAs, FPGAs |