DSP Faufale mo Intel FPGAs
Fa'amatalaga o oloa
O le oloa e taʻua o le DSP Builder mo Intel FPGAs. O se meafaigaluega faakomepiuta e mafai ai e tagata faʻaoga ona mamanuina ma faʻatino faʻasologa o faʻailoga numera (DSP) algorithms i luga ole Intel FPGAs. O le meafaigaluega e tuʻuina atu ai se faʻataʻitaʻiga faʻataʻitaʻi e tuʻufaʻatasia ma le MathWorks MATLAB ma le meafaigaluega Simulink, e faʻatagaina ai tagata faʻaoga e mamanuina faiga DSP e faʻaaoga ai se auala poloka poloka. O le meafaigaluega e eseese faʻaliliuga, ma le lomiga lata mai o le 22.4. O le oloa na faʻatautaia le tele o toe iloiloga, ma faʻasalalauga taʻitasi e faʻaalia ai foliga fou, faʻaleleia o pusa, ma faʻaleleia. O le laulau o tala fa'asolopito e maua ai se aotelega o suiga na faia i fa'aliliuga ta'itasi. O le oloa e lua lomiga poloka poloka: o le poloka masani ma le poloka maualuga. O lo'o avanoa le poloka masani mo Intel Quartus Prime Standard Edition, ae o lo'o avanoa le poloka maualuga mo Intel Quartus Prime Pro Edition ma le Intel Quartus Prime Standard Edition. O lo'o i ai i le oloa fa'atonuga faiga e mana'omia ona fa'amalieina mo le fa'apipi'iina lelei ma le fa'aogaina. E mana'omia ia le itiiti ifo ma le tasi le lomiga o le MathWorks MATLAB ma Simulink meafaigaluega, faatasi ai ma le lagolago mo 64-bit versions o le MATLAB. Ole Intel Quartus Prime software version e tatau ona fetaui ma le version o le DSP Builder mo Intel FPGA o loʻo faʻaaogaina. O lo'o fa'aogaina e le poloka fa'apitoa ituaiga Simulink fa'amautu mo fa'agaioiga uma ma mana'omia lomiga laiseneina o Simulink Fixed Point. E fautuaina foi e Intel le DSP System Toolbox ma le Communications System Toolbox mo galuega faaopoopo.
Fa'atonuga o le Fa'aaogaina o Mea
- Ia mautinoa o loʻo i ai sau faʻamatalaga fetaui o le MathWorks MATLAB ma Simulink meafaigaluega faʻapipiʻi i luga o lau fale faigaluega. E na'o le 64-bit versions o le MATLAB e lagolagoina e le meafaigaluega.
- Ia mautinoa o loʻo ia te oe le faʻaoga talafeagai o le Intel Quartus Prime software faʻapipiʻi. Ole fa'asologa e tatau ona fetaui ma le DSP Builder mo Intel FPGA o lo'o e fa'aogaina.
- Tatala le DSP Builder mo Intel FPGA ma tatala le ata faʻataʻitaʻi.
- Fuafua lau polokalama DSP e faʻaaoga ai le faʻaogaina o ata poloka e saunia e le meafaigaluega. Fa'aoga poloka avanoa ma foliga e fausia ai lau algorithm e mana'omia.
- Ave advantage o ituaiga Simulink fa'amautu mo galuega uma i lau mamanu. Ia mautinoa o loʻo ia te oe laisene talafeagai mo Simulink Fixed Point.
- Afai e te mana'omia ni galuega fa'aopoopo, mafaufau e fa'aoga le DSP System Toolbox ma le Communications System Toolbox, lea e fautuaina e Intel.
- A maeʻa lau mamanu, e mafai ona e gaosia mea e manaʻomia files mo le faʻatulagaina o se Intel FPGA.
E ala i le mulimuli i nei faʻatonuga faʻaoga, o le a mafai ai ona e mamanuina lelei ma faʻatinoina DSP algorithms i luga ole Intel FPGA e faʻaaoga ai le DSP Builder mo Intel FPGAs.
DSP Builder mo Intel® FPGAs Fa'asalalauga Fa'amatalaga
Fa'amatalaga Fa'atatau
- Alafua o le Poto
- Fa'apipi'i ma Laisene
Erratum
O le Errata o ni faaletonu o galuega po'o ni mea sese, e ono mafua ai ona alu ese le oloa mai faʻamatalaga faʻasalalau. O fa'amaumauga o fa'amaumauga e aofia ai mea sese, fa'amatalaga le manino, po'o fa'aletonu mai fa'amatalaga fa'asalalau o lo'o iai nei po'o pepa o oloa.
Mo faʻamatalaga atoa i le mea sese ma faʻamatalaga o loʻo aʻafia i le sese, tagaʻi i le Knowledge Base itulau o le Intel® webnofoaga.
Fa'amatalaga Fa'atatau
Alafua o le Poto
DSP Builder mo Intel FPGAs Advanced Blockset Revision History
| Fa'aliliuga | Aso | Fa'amatalaga |
| 22.4 | 2022.12.12 | Fa'aopoopo le Matrix Multiply Engine Design Example. |
| 22.3 | 2022.09.30 | • Siitia le faatinoga:
- Ua fa'aaoga nei e le DSP Builder le poloka FP DSP mo le FP16 ma le Bfloat16, fa'ata'amilo sa'o, Faaopoopo, Sub or AddSub i luga ole masini Intel Agilex - Tuuina atu avanoa i le DSP mamafa ma le DSP faʻataʻitaʻiga malamalama mo faʻamatalaga faʻapitoa ma faʻanatura i le DSP Builder blockset. - fa'aleleia atili le fa'aogaina o le fa'aogaina o le FP FFT mo fa'asologa FP e lua maualalo: FP16 ma le FP19. • Fa'aleleia atili le tu'ufa'atasia o le DSP Builder designs ma isi IP ile Platform Designer. — DSP Builder e le tatalaina ae o lo'o tu'u fa'atasi vete o fa'ailoga lavelave e fai ma fa'alāpotopotoga e tasi. — E mafai foi ona e tofia se matafaioi masani i le alavai. DSP Builder e otometi lava ona tofia le tele o alalaupapa ma igoa tulaga ese e ala i le faʻapipiʻiina o le faʻaoga ma le igoa faʻataʻitaʻiga DSP Builder. • Fa'aleleia le fa'aogaina o le FFT poloka e faʻaitiitia ai mea sese pe a suia le FFT tapulaʻa. • Tuuina atu le filifiliga e toe setiina le tulaga totonu o le FIR poloka i le taimi o se seti mafanafana. • Fa'aopoopoina se faletusi o lo'o iai poloka Simulink lea e lagolagoina e le DSP Builder. |
| 22.2 | 2022.03.30 | Fa'aitiitia le faitau aofa'i i totonu CORDIC poloka e faʻaitiitia ai le faʻaogaina o punaoa ma faʻateleina le saʻo. |
| faaauau… | ||
| Fa'aliliuga | Aso | Fa'amatalaga |
| 22.1 | 2022.06.30 | • Fa'aopoopo le lipoti o le le tumau i le GPIO poloka (e tutusa ma le taofiofia o lipoti i luga o le Auala IO
poloka). • Fa'aopoopoina se fefiloi tua-i-tua VFFT poloka, lea e lagolagoina le faʻaauauina o faʻamaumauga pe a suia le tele o le FFT e aunoa ma le faʻafefeina o le paipa FFT. • Faaopoopo le lagolago mo Intel Cyclone 10 LP, Intel MAX 10, Cyclone IV E+GX i le DSP Builder Advanced Pro. E tatau ona e tu'ufa'atasia le RTL fa'atupuina ma le lomiga a le Intel Quartus Std. • Fa'alautele le faiga e pulea le faitau-faitau i SharedMems poloka • Fa'aleleia le fa'apipi'iina o poloka DSP e ala i le fa'aliliuina Faaopoopo, Sub, ma Mux i se malosi AddSub poloka |
| 21.4 | 2021.12.30 | Faaopoopo AXI4StreamReceiver ma AXI4StreamTransmitter i le Fa'asalalau faletusi |
| 21.3 | 2021.09.30 | • Faaopoopo le DFT Library ma DFT, Toe OrderBlock, ma Toe OrderAndRescale poloka
• Fa'aopoopo le lagolago mo masini a le Afa V • Fa'aopoopo le fa'atonuga o le faitau tusi (RA) fa'atonu i poloka manatua a le DSP Builder • Fa'aopoopo i ai se poloka FFT fa'asolo i tua • Fa'aopoopo le agava'a e fa'apipi'i ai le DSP Builder e aunoa ma le mana'omia o se fa'apipi'i Intel Quartus Prime e fetaui lelei. |
| 21.1 | 2021.06.30 | • Faaopoopo Masini Malo i'u poloka ma mamanu example.
• Fa'aopoopo le lagolago mo le MATLAB version: R2020b |
| 20.1 | 2020.04.13 | Ave'ese le masini filifilia i totonu Fa'ailoga o Mea laulau. |
| 2019.09.01 | Fa'aopoopo le lagolago mo masini Intel Agilex®. | |
| 19.1 | 2019.04.01 | • Fa'aopoopo le lagolago mo ituaiga fou e lua o le float16_m7 (bfloat) ma le float19_m10.
• Fa'aopoopo le fa'aoga fa'alagolago. • Fa'aopoopo le FIFO fa'atumu fa'atumu lipoti. |
| 18.1 | 2018.09.17 | • Fa'aopoopoina le HDL fa'aulufale mai.
• Fa'aopoopo C++ fa'ata'ita'iga polokalame. |
| 18.0 | 2018.05.08 | • Fa'aopoopo le lagolago mo le fa'aitiitiga otometi o fa'ata'ita'iga a le DSP Builder. Toe fa'aitiitiga fa'aitiitiga e fuafua ai le seti la'ititi o tusi resitala i se mamanu e mana'omia le toe fa'aleleia, a'o fa'atumauina le sa'o lelei o le fa'atinoga. Fa'aiti'itia le aofa'i o resitara e toe fa'atūina e le DSP Builder e mafai ona fa'aleleia atili le lelei o fa'ai'uga fa'apea fa'aititia le vaega ma fa'ateleina Fmax.
• Faaopoopo le lagolago mo fasi fanua i le SharedMem poloka. O nei fanua e maua ai galuega fa'atusa tutusa ma le lagolago ole fanua o lo'o i ai i le RegField ma RegOut poloka. • Fa'aopoopoina le lagolago beta mo le fa'aulufaleina mai o le HDL, lea e tu'ufa'atasia ai VHDL po'o Verilog HDL fa'atusa fa'atasi i totonu ole DSP Builder design. Ona mafai lea ona e fa'apipi'iina le mamanu fa'aulufale mai ma vaega o le DSP Builder Simulink. O le fa'aulufaleina mai o le HDL e aofia ai se fa'aoga la'ititi fa'aoga, ae mana'omia se seti tusi. Mo le fa'aogaina o lenei vaega, e te mana'omia se laisene mo le meafaigaluega MathWorks HDL Verifier. |
| 17.1 | 2017.11.06 | • Faaopoopo super-sample NCO mamanu example.
• Fa'aopoopoina le lagolago mo Intel Cyclone® 10 ma le Intel Stratix® 10 masini. • Aveese fa'ata'ita'iga o Fa'ailoga poloka. • Ave'ese le filifiliga WYSIWYG i luga SynthesisInfo poloka. |
| 17.0 | 2017.05.05 | • Toe fa'ailogaina o le Intel
• Ua le toe faaaogaina Fa'ailoga poloka • Fa'aopoopo le Gaussian ma le Random Number Generator design examples • Fa'aopoopoina supers lapopo'a fesuia'iamptaʻitaʻia FFT mamanu example • Faaopoopo HybridVFFT poloka • Faaopoopo GeneralVTwiddle ma GeneralMultVTwiddle poloka |
| 16.1 | 2016.11.10 | • Fa'aopoopoina le 4-channel 2-antenna DUC ma le DDC mo le LTE reference design
• Faaopoopo BFU_simple poloka • Fausia lomiga Standard ma Pro. Pro lagolagoina Arria 10 masini; E lagolagoina uma isi aiga. • Ua le toe faaaogaina le Fa'ailoga poloka • Fa'aopoopo galuega mo le fa'atulagaina o le Avalon-MM fa'aoga fa'aoga i le DSP Builder menu |
| faaauau… | ||
| Fa'aliliuga | Aso | Fa'amatalaga |
| 16.0 | 2016.05.02 | • Toe faatulagaina faletusi
• Fa'aleleia i'uga gaugau i MAX 10 masini • Faaopoopo le mamanu fou examples: — Gaussian Random Number Generator — DUC_4C4T4R ma DDC_4C4T4R LTE numera-i luga ma lalo-liliu • Fa'aopoopo le fuafuaga fou FFT teuteu: prune_to_widths() |
| 15.1 | 2015.11.11 | • Ua le toe faaaogaina Tamomoe Quartus II ma Tamomoe Modelsim poloka
• Fa'aopoopoina le lagolago fa'alava o le uati • Fa'aopoopoina fa'alelei FIR toe fetu'una'i • Fa'aleleia feso'ota'iga pasi: - Faʻaleleia le siakiina ma le lipotia o mea sese - Fa'aleleia le sa'o fa'atusa - Faʻaleleia le faʻatinoina o le faʻatinoga o le faʻatonuga o pologa pasi - Fa'aleleia le kolosi o le uati • Suia nisi feso'ota'iga Avalon-MM • Fa'aopoopo poloka fou: — Pu'e Taua — Fanout — Taofi — Vectorfanout • Fa'aopoopo le IIR: fa'ata'ita'iga fa'ato'a fa'afefeteina fa'ato'a fua fa'atatau atoa • Fa'aopoopoina le fa'asalalauina ma le mauaina o le mamanu fa'asinomaga modem |
| 15.0 | Me 2015 | • Fa'aopoopoina le lagolago mo galuega fa'atino a SystemVerilog
• Faaopoopo i fafo manatuaga faletusi • Faaopoopo Manatu i fafo poloka • Faaopoopo mea fou Fa'ataga le tusi i luga o ports e lua tapula'a i DualMem poloka • Suia fa'amaufa'ailoga i luga AvalonMMSlaveSettings poloka |
| 14.1 | Tesema 2014 | • Fa'aopoopoina le lagolago mo Arria 10 poloka malo-opeopea
• Fa'aopoopo BusStimulus ma BusStimulusFilePoloka a le aufaitau ile fa'asologa o tusi resitala fa'ata'ita'iample. • Faaopoopo AvalonMMSlaveSettings poloka ma DSP Builder> Avalon Interfaces> Avalon-MM pologa filifiliga lisi • Aveese tapula'a pasi mai poloka Pule ma Fa'ailoga • Aveese le mamanu nei egamples: — Lanu Avanoa Su'e (Gaugau Fetufa'aiga Punaoa) - Fa'afeso'ota'i FIR Filter ma fa'afou fa'atasi — Uluai FIR Filter (Gaugau Fetufa'aiga Punaoa) — Nofofua-Stage IIR Filter (Gaugau Fetufa'aiga Punaoa) — Tolu-stage IIR Filter (Gaugau Fetufa'aiga Punaoa) • Faʻaopoopoina le lagolago faʻapipiʻi-i-le-loop • Fa'aopoopo poloka fou: — Fa'avasega-vaega fa'afefete — Fa'aputu-fa'atele fa'aputuga - Fa'aopoopo galuega fa'atino ile poloka numera • Fa'aopoopo mamanu fa'atasiamples: - Su'e avanoa lanu - FIR lavelave - CORDIC mai Primitive Blocks - Fa'aitiitiga vaega o le tumutumu — Gagau FIR — Fuafuaga Fa'atatau Fa'ai'uga Fuafuaga Su'esu'e — Fa'avasega Vector – fa'asologa ma fa'asolosolo |
| faaauau… | ||
| Fa'aliliuga | Aso | Fa'amatalaga |
| • Fa'aopoopo ata fa'asino:
- Fa'aitiitiga vaega o le tumutumu - Fa'atonu RF fa'atasi ma le Synthesizable Testbench — Fa'amama Fa'ai'uga — Toe fetuutuuna'i Decimation Filter — Fuafuaga Fa'atatau Fa'ai'uga Fuafuaga Su'esu'e • Ave'esea le fa'asoa fa'asoa puna'oa • Fa'afouina le faila ALU |
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| 14.0 | Iuni 2014 | • Fa'aopoopo le lagolago mo MAX 10 FPGAs.
• Aveese le lagolago mo masini a le afa III ma Stratix III • Fa'aleleia DSP Builder Run ModelSim filifiliga, lea e mafai ai nei ona e taʻavale ModelSim mo le mamanu pito i luga poʻo submodules taʻitasi • Suia le fa'atupuina o le HDL i le fa'atonuga tulaga o masini (i lalo o le fa'atonuga fa'atonu RTL) nai lo le fa'avasegaina o fa'atonuga. • Fa'aopoopo le fa'ailoga faitau ile fa'aoga pasi • Fa'aopoopo le uafu manino ile FIFO • Fa'ate'a poloka FFT 13 • Faaopoopo le mamanu fou examples: - Avalon-ST Interface (Input and Output FIFO Buffer) faʻatasi ai ma Backpressure - Avalon-ST Interface (Output FIFO Buffer) ma Backpressure — Galuega fa'amaumau numera - Fa'aa'a fa'afafa'ifa'atasi e fa'aaoga ai le CORDIC - Fa'asalaina — FFT tutusa — Fa'asa'o Fa'a-Fope FFT — A'a sikuea fa'aaoga CORDIC — FFT/iFFT e mafai ona sui — Fuafua-Size Fixed-Point FFT — Fuafua-Size Fixed-Point FFT e aunoa ma le BitReverseCoreC Block — Fuafua-Size Fixed-Point iFFT — Fuafua-Size Fixed-Point iFFT e aunoa ma le BitReverseCoreC Block — Fuafua-Size Floating Point FFT — Fuafua-Size Floating Point FFT e aunoa ma le BitReverseCoreC Block — Fuafua-Size Floating-Point iFFT — Fuafua-Size Floating-Point iFFT e aunoa ma le BitReverseCoreC Block • Fa'aopoopo poloka fou: - Fa'atuai Taula — Laina Fa'atuai ua mafai — Fa'agaoioi le Fa'atuai Fa'amatalaga — FFT2P, FFT4P, FFT8P, FFT16P, FFT32P, ma le FFT64P — FFT2X, FFT4X, FFT8X, FFT16X, FFT32X, ma le FFT64X — FFT2, FFT4, VFFT2, ma le VFFT4 — General Multitwiddle ma General Twiddle (GeneralMultiTwiddle, GeneralTwiddle) — Fa'ato'aga FFT (Hybrid_FFT) — FFT Fa'apa'i Fa'atasi (PFFT_Pipe) — Sauniuni |
| 13.1 | Novema 2013 | • Aveese le lagolago mo masini nei:
— Arria GX — Afa II — HardCopy II, HardCopy III, ma HardCopy IV — Stratix, Stratix II, Stratix GX, ma Stratix II GX • Fa'aleleia le tafega gaugau ALU • Fa'aopoopo galuega fou ile poloka Math. |
| faaauau… | ||
| Fa'aliliuga | Aso | Fa'amatalaga |
| • Fa'aopoopo le Simulink fi poloka filifiliga ile Const, DualMem, ma LUT poloka
• Faaopoopo le mamanu fou examples: — Fuafua-sa'o sa'o taimi moni FFT - Fa'afeso'ota'i le FIR Filter ma fa'afou fa'aputuga — Fa'alava fa'atuai taimi • Fa'aopoopo poloka fou: - Fa'atuai Taula — Polynomial — TwiddleAngle — TwiddleROM ma TwiddleROMF — VariableBitReverse — VFFT |
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| 13.0 | Me 2013 | • Fa'afou poloka masini ma le lisi fou o le Filifiliga Fa'atonu.
• Fa'aopoopo poloka ModelPrim fou: — Const Mult — Vaevae — MinMax — Faafitia — Oloa Sikala • Fa'aopoopoina poloka FFT fou e iva • Fa'aopoopoina fa'ata'ita'iga fou FFT e sefulu |
| 12.1 | Novema 2012 | • Fa'aopoopo le vaega gaugau ALU
• Fa'aopoopoina le sa'o sa'o o filifiliga fa'a'opeopea • Fa'aopoopo poloka ModelPrim fou nei: — AddSub - AddSubFused — CmpCtrl — Math — Maualuluga ma Laiti — MinMaxCtrl — Taamilomilo — Trig • Fa'aopoopo poloka FFT fou nei: — Su'esu'e Tu'u (EdgeDetect) — Vaevae fao (PulseDivider) — Fa'atele Fa'atele (PulseMultiplier) — Bit-Sui FFT fa'atasi ai ma Auga Fa'anatura (FFT_BR_Natural) • Fa'aopoopoina le ata fou FIR lea e iaiamples: — Super-sample fa'aitiitia o le filiga FIR — Super-sample vaega vaega FIR faamama • Fa'aopoopo le tulaga, saoasaoa, ma le fa'atonuga o lo'o iai mo afi AC (fa'atasi ai ma le gaugau ALU) fa'ata'ita'igaample |
Fa'amatalaga Fa'atatau
DSP Builder Advanced Blockset Tusitaulima
System Manaoga
- DSP Builder mo Intel FPGAs fa'atasi ma MathWorks MATLAB ma Simulink meafaigaluega fa'atasi ai ma le Intel Quartus® Prime software.
- Ia mautinoa ia le itiiti ifo ma le tasi le lomiga o le MathWorks MATLAB ma Simulink meafaigaluega o loʻo avanoa i luga o lau fale faigaluega ae e te leʻi faʻapipiʻiina le DSP Builder mo Intel FPGAs. E tatau ona e fa'aogaina le fa'aoga tutusa o le Intel Quartus Prime software ma le DSP Builder mo Intel FPGAs. DSP Builder mo Intel FPGAs na'o le lagolagoina o 64-bit versions o le MATLAB.
- Mai le v18.0, DSP Builder mo Intel FPGAs advanced blockset e avanoa mo Intel Quartus Prime Pro Edition ma le Intel Quartus Prime Standard Edition. DSP Builder mo Intel FPGAs standard blockset e na'o le Intel Quartus Prime Standard Edition e avanoa.
Laulau 2. Faufale DSP mo Intel FPGAs MATLAB Fa'alagolago
| Fa'aliliuga | MATLAB Lagolago Versions | ||
| DSP Builder Standard Blockset | DSP Builder Advanced Blockset | ||
| Intel Quartus Prime Standard Edition | Intel Quartus Prime Pro Edition | ||
| 22.4 | Le avanoa | R2022a R2021b R2021a R2020b R2020a | |
| 22.3 | Le avanoa | R2022a R2021b R2021a R2020b R2020a | |
| 22.1 | Le avanoa | R2021b R2021a R2020b R2020a R2019b | |
| 21.3 | Le avanoa | R2021a R2020b R2020a R2019b R2019a | |
| 21.1 | Le avanoa | R2020b R2020a R2019b R2019a R2018b | |
| 20.1 | Le avanoa | R2019b R2019a R2018b R2018a R2017b R2017a | |
| 19.3 | Le avanoa | R2019a R2018b R2018a R2017b | |
| faaauau… | |||
| Fa'aliliuga | MATLAB Lagolago Versions | ||
| DSP Builder Standard Blockset | DSP Builder Advanced Blockset | ||
| Intel Quartus Prime Standard Edition | Intel Quartus Prime Pro Edition | ||
| R2017a R2016b | |||
| 19.1 | Le lagolagoina | R2013a | R2018b R2018a R2017b R2017a R2016b |
| 18.1 | R2013a | R2013a | R2018a R2017b R2017a R2016b |
| 18.0 | R2013a | R2013a | R2017b R2017a R2016b R2016a R2015b |
| 17.1 | R2013a | R2013a | R2016a R2015b R2015a R2014b R2014a R2013b |
Fa'aaliga:
O le DSP Builder mo le Intel FPGAs advanced blockset e fa'aogaina ituaiga Simulink fa'amautu mo fa'agaioiga uma ma mana'omia lomiga laiseneina o Simulink Fixed Point. E fautuaina foi e Intel le DSP System Toolbox ma le Communications System Toolbox, lea e iai nisi mamanuample faaaogaina.
Fa'amatalaga Fa'atatau
Fa'apipi'i ma Laiseneina o Polokalama Intel.
DSP Builder mo Intel® FPGAs Fa'amatalaga Fa'amatalaga 9
Pepa / Punaoa
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Intel DSP Faufale mo Intel FPGAs [pdf] Taiala mo Tagata Fa'aoga DSP Fausia mo Intel FPGAs, Fausia mo Intel FPGAs, Intel FPGAs, FPGAs |