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Pandhuan Persiyapan Pustaka

Isine ndhelikake
1 Pambuka
2 Integrasi SoC Libero
3 Setup Aldec kanggo Active-HDL lan Riviera-Pro (Tanya Pitakonan)
4 Setup Incisive Cadence (Anyar Pitakonan)
5 Cadence Xcelium Setup (Microchip Login)
6 Siemens QuestaSim Setup/ModelSim Setup (Tanya Pitakonan)
7 Synopsys VCS Setup (Ask a Question)
8 Riwayat Revisi (Microchip Login
9 Dokumen / Sumber Daya
9.1 Referensi
10 Kiriman sing gegandhengan

Pambuka

(Takon Pitakonan)

Tujuan saka dokumen iki yaiku kanggo njlèntrèhaké prosedur kanggo nyiyapake lingkungan simulasi nggunakake proyek Libero SoC minangka input. Dokumentasi iki cocog karo perpustakaan sing wis dikompilasi sing kasedhiya kanggo digunakake karo Libero SoC v11.9 lan rilis piranti lunak sing luwih anyar. Pustaka sing disedhiyakake dikompilasi kanggo Verilog. Pangguna VHDL mbutuhake lisensi sing ngidini simulasi mode campuran.
Pustaka simulasi sing dikompilasi kasedhiya kanggo piranti ing ngisor iki:

  • Aldec Active-HDL
  • Aldec Riviera-PRO
  • Cadence Incisive Enterprise lan Xcelium
  • Siemens QuestaSim
  • Synopsys VCS

Kanggo njaluk perpustakaan kanggo simulator beda, hubungi Dhukungan Teknis Microchip.

Integrasi SoC Libero

(Takon Pitakonan)

Libero SoC ndhukung simulasi nggunakake ModelSim ME dening ngasilaken a run.do file. Iki file digunakake dening ModelSim ME / ModelSim Pro ME kanggo nyetel lan mbukak simulasi. Kanggo nggunakake alat simulasi liyane, sampeyan bisa generate ModelSim ME / ModelSim Pro ME run.do lan ngowahi script Tcl file kanggo nggunakake printah sing kompatibel karo simulator sampeyan.
1.1 Libero SoC Tcl File Generasi (Takon Pitakonan)
Sawise nggawe lan ngasilake desain ing Libero SoC, miwiti simulasi ModelSim ME / ModelSim Pro ME ing kabeh fase desain (presynth, postsynth, lan post-layout). Langkah iki ngasilake run.do file kanggo ModelSim ME / ModelSim Pro ME kanggo saben phase desain.
MICROCHIP Libero SoC Simulation Library Software - lambang penting: Sawise miwiti saben simulasi run, ganti jeneng run.do sing digawe otomatis file ing direktori simulasi kanggo nyegah Libero SoC nimpa sing file. Kanggo example, ing files bisa diganti jeneng kanggo presynth_run.do, postsynth_run.do lan postlayout_run.do.

Setup Aldec kanggo Active-HDL lan Riviera-Pro (Takon Pitakonan)

Run.do file digunakake dening ModelSim ME / ModelSim Pro ME bisa diowahi lan digunakake kanggo simulasi nggunakake simulator Aldec.
2.1 Variabel Lingkungan (Takon Pitakonan)
Setel variabel lingkungan menyang lisensi sampeyan file lokasi:
LM_LISENSI_FILE: kudu kalebu pointer menyang server lisensi.
2.2 Ngundhuh Pustaka Kompilasi (Takon Pitakonan)
Download perpustakaan kanggo Aldec Active-HDL lan Aldec Riviera-PRO saka Microchip websitus.
2.3 Ngonversi run.do kanggo simulasi Aldec (Takon Pitakonan)
Run.do files kui dening Libero SoC kanggo simulasi nggunakake Active-HDL lan alat Riviera-Pro bisa digunakake kanggo simulasi nggunakake Active-HDL lan Riviera-Pro karo owah-owahan siji. Tabel ing ngisor iki dhaptar printah Aldec-padha kanggo ngowahi ing ModelSim run.do file.
Tabel 2-1. Aldec Equivalent Commands

ModelSim Aktif-HDL
vlog alog
vcom acom
vlib alib
vsim asim
vmap amap

Ing ngisor iki minangkaample run.do related kanggo Aldec simulator.

  1. Setel lokasi direktori kerja saiki.
    nyetel dsn
  2. Setel jeneng perpustakaan sing bisa digunakake, peta lokasi, banjur peta lokasi kulawarga Microchip FPGA
    perpustakaan sing wis dikompilasi (umpamaneample, SmartFusion2) sing sampeyan gunakake desain sampeyan.
    alib presynth
    amap presynth presynth
    amap SmartFusion2
  3. Kompilasi kabeh HDL sing dibutuhake files digunakake ing desain karo perpustakaan dibutuhake.
    alog –work presynth temp.v (kanggo Verilog)
    alog –work presynth testbench.v
    acom –work presynth temp.vhd (kanggo Vhdl)
    acom –work presynth testbench.vhd
  4. Simulate desain.
    asim –L SmartFusion2 –L presynth –t 1ps presynth.testbench
    mlayu 10us

2.4 Masalah sing Dikenal (Takon Pitakonan)
Bagean iki nampilake masalah lan watesan sing dikenal.

  • Pustaka sing dikompilasi nganggo Riviera-PRO minangka platform khusus (yaiku perpustakaan 64-bit ora bisa mbukak ing platform 32-bit lan kosok balene).
  • Kanggo desain sing ngemot SERDES / MDDR / FDDR, gunakake pilihan ing ngisor iki ing run.do files nalika mbukak simulasi sawise nyusun rancangane:
    - Active-HDL: asim -o2
    – Riviera-PRO: asim –O2 (kanggo simulasi presynth lan post-layout) lan asim –O5 (kanggo simulasi post-layout)
    Persiyapan Aldec kanggo Active-HDL lan Riviera-Pro nduweni SAR sing ditundha ing ngisor iki. Kanggo informasi luwih lengkap, hubungi Dhukungan Teknis Microchip.
  • SAR 49908 - Active-HDL: Kesalahan VHDL kanggo simulasi blok Math
  • SAR 50627 - Riviera-PRO 2013.02: Kasalahan simulasi kanggo desain SERDES
  • SAR 50461 - Riviera-PRO: pilihan asim -O2/-O5 ing simulasi

Setup Incisive Cadence (Takon Pitakonan)

Sampeyan kudu nggawe skrip file padha ModelSim ME / ModelSim Pro ME run.do kanggo mbukak ing
Simulator Incisive Cadence. Tindakake langkah iki lan nggawe skrip file kanggo NCSim utawa nggunakake script file
kasedhiya kanggo ngowahi ModelSim ME / ModelSim Pro ME run.do files menyang konfigurasi files
dibutuhake kanggo mbukak simulasi nggunakake NCSim.
MICROCHIP Libero SoC Simulation Library Software - lambang Penting: Cadence wis mandheg ngeculake versi anyar saka Incisive Enterprise
simulator lan miwiti ndhukung simulator Xcelium.

3.1 Variabel Lingkungan (Takon Pitakonan)
Kanggo mbukak simulator Cadence Incisive, konfigurasi variabel lingkungan ing ngisor iki:

  1. LM_LISENSI_FILE: kudu kalebu pitunjuk kanggo lisensi file.
  2. cds_root: kudu nuding menyang lokasi direktori ngarep Instalasi Cadence Incisive.
  3. PATH: kudu nuding lokasi bin ing direktori alat sing ditunjuk dening cds_root yaiku,
    $cds_root/tools/bin/64bit (kanggo mesin 64-bit lan $ cds_root/tools/bin kanggo mesin 32-bit).
    Ana telung cara kanggo nyetel lingkungan simulasi yen ana ngalih ing antarane sistem operasi 64-bit lan 32-bit:

Kasus 1: Variabel PATH
Jalanake printah ing ngisor iki:
nyetel path = (install_dir/tools/bin/64bit $path) kanggo mesin 64bit lan
nyetel path = (install_dir / tools / bin $ path) kanggo mesin 32bit
Kasus 2: Nggunakake -64bit Command-line Option
Ing baris printah nemtokake pilihan -64bit kanggo njaluk eksekusi 64bit.
Kasus 3: Nyetel Variabel Lingkungan INCA_64BIT utawa CDS_AUTO_64BIT
Variabel INCA_64BIT dianggep minangka boolean. Sampeyan bisa nyetel variabel iki menyang sembarang nilai utawa string null.
setenv INCA_64BIT

MICROCHIP Libero SoC Simulation Library Software - lambang Penting: Ing Variabel lingkungan INCA_64BIT ora mengaruhi alat Cadence liyane, kayata alat IC. Nanging, kanggo alat Incisive, variabel INCA_64BIT ngatasi setelan kanggo variabel lingkungan CDS_AUTO_64BIT. Yen variabel lingkungan INCA_64BIT disetel, kabeh alat Incisive mbukak ing mode 64-bit. setenv CDS_AUTO_64BIT Klebu:INCA
MICROCHIP Libero SoC Simulation Library Software - lambang Penting: Ing string INCA kudu nganggo huruf gedhe. Kabeh executable kudu mbukak ing salah siji mode 32-bit utawa ing mode 64-bit, aja nyetel variabel kanggo kalebu siji eksekusi, kaya ing ngisor iki:
setenv CDS_AUTO_64BIT KANGGO:ncelab

Piranti Cadence liyane, kayata alat IC, uga nggunakake variabel lingkungan CDS_AUTO_64BIT kanggo ngontrol pilihan eksekusi 32-bit utawa 64-bit. Tabel ing ngisor iki nuduhake carane sampeyan bisa nyetel variabel CDS_AUTO_64BIT kanggo mbukak alat Incisive lan alat IC ing kabeh mode.
Tabel 3-1. Variabel CDS_AUTO_64BIT

CDS_AUTO_64BIT Variabel Piranti Incisive Piranti IC
setenv CDS_AUTO_64BIT ALL 64 bit 64 bit
setenv CDS_AUTO_64BIT NONE 32 bit 32 bit
setenv CDS_AUTO_64BIT EXCLUDE:ic_binary 64 bit 32 bit
setenv CDS_AUTO_64BIT EXCLUDE:INCA 32 bit 64 bit

MICROCHIP Libero SoC Simulation Library Software - lambang penting: Kabeh piranti Incisive kudu mbukak ing mode 32-bit utawa ing mode 64-bit, aja nganggo EXCLUDE kanggo ngilangi eksekusi tartamtu, kaya ing ngisor iki: setenv CDS_AUTO_64BIT EXCLUDE:ncelab
Yen sampeyan nyetel variabel CDS_AUTO_64BIT kanggo ngilangi alat Incisive (setenv CDS_AUTO_64BIT EXCLUDE:INCA), kabeh alat Incisive mbukak ing mode 32-bit. Nanging, pilihan baris printah -64bit ngatasi variabel lingkungan.
Konfigurasi ing ngisor iki filembantu sampeyan ngatur data lan ngontrol operasi alat lan utilitas simulasi:

  • Pemetaan perpustakaan file (cds.lib) - Nemtokake jeneng logis kanggo lokasi desain sampeyan.
  • Pustaka lan nggandhengake karo jeneng direktori fisik.
  • Variabel file (hdl.var) -Netepake variabel sing mengaruhi prilaku alat simulasi lan keperluan.

3.2 Ngundhuh Pustaka Kompilasi (Takon Pitakonan)
Download perpustakaan kanggo Cadence Incisive saka Microsemi's websitus.
3.3 Nggawe Skrip NCSim File (Takon Pitakonan)
Sawise nggawe salinan run.do files, tindakake langkah iki kanggo mbukak simulasi nggunakake NCSim:

  1. Nggawe cds.lib file sing nemtokake perpustakaan sing bisa diakses lan lokasi. Ing file ngandhut statements sing map jeneng logis perpustakaan menyang path direktori fisik. Kanggo example, yen sampeyan mlaku simulasi presynth, cds.lib file ditulis minangka ditampilake ing codeblock ing ngisor iki.
    DEFINE presynth ./presynth
    DEFINE COREAHBLITE_LIB ./COREAHBLITE_LIB
    DEFINE smartfusion2
  2. Nggawe hdl.var file, konfigurasi opsional file sing ngemot variabel konfigurasi, sing nemtokake cara lingkungan desain sampeyan dikonfigurasi. Variabel ing ngisor iki files kalebu:
    – Variabel sing digunakake kanggo nemtokake perpustakaan karya ing ngendi compiler nyimpen obyek kompilasi lan data asale liyane.
    – Kanggo Verilog, variabel (LIB_MAP, VIEW_MAP, WORK) sing digunakake kanggo nemtokake perpustakaan lan views kanggo nelusuri nalika elaborator mutusake masalah kedadean.
    - Variabel sing ngidini sampeyan nemtokake opsi lan argumen baris perintah kompiler, elaborator, lan simulator.
    Ing kasus simulasi presynth example ditampilake ing ndhuwur, ngandika kita duwe telung RTL files: av, bv, lan testbench.v, sing kudu dikompilasi dadi perpustakaan presynth, COREAHBLITE_LIB, lan presynth. hdl.var file bisa ditulis kaya sing ditampilake ing blok kode ing ngisor iki.
    DEFINE KARYA presynth
    DEFINE PROYEK_DIR files>
    DEFINE LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/av => presynth )
    DEFINE LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/bv => COREAHBLITE_LIB )
    DEFINE LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/testbench.v => presynth )
    DEFINE LIB_MAP ($LIB_MAP, + => presynth )
  3. Nglumpukake desain files nggunakake opsi ncvlog.
    ncvlog +incdir+ –cdslib ./cds.lib –hdlvar ./hdl.var –logfile
    ncvlog.log –update –linedebug av bv testbench.v
  4. Njlentrehake desain nggunakake ncelab. Elaborator mbangun hirarki desain adhedhasar informasi instansiasi lan konfigurasi ing desain, netepake konektivitas sinyal, lan ngitung nilai awal kanggo kabeh obyek ing desain. Hierarki desain sing dijlentrehake disimpen ing snapshot simulasi, yaiku perwakilan desain sampeyan sing digunakake simulator kanggo mbukak simulasi.
    ncelab –Pesen –cdslib ./cds.lib –hdlvar ./hdl.var –logfile ncelab.log –errormax 15 –
    akses +rwc –status worklib. : modul
    Elaborasi Sajrone simulasi Post-layout
    Ing cilik saka simulasi post-layout, pisanan SDF file kudu dikompilasi sadurunge njlentrehake nggunakake printah ncsdfc.
    ncsdfcfilejeneng>.sdf –outputfilejeneng>.sdf.X
    Sajrone njlentrehake, gunakake output SDF sing dikompilasi kanthi opsi –autosdf kaya sing ditampilake ing blok kode ing ngisor iki.
    ncelab -autosdf –Pesen –cdslib ./cds.lib –hdlvar ./hdl.var –logfile ncelab.log –errormax
    15 –akses +rwc –status worklib. : modul –sdf_cmd_file ./
    sdf_cmd_file
    sdf_cmd_file kudu kaya sing dituduhake ing blok kode ing ngisor iki.
    COMPILED_SDF_FILE = “ file>”
  5. Simulate nggunakake ncsim. Sawise njlentrehake gambar asli simulasi digawe, sing dimuat dening ncsim kanggo simulasi. Sampeyan bisa mbukak ing mode kumpulan utawa mode GUI.
    ncsim –Pesen –batch/-gui –cdslib ./cds.lib –hdlvar ./hdl.var –logfile ncsim.log –
    errormax 15 -status worklib. : modul

MICROCHIP Libero SoC Simulation Library Software - lambang penting: Kabeh telung langkah ing ndhuwur kanggo nyusun, njlentrehake, lan simulasi bisa dilebokake ing skrip cangkang file lan sumber saka command-line. Tinimbang nggunakake telung langkah iki, desain bisa simulasi ing siji langkah nggunakake ncverilog utawa pilihan irun minangka ditampilake ing codeblock ing ngisor iki.
ncverilog +incdir+ -cdslib ./cds.lib –hdlvar ./hdl.var
filedigunakake ing desain>
irun +incdir+ -cdslib ./cds.lib –hdlvar ./hdl.var files
digunakake ing desain>

3.3.1 Masalah sing Dikenal (Takon Pitakonan)
Testbench Workaround
Nggunakake statement ing ngisor iki kanggo nemtokake frekuensi jam ing testbench kui pangguna, utawa standar testbench kui Libero SoC ora bisa karo NCSim.
tansah @(SYSCLK)
#(SYSCLK_PERIOD / 2.0) SYSCLK <= !SYSCLK;
Ngowahi kaya ing ngisor iki kanggo mbukak simulasi:
tansah #(SYSCLK_PERIOD / 2.0) SYSCLK = ~SYSCLK;
MICROCHIP Libero SoC Simulation Library Software - lambang Penting: Dikompilasi perpustakaan kanggo NCSim minangka platform tartamtu (yaiku pustaka 64 bit ora kompatibel karo platform 32 bit lan kosok balene).
Simulasi Postsynth lan Post-layout Nggunakake MSS lan SERDES Nalika nindakake simulasi postsynth saka desain sing ngemot blok MSS utawa simulasi post-layout saka desain nggunakake SERDES, simulasi BFM ora bisa digunakake yen opsi –libmap
ora ditemtokake sajrone elaborasi. Iki amarga nalika njlentrehake, MSS ditanggulangi saka perpustakaan karya (amarga ikatan standar lan worklib dadi postsynth / post-layout) ing ngendi iku mung Fungsi Tetap.
Printah ncelab kudu ditulis minangka ditampilake ing blok kode ing ngisor iki kanggo mutusake masalah MSS
mblokir saka perpustakaan SmartFusion2 sing wis dikompilasi.

ncelab -libmap lib.map -libverbose -Pesen -akses +rwc cfg1
lan lib.map file kudu kaya ing ngisor iki:
konfigurasi cfg1;
desain ;
standar liblist smartfusion2 ;
endconfig
Iki mutusake masalah sel apa wae ing perpustakaan SmartFusion2 sadurunge nggoleki perpustakaan kerja yaiku postsynth/post-layout.
Opsi -libmap bisa digunakake kanthi standar sajrone elaborasi kanggo saben simulasi (presynth, postsynth, lan post-layout). Iki ngindhari masalah simulasi sing disebabake amarga resolusi kasus saka perpustakaan.
ncelab: *F, INTERR: PENGECUALIAN INTERNAL
Pangecualian alat ncelab iki minangka caveat kanggo desain sing ngemot FDDR ing SmartFusion 2 lan IGLOO 2 sajrone simulasi postsynth lan post-layout nggunakake opsi -libmap.
MICROCHIP Libero SoC Simulation Library Software - lambang penting: Masalah iki wis dilaporake menyang tim dhukungan Cadence (SAR 52113).

3.4 Sample Tcl lan Shell Script Files (Takon Pitakonan)
Ing ngisor iki files iku konfigurasi files needed kanggo nyetel desain lan shell script file kanggo mlaku printah NCSim.
Cds.lib
NE smartfusion2 /scratch/krydor/tmpspace/users/me/nc-vlog64/SmartFusion2
DEFINE COREAHBLITE_LIB ./COREAHBLITE_LIB
DEFINE presynth ./presynth

Hdl.var
DEFINE KARYA presynth
DEFINE PROJECT_DIR /scratch/krydor/tmpspace/sqausers/me/3rd_party_simulators/Cadence/IGLOO2/
ENVM/M2GL050/envm_fic1_ser1_v/eNVM_fab_master
DEFINE LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/komponen/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/core/coreahblite_addrdec.v => COREAHBLITE_LIB )
DEFINE LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/komponen/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/core/coreahblite_defaultslavesm.v => COREAHBLITE_LIB )
DEFINE LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/komponen/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/inti/coreahblite_masterstagev => COREAHBLITE_LIB )
DEFINE LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/komponen/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/core/coreahblite_slavearbiter.v => COREAHBLITE_LIB )
DEFINE LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/komponen/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/inti/coreahblite_slavestagev => COREAHBLITE_LIB )
DEFINE LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/komponen/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/core/coreahblite_matrix2x16.v => COREAHBLITE_LIB )
DEFINE LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/komponen/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/core/coreahblite.v => COREAHBLITE_LIB )
DEFINE LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/component/work/SB/CCC_0/SB_CCC_0_FCCC.v =>
presynth)
DEFINE LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/komponen/Actel/DirectCore/CoreConfigMaster/
2.0.101/rtl/vlog/core/coreconfigmaster.v => presynth )
DEFINE LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreConfigP/4.0.100/rtl/
vlog/core/coreconfigp.v => presynth )
DEFINE LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreResetP/5.0.103/rtl/
vlog/core/coreresetp_pcie_hotreset.v => presynth )
DEFINE LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreResetP/5.0.103/rtl/
vlog/core/coreresetp.v => presynth )
DEFINE LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/component/work/SB/FABOSC_0/SB_FABOSC_0_OSC.v =>
presynth)
DEFINE LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/component/work/SB_HPMS/SB_HPMS.v => presynth )
DEFINE LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/component/work/SB/SB.v => presynth )
DEFINE LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/component/work/SB_top/SERDES_IF_0/
SB_top_SERDES_IF_0_SERDES_IF.v => presynth )
DEFINE LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/component/work/SB_top/SB_top.v => presynth )
DEFINE LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/component/work/SB_top/testbench.v => presynth )
DEFINE LIB_MAP ($LIB_MAP, + => presynth )
Commands.csh
ncvlog +incdir+../../component/work/SB_top -cdslib ./cds.lib -hdlvar ./hdl.var -logfile
ncvlog.log -errormax 15 -update -linedebug
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite_addrdec.v
../../komponen/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/inti/
coreahblite_defaultslavesm.v
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite_masterstagev
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite_slavearbiter.v
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite_slavestagev
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite_matrix2x16.v
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite.v
../../component/work/SB/CCC_0/SB_CCC_0_FCCC.v
../../component/Actel/DirectCore/CoreConfigMaster/2.0.101/rtl/vlog/core/coreconfigmaster.v
../../component/Actel/DirectCore/CoreConfigP/4.0.100/rtl/vlog/core/coreconfigp.v
../../component/Actel/DirectCore/CoreResetP/5.0.103/rtl/vlog/core/coreresetp_pcie_hotreset.v
../../component/Actel/DirectCore/CoreResetP/5.0.103/rtl/vlog/core/coreresetp.v
../../komponen/kerja/SB/FABOSC_0/SB_FABOSC_0_OSC.v ../../komponen/kerja/SB_HPMS/SB_HPMS.v
../../komponen/kerja/SB/SB.v ../../komponen/kerja/SB_top/SERDES_IF_0/
SB_TOP_SERDES_IF_0_SERDES_IF.v
../../component/work/SB_top/SB_top.v ../../component/work/SB_top/testbench.v
ncelab -Pesen -cdslib ./cds.lib -hdlvar ./hdl.var
-work presynth -logfile ncelab.log -errormax 15 -akses +rwc -status presynth.testbench:modul
ncsim -Pesen -batch -cdslib ./cds.lib -hdlvar ./
hdl.var -logfile ncsim.log -errormax 15 -status presynth.testbench:modul

3.5 Otomasi (Takon Pitakonan)
Skripsi ing ngisor iki file ngowahi ModelSim run.do files menyang konfigurasi files needed kanggo mbukak simulasi nggunakake NCSim.
Skripsi File Panganggone
perl cadence_parser.pl presynth_run.do postsynth_run.do
postlayout_run.do Microsemi_Family
Location_of_Cadence_Precompiled_libraries

Cadence_parser.pl
#!/usr/bin/perl -w

################################################## ##############################################
##################
#Usage: perl questa_parser.pl presynth_run.do postsynth_run.do postlayout_run.do
Microsemi_Family Precompiled_Libraries_location#

################################################## ##############################################
##################
nggunakake POSIX;
nggunakake ketat;
sandi ($presynth, $postsynth, $postlayout, $kulawarga, $lib_location) = @ARGV;
&questa_parser ($presynth, $kulawarga, $lib_location);
&questa_parser ($postsynth, $kulawarga, $lib_location);
&questa_parser ($postlayout, $kulawarga, $lib_location);
sub questa_parser {
sandi $ModelSim_run_do = $_[0];
kula $actel_family = $_[1];
my $lib_location = $_[2];
sandi $ negara;
yen (-e "$ModelSim_run_do")
{
mbukak (INFILE,"$ModelSim_run_do");
sandi @ModelSim_run_do =FILE>;
sandi $ baris;
yen ($ModelSim_run_do =~ m/(presynth)/)
{
`mkdir QUESTA_PRESYNTH`;
mbukak (FILE,”>QUESTA_PRESYNTH/presynth_questa.do”);
$negara = $1;
} elsif ($ModelSim_run_do =~ m/(postsynth)/)
{
`mkdir QUESTA_POSTSYNTH`;
mbukak (FILE,">QUESTA_POSTSYNTH/postsynth_questa.do");
$negara = $1;
} elsif ($ModelSim_run_do =~ m/(postlayout)/ )
{
`mkdir QUESTA_POSTLAYOUT`;
mbukak (FILE,">QUESTA_POSTLAYOUT/postlayout_questa.do");
$negara = $1;
} liya
{
print "Salah Input sing diwenehake menyang file\n”;
print “#Usage: perl questa_parser.pl presynth_run.do postsynth_run.do postlayout_run.do
\"Lokasi_Perpustakaan\"\n";
}
foreach $line (@ModelSim_run_do)
{
#Operasi Umum
$line =~ s/..\/designer.*simulasi\///g;
$line =~ s/$state/$state\_questa/g;
#print OUTFILE "$line \n";
yen ($line =~ m/vmap\s+.*($actel_family)/)
{
print OUTFILE "vmap $actel_family \"$lib_location\"\n";
} elsif ($line =~ m/vmap\s+(.*._LIB)/)
{
$line =~ s/..\/komponen/..\/..\/komponen/g;
print OUTFILE "$line \n";
} elsif ($line =~ m/vsim/)
{
$line =~ s/vsim/vsim -novopt/g;
print OUTFILE "$line \n";
} liya
{
print OUTFILE "$line \n";
}
}
nutup (INFILE);
nutup (OUTFILE);
} liyane {
print "$ ModelSim_run_do ora ana. Run maneh simulasi \n";
}
}

Setup Xcelium Irama (Microchip Login)

Sampeyan kudu nggawe skrip file padha ModelSim ME / ModelSim Pro ME run.do kanggo mbukak simulator Cadence Xcelium. Tindakake langkah iki lan nggawe skrip file kanggo Xcelium utawa nggunakake script file kasedhiya kanggo ngowahi ModelSim ME / ModelSim Pro ME run.do files menyang konfigurasi files needed kanggo mbukak simulasi nggunakake Xcelium.
4.1 Variabel Lingkungan (Takon Pitakonan)
Kanggo mbukak Cadence Xcelium, konfigurasi variabel lingkungan ing ngisor iki:

  1. LM_LISENSI_FILE: kudu kalebu pitunjuk kanggo lisensi file.
  2. cds_root: kudu tumuju menyang lokasi direktori ngarep Instalasi Cadence Incisive.
  3. PATH: kudu nuding lokasi bin ing direktori alat sing ditunjuk dening cds_root (ie
    $cds_root/tools/bin/64bit (kanggo mesin 64 bit lan $cds_root/tools/bin kanggo 32 bit
    mesin).

Ana telung cara kanggo nyetel lingkungan simulasi yen ana ngalih ing antarane sistem operasi 64-bit lan 32-bit:
Kasus 1: Variabel PATH
nyetel path = (install_dir/tools/bin/64bit $path) kanggo mesin 64bit lan
nyetel path = (install_dir / tools / bin $ path) kanggo mesin 32bit
Kasus 2: Nggunakake -64bit Command-line Option
Ing baris printah nemtokake -64-bit pilihan kanggo njaluk eksekusi 64-bit.
Kasus 3: Nyetel Variabel Lingkungan INCA_64BIT utawa CDS_AUTO_64BIT
Variabel INCA_64BIT dianggep minangka boolean. Sampeyan bisa nyetel variabel iki menyang sembarang nilai utawa null
senar.
setenv INCA_64BIT

MICROCHIP Libero SoC Simulation Library Software - lambang Penting: Ing Variabel lingkungan INCA_64BIT ora mengaruhi alat Cadence liyane, kayata alat IC. Nanging, kanggo alat Incisive, variabel INCA_64BIT ngatasi setelan kanggo variabel lingkungan CDS_AUTO_64BIT. Yen variabel lingkungan INCA_64BIT et, kabeh alat Incisive mbukak ing mode 64-dicokot.
setenv CDS_AUTO_64BIT Klebu:INCA
MICROCHIP Libero SoC Simulation Library Software - lambang Penting: Ing string INCA kudu nganggo huruf gedhe. Kabeh executable kudu mbukak ing salah siji mode 2-bit utawa ing mode 64-bit, aja nyetel variabel kanggo kalebu siji eksekusi, kaya ing ngisor iki:
setenv CDS_AUTO_64BIT KANGGO:ncelab
Piranti Cadence liyane, kayata alat IC, uga nggunakake variabel lingkungan CDS_AUTO_64BIT kanggo ngontrol pilihan eksekusi 32-bit utawa 64-bit. Tabel ing ngisor iki nuduhake carane sampeyan bisa nyetel variabel CDS_AUTO_64BIT kanggo mbukak alat Incisive lan alat IC ing kabeh mode.

Tabel 4-1. Variabel CDS_AUTO_64BIT

CDS_AUTO_64BIT Variabel Piranti Incisive Piranti IC
setenv CDS_AUTO_64BIT ALL 64-dicokot 64-dicokot
setenv CDS_AUTO_64BIT NONE 32-dicokot 32-dicokot
setenv CDS_AUTO_64BIT
EXCLUDE:ic_binary		 64-dicokot 32-dicokot
setenv CDS_AUTO_64BIT EXCLUDE:INCA 32-dicokot 64-dicokot

MICROCHIP Libero SoC Simulation Library Software - lambang penting: Kabeh alat Incisive kudu mbukak ing mode 32-bit utawa ing mode 64-bit, aja nganggo EXCLUDE kanggo ngilangi eksekusi tartamtu, kaya ing ngisor iki:
setenv CDS_AUTO_64BIT EXCLUDE:ncelab
Yen sampeyan nyetel variabel CDS_AUTO_64BIT kanggo ngilangi alat Incisive (setenv
CDS_AUTO_64BIT EXCLUDE:INCA), kabeh alat Incisive mbukak ing mode 32-bit. Nanging, ing
-64bit pilihan baris printah overrides variabel lingkungan.
Konfigurasi ing ngisor iki filembantu sampeyan ngatur data lan ngontrol operasi alat lan utilitas simulasi:

  • Pemetaan perpustakaan file (cds.lib) nemtokake jeneng logis kanggo lokasi desain sampeyan.
  • Pustaka lan nggandhengake karo jeneng direktori fisik.
  • Variabel file (hdl.var) nemtokake variabel sing mengaruhi prilaku alat simulasi lan keperluan.

4.2 Ngundhuh Pustaka Kompilasi (Takon Pitakonan)
Download perpustakaan kanggo Cadence Xcelium saka Microsemi's websitus.
4.3 Nggawe skrip Xcelium file (Takon Pitakonan)
Sawise nggawe salinan run.do files, nindakake langkah ing ngisor iki kanggo mbukak simulasi nggunakake script Xcelium file.

  1. Nggawe cds.lib file sing nemtokake perpustakaan sing bisa diakses lan ing ngendi panggonane.
    Ing file ngandhut statements sing map jeneng logis perpustakaan menyang path direktori fisik. Kanggo example, yen sampeyan mlaku simulasi presynth, cds.lib file bisa ditulis kaya sing ditampilake ing blok kode ing ngisor iki.
    DEFINE presynth ./presynth
    DEFINE COREAHBLITE_LIB ./COREAHBLITE_LIB
    DEFINE smartfusion2
  2. Nggawe hdl.var file kang konfigurasi opsional file sing ngemot variabel konfigurasi, sing nemtokake cara lingkungan desain sampeyan dikonfigurasi. Iki kalebu:
    – Variabel sing digunakake kanggo nemtokake perpustakaan karya ing ngendi compiler nyimpen obyek kompilasi lan data asale liyane.
    – Kanggo Verilog, variabel (LIB_MAP, VIEW_MAP, WORK) sing digunakake kanggo nemtokake perpustakaan lan views kanggo nelusuri nalika elaborator mutusake masalah kedadean.
    - Variabel sing ngidini sampeyan nemtokake opsi lan argumen baris perintah kompiler, elaborator, lan simulator.
    Ing kasus simulasi presynth example ditampilake ing ndhuwur, ngandika kita duwe 3 RTL files av, bv, lan testbench.v, sing kudu dikompilasi dadi perpustakaan presynth, COREAHBLITE_LIB, lan presynth. hdl.var file bisa ditulis kaya sing ditampilake ing blok kode ing ngisor iki.
    DEFINE KARYA presynth
    DEFINE PROYEK_DIR files>
    DEFINE LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/av => presynth )
    DEFINE LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/bv => COREAHBLITE_LIB )
    DEFINE LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/testbench.v => presynth )
    DEFINE LIB_MAP ($LIB_MAP, + => presynth )
  3. Nglumpukake desain files nggunakake opsi ncvlog.
    xmvlog +incdir+ –cdslib ./cds.lib –hdlvar ./hdl.var –logfile
    ncvlog.log –update –linedebug av bv testbench.v
  4. Njlentrehake desain nggunakake ncelab. Elaborator mbangun hirarki desain adhedhasar informasi instansiasi lan konfigurasi ing desain, netepake konektivitas sinyal, lan ngitung nilai awal kanggo kabeh obyek ing desain. Hierarki desain sing dijlentrehake disimpen ing snapshot simulasi, yaiku perwakilan desain sampeyan sing digunakake simulator kanggo mbukak simulasi.
    Xcelium –Pesen –cdslib ./cds.lib –hdlvar ./hdl.var –logfile ncelab.log –errormax 15 –
    akses +rwc –status worklib. : modul
    Elaborasi Sajrone simulasi Post-layout
    Ing cilik saka simulasi post-layout, pisanan SDF file kudu dikompilasi sadurunge njlentrehake nggunakake printah ncsdfc.
    Xceliumfilejeneng>.sdf –outputfilejeneng>.sdf.X
    Sajrone njlentrehake, gunakake output SDF sing dikompilasi kanthi opsi –autosdf kaya sing ditampilake ing blok kode ing ngisor iki.
    xmelab -autosdf –Pesen –cdslib ./cds.lib –hdlvar ./hdl.var –logfile ncelab.log –errormax
    15 –akses +rwc –status worklib. : modul –sdf_cmd_file ./
    sdf_cmd_file
    sdf_cmd_file kudu kaya sing dituduhake ing blok kode ing ngisor iki.
    COMPILED_SDF_FILE = “ file>”
  5. Simulasi nggunakake Xcelium. Sawise njlentrehake gambar simulasi digawe sing dimuat dening Xcelium kanggo simulasi. Iki bisa ditindakake ing mode batch utawa mode GUI.
    xmsim –Pesen –batch/-gui –cdslib ./cds.lib –hdlvar ./hdl.var –logfile xmsim.log –
    errormax 15 -status worklib. : modul
    Setup Xcelium Cadence
    MICROCHIP Libero SoC Simulation Library Software - lambang Penting: Kabeh telung langkah ing ndhuwur kanggo nyusun, njlentrehake lan simulasi bisa dilebokake ing skrip cangkang file lan sumber saka command-line. Tinimbang nggunakake telung langkah iki, desain bisa simulasi ing siji langkah nggunakake pilihan ncverilog utawa xrun minangka ditampilake ing codeblock ing ngisor iki.
    xmverilog +incdir+ -cdslib ./cds.lib –hdlvar ./hdl.var
    filedigunakake ing desain>
    xrun +incdir+ -cdslib ./cds.lib –hdlvar ./hdl.var files
    digunakake ing desain>

4.3.1 Masalah sing Dikenal (Takon Pitakonan)
Testbench Workaround
Nggunakake pratelan ing ngisor iki kanggo nemtokake frekuensi jam ing testbench sing digawe dening pangguna utawa testbench standar sing digawe Libero SoC ora bisa digunakake karo Xcelium.
tansah @(SYSCLK)
#(SYSCLK_PERIOD / 2.0) SYSCLK <= !SYSCLK;
Ngowahi kaya ing ngisor iki kanggo mbukak simulasi:
tansah #(SYSCLK_PERIOD / 2.0) SYSCLK = ~SYSCLK;

MICROCHIP Libero SoC Simulation Library Software - lambang penting: Pustaka sing dikompilasi kanggo Xcelium khusus platform (yaiku perpustakaan 64 bit ora kompatibel karo platform 32 bit lan kosok balene).
Simulasi Postsynth lan Post-layout nggunakake MSS lan SERDES
Nalika nglakokake simulasi postsynth saka desain sing ngemot blok MSS, utawa simulasi post-layout saka desain nggunakake SERDES, simulasi BFM ora bisa digunakake yen opsi -libmap ora ditemtokake sajrone elaborasi. Iki amarga nalika njlentrehake, MSS ditanggulangi saka perpustakaan karya (amarga ikatan standar lan worklib dadi postsynth / post-layout) ing ngendi iku mung Fungsi Tetap.
Printah ncelab kudu ditulis minangka ditampilake ing pemblokiran kode ing ngisor iki kanggo mutusake masalah pemblokiran MSS saka SmartFusion2 perpustakaan precompiled.
xmelab -libmap lib.map -libverbose -Pesen -akses +rwc cfg1
lan lib.map file kudu kaya ing ngisor iki:
konfigurasi cfg1;
desain ;
standar liblist smartfusion2 ;
endconfig
Iki kudu ngrampungake sel apa wae ing perpustakaan SmartFusion2 sadurunge katon ing perpustakaan karya yaiku postsynth/post-layout.
Opsi -libmap bisa digunakake kanthi standar sajrone elaborasi kanggo saben simulasi (presynth, postsynth lan post-layout). Iki ngindhari masalah simulasi sing disebabake amarga resolusi kasus saka perpustakaan.
xmelab: *F,INTERR: PENGECUALIAN INTERNAL
Pangecualian alat ncelab iki minangka caveat kanggo desain sing ngemot FDDR ing SmartFusion2 lan IGLOO2
sajrone simulasi postsynth lan post-layout nggunakake opsi -libmap.
MICROCHIP Libero SoC Simulation Library Software - lambang penting: Masalah iki wis dilaporake menyang tim dhukungan Cadence (SAR 52113).

4.4 Sample Tcl lan shell script files (Takon Pitakonan)
Ing ngisor iki files iku konfigurasi files needed kanggo nyetel desain lan shell script file kanggo mlaku printah Xcelium.
Cds.lib
DEFINE smartfusion2 /scratch/krydor/tmpspace/users/me/nc-vlog64/SmartFusion2
DEFINE COREAHBLITE_LIB ./COREAHBLITE_LIB
DEFINE presynth ./presynth
Hdl.var
DEFINE KARYA presynth
DEFINE PROJECT_DIR /scratch/krydor/tmpspace/sqausers/me/3rd_party_simulators/Cadence/IGLOO2/
ENVM/M2GL050/envm_fic1_ser1_v/eNVM_fab_master
DEFINE LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/komponen/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/core/coreahblite_addrdec.v => COREAHBLITE_LIB )
DEFINE LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/komponen/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/core/coreahblite_defaultslavesm.v => COREAHBLITE_LIB )
DEFINE LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/komponen/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/inti/coreahblite_masterstagev => COREAHBLITE_LIB )
DEFINE LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/komponen/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/core/coreahblite_slavearbiter.v => COREAHBLITE_LIB )
DEFINE LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/komponen/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/inti/coreahblite_slavestagev => COREAHBLITE_LIB )
DEFINE LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/komponen/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/core/coreahblite_matrix2x16.v => COREAHBLITE_LIB )
DEFINE LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/komponen/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/core/coreahblite.v => COREAHBLITE_LIB )
DEFINE LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/component/work/SB/CCC_0/SB_CCC_0_FCCC.v =>
presynth)
DEFINE LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/komponen/Actel/DirectCore/CoreConfigMaster/
2.0.101/rtl/vlog/core/coreconfigmaster.v => presynth )
DEFINE LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreConfigP/4.0.100/rtl/
vlog/core/coreconfigp.v => presynth )
DEFINE LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreResetP/5.0.103/rtl/
vlog/core/coreresetp_pcie_hotreset.v => presynth )
DEFINE LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreResetP/5.0.103/rtl/
vlog/core/coreresetp.v => presynth )
DEFINE LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/component/work/SB/FABOSC_0/SB_FABOSC_0_OSC.v =>
presynth)
DEFINE LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/component/work/SB_HPMS/SB_HPMS.v => presynth )
DEFINE LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/component/work/SB/SB.v => presynth )
DEFINE LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/component/work/SB_top/SERDES_IF_0/
SB_top_SERDES_IF_0_SERDES_IF.v => presynth )
DEFINE LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/component/work/SB_top/SB_top.v => presynth )
DEFINE LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/component/work/SB_top/testbench.v => presynth )
DEFINE LIB_MAP ($LIB_MAP, + => presynth )
Commands.csh
ncvlog +incdir+../../component/work/SB_top -cdslib ./cds.lib -hdlvar ./hdl.var -logfile
ncvlog.log -errormax 15 -update -linedebug
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite_addrdec.v
../../komponen/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/inti/
coreahblite_defaultslavesm.v
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite_masterstagev
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite_slavearbiter.v
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite_slavestagev
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite_matrix2x16.v
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite.v
../../component/work/SB/CCC_0/SB_CCC_0_FCCC.v
../../component/Actel/DirectCore/CoreConfigMaster/2.0.101/rtl/vlog/core/coreconfigmaster.v
../../component/Actel/DirectCore/CoreConfigP/4.0.100/rtl/vlog/core/coreconfigp.v
../../component/Actel/DirectCore/CoreResetP/5.0.103/rtl/vlog/core/coreresetp_pcie_hotreset.v
../../component/Actel/DirectCore/CoreResetP/5.0.103/rtl/vlog/core/coreresetp.v
../../komponen/kerja/SB/FABOSC_0/SB_FABOSC_0_OSC.v ../../komponen/kerja/SB_HPMS/SB_HPMS.v
../../komponen/kerja/SB/SB.v ../../komponen/kerja/SB_top/SERDES_IF_0/
SB_TOP_SERDES_IF_0_SERDES_IF.v
../../component/work/SB_top/SB_top.v ../../component/work/SB_top/testbench.v
ncelab -Pesen -cdslib ./cds.lib -hdlvar ./hdl.var
-work presynth -logfile ncelab.log -errormax 15 -akses +rwc -status presynth.testbench:modul
ncsim -Pesen -batch -cdslib ./cds.lib -hdlvar ./
hdl.var -logfile ncsim.log -errormax 15 -status presynth.testbench:modul

4.5 Otomasi (Microchip Login)
Skripsi ing ngisor iki file ngowahi ModelSim run.do files menyang konfigurasi files needed kanggo mbukak simulasi nggunakake Xcelium.
Skripsi File Panganggone
perl cadence_parser.pl presynth_run.do postsynth_run.do
postlayout_run.do Microsemi_Family
Location_of_Cadence_Precompiled_libraries
Cadence_parser.pl
#!/usr/bin/perl -w

################################################## ##############################################
##################
#Usage: perl questa_parser.pl presynth_run.do postsynth_run.do postlayout_run.do
Microsemi_Family Precompiled_Libraries_location#

################################################## ##############################################
##################
nggunakake POSIX;
nggunakake ketat;
sandi ($presynth, $postsynth, $postlayout, $kulawarga, $lib_location) = @ARGV;
&questa_parser ($presynth, $kulawarga, $lib_location);
&questa_parser ($postsynth, $kulawarga, $lib_location);

&questa_parser ($postlayout, $kulawarga, $lib_location);
sub questa_parser {
sandi $ModelSim_run_do = $_[0];
kula $actel_family = $_[1];
my $lib_location = $_[2];
sandi $ negara;
yen (-e "$ModelSim_run_do")
{
mbukak (INFILE,"$ModelSim_run_do");
sandi @ModelSim_run_do =FILE>;
sandi $ baris;
yen ($ModelSim_run_do =~ m/(presynth)/)
{
`mkdir QUESTA_PRESYNTH`;
mbukak (FILE,”>QUESTA_PRESYNTH/presynth_questa.do”);
$negara = $1;
} elsif ($ModelSim_run_do =~ m/(postsynth)/)
{
`mkdir QUESTA_POSTSYNTH`;
mbukak (FILE,">QUESTA_POSTSYNTH/postsynth_questa.do");
$negara = $1;
} elsif ($ModelSim_run_do =~ m/(postlayout)/ )
{
`mkdir QUESTA_POSTLAYOUT`;
mbukak (FILE,">QUESTA_POSTLAYOUT/postlayout_questa.do");
$negara = $1;
} liya
{
print "Salah Input sing diwenehake menyang file\n”;
print “#Usage: perl questa_parser.pl presynth_run.do postsynth_run.do postlayout_run.do
\"Lokasi_Perpustakaan\"\n";
}
foreach $line (@ModelSim_run_do)
{
#Operasi Umum
$line =~ s/..\/designer.*simulasi\///g;
$line =~ s/$state/$state\_questa/g;
#print OUTFILE "$line \n";
yen ($line =~ m/vmap\s+.*($actel_family)/)
{
print OUTFILE "vmap $actel_family \"$lib_location\"\n";
} elsif ($line =~ m/vmap\s+(.*._LIB)/)
{
$line =~ s/..\/komponen/..\/..\/komponen/g;
print OUTFILE "$line \n";
} elsif ($line =~ m/vsim/)
{
$line =~ s/vsim/vsim -novopt/g;
print OUTFILE "$line \n";
} liya
{
print OUTFILE "$line \n";
}
}
nutup (INFILE);
nutup (OUTFILE);
} liyane {
print "$ ModelSim_run_do ora ana. Run maneh simulasi \n";
}
}

Siemens QuestaSim Setup/ModelSim Setup (Takon Pitakonan)

Run.do files, kui dening Libero SoC kanggo simulasi nggunakake ModelSim Microsemi Editions, bisa digunakake kanggo simulasi nggunakake QuestaSim / ModelSim SE / DE / PE karo owah-owahan siji. Ing ModelSim ME / ModelSim Pro ME run.do file, lokasi perpustakaan sing wis dikompilasi kudu diowahi.
MICROCHIP Libero SoC Simulation Library Software - lambang penting: 
Kanthi gawan, alat simulasi saliyane ModelSim Pro ME nindakake optimasi desain sajrone simulasi sing bisa nyebabake visibilitas menyang artefak simulasi kayata obyek desain lan stimulus input.
Iki biasane mbiyantu nyuda runtime simulasi kanggo simulasi Komplek, nggunakake verbose, testbenches poto-mriksa. Nanging, optimasi standar bisa uga ora cocog kanggo kabeh simulasi, utamane yen sampeyan ngarepake mriksa asil simulasi kanthi grafis nggunakake jendela gelombang.
Kanggo ngatasi masalah sing disebabake optimasi iki, sampeyan kudu nambah prentah sing cocog lan argumen sing gegandhengan sajrone simulasi kanggo mulihake visibilitas menyang desain. Kanggo prentah khusus alat, deleng dokumentasi simulator sing digunakake.

5.1 Variabel Lingkungan (Takon Pitakonan)
Ing ngisor iki minangka variabel lingkungan sing dibutuhake.

  • LM_LISENSI_FILE: kudu kalebu path kanggo lisensi file.
  • MODEL_TECH: kudu ngenali path menyang lokasi direktori ngarep instalasi QuestaSim.
  • PATH: kudu tumuju menyang lokasi eksekusi sing ditunjuk dening MODEL_TECH.

5.2 Ngonversi run.do kanggo Mentor QuestaSim (Takon Pitakonan)
Run.do files kui dening Libero SoC kanggo simulasi nggunakake ModelSim Microsemi Editions bisa digunakake kanggo simulasi nggunakake QuestaSim / ModelSim_SE karo owah-owahan siji.
MICROCHIP Libero SoC Simulation Library Software - lambang Penting: Kabeh designs kang simulasi nggunakake QuestaSim kudu kalebu -novopt
pilihan bebarengan karo vsim printah ing script run.do files.
5.3 Ngundhuh Pustaka Kompilasi (Takon Pitakonan)
Download perpustakaan kanggo Mentor Graphics QuestaSim saka Microsemi's websitus.

Synopsys VCS Setup (Takon Pitakonan)

Aliran sing disaranake dening Microsemi gumantung marang aliran Elaborate lan Compile ing VCS. Dokumen iki kalebu skrip file sing nggunakake script run.do files kui dening Libero SoC lan ngasilake persiyapan files needed kanggo simulasi VCS. Skripsi file nggunakake run.do file kanggo nindakake ing ngisor iki.

  • Nggawe pemetaan perpustakaan file, kang wis rampung nggunakake synopsys_sim.setup file dumunung ing direktori padha ngendi simulasi VCS mlaku.
  • Nggawe skrip cangkang file kanggo njlentrehake lan ngumpulake desain sampeyan nggunakake VCS.

6.1 Variabel Lingkungan (Takon Pitakonan)
Setel variabel lingkungan sing cocog kanggo VCS adhedhasar persiyapan sampeyan. Variabel lingkungan sing dibutuhake miturut dokumentasi VCS yaiku:

  • LM_LISENSI_FILE: kudu kalebu pointer menyang server lisensi.
  • VCS_HOME: kudu nuduhake lokasi direktori ngarep instalasi VCS.
  • PATH: kudu kalebu pointer menyang direktori bin ing ngisor direktori VCS_HOME.

6.2 Ngundhuh Pustaka Kompilasi (Takon Pitakonan)
Download perpustakaan kanggo Synopsys VCS saka Microsemi's websitus.
6.3 Skrip Simulasi VCS File (Takon Pitakonan)
Sawise nyiyapake VCS lan ngasilake desain lan run.do beda filesaka Libero SoC, sampeyan kudu:

  1. Nggawe pemetaan perpustakaan file synopsys_sim.setup; iki file ngemot penunjuk menyang lokasi kabeh perpustakaan sing bakal digunakake dening desain.
    MICROCHIP Libero SoC Simulation Library Software - lambang  Penting: Ing file jeneng kudu ora ngganti lan kudu dumunung ing direktori padha ngendi simulasi mlaku. Iki mantanample kanggo kuwi a file kanggo simulasi presynthesis.
    KERJA > EFAULT
    SmartFusion2:
    presynth: ./presynth
    DEFAULT : ./karya
  2. Njlentrehake desain sing beda files, kalebu testbench, nggunakake printah vlogan ing VCS. Prentah kasebut bisa uga kalebu ing skrip cangkang file. Ngisor iki mantanample saka printah sing perlu kanggo njlimet desain ditetepake ing rtl.v karo testbench ditetepake ing
    testbench.v.
    vlogan +v2k -work presynth rtl.v
    vlogan +v2k -work presynth testbench.v
  3. Kompilasi desain nggunakake VCS nggunakake printah ing ngisor iki.
    vcs –sim_res=1fs presynth.testbench
    Cathetan: Ing résolusi wektu saka simulasi kudu disetel kanggo 1fs kanggo simulasi fungsi bener.
  4. Sawise desain wis disusun, miwiti simulasi nggunakake printah ing ngisor iki.
    ./simv
  5. Kanggo simulasi back-anotasi, printah VCS kudu kaya sing ditampilake ing pamblokiran kode ing ngisor iki.
    vcs postlayout.testbench –sim_res=1fs –sdf maks: .
    jeneng>: file path> –gui –l postlayout.log

6.4 Watesan/Pengecualian (Takon Pitakonan)
Ing ngisor iki watesan / pangecualian saka persiyapan Synopsys VCS.

  • simulasi VCS bisa mbukak mung kanggo proyek Verilog saka Libero SoC. Simulator VCS nduweni syarat basa VHDL sing ketat sing ora ditindakake dening VHDL sing digawe otomatis Libero SoC. files.
  • Sampeyan kudu $ rampung statement ing testbench Verilog kanggo mungkasi simulasi kapan pengin.
    MICROCHIP Libero SoC Simulation Library Software - lambang Penting: Nalika simulasi mbukak ing mode GUI, wektu mbukak bisa kasebut ing GUI.

6.5 Sample Tcl lan Shell Script Files (Takon Pitakonan)
Perl ing ngisor iki ngotomatisasi generasi synopsys_sim.setup file uga skrip cangkang sing cocog files dibutuhake kanggo njlimet, ngumpulake, lan simulasi desain.
Yen desain nggunakake MSS, nyalin test.vec file dumunung ing folder simulasi proyek Libero SoC menyang folder simulasi VCS. Bagean ing ngisor iki ngemot sample run.do files kui dening Libero SoC, kalebu pemetaan perpustakaan cocog lan shell script files needed kanggo simulasi VCS.
6.5.1 Pra-sintesis (Takon Pitakonan)
Presynth_run.do
kanthi tenang nyetel ACTELLIBNAME SmartFusion2
kanthi tenang nyetel PROJECT_DIR "/sqa/users/me/VCS_Tests/Test_DFF"
yen {[file ana presynth/_info]} {
echo "INFO: Simulasi perpustakaan presynth wis ana"
} liyane {
vlib presynth
}
vmap presynth presynth
vmap SmartFusion2 “/captures/lin/11_0_0_23_11prod/lib/ModelSim/precompiled/vlog/smartfusion2”
vlog -work presynth "${PROJECT_DIR}/component/work/SD1/SD1.v"
vlog "+incdir+${PROJECT_DIR}/stimulus" -work presynth "${PROJECT_DIR}/stimulus/SD1_TB1.v"
vsim -L SmartFusion2 -L presynth -t 1fs presynth.SD1_TB1
tambah gelombang /SD1_TB1/*
tambah log -r /*
mlaku 1000ns
presynth_main.csh
#!/bin/csh -f
atur PROJECT_DIR = "/sqa/users/Me/VCS_Tests/Test_DFF"
/cad_design/tools/vcs.dir/E-2011.03/bin/vlogan +v2k -work presynth “${PROJECT_DIR}/component/
kerja/SD1/SD1.v”
/cad_design/tools/vcs.dir/E-2011.03/bin/vlogan +v2k “+incdir+${PROJECT_DIR}/stimulus” -work
presynth "${PROJECT_DIR}/stimulus/SD1_TB1.v"
/cad_design/tools/vcs.dir/E-2011.03/bin/vcs -sim_res=1fs presynth.SD1_TB1 -l compile.log
./simv -l run.log
Synopsys_sim.setup
KARYA > DEFAULT
SmartFusion2 : /VCS/SmartFusion2
presynth: ./presynth
DEFAULT : ./karya

6.5.2 Pasca-sintesis (Takon Pitakonan)
postsynth_run.do
kanthi tenang nyetel ACTELLIBNAME SmartFusion2
kanthi tenang nyetel PROJECT_DIR "/sqa/users/Me/VCS_Tests/Test_DFF"
yen {[file ana postsynth/_info]} {
echo "INFO: Simulasi perpustakaan postsynth wis ana"
} liyane {
vlib postsynth
}
vmap postsynth postsynth
vmap SmartFusion2 “//idm/captures/pc/11_0_1_12_g4x/Designer/lib/ModelSim/precompiled/vlog/
SmartFusion 2"
vlog -work postsynth "${PROJECT_DIR}/synthesis/SD1.v"
vlog "+incdir+${PROJECT_DIR}/stimulus" -work postsynth "${PROJECT_DIR}/stimulus/SD1_TB1.v"
vsim -L SmartFusion2 -L postsynth -t 1fs postsynth.SD1_TB1
tambah gelombang /SD1_TB1/*
tambah log -r /*
mlaku 1000ns
log SD1_TB1/*
metu
Postsynth_main.csh
#!/bin/csh -f
atur PROJECT_DIR = "/sqa/users/Me/VCS_Tests/Test_DFF"
/cad_design/tools/vcs.dir/E-2011.03/bin/vlogan +v2k -work postsynth “${PROJECT_DIR}/synthesis/
SD 1.v”
/cad_design/tools/vcs.dir/E-2011.03/bin/vlogan +v2k “+incdir+${PROJECT_DIR}/stimulus” -work
postsynth "${PROJECT_DIR}/stimulus/SD1_TB1.v"
/cad_design/tools/vcs.dir/E-2011.03/bin/vcs -sim_res=1fs postsynth.SD1_TB1 -l compile.log
./simv -l run.log
Synopsys_sim.setup
KARYA > DEFAULT
SmartFusion2 : /VCS/SmartFusion2
postsynth: ./postsynth
DEFAULT : ./karya
6.5.3 Post-layout (Takon Pitakonan)
postlayout_run.do
kanthi tenang nyetel ACTELLIBNAME SmartFusion2
kanthi tenang nyetel PROJECT_DIR "E:/ModelSim_Work/Test_DFF"
yen {[file ana ../designer/SD1/simulation/postlayout/_info]} {
echo "INFO: Pustaka simulasi ../designer/SD1/simulation/postlayout already exists"
} liyane {
vlib ../designer/SD1/simulation/postlayout
}
vmap postlayout ../designer/SD1/simulation/postlayout
vmap SmartFusion2 “//idm/captures/pc/11_0_1_12_g4x/Designer/lib/ModelSim/precompiled/vlog/
SmartFusion 2"
vlog -postlayout kerja "${PROJECT_DIR}/designer/SD1/SD1_ba.v"
vlog "+incdir+${PROJECT_DIR}/stimulus" -postlayout kerja "${PROJECT_DIR}/stimulus/SD1_TB1.v"
vsim -L SmartFusion2 -L postlayout -t 1fs -sdfmax /SD1_0=${PROJECT_DIR}/designer/SD1/
SD1_ba.sdf postlayout.SD1_TB1
tambah gelombang /SD1_TB1/*
tambah log -r /*
mlaku 1000ns
Postlayout_main.csh
#!/bin/csh -f
atur PROJECT_DIR = "/VCS_Tests/Test_DFF"
/cad_design/tools/vcs.dir/E-2011.03/bin/vlogan +v2k -postlayout kerja “${PROJECT_DIR}/
desainer/SD1/SD1_ba.v”
/cad_design/tools/vcs.dir/E-2011.03/bin/vlogan +v2k “+incdir+${PROJECT_DIR}/stimulus” -work
postlayout "${PROJECT_DIR}/stimulus/SD1_TB1.v"
/cad_design/tools/vcs.dir/E-2011.03/bin/vcs -sim_res=1fs postlayout.SD1_TB1 -sdf

max:SD1_TB1.SD1_0:${PROJECT_DIR}/designer/SD1/SD1_ba.sdf -l compile.log
./simv -l run.log
Synopsys_sim.setup
KARYA > DEFAULT
SmartFusion2 : /VCS/SmartFusion2
postlayout: ./postlayout
DEFAULT: ./workVCS
6.6 Otomasi (Takon Pitakonan)
Aliran kasebut bisa otomatis nggunakake skrip Perl ing ngisor iki file kanggo ngowahi ModelSim run.do files menyang skrip cangkang sing kompatibel karo VCS files, nggawe direktori sing tepat ing direktori simulasi Libero SoC, banjur mbukak simulasi.
Jalanake skrip file nggunakake sintaksis ing ngisor iki.
perl vcs_parse.pl presynth_run.do postsynth_run.do postlayout_run.do
Vcs_parse_pl
#!/usr/bin/perl -w
################################################## ############################
#
#Usage: perl vcs_parse.pl presynth_run.do postsynth_run.do postlayout_run.do
#
################################################## ############################
my ($presynth, $postsynth, $postlayout) = @ARGV;
if(system(“mkdir VCS_Presynth”)) {print “mkdir failed:\n”;}
if(system(“mkdir VCS_Postsynth”)) {print “mkdir failed:\n”;}
if(system(“mkdir VCS_Postlayout”)) {print “mkdir failed:\n”;}
chdir(VCS_Presynth);
`cp ../$ARGV[0] .` ;
&parse_do ($presynth,"presynth");
chdir (“../”);
chdir(VCS_Possynth);
`cp ../$ARGV[1] .` ;
&parse_do($postsynth,"postsynth");
chdir (“../”);
chdir(VCS_Postlayout);
`cp ../$ARGV[2] .` ;
&parse_do ($postlayout,"postlayout");
chdir (“../”);
sub parse_do {
sandi $ vlog = "/cad_design/tools/vcs.dir/E-2011.03/bin/vlogan +v2k" ;
sandi%LIB = ();
$kufile = $_[0] ;
$negaraku = $_[1];
mbukak (INFILE,”$file”) || mati "Ora bisa mbukak File Alesan bisa uga:$!”;
if ($state eq "presynth")
{
mbukak(OUT1,">presynth_main.csh") || mati "Ora bisa nggawe Command File Alesan bisa uga:$!”;
}
elsif ($state eq “postsynth” )
{
mbukak(OUT1,">postsynth_main.csh") || mati "Ora bisa nggawe Command File Alesan bisa uga:$!”;
}
elsif ($state eq "postlayout")
{
mbukak(OUT1,">postlayout_main.csh") || mati "Ora bisa nggawe Command File Alesan bisa uga:$!”;
}
liyane
{
print "Simulasi State is missing \n" ;
}
mbukak(OUT2,">synopsys_sim.setup") || mati "Ora bisa nggawe Command File Alesan bisa uga:$!”;
# .csh file
print OUT1 "#!/bin/csh -f\n\n\n" ;
#SETUP FILE
print OUT2 "WORK > DEFAULT\n" ;
print OUT2 “SmartFusion2 : /sqa/users/Aditya/VCS/SmartFusion2\n” ;
while ($line =FILE>)
{

Synopsys VCS Setup

if ($line =~ m/quietly set PROJECT_DIR\s+\”(.*?)\”/)
{
print OUT1 "set PROJECT_DIR = \"$1\"\n\n\n" ;
}
elsif ($line =~ m/vlog.*\.v\”/ )
{
if ($line =~ m/\s+(\w*?)\_LIB/)
{
#print “\$1 =$1 \n” ;
$temp = “$1″.”_LIB”;
#print “Temp = $temp \n” ;
$LIB{$temp}++;
}
chomp($line);
$line =~ s/^vlog/$vlog/ ;
$baris =~ s/ //g;
print OUT1 "$line\n";
}
elsif ( ($line =~ m/vsim.*presynth\.(.*)/) || ($line =~ m/vsim.*postsynth\.(.*)/) || ($line
=~ m/vsim.*postlayout\.(.*)/) )
{
$tb = $1 ;
$tb =~ s/ //g;
chomp($tb);
#print "Nama TB : $tb \n";
if ($line =~ m/sdf(.*)\.sdf/)
{
chomp($line);
$line = $1;
#print "LINE : $line \n" ;
yen ($baris =~ m/maks/)
{
$line =~ s/maks \/// ;
$line =~ s/=/:/;
print OUT1 "\n\n/cad_design/tools/vcs.dir/E-2011.03/bin/vcs -sim_res=1fs postlayout.$tb -sdf
maks:$tb.$line.sdf -l compile.log\n” ;
}
elsif ($line =~ m/min/)
{
$line =~ s/min \/// ;
$line =~ s/=/:/;
print OUT1 "\n\n/cad_design/tools/vcs.dir/E-2011.03/bin/vcs -sim_res=1fs postlayout.$tb -sdf
min:$tb.$line.sdf -l compile.log\n” ;
}
elsif ($line =~ m/typ/)
{
$line =~ s/typ \/// ;
$line =~ s/=/:/;
print OUT1 "\n\n/cad_design/tools/vcs.dir/E-2011.03/bin/vcs -sim_res=1fs postlayout.$tb -sdf
typ:$tb.$line.sdf -l compile.log\n” ;
}
#-sdfmax /M3_FIC32_0=${PROJECT_DIR}/designer/M3_FIC32/M3_FIC32_ba.sdf — Format ModelSim SDF
#$sdf = "-sdf max: testbench.M3_FIC32_0: ${PROJECT_DIR}/designer/M3_FIC32/M3_FIC32_ba.sdf"; -VCS
format SDF
}
}
}
nyetak
OUT1 "\n\n"
;
if
($state eq "presynth"
)
{
nyetak
OUT2 "presynth
: ./presynth\n”
;
nyetak
OUT1 "/cad_design/tools/vcs.dir/E-2011.03/bin/vcs
-sim_res=1fs presynth.$tb -l
compile.log\n”
;
}
elsif
($state eq "postsynth"
)
{
nyetak
OUT2 "postsynth
: ./postsynth\n”
;
nyetak
OUT1 "/cad_design/tools/vcs.dir/E-2011.03/bin/vcs
-sim_res=1fs postsynth.$tb -l
compile.log\n”
;
}
elsif
($state eq "postlayout"
)
{
print OUT2 "postlayout : ./postlayout\n" ;
}
liyane
{
print "Simulasi State is missing \n" ;
}
foreach $i (kunci %LIB)
{
#print “Kunci : $i Nilai : $LIB{$i} \n” ;
print OUT2 “$i : ./$i\n” ;
}
print OUT1 "\n\n" ;
print OUT1 “./simv -l run.log\n” ;
print OUT2 “DEFAULT : ./work\n” ;
nutup INFILE;
nutup OUT1;
nutup OUT2;
}

Riwayat Revisi (Microchip Login

Riwayat revisi nggambarake owah-owahan sing ditindakake ing dokumen kasebut. Owah-owahan
didaftar kanthi revisi, diwiwiti saka publikasi paling anyar.

Revisi Tanggal Katrangan
A 12/2023 Owah-owahan ing ngisor iki ditindakake ing revisi iki:
• Dokumen diowahi kanggo Cithakan Microchip. Revisi wiwitan.
• Dianyari bagean 5. Siemens QuestaSim Setup / ModelSim Setup kanggo kalebu cathetan anyar sing nerangake impact ing visibilitas sak simulasi lan Optimization.

Dhukungan FPGA Microchip
Klompok produk Microchip FPGA ndhukung produk karo macem-macem layanan dhukungan, kalebu Layanan Pelanggan, Pusat Dhukungan Teknis Pelanggan, a websitus, lan kantor sales donya.
Pelanggan disaranake ngunjungi sumber online Microchip sadurunge ngubungi dhukungan amarga kemungkinan pitakone wis dijawab.
Hubungi Pusat Dhukungan Teknis liwat websitus ing www.microchip.com/support. Sebutake nomer Komponen Piranti FPGA, pilih kategori kasus sing cocog, lan upload desain files nalika nggawe cilik support technical.
Hubungi Layanan Pelanggan kanggo dhukungan produk non-teknis, kayata rega produk, upgrade produk, informasi nganyari, status pesenan, lan wewenang.

  • Saka Amerika Utara, telpon 800.262.1060
  • Saka negara liya, hubungi 650.318.4460
  • Fax, saka ngendi wae ing donya, 650.318.8044

Informasi Microchip
Microchip kasebut Websitus
Microchip nyedhiyakake dhukungan online liwat kita websitus ing www.microchip.com/. Iki websitus digunakake kanggo nggawe files lan informasi gampang kasedhiya kanggo pelanggan. Sawetara konten sing kasedhiya kalebu:

  • Dhukungan Produk - Lembar data lan kesalahan, cathetan aplikasi lan sampprogram le, sumber desain, Panuntun pangguna lan dokumen support hardware, Rilis piranti lunak paling anyar lan piranti lunak arsip
  • Dhukungan Teknis Umum - Pitakonan sing Sering Ditakoni (FAQ), panjalukan dhukungan teknis, grup diskusi online, daftar anggota program mitra desain Microchip
  • Bisnis Microchip - Pandhuan pamilih lan pesenan produk, siaran pers Microchip paling anyar, dhaptar seminar lan acara, dhaptar kantor penjualan Microchip, distributor lan perwakilan pabrik

Layanan Notifikasi Ganti Produk
Layanan kabar pangowahan produk Microchip mbantu para pelanggan tetep saiki ing produk Microchip. Pelanggan bakal nampa kabar email yen ana owah-owahan, nganyari, revisi utawa kesalahan sing ana gandhengane karo kulawarga produk utawa alat pangembangan sing dikarepake.
Kanggo ndhaftar, pindhah menyang www.microchip.com/pcn lan tindakake pandhuan registrasi.
Dhukungan Pelanggan
Pangguna produk Microchip bisa nampa pitulung liwat sawetara saluran:

  • Distributor utawa Perwakilan
  • Kantor Penjualan Lokal
  • Embedded Solution Engineer (ESE)
  • Dhukungan Teknis

Pelanggan kudu hubungi distributor, wakil utawa ESE kanggo dhukungan. Kantor penjualan lokal uga kasedhiya kanggo mbantu para pelanggan. Dhaptar kantor penjualan lan lokasi kalebu ing dokumen iki.
Dhukungan teknis kasedhiya liwat websitus ing: www.microchip.com/support
Fitur Proteksi Kode Piranti Microchip
Elinga rincian ing ngisor iki babagan fitur perlindungan kode ing produk Microchip:

  • Produk Microchip cocog karo spesifikasi sing ana ing Lembar Data Microchip tartamtu.
  • Microchip percaya yen kulawarga produk kasebut aman nalika digunakake kanthi cara sing dikarepake, ing spesifikasi operasi, lan ing kahanan normal.
  • Nilai Microchip lan agresif nglindhungi hak properti intelektual sawijining. Usaha kanggo nglanggar fitur perlindungan kode produk Microchip dilarang banget lan bisa uga nglanggar Digital Millennium Copyright Act.
  • Microchip utawa pabrikan semikonduktor liyane ora bisa njamin keamanan kode kasebut. Proteksi kode ora ateges manawa produk kasebut "ora bisa dipecah".
    Proteksi kode terus berkembang. Microchip nduweni komitmen kanggo terus ningkatake fitur perlindungan kode produk kita.

Kabar Legal
Publikasi iki lan informasi ing kene mung bisa digunakake karo produk Microchip, kalebu kanggo ngrancang, nguji, lan nggabungake produk Microchip karo aplikasi sampeyan. Panganggone informasi iki kanthi cara liya nglanggar syarat kasebut. Informasi babagan aplikasi piranti diwenehake mung kanggo penak sampeyan lan bisa uga diganti karo nganyari. Sampeyan tanggung jawab kanggo mesthekake yen aplikasi sampeyan cocog karo spesifikasi sampeyan. Hubungi kantor sales Microchip lokal kanggo dhukungan tambahan utawa, entuk dhukungan tambahan ing www.microchip.com/en-us/support/design-help/client-support-services.
INFORMASI IKI DISEDIAKAN BY MICROCHIP "AS IS". MICROCHIP TANPA REPRESENTASI UTAWA JAMINAN APA SAJA APA SAJA UTAWA TERSURAT, TERTULIS UTAWA LISAN, STATUTORY UTAWA LAIN, sing ana hubungane karo informasi kasebut kalebu nanging ora winates karo JAMINAN NON-INFLARITY, NON-INFRINGEMENT. TUJUAN, Utawa JAMINAN sing ana gandhengane karo KONDISI, KUALITAS, UTAWA KINERJA.
MICROCHIP ORA TANGGUH TANGGUNG JAWAB ANGGAP, KHUSUS, PUNITIF, INSIDENTAL, UTAWA KONSEQUENTIAL RUGI, RUSAK, BIAYA, UTAWA BAYARAN APA SAJA KANGGO ING INFORMASI UTAWA PENGGUNAAN, NANGUN SING DIBUAT, SANAYAN ANA KEMUNGKINAN UTAWA KERUSAKAN SING BISA DIPIKIR. TO THE FULLEST EXTENT diijini dening hukum, TANGGUNG JAWAB TOTAL MICROCHIP ING ALL CLAIMS ing sembarang cara sing ana hubungane karo informasi utawa panggunaan ora ngluwihi jumlah biaya, yen ana, sing sampeyan wis mbayar langsung menyang microchip kanggo informasi.
Panggunaan piranti Microchip ing support urip lan / utawa aplikasi safety tanggung ing resiko panuku, lan panuku setuju kanggo defend, indemnify lan terus Microchip mbebayani saka samubarang lan kabeh karusakan, claims, cocog, utawa expenses asil saka nggunakake kuwi. Ora ana lisensi sing diwenehake, kanthi implisit utawa liya, miturut hak properti intelektual Microchip kajaba kasebut.
merek dagang
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AgileSwitch, APT, ClockWorks, Perusahaan Solusi Kontrol Embedded, EtherSynch, Flashtec, Kontrol Kacepetan Hiper, Beban HyperLight, Libero, motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus, logo ProASIC Plus, Quiet- Wire, SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub, TimePictra, TimeProvider, TrueTime, lan ZL minangka merek dagang kadhaptar saka Microchip Technology Incorporated ing AS
Penindasan Kunci Adjacent, AKS, Analog-kanggo-Digital Age, Kapasitor Apa wae, AnyIn, AnyOut, Switching Augmented, BlueSky, BodyCom, Clockstudio, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net Average Matching, Dynamic Matching , DAM, ECAN, Espresso T1S, EtherGREEN, GridTime, IdealBridge, In-Circuit Serial Programming, ICSP, INICnet, Intelligent Paralleling, IntelliMOS, Inter-Chip Connectivity, JitterBlocker, Knob-on-Display, KoD, maxCrypto, maxView, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net,
PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, RTAX, RTG4, SAMICE, Serial Quad I/O, simpleMAP, SimpliPHY, SmartBuffer, SmartHLS, SMART-IS, storClad, SQI, SuperSwitcher,
SuperSwitcher II, Switchtec, SynchroPHY, Total Endurance, Trusted Time, TSHARC, USBCheck, VariSense, VectorBlox, VeriPHY, ViewSpan, WiperLock, XpressConnect, lan ZENA minangka merek dagang saka Microchip Technology Incorporated
ing AS lan negara liyane.
SQTP minangka tandha layanan saka Microchip Technology Incorporated ing AS
Logo Adaptec, Frequency on Demand, Silicon Storage Technology, lan Symmcom minangka merek dagang kadhaptar saka Microchip Technology Inc. ing negara liya.
GestIC minangka merek dagang kadhaptar saka Microchip Technology Germany II GmbH & Co. KG, anak perusahaan saka Microchip Technology Inc., ing negara liya.
Kabeh merek dagang liyane sing kasebut ing kene minangka properti saka perusahaan kasebut.
© 2023, Microchip Technology Incorporated lan anak perusahaan. Kabeh hak dilindhungi undhang-undhang.
ISBN: 978-1-6683-3694-6
Sistem Manajemen Mutu
Kanggo informasi babagan Sistem Manajemen Kualitas Microchip, bukak www.microchip.com/quality.

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DS50003627A –

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MICROCHIP Libero SoC Simulation Library Software [pdf] Pandhuan pangguna
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