Libero SoC Ketsiso
Litaelo tsa ho Seta Laebrari
Selelekela
Sepheo sa tokomane ena ke ho hlalosa mokhoa oa ho theha tikoloho ea ho etsisa ho sebelisa morero oa Libero SoC e le ho kenya letsoho. Litokomane tsena li lumellana le lilaebrari tse hlophisitsoeng esale pele tse fanoeng hore li sebelisoe le Libero SoC v11.9 le lintlafatso tse ncha tsa software. Lilaebrari tse fanoeng li hlophisitsoe bakeng sa Verilog. Basebelisi ba VHDL ba hloka laesense e lumellang papiso ea mofuta o tsoakiloeng.
Lilaebrari tse hlophisitsoeng tsa papiso li fumaneha bakeng sa lisebelisoa tse latelang:
- Aldec Active-HDL
- Aldec Riviera-PRO
- Cadence Incisive Enterprise le Xcelium
- Siemens QuestaSim
- Litlhaloso tsa VCS
Ho kopa laeborari bakeng sa simulator e fapaneng, ikopanye Tšehetso ea Theknoloji ea Microchip.
Libero SoC Kopanyo
Libero SoC e ts'ehetsa ketsiso e sebelisang ModelSim ME ka ho hlahisa run.do file. Sena file e sebelisoa ke ModelSim ME/ModelSim Pro ME ho theha le ho tsamaisa papiso. Ho sebelisa lisebelisoa tse ling tsa papiso, o ka hlahisa ModelSim ME/ModelSim Pro ME run.do le ho fetola mongolo oa Tcl. file ho sebelisa litaelo tse tsamaellanang le simulator ea hau.
1.1 Libero SoC Tcl File Moloko (Botsa Potso)
Kamora ho theha le ho hlahisa moralo ho Libero SoC, qala mohlala oa ModelSim ME/ModelSim Pro ME tlasa mekhahlelo eohle ea meralo (presynth, postsynth, le post-layout). Mohato ona o hlahisa run.do file bakeng sa ModelSim ME/ModelSim Pro ME bakeng sa mohato o mong le o mong oa moralo.
Bohlokoa: Kamora ho qala ts'ebetso e 'ngoe le e' ngoe ea papiso, reha lebitso la "auto-generated run.do". file tlas'a bukana ea simulation ho thibela Libero SoC ho e ngola file. Bakeng sa mohlalaample, le files e ka rehoa hape ho presynth_run.do, postsynth_run.do le postlayout_run.do.
Aldec Setup bakeng sa Active-HDL le Riviera-Pro (Botsa Potso)
The run.do file e sebelisoang ke ModelSim ME/ModelSim Pro ME e ka fetoloa le ho sebelisoa bakeng sa papiso e sebelisang li-simulator tsa Aldec.
2.1 Phapang ea Tikoloho (Botsa Potso)
Beha maemo a fapaneng a tikoloho ho laesense ea hau file sebaka:
LM_LICENSE_FILE: e tlameha ho kenyelletsa sesupa ho seva sa laesense.
2.2 Khoasolla Laeborari e Kopantsoeng (Botsa Potso)
Khoasolla lilaebrari tsa Aldec Active-HDL le Aldec Riviera-PRO ho tsoa ho Microchip. websebaka.
2.3 Ho fetolela run.do bakeng sa simulation ea Aldec (Botsa Potso)
The run.do files e hlahisitsoeng ke Libero SoC bakeng sa lipapiso tse sebelisang sesebelisoa sa Active-HDL le Riviera-Pro e ka sebelisoa bakeng sa lipapiso tse sebelisang Active-HDL le Riviera-Pro ka phetoho e le 'ngoe. Tafole e latelang e thathamisa litaelo tse lekanang le Aldec ho fetoloa ho ModelSim run.do file.
Lethathamo la 2-1. Litaelo tse lekanang tsa Aldec
| ModelSim | HDL e sebetsang |
| vlog | alog |
| vcom | acom |
| vlib | alib |
| vsim | asim |
| vmap | amap |
Latelang ke joalo kaample run.do e amanang le lisimulator tsa Aldec.
- Beha sebaka sa buka ea hona joale ea ho sebetsa.
beha dsn - Beha lebitso la laeborari e sebetsang, 'mapa sebaka sa eona, ebe u etsa 'mapa sebaka sa lelapa la Microchip FPGA
lilaebrari tse hlophisitsoeng esale pele (mohlalaample, SmartFusion2) eo u sebelisang moralo oa hau ho eona.
alib presynth
amap presynth presynth
amap SmartFusion2 - Kopanya HDL eohle e hlokahalang files sebelisoa moahong o nang le laebrari e hlokahalang.
alog -work presynth temp.v (bakeng sa Verilog)
alog –work presynth testbench.v
acom -work presynth temp.vhd (bakeng sa Vhdl)
acom -work presynth testbench.vhd - Etsisa moralo.
asim –L SmartFusion2 –L presynth –t 1ps presynth.testbench
matha 10us
2.4 Litaba Tse Tsejoang (Botsa Potso)
Karolo ena e thathamisa litaba tse tsebahalang le meeli.
- Lilaebrari tse hlophisitsoeng ho sebelisoa Riviera-PRO li sebetsa ka mokhoa o ikhethileng (ke hore, lilaeborari tsa 64-bit li ke ke tsa tsamaisoa sethaleng sa 32-bit le ka tsela e fapaneng).
- Bakeng sa meralo e nang le SEDES/MDDR/FDDR, sebelisa khetho e latelang ho run.do ea hau files ha ba ntse ba etsa lipapiso ka mor'a ho hlophisa meralo ea bona:
– Active-HDL: asim –o2
- Riviera-PRO: asim -O2 (bakeng sa lipapiso tsa presynth le tsa morao-rao) le asim -O5 (bakeng sa lipapiso tsa morao-rao)
Setupo sa Aldec bakeng sa Active-HDL le Riviera-Pro se na le li-SAR tse emetseng tse latelang. Ho fumana lintlha tse ling, ikopanye Tšehetso ea Theknoloji ea Microchip. - SAR 49908 - Active-HDL: Phoso ea VHDL bakeng sa lipapiso tsa block block
- SAR 50627 - Riviera-PRO 2013.02: Liphoso tsa papiso bakeng sa meralo ea SEDES
- SAR 50461 - Riviera-PRO: khetho ea asim -O2/-O5 ka lipapiso
Cadence Incisive Setup (Botsa Potso)
U hloka ho etsa script file e ts'oanang le ModelSim ME/ModelSim Pro ME run.do to run the
Cadence Incisive simulator. Latela mehato ena 'me u thehe script file bakeng sa NCSim kapa sebelisa script file
e fanoeng ho fetolela ModelSim ME/ModelSim Pro ME run.do files ho tlhophiso files
e hlokahalang ho tsamaisa lipapiso ho sebelisa NCSim.
Bohlokoa: Cadence e emisitse ho hlahisa mefuta e mecha ea Incisive Enterprise
simulator mme a qala ho ts'ehetsa simulator ea Xcelium.
3.1 Liphetoho tsa Tikoloho (Botsa Potso)
Ho tsamaisa simulator ea Cadence Incisive, lokisa mefuta e latelang ea tikoloho:
- LM_LICENSE_FILE: e tlameha ho kenyelletsa sesupo ho laesense file.
- cds_root: e tlameha ho supa sebaka sa buka ea lehae ea Cadence Incisive Installation.
- PATH: e tlameha ho supa sebaka sa bin tlas'a sesebelisoa sa lisebelisoa se bontšitsoeng ke cds_root ke hore,
$cds_root/tools/bin/64bit (bakeng sa mochini oa 64-bit le $cds_root/tools/bin bakeng sa mochini oa 32-bit).
Ho na le mekhoa e meraro ea ho theha tikoloho ea papiso haeba ho ka ba le phetoho lipakeng tsa sistimi ea 64-bit le 32-bit:
Taba ea 1: PATH E feto-fetoha
Etsa taelo e latelang:
beha tsela = (install_dir/tools/bin/64bit $path) bakeng sa mechini ea 64bit le
beha tsela = (install_dir/tools/bin $path) bakeng sa mechini ea 32bit
Taba ea 2: Ho sebelisa khetho ea -64bit Command-line
Moleng oa taelo hlalosa -64bit khetho e le hore u ka kopa 64bit e ka phethisoang.
Boemo ba 3: Ho Beakanya Boemo ba Boemo ba INCA_64BIT kapa CDS_AUTO_64BIT
Mofuta oa INCA_64BIT o nkuoa joalo ka boolean. O ka beha phapang ena boleng bofe kapa bofe kapa khoele e se nang letho.
setenv INCA_64BIT
Bohlokoa: The INCA_64BIT e fapaneng ea tikoloho ha e ame lisebelisoa tse ling tsa Cadence, joalo ka lisebelisoa tsa IC. Leha ho le joalo, bakeng sa lisebelisoa tsa Incisive, mofuta oa INCA_64BIT o feta boemo ba CDS_AUTO_64BIT ea tikoloho. Haeba sebopeho sa tikoloho sa INCA_64BIT se setiloe, lisebelisoa tsohle tsa Incisive li sebetsa ka mokhoa oa 64-bit. setenv CDS_AUTO_64BIT KENYETSA:INCA
Bohlokoa: The khoele INCA e tlameha ho ba ka litlhaku tse kholo. Lintho tsohle tse ka etsoang li tlameha ho tsamaisoa ka mokhoa oa 32-bit kapa ka mokhoa oa 64-bit, u se ke ua beha phapang ho kenyelletsa e le 'ngoe e ka phethisoang, joalo ka tse latelang:
setenv CDS_AUTO_64BIT KENYETSA:ncelab
Lisebelisoa tse ling tsa Cadence, tse kang lisebelisoa tsa IC, le tsona li sebelisa CDS_AUTO_64BIT e fapaneng ea tikoloho ho laola khetho ea 32-bit kapa 64-bit e ka sebelisoang. Tafole e latelang e bonts'a hore na u ka beha mofuta oa CDS_AUTO_64BIT joang ho tsamaisa lisebelisoa tsa Incisive le lisebelisoa tsa IC ka mekhoa eohle.
Lethathamo la 3-1. CDS_AUTO_64BIT Mefuta e sa tšoaneng
| CDS_AUTO_64BIT E feto-fetoha | Lisebelisoa tse Incisive | Lisebelisoa tsa IC |
| setenv CDS_AUTO_64BIT TSOHLE | 64 hanyane | 64 hanyane |
| setenv CDS_AUTO_64BIT NO | 32 hanyane | 32 hanyane |
| setenv CDS_AUTO_64BIT KHETHA:ic_binary | 64 hanyane | 32 hanyane |
| setenv CDS_AUTO_64BIT EXCLUDE:INCA | 32 hanyane | 64 hanyane |
Bohlokoa: Lisebelisoa tsohle tsa Incisive li tlameha ho tsamaisoa ka mokhoa oa 32-bit kapa ka mokhoa oa 64-bit, u se ke ua sebelisa EXCLUDE ho qhelela ka thoko e itseng e ka phethisoang, joalo ka ho latelang: setenv CDS_AUTO_64BIT EXCLUDE:ncelab
Haeba u seta CDS_AUTO_64BIT e fapaneng hore e se kenyeletse lisebelisoa tsa Incisive (setenv CDS_AUTO_64BIT EXCLUDE:INCA), lisebelisoa tsohle tsa Incisive li tsamaisoa ka mokhoa oa 32-bit. Leha ho le joalo, khetho ea line-taelo ea -64bit e feta phapang ea tikoloho.
Tlhophiso e latelang files e o thusa ho laola data ea hau le ho laola ts'ebetso ea lisebelisoa le lisebelisoa tsa papiso:
- 'Mapa oa laebrari file (cds.lib)—E hlalosa lebitso le utloahalang bakeng sa sebaka sa moetso oa hau.
- Lilaebrari le ho li amahanya le mabitso a li-directory tsa tlhaho.
- Mefuta e fapaneng file (hdl.var) -E hlalosa lintho tse fapaneng tse amang boitšoaro ba lisebelisoa le lisebelisoa tsa ho etsisa.
3.2 Khoasolla Laeborari e Kopantsoeng (Botsa Potso)
Khoasolla lilaebrari tsa Cadence Incisive ho tsoa ho Microsemi's websebaka.
3.3 Ho theha Sengoloa sa NCSim File (Botsa Potso)
Kamora ho etsa kopi ea run.do files, etsa mehato ena ho tsamaisa papiso ea hau u sebelisa NCSim:
- Theha cds.lib file e hlalosang dilaeborari tse fihlellehang le sebaka sa tsona. The file e na le lipolelo tse fanang ka 'mapa oa mabitso a laebrari ho litsela tsa bona tsa pokello ea mabitso. Bakeng sa mohlalaample, haeba u sebelisa ketsiso ea presynth, cds.lib file e ngotsoe joalo ka ha ho bonts'itsoe ho codeblock e latelang.
HLALOSA presynth ./presynth
DEFINE COREAHBLITE_LIB ./COREAHBLITE_LIB
HLALOSA smartfusion2 - Theha hdl.var file, tlhophiso ea boikhethelo file e nang le mefuta-futa ea tlhophiso, e bontšang hore na tikoloho ea hau ea moralo e hlophisitsoe joang. Phapang e latelang files li kenyelelitsoe:
- Liphetoho tse sebelisetsoang ho hlakisa laeborari ea mosebetsi moo moqapi a bolokang lintho tse bokelletsoeng le lintlha tse ling tse nkiloeng.
- Bakeng sa Verilog, mefuta e fapaneng (LIB_MAP, VIEW_MAP, MOSEBETSI) tse sebelisoang ho hlakisa lilaeborari le views ho batla ha mohlalosi a rarolla maemo.
- Liphetoho tse u lumellang hore u hlalose likhetho le likhang tsa mola oa taelo, oa ho qaqisa le oa simulator.
Tabeng ea ketsiso ea presynth example bontšitsoeng ka holimo, re re na le tse tharo RTL files: av, bv, le testbench.v, tse hlokang ho hlophisoa hore e be lilaebrari tsa presynth, COREAHBLITE_LIB, le presynth ka ho latellana. The HDl.var file e ka ngoloa joalo ka ha ho bonts'itsoe ho codeblock e latelang.
HLALOSA MOSEBETSI presynth
HLALOSA PROJECT_DIR files>
TLHALOSA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/av => presynth )
TLHALOSA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/bv => COREAHBLITE_LIB )
TLHALOSA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/testbench.v => presynth )
HLALOSA LIB_MAP ( $LIB_MAP, + => presynth ) - Kopanya moralo files sebelisa khetho ea ncvlog.
ncvlog +incdir+ –cdslib ./cds.lib –hdlvar ./hdl.var –logfile
ncvlog.log -update -linedebug av bv testbench.v - Hlahisa moralo o sebelisa ncelab. Setsebi se theha sehlopha sa moralo se ipapisitseng le tlhaiso-leseling le tlhophiso moralong, se theha khokahano ea mats'oao, 'me se bala litekanyetso tsa mantlha tsa lintho tsohle tse moralong. Taolo e hlophisitsoeng ea moralo e bolokiloe setšoantšong sa ketsiso, e leng setšoantšo sa moralo oa hau oo simulator e o sebelisang ho etsa ketsiso.
ncelab –Molaetsa –cdslib ./cds.lib –hdlvar ./hdl.var –logfile celab.log -errormax 15 -
fihlella +rwc -status worklib. :mojule
Elaboration Nakong ea Ketsiso ea Post-rolaut
Tabeng ea lipapiso tsa ka morao ho moralo, pele SDF file e hloka ho hlophisoa pele ho hlakisoa ho sebelisa taelo ea ncsdfc.
ncdfcfilelebitso>.sdf -outputfilelebitso>.sdf.X
Nakong ea ho hlakisoa sebelisa tlhahiso e hlophisitsoeng ea SDF ka khetho ea -autosdf joalo ka ha ho bonts'itsoe ho codeblock e latelang.
ncelab -autosdf –Molaetsa –cdslib ./cds.lib –hdlvar ./hdl.var –logfile celab.log -errormax
15 -access +rwc -status worklib. :mojule -sdf_cmd_file ./
sdf_cmd_file
sdf_cmd_file e tlameha ho ba joalo ka ha ho bonts'itsoe ho codeblock e latelang.
COMPILED_SDF_FILE =“ file>” - Etsisa ka ho sebelisa ncsim. Kamora ho hlakisoa ho etsoa senepe sa ketsiso, se kentsoeng ke ncsim bakeng sa papiso. O ka matha ka batch mode kapa GUI mode.
ncsim –Molaetsa –batch/-gui –cdslib ./cds.lib –hdlvar ./hdl.var –logfile ncsim.log -
errormax 15 -status worklib. :module
Bohlokoa: Mehato eohle e meraro e ka holimo ea ho bokella, ho qaqisa le ho etsisa e ka kenngoa ka har'a script ea khetla file 'me e nkiloe moleng oa taelo. Sebakeng sa ho sebelisa mehato ena e meraro, moralo o ka etsisoa mohatong o le mong o sebelisa khetho ea ncverilog kapa irun joalo ka ha ho bonts'itsoe ho codeblock e latelang.
ncverilog +incdir+ -cdslib ./cds.lib –hdlvar ./hdl.var
files sebelisoa ho moralo>
irun +incdir+ -cdslib ./cds.lib –hdlvar ./hdl.var files
e sebelisitsoeng moralong>
3.3.1 Litaba Tse Tsejoang (Botsa Potso)
Testbench Workaround
Ho sebelisa polelo e latelang bakeng sa ho hlakisa maqhubu a oache ho testbench e hlahisoang ke mosebelisi, kapa testbench ea kamehla e hlahisoang ke Libero SoC ha e sebetse le NCSim.
kamehla @(SYSCLK)
#(SYSCLK_PERIOD / 2.0) SYSCLK <= !SYSCLK;
Fetola ka tsela e latelang ho etsa ketsiso:
kamehla #(SYSCLK_PERIOD / 2.0) SYSCLK = ~SYSCLK;
Bohlokoa: E hlophisitsoe lilaeborari tsa NCSim li na le sethala se ikhethileng (ke hore, lilaeborari tsa 64 bit ha li tsamaellane le sethala sa 32 bit le ka tsela e fapaneng).
Postsynth le Post-Layout Simulations U sebelisa MSS le SERDES Ha u ntse u etsa lipapiso tsa postsynth tsa meralo e nang le boloko ba MSS kapa lipapiso tsa morao-rao tsa meralo e sebelisang SERDES, lipapiso tsa BFM ha li sebetse haeba khetho ea -libmap e.
ha e hlalosoe nakong ea tlhahiso. Lebaka ke hobane nakong ea tlhaloso, MSS e rarolloa ho tloha laebraring ea mosebetsi (ka lebaka la ho tlamaha ha kamehla le mosebetsi oa ho sebetsa e le postsynth / post-layout) moo e leng Mosebetsi o tsitsitseng feela.
Taelo ea ncelab e tlameha ho ngoloa joalo ka ha ho bonts'itsoe khoutu e latelang ho rarolla MSS
thibela ho tsoa laebraring e hlophisitsoeng ea SmartFusion2.
ncelab -libmap lib.map -libverbose -Molaetsa -access +rwc cfg1
le lib.mapa file e tlameha ho ba ka tsela e latelang:
lokisa cfg1;
moralo ;
default liblist smartfusion2 ;
endconfig
Sena se rarolla sele e 'ngoe le e' ngoe e laebraring ea SmartFusion2 pele u sheba laebraring ea mosebetsi, ke hore, postsynth/ post-layout.
Khetho ea -libmap e ka sebelisoa ka mokhoa o ikhethileng nakong ea tlhahiso-leseling bakeng sa papiso e 'ngoe le e' ngoe (presynth, postsynth, le post-layout). Sena se qoba mathata a ketsiso a bakoang ke tharollo ea maemo a tsoang lilaeboraring.
ncelab: *F,INTERR: MOKHELO KA HARE
Mokhelo ona oa sesebelisoa sa ncelab ke lekoa la meralo e nang le FDDR ho SmartFusion 2 le IGLOO 2 nakong ea lipapiso tsa postsynth le tsa morao-rao tse sebelisang -libmap khetho.
Bohlokoa: Taba ena e tlalehetse sehlopha sa tšehetso sa Cadence (SAR 52113).
3.4 Sample Tcl le Shell Script FilesBotsa Potso)
E latelang files ke tlhophiso files e hlokahalang bakeng sa ho theha moralo le mongolo oa khetla file bakeng sa ho tsamaisa litaelo tsa NCSim.
Cds.lib
NE smartfusion2 /scratch/krydor/tmpspace/users/me/nc-vlog64/SmartFusion2
DEFINE COREAHBLITE_LIB ./COREAHBLITE_LIB
HLALOSA presynth ./presynth
Hdl.var
HLALOSA MOSEBETSI presynth
HLALOSA PROJECT_DIR /scratch/krydor/tmpspace/sqausers/me/3rd_party_simulators/Cadence/IGLOO2/
ENVM/M2GL050/envm_fic1_ser1_v/eNVM_fab_master
TLHALOSA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/core/coreahblite_addrdec.v => COREAHBLITE_LIB )
TLHALOSA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/core/coreahblite_defaultslavesm.v => COREAHBLITE_LIB )
TLHALOSA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/core/coreahblite_masterstagev => COREAHBLITE_LIB )
TLHALOSA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/core/coreahblite_slavearbiter.v => COREAHBLITE_LIB )
TLHALOSA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/core/coreahblite_slavestagev => COREAHBLITE_LIB )
TLHALOSA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/core/coreahblite_matrix2x16.v => COREAHBLITE_LIB )
TLHALOSA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/core/coreahblite.v => COREAHBLITE_LIB )
TLHALOSA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB/CCC_0/SB_CCC_0_FCC.v =>
presynth )
TLHALOSA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreConfigMaster/
2.0.101/rtl/vlog/core/coreconfigmaster.v => presynth )
TLHALOSA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreConfigP/4.0.100/rtl/
vlog/core/coreconfigp.v => presynth )
TLHALOSA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreResetP/5.0.103/rtl/
vlog/core/coresetp_pcie_hotreset.v => presynth )
TLHALOSA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreResetP/5.0.103/rtl/
vlog/core/coresetp.v => presynth )
TLHALOSA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB/FABOSC_0/SB_FABOSC_0_OSC.v =>
presynth )
TLHALOSA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB_HPMS/SB_HPMS.v => presynth )
TLHALOSA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB/SB.v => presynth )
TLHALOSA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB_top/SERDES_IF_0/
SB_top_SERDES_IF_0_SERDES_IF.v => presynth )
TLHALOSA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB_top/SB_top.v => presynth )
TLHALOSA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB_top/testbench.v => presynth )
HLALOSA LIB_MAP ( $LIB_MAP, + => presynth )
Litaelo.csh
ncvlog +incdir+../../component/work/SB_top -cdslib ./cds.lib -hdlvar ./hdl.var -logfile
ncvlog.log -errormax 15 -update -linedebug
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite_addrdec.v
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/
coreahblite_defaultslavesm.v
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite_masterstagev
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite_slavearbiter.v
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite_slavestagev
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite_matrix2x16.v
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite.v
../../component/work/SB/CCC_0/SB_CCC_0_FCCC.v
../../component/Actel/DirectCore/CoreConfigMaster/2.0.101/rtl/vlog/core/coreconfigmaster.v
../../component/Actel/DirectCore/CoreConfigP/4.0.100/rtl/vlog/core/coreconfigp.v
../../component/Actel/DirectCore/CoreResetP/5.0.103/rtl/vlog/core/coreresetp_pcie_hotreset.v
../../component/Actel/DirectCore/CoreResetP/5.0.103/rtl/vlog/core/coreresetp.v
../../component/work/SB/FABOSC_0/SB_FABOSC_0_OSC.v ../../component/work/SB_HPMS/SB_HPMS.v
../../component/work/SB/SB.v ../../component/work/SB_top/SERDES_IF_0/
SB_top_SERDES_IF_0_SERDES_IF.v
../../component/work/SB_top/SB_top.v ../../component/work/SB_top/testbench.v
ncelab -Molaetsa -cdslib ./cds.lib -hdlvar ./hdl.var
-work presynth -logfile ncelab.log -errormax 15 -access +rwc -status presynth.testbench:mojule
ncsim -Molaetsa -batch -cdslib ./cds.lib -hdlvar ./
hdl.var -logfile ncsim.log -errormax 15 -status presynth.testbench:mojule
3.5 Boiketsetso (Botsa Potso)
Mongolo o latelang file e fetola ModelSim run.do files ho tlhophiso files e hlokahalang ho etsa lipapiso ho sebelisa NCSim.
Script File Tšebeliso
perl cadence_parser.pl presynth_run.do postsynth_run.do
postlayout_run.do Microsemi_Family
Location_of_Cadence_Precompiled_libraries
Cadence_parser.pl
#!/usr/bin/perl -w
########################################################### #################################################
###################
#Tšebeliso: perl questa_parser.pl presynth_run.do postsynth_run.do postlayout_run.do
Microsemi_Family Precompiled_Libraries_location#
########################################################### #################################################
###################
sebelisa POSIX;
sebelisa ka thata;
eaka ($ presynth, $postsynth, $postlayout, $lelapa, $lib_location) = @ARGV;
&questa_parser($presynth, $family, $lib_location);
&questa_parser($postsynth, $family, $lib_location);
&questa_parser($postlayout, $lelapa, $lib_location);
sub questa_parser {
my $ModelSim_run_do = $_[0];
my $ actel_family = $_[1];
my $lib_location = $_[2];
boemo ba ka ba $;
haeba (-e "$ModelSim_run_do")
{
bula (INFILE,”$ModelSim_run_do”);
my @ModelSim_run_do =FILE>;
mohala oa ka oa $;
haeba ( $ModelSim_run_do =~ m/(presynth)/)
{
`mkdir QUESTA_PRESYNTH`;
bula (OUTFILE,”>QUESTA_PRESYNTH/presynth_questa.do”);
$ naha = $ 1;
} elsif ( $ModelSim_run_do =~ m/(postsynth)/)
{
`mkdir QUESTA_POSTSYNTH`;
bula (OUTFILE,”>QUESTA_POSTSYNTH/postsynth_questa.do”);
$ naha = $ 1;
} elsif ( $ModelSim_run_do =~ m/(postlayout)/ )
{
`mkdir QUESTA_POSTLAYOUT`;
bula (OUTFILE,”>QUESTA_POSTLAYOUT/postlayout_questa.do”);
$ naha = $ 1;
} e mong
{
printa “Litlhahiso tse Fosahetseng tse fanoeng ho file\n";
hatisa "#Usage: perl questa_parser.pl presynth_run.do postsynth_run.do postlayout_run.do
\"Laeborari_sebaka\"\n";
}
foreach $line (@ModelSim_run_do)
{
# Ts'ebetso e akaretsang
$ mola =~ s/..\/moqapi.*ketsiso\///g;
$ mola =~ s/$state/$state\_questa/g;
#hatisaFILE "$line \n";
haeba ($line =~ m/vmap\s+.*($actel_family)/)
{
hatisaFILE “vmap $actel_family \”$lib_location\”\n”;
} elsif ($line =~ m/vmap\s+(.*._LIB)/)
{
$ mola =~ s/..\/component/..\/..\/component/g;
hatisaFILE "$line \n";
} elsif ($line =~ m/vsim/)
{
$ mola =~ s/vsim/vsim -novopt/g;
hatisaFILE "$line \n";
} e mong
{
hatisaFILE "$line \n";
}
}
koala(INFILE);
koala(OUTFILE);
} tse ling {
hatisa "$ModelSim_run_do ha e eo. Etsa ketsiso hape \n";
}
}
Setupo sa Cadence Xcelium (Ho kena ha Microchip)
U hloka ho etsa script file e tšoanang le ModelSim ME/ModelSim Pro ME run.do ho tsamaisa simulator ea Cadence Xcelium. Latela mehato ena 'me u thehe script file bakeng sa Xcelium kapa sebelisa script file e fanoeng ho fetolela ModelSim ME/ModelSim Pro ME run.do files ho tlhophiso files e hlokahalang ho etsa lipapiso ho sebelisa Xcelium.
4.1 Liphetoho tsa Tikoloho (Botsa Potso)
Ho tsamaisa Cadence Xcelium, lokisa mefuta e latelang ea tikoloho:
- LM_LICENSE_FILE: e tlameha ho kenyelletsa sesupo ho laesense file.
- cds_root: e tlameha ho supa sebaka sa buka ea lehae ea Cadence Incisive Installation.
- PATH: e tlameha ho supa sebaka sa bin tlasa bukana ea lisebelisoa e bontšitsoeng ke cds_root (ke hore
$cds_root/tools/bin/64bit (bakeng sa mochini oa 64 bit le $cds_root/tools/bin bakeng sa 32 bit
mochini).
Ho na le mekhoa e meraro ea ho theha tikoloho ea papiso haeba ho ka ba le phetoho lipakeng tsa sistimi ea 64-bit le 32-bit:
Taba ea 1: PATH E feto-fetoha
beha tsela = (install_dir/tools/bin/64bit $path) bakeng sa mechini ea 64bit le
beha tsela = (install_dir/tools/bin $path) bakeng sa mechini ea 32bit
Taba ea 2: Ho sebelisa khetho ea -64bit Command-line
Moleng oa taelo hlalosa -64bit khetho e le hore u ka kopa 64-bit e ka phethisoang.
Boemo ba 3: Ho Beakanya Boemo ba Boemo ba INCA_64BIT kapa CDS_AUTO_64BIT
Mofuta oa INCA_64BIT o nkuoa joalo ka boolean. O ka beha phapang ena ho boleng bofe kapa bofe kapa ho lefeela
khoele.
setenv INCA_64BIT
Bohlokoa: The INCA_64BIT e fapaneng ea tikoloho ha e ame lisebelisoa tse ling tsa Cadence, joalo ka lisebelisoa tsa IC. Leha ho le joalo, bakeng sa lisebelisoa tsa Incisive, mofuta oa INCA_64BIT o feta boemo ba CDS_AUTO_64BIT ea tikoloho. Haeba sebopeho sa tikoloho sa INCA_64BIT se le teng, lisebelisoa tsohle tsa Incisive li sebetsa ka mokhoa oa 64-bit.
setenv CDS_AUTO_64BIT KENYETSA:INCA
Bohlokoa: The khoele INCA e tlameha ho ba ka litlhaku tse kholo. Lintho tsohle tse ka etsoang li tlameha ho tsamaisoa ka mokhoa oa 2-bit kapa ka mokhoa oa 64-bit, u se ke ua beha phapang ho kenyelletsa e le 'ngoe e ka phethisoang, joalo ka tse latelang:
setenv CDS_AUTO_64BIT KENYETSA:ncelab
Lisebelisoa tse ling tsa Cadence, tse kang lisebelisoa tsa IC, le tsona li sebelisa CDS_AUTO_64BIT e fapaneng ea tikoloho ho laola khetho ea 32-bit kapa 64-bit e ka sebelisoang. Tafole e latelang e bonts'a hore na u ka beha mofuta oa CDS_AUTO_64BIT joang ho tsamaisa lisebelisoa tsa Incisive le lisebelisoa tsa IC ka mekhoa eohle.
Lethathamo la 4-1. CDS_AUTO_64BIT Mefuta e sa tšoaneng
| CDS_AUTO_64BIT E feto-fetoha | Lisebelisoa tse Incisive | Lisebelisoa tsa IC |
| setenv CDS_AUTO_64BIT TSOHLE | 64-bit | 64-bit |
| setenv CDS_AUTO_64BIT NO | 32-bit | 32-bit |
| setenv CDS_AUTO_64BIT HO HLOKAHALA:ic_binary |
64-bit | 32-bit |
| setenv CDS_AUTO_64BIT EXCLUDE:INCA | 32-bit | 64-bit |
Bohlokoa: Lisebelisoa tsohle tsa Incisive li tlameha ho tsamaisoa ka mokhoa oa 32-bit kapa ka mokhoa oa 64-bit, u se ke oa sebelisa EXCLUDE ho qhelela ka thoko e itseng e ka phethisoang, joalo ka ho tse latelang:
setenv CDS_AUTO_64BIT EXCLUDE:ncelab
Haeba u seta CDS_AUTO_64BIT e fapaneng ho kenyelletsa lisebelisoa tsa Incisive (setenv).
CDS_AUTO_64BIT EXCLUDE:INCA), lisebelisoa tsohle tsa Incisive li tsamaisoa ka mokhoa oa 32-bit. Leha ho le joalo, the
-64bit khetho ea mola oa taelo e feta ho feto-fetoha ha tikoloho.
Tlhophiso e latelang files e o thusa ho laola data ea hau le ho laola ts'ebetso ea lisebelisoa le lisebelisoa tsa papiso:
- 'Mapa oa laebrari file (cds.lib) e hlalosa lebitso le utloahalang bakeng sa sebaka sa moralo oa hau.
- Lilaebrari le ho li amahanya le mabitso a li-directory tsa tlhaho.
- Mefuta e fapaneng file (hdl.var) e hlalosa mefuta e fapaneng e amang boitšoaro ba lisebelisoa le lisebelisoa tsa papiso.
4.2 Khoasolla Laeborari e Kopantsoeng (Botsa Potso)
Khoasolla lilaebrari tsa Cadence Xcelium ho tsoa ho Microsemi's websebaka.
4.3 Ho theha mongolo oa Xcelium file (Botsa Potso)
Kamora ho etsa kopi ea run.do files, etsa mehato e latelang ho tsamaisa papiso ea hau u sebelisa mongolo oa Xcelium file.
- Theha cds.lib file e hlalosang hore na ke lilaebrari life tse fumanehang le moo li leng teng.
The file e na le lipolelo tse fanang ka 'mapa oa mabitso a laebrari ho litsela tsa bona tsa pokello ea mabitso. Bakeng sa mohlalaample, haeba u sebelisa ketsiso ea presynth, cds.lib file e ka ngoloa joalo ka ha ho bonts'itsoe ho codeblock e latelang.
HLALOSA presynth ./presynth
DEFINE COREAHBLITE_LIB ./COREAHBLITE_LIB
HLALOSA smartfusion2 - Theha hdl.var file e leng tlhophiso ya boikgethelo file e nang le mefuta-futa ea tlhophiso, e bontšang hore na tikoloho ea hau ea moralo e hlophisitsoe joang. Tsena li kenyelletsa:
- Liphetoho tse sebelisetsoang ho hlakisa laeborari ea mosebetsi moo moqapi a bolokang lintho tse bokelletsoeng le lintlha tse ling tse nkiloeng.
- Bakeng sa Verilog, mefuta e fapaneng (LIB_MAP, VIEW_MAP, MOSEBETSI) tse sebelisoang ho hlakisa lilaeborari le views ho batla ha mohlalosi a rarolla maemo.
- Liphetoho tse u lumellang hore u hlalose likhetho le likhang tsa mola oa taelo, oa ho qaqisa le oa simulator.
Tabeng ea ketsiso ea presynth example e bontšitsoeng ka holimo, e re re na le 3 RTL files av, bv, le testbench.v, tse hlokang ho hlophisoa hore e be presynth, COREAHBLITE_LIB, le lilaeborari tsa presynth ka ho latellana. The HDl.var file e ka ngoloa joalo ka ha ho bonts'itsoe ho codeblock e latelang.
HLALOSA MOSEBETSI presynth
HLALOSA PROJECT_DIR files>
TLHALOSA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/av => presynth )
TLHALOSA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/bv => COREAHBLITE_LIB )
TLHALOSA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/testbench.v => presynth )
HLALOSA LIB_MAP ( $LIB_MAP, + => presynth ) - Kopanya moralo files sebelisa khetho ea ncvlog.
xmvlog +incdir+ –cdslib ./cds.lib –hdlvar ./hdl.var –logfile
ncvlog.log -update -linedebug av bv testbench.v - Hlahisa moralo o sebelisa ncelab. Setsebi se theha sehlopha sa moralo se ipapisitseng le tlhaiso-leseling le tlhophiso moralong, se theha khokahano ea mats'oao, 'me se bala litekanyetso tsa mantlha tsa lintho tsohle tse moralong. Taolo e hlophisitsoeng ea moralo e bolokiloe setšoantšong sa ketsiso, e leng setšoantšo sa moralo oa hau oo simulator e o sebelisang ho etsa ketsiso.
Xcelium –Molaetsa –cdslib ./cds.lib –hdlvar ./hdl.var –logfile celab.log -errormax 15 -
fihlella +rwc -status worklib. :mojule
Elaboration Nakong ea Ketsiso ea Post-rolaut
Tabeng ea lipapiso tsa ka morao ho moralo, pele SDF file e hloka ho hlophisoa pele ho hlakisoa ho sebelisa taelo ea ncsdfc.
Xceliumfilelebitso>.sdf -outputfilelebitso>.sdf.X
Nakong ea ho hlakisoa sebelisa tlhahiso e hlophisitsoeng ea SDF ka khetho ea -autosdf joalo ka ha ho bonts'itsoe ho codeblock e latelang.
xmelab -autosdf –Molaetsa –cdslib ./cds.lib –hdlvar ./hdl.var –logfile celab.log -errormax
15 -access +rwc -status worklib. :mojule -sdf_cmd_file ./
sdf_cmd_file
sdf_cmd_file e tlameha ho ba joalo ka ha ho bonts'itsoe ho codeblock e latelang.
COMPILED_SDF_FILE =“ file>” - Etsisa ho sebelisa Xcelium. Kamora ho hlakisoa ho etsoa senepe sa ketsiso se jarollotsoeng ke Xcelium bakeng sa papiso. Sena se ka tsamaisoa ka batch mode kapa GUI mode.
xmsim –Molaetsa –batch/-gui –cdslib ./cds.lib –hdlvar ./hdl.var –logfile xmsim.log -
errormax 15 -status worklib. :module
Setupo sa Cadence Xcelium
Bohlokoa: Tsohle mehato e meraro e ka holimo ea ho bokella, ho hlalosa le ho etsisa e ka kenngoa ka har'a script ea khetla file 'me e nkiloe moleng oa taelo. Sebakeng sa ho sebelisa mehato ena e meraro, moralo o ka etsisoa mohatong o le mong o sebelisa khetho ea ncverilog kapa xrun joalo ka ha ho bonts'itsoe ho codeblock e latelang.
xmverilog +incdir+ -cdslib ./cds.lib –hdlvar ./hdl.var
files sebelisoa ho moralo>
xrun + incdir+ -cdslib ./cds.lib –hdlvar ./hdl.var files
e sebelisitsoeng moralong>
4.3.1 Litaba Tse Tsejoang (Botsa Potso)
Testbench Workaround
Ho sebelisa polelo e latelang bakeng sa ho hlakisa maqhubu a oache ho testbench e hlahisoang ke mosebelisi kapa testbench ea kamehla e hlahisoang ke Libero SoC ha e sebetse le Xcelium.
kamehla @(SYSCLK)
#(SYSCLK_PERIOD / 2.0) SYSCLK <= !SYSCLK;
Fetola ka tsela e latelang ho etsa ketsiso:
kamehla #(SYSCLK_PERIOD / 2.0) SYSCLK = ~SYSCLK;
Bohlokoa: Lilaeborari tse bokelletsoeng tsa Xcelium li ikhethile ka sethala (ke hore, lilaeborari tsa 64 bit ha li tsamaellane le sethala sa 32 bit le ka tsela e fapaneng).
Postsynth le Post-layout Simulations sebelisa MSS le SERDES
Ha u ntse u etsa lipapiso tsa postsynth tsa meralo e nang le li-block tsa MSS, kapa lipapiso tsa morao-rao tsa meralo e sebelisang SERDES, lipapiso tsa BFM ha li sebetse haeba khetho ea -libmap e sa hlalosoa nakong ea tlhaloso. Lebaka ke hobane nakong ea tlhaloso, MSS e rarolloa ho tloha laebraring ea mosebetsi (ka lebaka la ho tlamaha ha kamehla le mosebetsi oa ho sebetsa e le postsynth / post-layout) moo e leng Mosebetsi o tsitsitseng feela.
Taelo ea ncelab e tlameha ho ngoloa joalo ka ha ho bonts'itsoe ka har'a khoutu e latelang ho rarolla boloko ba MSS ho tsoa laebraring e hlophisitsoeng ea SmartFusion2.
xmelab -libmap lib.map -libverbose -Molaetsa -access +rwc cfg1
le lib.mapa file e tlameha ho ba ka tsela e latelang:
lokisa cfg1;
moralo ;
default liblist smartfusion2 ;
endconfig
Sena se tlameha ho rarolla sele efe kapa efe e laebraring ea SmartFusion2 pele u sheba laebraring ea mosebetsi ke hore postsynth/post-layout.
Khetho ea -libmap e ka sebelisoa ka ho sa feleng nakong ea tlhahiso-leseling bakeng sa papiso e 'ngoe le e' ngoe (presynth, postsynth le post-layout). Sena se qoba mathata a ketsiso a bakoang ke tharollo ea maemo a tsoang lilaeboraring.
xmelab: *F,INTERR: MOKHELO KA HARE
Mokhelo ona oa sesebelisoa sa ncelab ke leqheka bakeng sa meralo e nang le FDDR ho SmartFusion2 le IGLOO2.
nakong ea lipapiso tsa postsynth le tsa morao-rao tse sebelisang -libmap khetho.
Bohlokoa: Taba ena e tlalehetse sehlopha sa tšehetso sa Cadence (SAR 52113).
4.4 Sample Tcl le shell script filesBotsa Potso)
E latelang files ke tlhophiso files e hlokahalang bakeng sa ho theha moralo le mongolo oa khetla file bakeng sa ho tsamaisa litaelo tsa Xcelium.
Cds.lib
HLALOSA smartfusion2 /scratch/krydor/tmpspace/users/me/nc-vlog64/SmartFusion2
DEFINE COREAHBLITE_LIB ./COREAHBLITE_LIB
HLALOSA presynth ./presynth
Hdl.var
HLALOSA MOSEBETSI presynth
HLALOSA PROJECT_DIR /scratch/krydor/tmpspace/sqausers/me/3rd_party_simulators/Cadence/IGLOO2/
ENVM/M2GL050/envm_fic1_ser1_v/eNVM_fab_master
TLHALOSA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/core/coreahblite_addrdec.v => COREAHBLITE_LIB )
TLHALOSA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/core/coreahblite_defaultslavesm.v => COREAHBLITE_LIB )
TLHALOSA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/core/coreahblite_masterstagev => COREAHBLITE_LIB )
TLHALOSA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/core/coreahblite_slavearbiter.v => COREAHBLITE_LIB )
TLHALOSA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/core/coreahblite_slavestagev => COREAHBLITE_LIB )
TLHALOSA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/core/coreahblite_matrix2x16.v => COREAHBLITE_LIB )
TLHALOSA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/core/coreahblite.v => COREAHBLITE_LIB )
TLHALOSA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB/CCC_0/SB_CCC_0_FCC.v =>
presynth )
TLHALOSA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreConfigMaster/
2.0.101/rtl/vlog/core/coreconfigmaster.v => presynth )
TLHALOSA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreConfigP/4.0.100/rtl/
vlog/core/coreconfigp.v => presynth )
TLHALOSA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreResetP/5.0.103/rtl/
vlog/core/coresetp_pcie_hotreset.v => presynth )
TLHALOSA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreResetP/5.0.103/rtl/
vlog/core/coresetp.v => presynth )
TLHALOSA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB/FABOSC_0/SB_FABOSC_0_OSC.v =>
presynth )
TLHALOSA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB_HPMS/SB_HPMS.v => presynth )
TLHALOSA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB/SB.v => presynth )
TLHALOSA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB_top/SERDES_IF_0/
SB_top_SERDES_IF_0_SERDES_IF.v => presynth )
TLHALOSA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB_top/SB_top.v => presynth )
TLHALOSA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB_top/testbench.v => presynth )
HLALOSA LIB_MAP ( $LIB_MAP, + => presynth )
Litaelo.csh
ncvlog +incdir+../../component/work/SB_top -cdslib ./cds.lib -hdlvar ./hdl.var -logfile
ncvlog.log -errormax 15 -update -linedebug
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite_addrdec.v
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/
coreahblite_defaultslavesm.v
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite_masterstagev
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite_slavearbiter.v
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite_slavestagev
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite_matrix2x16.v
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite.v
../../component/work/SB/CCC_0/SB_CCC_0_FCCC.v
../../component/Actel/DirectCore/CoreConfigMaster/2.0.101/rtl/vlog/core/coreconfigmaster.v
../../component/Actel/DirectCore/CoreConfigP/4.0.100/rtl/vlog/core/coreconfigp.v
../../component/Actel/DirectCore/CoreResetP/5.0.103/rtl/vlog/core/coreresetp_pcie_hotreset.v
../../component/Actel/DirectCore/CoreResetP/5.0.103/rtl/vlog/core/coreresetp.v
../../component/work/SB/FABOSC_0/SB_FABOSC_0_OSC.v ../../component/work/SB_HPMS/SB_HPMS.v
../../component/work/SB/SB.v ../../component/work/SB_top/SERDES_IF_0/
SB_top_SERDES_IF_0_SERDES_IF.v
../../component/work/SB_top/SB_top.v ../../component/work/SB_top/testbench.v
ncelab -Molaetsa -cdslib ./cds.lib -hdlvar ./hdl.var
-work presynth -logfile ncelab.log -errormax 15 -access +rwc -status presynth.testbench:mojule
ncsim -Molaetsa -batch -cdslib ./cds.lib -hdlvar ./
hdl.var -logfile ncsim.log -errormax 15 -status presynth.testbench:mojule
4.5 Boiketsetso (Ho kena ha Microchip)
Mongolo o latelang file e fetola ModelSim run.do files ho tlhophiso files e hlokahalang ho etsa lipapiso ho sebelisa Xcelium.
Script File Tšebeliso
perl cadence_parser.pl presynth_run.do postsynth_run.do
postlayout_run.do Microsemi_Family
Location_of_Cadence_Precompiled_libraries
Cadence_parser.pl
#!/usr/bin/perl -w
########################################################### #################################################
###################
#Tšebeliso: perl questa_parser.pl presynth_run.do postsynth_run.do postlayout_run.do
Microsemi_Family Precompiled_Libraries_location#
########################################################### #################################################
###################
sebelisa POSIX;
sebelisa ka thata;
eaka ($ presynth, $postsynth, $postlayout, $lelapa, $lib_location) = @ARGV;
&questa_parser($presynth, $family, $lib_location);
&questa_parser($postsynth, $family, $lib_location);
&questa_parser($postlayout, $lelapa, $lib_location);
sub questa_parser {
my $ModelSim_run_do = $_[0];
my $ actel_family = $_[1];
my $lib_location = $_[2];
boemo ba ka ba $;
haeba (-e "$ModelSim_run_do")
{
bula (INFILE,”$ModelSim_run_do”);
my @ModelSim_run_do =FILE>;
mohala oa ka oa $;
haeba ( $ModelSim_run_do =~ m/(presynth)/)
{
`mkdir QUESTA_PRESYNTH`;
bula (OUTFILE,”>QUESTA_PRESYNTH/presynth_questa.do”);
$ naha = $ 1;
} elsif ( $ModelSim_run_do =~ m/(postsynth)/)
{
`mkdir QUESTA_POSTSYNTH`;
bula (OUTFILE,”>QUESTA_POSTSYNTH/postsynth_questa.do”);
$ naha = $ 1;
} elsif ( $ModelSim_run_do =~ m/(postlayout)/ )
{
`mkdir QUESTA_POSTLAYOUT`;
bula (OUTFILE,”>QUESTA_POSTLAYOUT/postlayout_questa.do”);
$ naha = $ 1;
} e mong
{
printa “Litlhahiso tse Fosahetseng tse fanoeng ho file\n";
hatisa "#Usage: perl questa_parser.pl presynth_run.do postsynth_run.do postlayout_run.do
\"Laeborari_sebaka\"\n";
}
foreach $line (@ModelSim_run_do)
{
# Ts'ebetso e akaretsang
$ mola =~ s/..\/moqapi.*ketsiso\///g;
$ mola =~ s/$state/$state\_questa/g;
#hatisaFILE "$line \n";
haeba ($line =~ m/vmap\s+.*($actel_family)/)
{
hatisaFILE “vmap $actel_family \”$lib_location\”\n”;
} elsif ($line =~ m/vmap\s+(.*._LIB)/)
{
$ mola =~ s/..\/component/..\/..\/component/g;
hatisaFILE "$line \n";
} elsif ($line =~ m/vsim/)
{
$ mola =~ s/vsim/vsim -novopt/g;
hatisaFILE "$line \n";
} e mong
{
hatisaFILE "$line \n";
}
}
koala(INFILE);
koala(OUTFILE);
} tse ling {
hatisa "$ModelSim_run_do ha e eo. Etsa ketsiso hape \n";
}
}
Siemens QuestaSim Setup/ModelSim Setup (Botsa Potso)
The run.do files, e hlahisoang ke Libero SoC bakeng sa lipapiso tse sebelisang Likhatiso tsa ModelSim Microsemi, li ka sebelisoa bakeng sa ho etsisa ho sebelisa QuestaSim / ModelSim SE / DE / PE ka phetoho e le 'ngoe. Ho ModelSim ME/ModelSim Pro ME run.do file, sebaka sa lilaebrari tse bokelletsoeng esale pele se hloka ho fetoloa.
Bohlokoa:
Ka nako e sa lekanyetsoang, sesebelisoa sa papiso ntle le ModelSim Pro ME se etsa ntlafatso ea moralo nakong ea papiso e ka amang ponahalo ea lintho tsa maiketsetso tse kang lintho tsa moralo le tšusumetso ea ho kenya.
Hangata sena se thusa ho fokotsa nako ea ho etsa ketsiso bakeng sa lipapiso tse rarahaneng, ho sebelisoa li-testbenche tsa verbose, tsa ho itlhahloba. Leha ho le joalo, lintlafatso tsa kamehla li kanna tsa se tšoanele lipapiso tsohle, haholo maemong ao u lebelletseng ho lekola liphetho tsa papiso u sebelisa fensetere ea wave.
Ho rarolla mathata a bakiloeng ke ntlafatso ena, o tlameha ho eketsa litaelo tse nepahetseng le likhang tse amanang le tsona nakong ea papiso ho khutlisetsa ponahalo moralong. Bakeng sa litaelo tse tobileng tsa lisebelisoa, bona litokomane tsa simulator e ntseng e sebelisoa.
5.1 Liphetoho tsa Tikoloho (Botsa Potso)
Lintlha tse latelang ke tse hlokahalang tsa tikoloho.
- LM_LICENSE_FILE: e tlameha ho kenyelletsa tsela e lebang laesense file.
- MODEL_TECH: e tlameha ho supa tsela e lebang bukeng ea lehae ea ho kenya QuestaSim.
- PATH: e tlameha ho supa sebaka se sebetsang se bonts'itsoeng ke MODEL_TECH.
5.2 Ho fetolela run.do bakeng sa Mentor QuestaSim (Botsa Potso)
The run.do files e hlahisoang ke Libero SoC bakeng sa lipapiso tse sebelisang ModelSim Microsemi Editions li ka sebelisoa bakeng sa lipapiso tse sebelisang QuestaSim/ModelSim_SE ka phetoho e le 'ngoe.
Bohlokoa: Tsohle meralo e etsisoang ho sebelisa QuestaSim e tlameha ho kenyelletsa -novopt
khetho hammoho le taelo ea vsim ho run.do script files.
5.3 Khoasolla Laeborari e Kopantsoeng (Botsa Potso)
Khoasolla lilaebrari tsa Mentor Graphics QuestaSim ho tsoa ho Microsemi's websebaka.
Setupo sa Synopsys VCS (Botsa Potso)
Phallo e khothalletsoang ke Microsemi e itšetlehile ka Phallo ea Elaborate le Compile ho VCS. Tokomane ena e kenyelletsa mongolo file e sebelisang mongolo oa run.do files e hlahisoang ke Libero SoC mme e hlahisa setup files e hlokahalang bakeng sa ketsiso ea VCS. Mongolo file sebelisa matha.etsa file ho etsa tse latelang.
- Etsa 'mapa oa pokello ea libuka file, e etsoang ho sebelisoa synopys_sim.setup file e fumaneha bukeng e le 'ngoe moo ketsiso ea VCS e sebetsang teng.
- Etsa script ea khetla file ho hlalosa le ho hlophisa moralo oa hau ka VCS.
6.1 Liphetoho tsa Tikoloho (Botsa Potso)
Beha maemo a nepahetseng a tikoloho bakeng sa VCS ho latela setaele sa hau. Liphetoho tsa tikoloho tse hlokahalang ho latela litokomane tsa VCS ke:
- LM_LICENSE_FILE: e tlameha ho kenyelletsa sesupa ho seva sa laesense.
- VCS_HOME: e tlameha ho supa sebaka sa buka ea lehae ea VCS.
- PATH: e tlameha ho kenyelletsa sesupo ho buka ea bin ka tlase ho bukana ea VCS_HOME.
6.2 Khoasolla Laeborari e Kopantsoeng (Botsa Potso)
Khoasolla lilaebrari tsa Synopsy VCS ho tsoa ho Microsemi's websebaka.
6.3 Sengoloa sa Ketsiso sa VCS File (Botsa Potso)
Kamora ho theha VCS le ho hlahisa moralo le mefuta e fapaneng ea run.do fileHo tsoa ho Libero SoC, o tlameha ho:
- Etsa 'mapa oa laeborari file synopys_sim.seta; sena file e na le lisupa tsa sebaka sa lilaebrari tsohle tse tla sebelisoa ke moralo.
Bohlokoa: The file lebitso ha lea lokela ho fetoha 'me le tlameha ho behoa bukeng e le 'ngoe moo patsiso e sebetsang teng. Ex ke enaample bakeng sa tse joalo file bakeng sa ketsiso ea presynthesis.
MOSEBETSI > HLOKO
SmartFusion2 :
presynth: ./presynth
TLHOKOMELISO : ./work - Hlahisa moralo o fapaneng files, ho kenyelletsa le testbench, ho sebelisa taelo ea vlogan ho VCS. Litaelo tsena li ka kenyelletsoa ho script ea khetla file. E latelang ke example ea litaelo tse hlokahalang ho hlakisa moralo o hlalositsoeng ho rtl.v le testbench ea eona e hlalositsoeng ho
testbench.v.
vlogan +v2k -work presynth rtl.v
vlogan +v2k -work presynth testbench.v - Kopanya moralo ka VCS u sebelisa taelo e latelang.
vcs –sim_res=1fs presynth.testbench
Tlhokomeliso: The qeto ea nako ea ketsiso e tlameha ho hlophisoa ho 1fs bakeng sa papiso e nepahetseng ea ts'ebetso. - Hang ha moralo o hlophisitsoe, qala ketsiso u sebelisa taelo e latelang.
./simv - Bakeng sa papiso ea morao-rao, taelo ea VCS e tlameha ho ba joalo ka ha e bonts'itsoe ho codeblock e latelang.
vcs postlayout.testbench -sim_res=1fs -sdf max: .
lebitso>: file tsela> -gui -l postlayout.log
6.4 Meeli/Mekhelo (Botsa Potso)
Tse latelang ke mefokolo/mekhelo ea ho seta ha Synopsys VCS.
- Lipapiso tsa VCS li ka sebetsoa feela bakeng sa merero ea Verilog ea Libero SoC. Simulator ea VCS e na le litlhoko tse thata tsa puo ea VHDL tse sa fihlelletsoeng ke Libero SoC e iketselitseng VHDL. files.
- U tlameha ho ba le polelo ea ho qetela ea $ Verilog testbench ho emisa ketsiso neng kapa neng ha u batla.
Bohlokoa: Neng lipapiso li tsamaisoa ka mokhoa oa GUI, nako ea ho matha e ka hlalosoa ho GUI.
6.5 Sample Tcl le Shell Script FilesBotsa Potso)
Perl e latelang e iketsetsa tlhahiso ea synopsys_sim.setup file mmoho le mongolo wa khetla o tsamaelanang fileHo hlokahala ho qaqisa, ho hlophisa le ho etsisa moralo.
Haeba moralo o sebelisa MSS, kopitsa test.vec file e fumanehang foldareng ea papiso ea projeke ea Libero SoC ka har'a foldara ea simulation ea VCS. Likarolo tse latelang li na le sample matha.etsa files e hlahisitsoeng ke Libero SoC, ho kenyeletsoa 'mapa oa laebrari o tsamaellanang le mongolo oa khetla files e hlokahalang bakeng sa ketsiso ea VCS.
6.5.1 Tšimoloho ea pele (Botsa Potso)
Presynth_run.do
beha ka khutso ACTELLIBNAME SmartFusion2
beha PROJECT_DIR ka khutso "/sqa/users/me/VCS_Tests/Test_DFF"
haeba {[file e teng presynth/_info]} {
echo "INFO: Presynth ea laeborari ea simulation e se e ntse e le teng"
} tse ling {
vlib presynth
}
vmap presynth presynth
vmap SmartFusion2 “/captures/lin/11_0_0_23_11prod/lib/ModelSim/precompiled/vlog/smartfusion2”
vlog -work presynth "${PROJECT_DIR}/component/work/SD1/SD1.v"
vlog “+ incdir+${PROJECT_DIR}/stimulus” -work presynth “${PROJECT_DIR}/stimulus/SD1_TB1.v”
vsim -L SmartFusion2 -L presynth -t 1fs presynth.SD1_TB1
eketsa wave /SD1_TB1/*
eketsa log -r /*
matha 1000ns
presynth_main.csh
#!/bin/csh -f
beha PROJECT_DIR = "/sqa/users/Me/VCS_Tests/Test_DFF"
/cad_design/tools/vcs.dir/E-2011.03/bin/vlogan +v2k -work presynth “${PROJECT_DIR}/component/
work/SD1/SD1.v”
/cad_design/tools/vcs.dir/E-2011.03/bin/vlogan +v2k “+incdir+${PROJECT_DIR}/stimulus” -sebetsa
presynth “${PROJECT_DIR}/stimulus/SD1_TB1.v”
/cad_design/tools/vcs.dir/E-2011.03/bin/vcs -sim_res=1fs presynth.SD1_TB1 -l compile.log
./simv -l run.log
Synopsys_sim.setup
MOSEBETSI > MOHLOMI
SmartFusion2: /VCS/SmartFusion2
presynth: ./presynth
TLHOKOMELISO : ./work
6.5.2 Kamor'a synthese (Botsa Potso)
postsynth_run.do
beha ka khutso ACTELLIBNAME SmartFusion2
beha PROJECT_DIR ka khutso "/sqa/users/Me/VCS_Tests/Test_DFF"
haeba {[file e teng postsynth/_info]} {
echo "INFO: Laeborari ea simulation postsynth e se e ntse e le teng"
} tse ling {
vlib postsynth
}
vmap postsynth postsynth
vmap SmartFusion2 “//idm/captures/pc/11_0_1_12_g4x/Designer/lib/ModelSim/precompiled/vlog/
SmartFusion2”
vlog -work postsynth "${PROJECT_DIR}/synthesis/SD1.v"
vlog “+ incdir+${PROJECT_DIR}/stimulus” -work postsynth “${PROJECT_DIR}/stimulus/SD1_TB1.v”
vsim -L SmartFusion2 -L postsynth -t 1fs postsynth.SD1_TB1
eketsa wave /SD1_TB1/*
eketsa log -r /*
matha 1000ns
log SD1_TB1/*
Etsoa
Postsynth_main.csh
#!/bin/csh -f
beha PROJECT_DIR = "/sqa/users/Me/VCS_Tests/Test_DFF"
/cad_design/tools/vcs.dir/E-2011.03/bin/vlogan +v2k -work postsynth “${PROJECT_DIR}/synthesis/
SD1.v”
/cad_design/tools/vcs.dir/E-2011.03/bin/vlogan +v2k “+incdir+${PROJECT_DIR}/stimulus” -sebetsa
postsynth “${PROJECT_DIR}/stimulus/SD1_TB1.v”
/cad_design/tools/vcs.dir/E-2011.03/bin/vcs -sim_res=1fs postsynth.SD1_TB1 -l compile.log
./simv -l run.log
Synopsys_sim.setup
MOSEBETSI > MOHLOMI
SmartFusion2: /VCS/SmartFusion2
postsynth: ./postsynth
TLHOKOMELISO : ./work
6.5.3 Moralo oa morao-rao (Botsa Potso)
postlayout_run.do
beha ka khutso ACTELLIBNAME SmartFusion2
seta PROJECT_DIR ka khutso "E:/ModelSim_Work/Test_DFF"
haeba {[file e teng ../designer/SD1/simulation/postlayout/_info]} {
echo "INFO: laeborari ea ketsiso ../designer/SD1/simulation/postlayout e se e le teng"
} tse ling {
vlib ../designer/SD1/simulation/postlayout
}
vmap postlayout ../designer/SD1/simulation/postlayout
vmap SmartFusion2 “//idm/captures/pc/11_0_1_12_g4x/Designer/lib/ModelSim/precompiled/vlog/
SmartFusion2”
vlog -work postlayout "${PROJECT_DIR}/designer/SD1/SD1_ba.v"
vlog "+ incdir+${PROJECT_DIR}/stimulus" -moralo oa mosebetsi "${PROJECT_DIR}/stimulus/SD1_TB1.v"
vsim -L SmartFusion2 -L postlayout -t 1fs -sdfmax /SD1_0=${PROJECT_DIR}/designer/SD1/
SD1_ba.sdf postlayout.SD1_TB1
eketsa wave /SD1_TB1/*
eketsa log -r /*
matha 1000ns
Postlayout_main.csh
#!/bin/csh -f
beha PROJECT_DIR = "/VCS_Tests/Test_DFF"
/cad_design/tools/vcs.dir/E-2011.03/bin/vlogan +v2k -work postlayout “${PROJECT_DIR}/
moqapi/SD1/SD1_ba.v”
/cad_design/tools/vcs.dir/E-2011.03/bin/vlogan +v2k “+incdir+${PROJECT_DIR}/stimulus” -sebetsa
moralo oa poso "${PROJECT_DIR}/stimulus/SD1_TB1.v"
/cad_design/tools/vcs.dir/E-2011.03/bin/vcs -sim_res=1fs postlayout.SD1_TB1 -sdf
max:SD1_TB1.SD1_0:${PROJECT_DIR}/designer/SD1/SD1_ba.sdf -l compile.log
./simv -l run.log
Synopsys_sim.setup
MOSEBETSI > MOHLOMI
SmartFusion2: /VCS/SmartFusion2
sebopeho sa poso: ./postlayout
DEFAULT : ./workVCS
6.6 Boiketsetso (Botsa Potso)
Phallo e ka etsoa ka mokhoa o ikemetseng ho sebelisa script e latelang ea Perl file ho fetolela ModelSim run.do files ho sengoloa sa khetla se lumellanang le VCS files, theha li-directory tse nepahetseng ka har'a bukana ea simulation ea Libero SoC, ebe u tsamaisa lipapiso.
Kenya mongolo file ho sebelisa syntax e latelang.
perl vcs_parse.pl presynth_run.do postsynth_run.do postlayout_run.do
Vcs_parse_pl
#!/usr/bin/perl -w
#############################################################################################
#
#Tšebeliso: perl vcs_parse.pl presynth_run.do postsynth_run.do postlayout_run.do
#
#############################################################################################
eaka ($ presynth, $postsynth, $postlayout) = @ARGV;
haeba(system(“mkdir VCS_Presynth”)) {print “mkdir hlolehile:\n”;}
haeba(sistimi(“mkdir VCS_Postsynth”)) {printa “mkdir hlolehile:\n”;}
haeba(system(“mkdir VCS_Postlayout”)) {print “mkdir hlolehile:\n”;}
chdir(VCS_Presynth);
`cp ../$ARGV[0] .` ;
&parse_do($presynth,"presynth");
chdir (“../”);
chdir(VCS_Postsynth);
`cp ../$ARGV[1] .` ;
&parse_do($postsynth,"postsynth");
chdir (“../”);
chdir(VCS_Postlayout);
`cp ../$ARGV[2] .` ;
&parse_do($postroneout,"postplayout");
chdir (“../”);
karolo e nyane_etsa {
my $ vlog = “/cad_design/tools/vcs.dir/E-2011.03/bin/vlogan +v2k” ;
%LIB eaka = ();
$ ea kafile = $_[0] ;
boemo ba ka ba $ = $_[1];
bula(INFILE,”$file”) || shoa “Ha e khone ho bula File Lebaka e ka ba:$!”;
haeba ($state eq “presynth”)
{
bula(OUT1,”>presynth_main.csh”) || "Ha ke khone ho theha Command File Lebaka e ka ba:$!”;
}
elsif ($state eq “postsynth”)
{
bula(OUT1,”>postsynth_main.csh”) || "Ha ke khone ho theha Command File Lebaka e ka ba:$!”;
}
elsif ($state eq "postlayout")
{
bula(OUT1,”>postlayout_main.csh”) || "Ha ke khone ho theha Command File Lebaka e ka ba:$!”;
}
tse ling
{
hatisa "Simulation State is missing \n" ;
}
bula(OUT2,”>synopsys_sim.setup”) || "Ha ke khone ho theha Command File Lebaka e ka ba:$!”;
# .csh file
hatisa OUT1 “#!/bin/csh -f\n\n\n” ;
#TLHOPHISO FILE
hatisa OUT2 “MOSEBETSI OA > DEFAULT\n” ;
hatisa OUT2 "SmartFusion2 : /sqa/users/Aditya/VCS/SmartFusion2\n" ;
ha ($ line =FILE>)
{
Setupo sa Synopsys VCS
haeba ($line =~ m/seta ka khutso PROJECT_DIR\s+\”(.*?)\”/)
{
hatisa OUT1 “set PROJECT_DIR = \”$1\”\n\n\n” ;
}
elsif ( $line =~ m/vlog.*\.v\”/ )
{
haeba ($line =~ m/\s+(\w*?)\_LIB/)
{
#printa “\$1 =$1 \n” ;
$temp = “$1″.”_LIB”;
#print "Temp = $ temp \n" ;
$LIB{$temp}++;
}
chomp ($ line);
$ mola =~ s/^vlog/$vlog/ ;
$ mola =~ s/ //g;
hatisa OUT1 “$line\n”;
}
elsif ( ($line =~ m/vsim.*presynth\.(.*)/) || ($line =~ m/vsim.*postsynth\.(.*)/) || ($line
=~ m/vsim.*postlayout\.(.*)/) )
{
$TB = $1 ;
$tb =~ s/ //g;
chomp($tb);
#printa “Lebitso la TB : $tb \n”;
haeba ( $line =~ m/sdf(.*)\.sdf/)
{
chomp ($ line);
$ mola = $ 1 ;
#printa “LINE : $line \n” ;
haeba ($line =~ m/max/)
{
$ mola =~ s/max \/// ;
$ mola =~ s/=/:/;
hatisa OUT1 “\n\n/cad_design/tools/vcs.dir/E-2011.03/bin/vcs -sim_res=1fs postlayout.$tb -sdf
max:$tb.$line.sdf -l compile.log\n” ;
}
elsif ($line =~ m/min/)
{
$ mola =~ s/min \/// ;
$ mola =~ s/=/:/;
hatisa OUT1 “\n\n/cad_design/tools/vcs.dir/E-2011.03/bin/vcs -sim_res=1fs postlayout.$tb -sdf
mets:$tb.$line.sdf -l compile.log\n” ;
}
elsif ($line =~ m/typ/)
{
$ mola =~ s/thapa \///;
$ mola =~ s/=/:/;
hatisa OUT1 “\n\n/cad_design/tools/vcs.dir/E-2011.03/bin/vcs -sim_res=1fs postlayout.$tb -sdf
mofuta:$tb.$line.sdf -l compile.log\n” ;
}
#-sdfmax /M3_FIC32_0=${PROJECT_DIR}/designer/M3_FIC32/M3_FIC32_ba.sdf — Sebopeho sa ModelSim SDF
#$sdf = “-sdf max:testbench.M3_FIC32_0:${PROJECT_DIR}/designer/M3_FIC32/M3_FIC32_ba.sdf”; - VCS
Sebopeho sa SDF
}
}
}
hatisa
OUT1 “\n\n”
;
if
($state eq “presynth”
)
{
hatisa
OUT2 “presynth
: ./presynth\n”
;
hatisa
OUT1 “/cad_design/tools/vcs.dir/E-2011.03/bin/vcs
-sim_res=1fs presynth.$tb -l
compile.log\n”
;
}
elsif
($state eq “postsynth”
)
{
hatisa
OUT2 “postsynth
: ./postsynth\n”
;
hatisa
OUT1 “/cad_design/tools/vcs.dir/E-2011.03/bin/vcs
-sim_res=1fs postsynth.$tb -l
compile.log\n”
;
}
elsif
($state eq "postlayout"
)
{
hatisa OUT2 “postlayout : ./postlayout\n” ;
}
tse ling
{
hatisa "Simulation State is missing \n" ;
}
foreach $i (linotlolo %LIB)
{
#print "Key : $i Value : $LIB{$i} \n" ;
hatisa OUT2 “$i : ./$i\n” ;
}
hatisa OUT1 “\n\n” ;
hatisa OUT1 “./simv -l run.log\n” ;
hatisa OUT2 “DEFAULT : ./work\n” ;
koala INFILE;
koala OUT1;
koala OUT2;
}
Nalane ea Tlhabollo (Ho kena ha Microchip
Nalane ea ntlafatso e hlalosa liphetoho tse kentsoeng tšebetsong tokomaneng. Liphetoho
li thathamisitsoe ka ntlafatso, ho qala ka khatiso ea morao-rao.
| Khatiso | Letsatsi | Tlhaloso |
| A | 12/2023 | Liphetoho tse latelang li entsoe tokisong ena: • Tokomane e fetoletsoe ho thempleite ea Microchip. Phetolelo ea Pele. • Karolo e ntlafalitsoeng ea 5. Siemens QuestaSim Setup/ModelSim Setup ho kenyelletsa molaetsa o mocha o hlalosang phello ea ponahalo nakong ea ketsiso le ho ntlafatsa. |
Tšehetso ea Microchip FPGA
Sehlopha sa lihlahisoa tsa Microchip FPGA se tšehetsa lihlahisoa tsa sona ka lits'ebeletso tse fapaneng tsa tšehetso, ho kenyeletsoa Ts'ebeletso ea Bareki, Setsi sa Ts'ehetso ea Tekheniki ea Bareki, a websebaka, le liofisi tsa thekiso lefatšeng ka bophara.
Bareki ba khothaletsoa ho etela lisebelisoa tsa Marang-rang tsa Microchip pele ba ikopanya le tšehetso kaha ho ka etsahala hore ebe lipotso tsa bona li se li arajoa.
Ikopanye le Setsi sa Tšehetso ea Setsebi ka ho website at www.microchip.com/support. Bolela nomoro ea Karolo ea Sesebelisoa sa FPGA, khetha mofuta o nepahetseng oa linyeoe, 'me u hlophise moralo files ha u ntse u theha nyeoe ea tšehetso ea tekheniki.
Ikopanye le Tshebeletso ya Bareki bakeng sa tshehetso ya dihlahiswa tseo e seng tsa botekgeniki, jwalo ka ditheko tsa sehlahiswa, dintlafatso tsa sehlahiswa, tlhahisoleseding e ntjhafatsa, boemo ba odara, le tumello.
- Ho tsoa Amerika Leboea, letsetsa 800.262.1060
- Ho tsoa lefats'eng lohle, letsetsa 650.318.4460
- Fax, ho tsoa kae kapa kae lefatšeng, 650.318.8044
Boitsebiso ba Microchip
Microchip Websebaka
Microchip e fana ka tšehetso ea inthaneteng ka rona website at www.microchip.com/. Sena websebaka se sebedisoang ho etsa files le tlhahisoleseding e fumaneha habonolo ho bareki. Tse ling tsa litaba tse fumanehang li kenyelletsa:
- Tšehetso ea Sehlahisoa - Lipampiri tsa data le errata, lintlha tsa kopo le sample mananeo, lisebelisoa tsa moralo, litataiso tsa basebelisi le litokomane tsa tšehetso ea hardware, lintlafatso tsa morao-rao tsa software le li-archived software
- Tšehetso e Akaretsang ea Tekheniki - Lipotso Tse Botsoang Khafetsa (FAQs), likopo tsa tšehetso ea tekheniki, lihlopha tsa lipuisano tsa inthaneteng, lethathamo la litho tsa lenaneo la balekane ba Microchip
- Khoebo ea Microchip - Mokhethoa oa lihlahisoa le litataiso tsa ho odara, likhatiso tsa morao-rao tsa khatiso tsa Microchip, lethathamo la lithupelo le liketsahalo, lethathamo la liofisi tsa thekiso ea Microchip, barekisi le baemeli ba feme.
Ts'ebeletso ea Tsebiso ea Phetoho ea Sehlahisoa
Ts'ebeletso ea tsebiso ea phetoho ea sehlahisoa sa Microchip e thusa ho boloka bareki ba le teng ka lihlahisoa tsa Microchip. Ba ngolisitseng ba tla fumana tsebiso ea lengolo-tsoibila neng kapa neng ha ho na le liphetoho, lintlafatso, lintlafatso kapa liphoso tse amanang le sehlahisoa se itseng sa lelapa kapa sesebelisoa sa ntlafatso sa thahasello.
Ho ngodisa, eya ho www.microchip.com/pcn 'me u latele litaelo tsa ho ngolisa.
Tšehetso ea Bareki
Basebelisi ba lihlahisoa tsa Microchip ba ka fumana thuso ka likanale tse 'maloa:
- Morekisi kapa Moemedi
- Ofisi ea Thekiso ea Lehae
- Embedded Solutions Engineer (ESE)
- Tšehetso ea tekheniki
Bareki ba lokela ho ikopanya le mofani oa bona oa thepa, moemeli kapa ESE bakeng sa tšehetso. Liofisi tsa thekiso ea lehae le tsona li teng ho thusa bareki. Lethathamo la liofisi tsa thekiso le libaka li kenyelelitsoe tokomaneng ena.
Tšehetso ea tekheniki e fumaneha ka ho websebaka ho: www.microchip.com/support
Karolo ea Tšireletso ea Khoutu ea Lisebelisoa tsa Microchip
Ela hloko lintlha tse latelang tsa ts'ireletso ea khoutu lihlahisoa tsa Microchip:
- Lihlahisoa tsa Microchip li kopana le litlhaloso tse fumanehang ho Microchip Data Sheet ea bona.
- Microchip e lumela hore lihlahisoa tsa eona li sireletsehile ha li sebelisoa ka mokhoa o reriloeng, ka har'a litlhaloso tsa ts'ebetso, le tlas'a maemo a tloaelehileng.
- E boloka boleng ba Microchip mme ka mabifi e sireletsa litokelo tsa eona tsa thepa ea mahlale. Boiteko ba ho tlola likarolo tsa ts'ireletso ea khoutu ea sehlahisoa sa Microchip bo thibetsoe ka thata 'me bo ka tlola Molao oa Copyright oa Millennium oa Digital.
- Ha ho Microchip kapa moetsi ofe kapa ofe oa semiconductor ea ka netefatsang ts'ireletso ea khoutu ea eona. Tšireletso ea khoutu ha e bolele hore re tiisa hore sehlahisoa "se ke ke sa robeha".
Tšireletso ea khoutu e lula e fetoha. Microchip e ikemiselitse ho tsoela pele ho ntlafatsa likarolo tsa ts'ireletso ea khoutu ea lihlahisoa tsa rona.
Tsebiso ea Molao
Khatiso ena le lintlha tse mona li ka sebelisoa feela le lihlahisoa tsa Microchip, ho kenyeletsoa ho rala, ho leka, le ho kopanya lihlahisoa tsa Microchip le kopo ea hau. Tšebeliso ea tlhahisoleseling ena ka tsela efe kapa efe e tlola melaoana ena. Lintlha mabapi le lits'ebetso tsa sesebelisoa li fanoe molemong oa hau feela 'me li ka nkeloa sebaka ke liapdeite. Ke boikarabello ba hau ho netefatsa hore kopo ea hau e kopana le litlhaloso tsa hau. Ikopanye le ofisi ea thekiso ea Microchip ea lehae bakeng sa tšehetso e eketsehileng kapa, fumana tšehetso e eketsehileng ho www.microchip.com/en-us/support/design-help/client-support-services.
TSEBISO ENA E FUMANA KE MICROCHIP "JOALOKAHA E LE". MICROCHIP HA E ETSE LITLHAKISO KAPA LITIISETSO TSA MOFUTA OFE kapa O fe Ebang E BONAHALA KAPA E BONAHALA, E NGOLOA KAPA MOLOMO, MOLAO KAPA HO SE EMONG, E Amanang le LITSEBISO HO kenyeletsoa EMPA E SA FUMANE LE TIISETSO EFE KAPA EFE E FUMANEHLENG LE TLAMELO. BAKENG SA MORERO O KHETHEHILENG, KAPA LITIISETSO TSE AMANG LE MAEMO A OONA, BOLEMO, KAPA KETSAHALO EA OONA.
HA HO LE TSATSAHALO, MICROCHIP E TLA BA MOTHO OA MOLATO BAKENG SA LITABA LIFE, TSE KHETHEHILENG, TSA KOTSI, TSATSAHALO, KAPA TAHLEHELO E LATELANG, TŠENYEHO, LITŠEnyehelo, KAPA LITJEHO TSA MOFUTA OFE O TLANG LE LITSEBISO KAPA TŠEBELETSO EA LONA, LE HO KA ETSAHALA KETSAHALO E ETSANG. TSE KA E KA ETSAHANG KAPA MESEKO E BONAHALA. HO FIHLELA KA HO FETISISA HO DUMELLA KE MOLAO, BOIKARABELO KAOFELA BA MICROCHIP HO LIKELETSO KAOFELA KA TSELA EFE KAPA E MABAPI LE TSEBISO KAPA TŠEBELETSO EA YONA E KE KE E FEELA BOLIMO OA LITEFO, HA E LE TSE LE FELA, TSEO U LI LEFILENG KA THOTLHALA BAKENG SA MICROCHIP.
Tšebeliso ea lisebelisoa tsa Microchip ts'ehetso ea bophelo le/kapa lits'ebetso tsa ts'ireletso e kotsing ea moreki, 'me moreki o lumela ho sireletsa, ho qosa le ho boloka Microchip e se nang kotsi ho tsoa lits'enyehelo tsohle, likopo, lisutu, kapa litšenyehelo tse bakoang ke ts'ebeliso e joalo. Ha ho lilaesense tse fetisoang, ka mokhoa o hlakileng kapa ka tsela e 'ngoe, tlasa litokelo life kapa life tsa thepa ea mahlale a Microchip ntle le ha ho boletsoe ka tsela e ngoe.
Matšoao a khoebo
Lebitso la Microchip le logo, logo ea Microchip, Adaptec, AVR, logo ea AVR, AVR Freaks, BesTime, BitCloud, CryptoMemory, CryptoRF, dsPIC, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXStylus MediaLB, megaAVR, Microsemi, Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, PolarFire, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetri , SyncServer, Tachyon, TimeSource, tinyAVR, UNI/O, Vectron, le XMEGA ke matšoao a ngolisitsoeng a khoebo a Microchip Technology Incorporated USA le linaheng tse ling.
AgileSwitch, APT, ClockWorks, The Embedded Control Solutions Company, EtherSynch, Flashtec, Hyper Speed Taolo, HyperLight Load, Libero, motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus, logo ea ProASIC Plus, Quiet- Wire, SmartFusion, Sync,TimePyTime,TimeTime,TimeTime, Sync,TimeTime,TextTime , mme ZL ke matshwao a kgwebo a ngodisitsweng a Microchip Technology Incorporated naheng ya USA
Khatello ea Bohlokoa e Haufi, AKS, Analog-for-the-Digital Age, AnyCapacitor, AnyIn, AnyOut, Augmented Switching, BlueSky, BodyCom, Clockstudio, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEmic DAMSrage, EAMsvenet, dsPICDEM DAMSrage, EAMsvenet therGREEN, GridTime, IdealBridge, In-Circuit Serial Programming, ICSP, INICnet, Intelligent Paralleling, IntelliMOS, Inter-Chip Connectivity, JitterBlocker, Knob-on-Display, KoD, maxCrypto, maxView, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net,
PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, RTAX, RTG4, SAMICE, Serial Quad I/O, simpleMAP, SimpliPHY, SmartBuffer, SmartHLS, SMART-IS, storClad, SQI, SuperSwitcher,
SuperSwitcher II, Switchtec, SynchroPHY, Kakaretso ea Mamello, Nako e Tšeptjoang, TSHARC, USBCheck, VariSense, VectorBlox, VeriPHY, ViewSpan, WiperLock, XpressConnect, le ZENA ke matshwao a kgwebo a Microchip Technology Incorporated
USA le linaheng tse ling.
SQTP ke letšoao la ts'ebeletso la Microchip Technology Incorporated USA
Letšoao la Adaptec, Frequency on Demand, Silicon Storage Technology, le Symmcom ke matšoao a ngolisitsoeng a khoebo a Microchip Technology Inc. linaheng tse ling.
GestIC ke letshwao la kgwebo le ngodisitsweng la Microchip Technology Germany II GmbH & Co. KG, e leng lekala la Microchip Technology Inc., dinaheng tse ding.
Matšoao a mang kaofela a boletsoeng mona ke thepa ea lik'hamphani tse fapaneng.
© 2023, Microchip Technology Incorporated le lithuso tsa eona. Litokelo tsohle li sirelelitsoe.
ISBN: 978-1-6683-3694-6
Tsamaiso ea Tsamaiso ea Boleng
Ho fumana leseli mabapi le Tsamaiso ea Tsamaiso ea Boleng ea Microchip, ka kopo etela www.microchip.com/quality.
| LIMAKASE | ASIA/PACIFIC | ASIA/PACIFIC | ULAYA |
| Ofisi ea Khoebo 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Mohala: 480-792-7200 Fax: 480-792-7277 Tšehetso ea tekheniki: www.microchip.com/support Web Aterese: www.microchip.com Atlanta Duluth, GA Mohala: 678-957-9614 Fax: 678-957-1455 Austin, TX Mohala: 512-257-3370 Boston Westborough, MA Mohala: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Mohala: 630-285-0071 Fax: 630-285-0075 Dallas Addison, TX Mohala: 972-818-7423 Fax: 972-818-2924 Detroit Novi, MI Mohala: 248-848-4000 Houston, TX Mohala: 281-894-5983 Indianapolis Noblesville, IN Mohala: 317-773-8323 Fax: 317-773-5453 Mohala: 317-536-2380 Los Angeles Mission Viejo, CA Mohala: 949-462-9523 Fax: 949-462-9608 Mohala: 951-273-7800 Raleigh, NC Mohala: 919-844-7510 New York, NY Mohala: 631-435-6000 San Jose, CA Mohala: 408-735-9110 Mohala: 408-436-4270 Canada - Toronto Mohala: 905-695-1980 Fax: 905-695-2078 |
Australia - Sydney Mohala: 61-2-9868-6733 China - Beijing Mohala: 86-10-8569-7000 China - Chengdu Mohala: 86-28-8665-5511 China - Chongqing Mohala: 86-23-8980-9588 China - Dongguan Mohala: 86-769-8702-9880 China - Guangzhou Mohala: 86-20-8755-8029 China - Hangzhou Mohala: 86-571-8792-8115 China - Hong Kong SAR Mohala: 852-2943-5100 China - Nanjing Mohala: 86-25-8473-2460 China - Qingdao Mohala: 86-532-8502-7355 China - Shanghai Mohala: 86-21-3326-8000 China - Shenyang Mohala: 86-24-2334-2829 China - Shenzhen Mohala: 86-755-8864-2200 China - Suzhou Mohala: 86-186-6233-1526 China - Wuhan Mohala: 86-27-5980-5300 China - Xian Mohala: 86-29-8833-7252 China - Xiamen Mohala: 86-592-2388138 China - Zhuhai Mohala: 86-756-3210040 |
India - Bangalore Mohala: 91-80-3090-4444 India - New Delhi Mohala: 91-11-4160-8631 India - Pune Mohala: 91-20-4121-0141 Japane - Osaka Mohala: 81-6-6152-7160 Japane - Tokyo Mohala: 81-3-6880-3770 Korea - Daegu Mohala: 82-53-744-4301 Korea - Seoul Mohala: 82-2-554-7200 Malaysia - Kuala Lumpur Mohala: 60-3-7651-7906 Malaysia - Penang Mohala: 60-4-227-8870 Philippines - Manila Mohala: 63-2-634-9065 Singapore Mohala: 65-6334-8870 Taiwan - Hsin Chu Mohala: 886-3-577-8366 Taiwan - Kaohsiung Mohala: 886-7-213-7830 Taiwan - Taipei Mohala: 886-2-2508-8600 Thailand - Bangkok Mohala: 66-2-694-1351 Vietnam - Ho Chi Minh Mohala: 84-28-5448-2100 |
Austria - Wels Mohala: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Mohala: 45-4485-5910 Fax: 45-4485-2829 Finland - Espoo Mohala: 358-9-4520-820 Fora - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Jeremane - Ho khabisa Mohala: 49-8931-9700 Jeremane - Haan Mohala: 49-2129-3766400 Jeremane - Heilbronn Mohala: 49-7131-72400 Jeremane - Karlsruhe Mohala: 49-721-625370 Jeremane - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Jeremane - Rosenheim Mohala: 49-8031-354-560 Iseraele - Ra'anana Mohala: 972-9-744-7705 Italy - Milan Mohala: 39-0331-742611 Fax: 39-0331-466781 Italy - Padova Mohala: 39-049-7625286 Netherlands - Drunen Mohala: 31-416-690399 Fax: 31-416-690340 Norway - Trondheim Mohala: 47-72884388 Poland - Warsaw Mohala: 48-22-3325737 Romania - Bucharest Tel: 40-21-407-87-50 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 Sweden - Gothenberg Tel: 46-31-704-60-40 Sweden - Stockholm Mohala: 46-8-5090-4654 UK - Wokingham Mohala: 44-118-921-5800 Fax: 44-118-921-5820 |
© 2023 Microchip Technology Inc. le makalana a eona
DS50003627A -
Litokomane / Lisebelisoa
 |
MICROCHIP Libero SoC Simulation Library Software [pdf] Bukana ea Mosebelisi DS50003627A, Libero SoC Simulation Library Software, SoC Simulation Library Software, Ketsiso Library Software, Library Software, Software |
