MICROCHIP Libero SoC Simulation Library Software Guide User

Libero SoC Simulation
Fa'atonuga Seti Faletusi

Mataupu lalafi

1 Folasaga

2 Libero SoC Integration

3 Aldec Setup mo Active-HDL ma Riviera-Pro (Fai se Fesili)

4 Fa'atonu Fa'asa'oga (Fa'ai se Fesili)

5 Seti Cadence Xcelium (Microchip Login)

6 Siemens QuestaSim Setup/ModelSim Setup (Fai se Fesili)

7 Synopsys VCS Setup (Fai se Fesili)

8 Toe Iloilo Tala'aga (Microchip Login

9 Pepa / Punaoa

9.1 Fa'asinomaga

10 Fa'amatalaga Fa'atatau

Folasaga

(Fai se Fesili)

O le faʻamoemoega o lenei pepa o le faʻamatalaina lea o le faʻagasologa o le faʻatulagaina o le siosiomaga faʻataʻitaʻiga e faʻaaoga ai se poloketi Libero SoC e fai ma faʻaoga. O lenei faʻamaumauga e fetaui ma faletusi na tuʻufaʻatasia muamua na tuʻuina atu mo le faʻaogaina ma le Libero SoC v11.9 ma faʻasalalauga fou. O faletusi ua saunia ua tuufaatasia mo Verilog. E manaʻomia e tagata faʻaoga VHDL se laisene e faʻatagaina ai le faʻaogaina o faiga faʻafefiloi.
O loʻo avanoa faletusi faʻataʻitaʻi tuʻufaʻatasia mo meafaigaluega nei:

Aldec Active-HDL
Aldec Riviera-PRO

Cadence Incisive Enterprise ma le Xcelium
Siemens QuestaSim

Synopsys VCS

Ina ia talosagaina se faletusi mo se isi simulator, fa'afeso'ota'i Lagolago Fa'atekinisi Microchip.

Libero SoC Integration

(Fai se Fesili)

E lagolagoina e Libero SoC le faʻataʻitaʻiga e faʻaaoga ai le ModelSim ME e ala i le fatuina o se run.do file. Lenei file o loʻo faʻaaogaina e ModelSim ME / ModelSim Pro ME e faʻatutu ma faʻatautaia le faʻataʻitaʻiga. Mo le faʻaogaina o isi meafaigaluega faʻataʻitaʻiga, e mafai ona e faʻatupuina le ModelSim ME / ModelSim Pro ME run.do ma suia le Tcl script file e fa'aoga tulafono e fetaui ma lau simulator.
1.1 Libero SoC Tcl File Tupulaga (Fai se Fesili)
A maeʻa ona fatuina ma faʻatupuina le mamanu ile Libero SoC, amata se faʻataʻitaʻiga ModelSim ME / ModelSim Pro ME i lalo o vaega uma o mamanu (presynth, postsynth, ma post-layout). Ole la'asaga lea e maua ai le run.do file mo le ModelSim ME/ModelSim Pro ME mo vaega ta'itasi mamanu.
Taua: A uma ona amata ta'aloga fa'ata'ita'iga ta'itasi, toe fa'aigoa le auto-generated run.do file i lalo o le faʻasologa faʻataʻitaʻiga e puipuia ai le Libero SoC mai le faʻaaogaina o lena mea file. Mo example, le files e mafai ona toe faaigoa i le presynth_run.do, postsynth_run.do ma postlayout_run.do.

Aldec Setup mo Active-HDL ma Riviera-Pro (Fai se Fesili)

O le tamoe.do file faʻaaogaina e le ModelSim ME / ModelSim Pro ME e mafai ona faʻaleleia ma faʻaoga mo faʻataʻitaʻiga e faʻaaoga ai le Aldec simulators.
2.1 Siosiomaga Fesuia'i (Fai se Fesili)
Seti lou siosiomaga fesuiaiga i lau laisene file nofoaga:
LM_LICENSE_FILE: e tatau ona aofia ai se faasinoala i le server laisene.
2.2 La'u mai le Faletusi Tu'ufa'atasi (Fai se Fesili)
Sii mai faletusi mo le Aldec Active-HDL ma le Aldec Riviera-PRO mai le Microchip webnofoaga.
2.3 Suia le run.do mo Aldec simulation (Fai se Fesili)
O le tamoe.do files gaosia e Libero SoC mo faʻataʻitaʻiga e faʻaaoga ai le Active-HDL ma Riviera-Pro meafaigaluega e mafai ona faʻaogaina mo faʻataʻitaʻiga e faʻaaoga ai Active-HDL ma Riviera-Pro ma se suiga e tasi. O le laulau o loʻo i lalo o loʻo lisiina ai tulafono tutusa Aldec e sui i le ModelSim run.do file.
Laulau 2-1. Aldec Equivalent Poloaiga

ModelSim	Active-HDL
vlog	alogo
vcom	acom
vlib	alib
vsim	asim
vmap	amap

O lo'o mulimuli mai e pei oample run.do e fesoʻotaʻi ma Aldec simulators.

Seti le nofoaga o lo'o iai le lisi o galuega.
seti dsn
Seti se igoa faletusi galue, fa'afanua lona nofoaga, ona fa'afanua lea o le nofoaga o le aiga Microchip FPGA
faletusi fa'apipi'i muamua (mo fa'ataample, SmartFusion2) lea o loʻo e faʻatinoina ai lau mamanu.
alib presynth
amap presynth presynth
amap SmartFusion2

Fa'atasi uma le HDL e mana'omia files fa'aoga i le mamanu ma le faletusi mana'omia.
alog –work presynth temp.v (mo Verilog)
alog –work presynth testbench.v
acom –work presynth temp.vhd (mo Vhdl)
acom –work presynth testbench.vhd
Fa'ata'ita'i le mamanu.
asim –L SmartFusion2 –L presynth –t 1ps presynth.testbench
tamoe 10us

2.4 Fa'amatalaga Mata'utia (Fai se Fesili)
O lenei vaega o lo'o lisiina ai fa'afitauli ma tapula'a ua iloa.

O faletusi o lo'o tu'ufa'atasia e fa'aaoga ai le Riviera-PRO e fa'apitoa i luga ole laiga (fa'atusa, 64-bit faletusi e le mafai ona fa'atautaia ile 32-bit platform ma le isi itu).

Mo mamanu o loʻo iai SERDES/MDDR/FDDR, faʻaoga le filifiliga lea i lau run.do files aʻo faʻatautaia faʻataʻitaʻiga pe a uma ona tuʻufaʻatasia a latou mamanu:
– Active-HDL: asim –o2
- Riviera-PRO: asim -O2 (mo presynth ma post-layout simulations) ma asim -O5 (mo faʻataʻitaʻiga post-layout)
O le seti Aldec mo Active-HDL ma Riviera-Pro o loʻo i ai SAR o loʻo faʻatali. Mo nisi fa'amatalaga, fa'afeso'ota'i Lagolago Fa'atekinisi Microchip.
SAR 49908 - Active-HDL: VHDL Error mo faʻataʻitaʻiga poloka Math

SAR 50627 - Riviera-PRO 2013.02: Faʻataʻitaʻiga mea sese mo SERDES mamanu
SAR 50461 - Riviera-PRO: asim -O2/-O5 filifiliga i faʻataʻitaʻiga

Fa'atonu Fa'asa'oga (Fai se Fesili)

E mana'omia ona e faia se tala file tutusa i le ModelSim ME/ModelSim Pro ME run.do e tamoe le
Cadence Incisive simulator. Mulimuli i laasaga nei ma fai tusitusiga file mo NCSim pe faʻaaoga le faʻamatalaga file
saunia e faaliliu le ModelSim ME/ModelSim Pro ME run.do files i le faatulagaga files
manaʻomia e faʻatautaia ai faʻataʻitaʻiga e faʻaaoga ai le NCSim.
Taua: Cadence ua taofia le tatalaina o lomiga fou o le Incisive Enterprise
simulator ma amata ona lagolagoina le Xcelium simulator.

3.1 Siosiomaga Fesuia'iga (Fai se Fesili)
Ina ia faʻatautaia le Cadence Incisive simulator, faʻapipiʻi suiga o le siosiomaga nei:

LM_LICENSE_FILE: e tatau ona aofia ai se faasinoala ile laisene file.
cds_root: e tatau ona faasino i le nofoaga o le lisi o fale o le Cadence Incisive Installation.

PATH: e tatau ona faasino i le talone nofoaga i lalo o le meafaigaluega tusi tusi faasino e cds_root o lona uiga,
$cds_root/tools/bin/64bit (mo se masini 64-bit ma le $cds_root/tools/bin mo se masini 32-bit).
E tolu auala e faʻatulagaina ai le siosiomaga faʻataʻitaʻiga i le tulaga o se ki i le va o le 64-bit ma le 32-bit operating system:

Tulaga 1: FUAFUAGA PATH
Fa'atonu le poloaiga lenei:
seti ala = (install_dir/tools/bin/64bit $path) mo masini 64bit ma
seti ala = (install_dir/tools/bin $path) mo masini 32bit
Tulaga 2: Fa'aaoga le -64bit Command-line Filifiliga
I le laina faʻatonuga faʻamaonia -64bit filifiliga ina ia faʻaogaina le 64bit executable.
Tulaga 3: Fa'atulaga le INCA_64BIT po'o le CDS_AUTO_64BIT Siosiomaga Su'esu'e
Ole suiga ole INCA_64BIT ole fa'atatau ole boolean. E mafai ona e setiina lenei fesuiaiga i soʻo se tau poʻo se manoa null.
setenv INCA_64BIT

O isi mea faigaluega Cadence, e pei o meafaigaluega IC, faʻaaoga foi le suiga ole siosiomaga CDS_AUTO_64BIT e pulea ai le filifiliga o le 32-bit poʻo le 64-bit executables. O le siata o loʻo i lalo o loʻo faʻaalia ai pe faʻapefea ona e setiina le CDS_AUTO_64BIT fesuiaiga e faʻatautaia ai meafaigaluega Incisive ma meafaigaluega IC i auala uma.
Laulau 3-1. CDS_AUTO_64BIT Fesuiaiga

CDS_AUTO_64BIT Fesuiaiga	Meafaigaluega fa'amalosi	Meafaigaluega IC
setenv CDS_AUTO_64BIT UMA	64 bit	64 bit
setenv CDS_AUTO_64BIT LEAI	32 bit	32 bit
setenv CDS_AUTO_64BIT TU'U'ĀINA:ic_binary	64 bit	32 bit
setenv CDS_AUTO_64BIT SE'E FAAMATALAGA: INCA	32 bit	64 bit

Taua: E tatau ona fa'atino uma meafaigaluega fa'apitoa i le 32-bit mode po'o le 64-bit mode, aua le fa'aogaina le EXCLUDE e le aofia ai se fa'atonuga fa'apitoa, e pei o mea nei: setenv CDS_AUTO_64BIT EXCLUDE:ncelab
Afai e te setiina le fesuiaiga CDS_AUTO_64BIT e le aofia ai meafaigaluega Incisive (setenv CDS_AUTO_64BIT EXCLUDE:INCA), o meafaigaluega uma Incisive e faʻatautaia i le 32-bit mode. Ae ui i lea, o le -64bit command-line filifiliga e faʻafefe ai le fesuiaiga o le siosiomaga.
O le fa'atulagaina lea files fesoasoani ia te oe e pulea au faʻamatalaga ma pulea le faʻaogaina o meafaigaluega faʻataʻitaʻi ma mea aoga:

Fa'afanua faletusi file (cds.lib)—Fa'amatala se igoa talafeagai mo le nofoaga o lau mamanu.
Faletusi ma fa'afeso'ota'i i igoa o fa'amaumauga fa'aletino.
Fuafuaga file (hdl.var)—Fa'amatala suiga e a'afia ai le amio o mea faigaluega fa'ata'ita'i ma mea aoga.

3.2 La'u mai le Faletusi Tu'ufa'atasi (Fai se Fesili)
La'u mai faletusi mo Cadence Incisive mai Microsemi's webnofoaga.
3.3 Fausia le NCSim Script File (Fai se Fesili)
A uma ona faia se kopi o le run.do files, fai laasaga nei e faʻatino ai lau faʻataʻitaʻiga e faʻaaoga ai le NCSim:

Fausia se cds.lib file e fa'amatala ai faletusi e mafai ona maua ma lo latou nofoaga. O le file o lo'o i ai fa'amatalaga e fa'afanua igoa fa'atatau a le faletusi i a latou ala fa'asinotonu fa'aletino. Mo example, afai o loo e tamoe presynth simulation, le cds.lib file ua tusia e pei ona faaalia i le codeblock lea.
FAAMATALAGA presynth ./presynth
FAAMATALAGA COREAHBLITE_LIB ./COREAHBLITE_LIB
FA'AMANATU smartfusion2
Fausia se hdl.var file, o se faatulagaga e filifili ai file o lo'o i ai fesuiaiga fetuutuunai, e fuafua ai pe fa'afefea ona fa'atulagaina lau siosiomaga mamanu. O le fesuiaiga lea files e aofia ai:
- Fuafuaga e faʻaaogaina e faʻamaonia ai le faletusi galuega lea e teu ai e le tagata faʻapipiʻi mea faʻapipiʻi ma isi faʻamaumauga.
- Mo Verilog, fesuiaiga (LIB_MAP, VIEW_MAP, GALUEGA) e faʻaaogaina e faʻamaonia ai faletusi ma views e su'esu'e pe a fo'ia e le fa'amatala fa'ata'ita'iga.
- Fuafuaga e mafai ai e oe ona faʻamatalaina le tuʻufaʻatasia, faʻamatalaga, ma le simulator filifiliga laina laina ma finauga.
I le tulaga o presynth simulation exampLe faʻaalia i luga, fai mai e tolu a matou RTL files: av, bv, ma le testbench.v, lea e manaʻomia ona tuʻufaʻatasia i le presynth, COREAHBLITE_LIB, ma le presynth faletusi. O le hdl.var file e mafai ona tusia e pei ona faʻaalia i le codeblock lea.
FAAMATALAGA GALUEGA presynth
FA'AMANATU POLOKALE_DIR files>
FAAMANATU LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/av => presynth )
FAAMANATU LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/bv => COREAHBLITE_LIB )
FAAMANATU LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/testbench.v => presynth )
FAAMANATU LIB_MAP ($LIB_MAP, + => presynth )
Tuufaatasia le mamanu files fa'aoga ncvlog filifiliga.
ncvlog +incdir+ –cdslib ./cds.lib –hdlvar ./hdl.var –logfile
ncvlog.log –update –linedebug av bv testbench.v
Fa'amatala le mamanu e fa'aaoga ai le ncelab. E fausia e le elaborator se fa'asologa o mamanu e fa'avae i luga o fa'amatalaga vave ma fa'asologa i totonu o le mamanu, fa'atūina le feso'ota'iga fa'ailo, ma fa'atatau muamua tau mo mea uma i totonu o le mamanu. O lo'o fa'aputuina le fa'asologa o fa'ata'ita'iga fa'ata'ita'iga, o le fa'atusa lea o lau fa'ata'ita'iga o lo'o fa'aogaina e le simulator e fa'atino ai le fa'ata'ita'iga.
ncelab –Message –cdslib ./cds.lib –hdlvar ./hdl.var –logfile ncelab.log –errormax 15 –
avanoa +rwc –status worklib. : module
Fa'amatalaga I le taimi o le fa'ata'ita'iga Fa'ata'oto
I le tulaga o faʻataʻitaʻiga post-layout, muamua le SDF file e manaʻomia le tuʻufaʻatasia aʻo leʻi faʻamalamalamaina le faʻaaogaina o le ncsdfc poloaiga.
ncsdfcfileigoa>.sdf –outputfileigoa>.sdf.X
I le taimi o faʻamatalaga faʻaaoga le SDF faʻapipiʻi faʻatasi ma -autosdf filifiliga e pei ona faʻaalia i le codeblock o loʻo mulimuli mai.
ncelab -autosdf –Message –cdslib ./cds.lib –hdlvar ./hdl.var –logfile ncelab.log –errormax
15 –access +rwc –status worklib. :module –sdf_cmd_file ./
sdf_cmd_file
Le sdf_cmd_file e tatau ona fa'aalia i le codeblock lea.
COMPILED_SDF_FILE = “ file>”
Fa'ata'ita'i fa'aaoga le ncsim. A maeʻa faʻamalamalamaga e faia se ata faʻataʻitaʻiga, lea e utaina e ncsim mo faʻataʻitaʻiga. E mafai ona e tamoʻe i le faiga faʻavae poʻo le GUI mode.
ncsim –Message –batch/-gui –cdslib ./cds.lib –hdlvar ./hdl.var –logfile ncsim.log –
errormax 15 -status worklib. : module

Taua: O laasaga uma e tolu o loʻo i luga o le tuʻufaʻatasia, faʻamalamalamaina, ma faʻataʻitaʻiga e mafai ona tuʻuina i totonu o se atigi tusitusiga file ma afua mai i le laina faʻatonu. Nai lo le faʻaogaina o nei laasaga e tolu, e mafai ona faʻataʻitaʻiina le mamanu i le laasaga e tasi e faʻaaoga ai le ncverilog poʻo le irun filifiliga e pei ona faʻaalia i le codeblock o loʻo mulimuli mai.
ncverilog +incdir+ -cdslib ./cds.lib –hdlvar ./hdl.var
files fa'aaogaina i le mamanu>
irun +incdir+ -cdslib ./cds.lib –hdlvar ./hdl.var files
fa'aaogaina i le mamanu>

3.3.1 Fa'amatalaga Mata'utia (Fai se Fesili)
Fa'ata'ita'iga a le Testbench
O le faʻaaogaina o le faʻamatalaga o loʻo i lalo mo le faʻamautinoaina o le taimi o le uati i le suʻega suʻega na faia e le tagata faʻaoga, poʻo le faʻaogaina o le suʻega faʻataʻitaʻiga na faia e Libero SoC e le galue ma NCSim.
i taimi uma @(SYSCLK)
#(SYSCLK_PERIOD / 2.0) SYSCLK <= !SYSCLK;
Suia e pei ona taua i lalo e fai ai le fa'ata'ita'iga:
i taimi uma #(SYSCLK_PERIOD / 2.0) SYSCLK = ~SYSCLK;
Taua: Tuufaatasi faletusi mo NCSim e fa'apitoa fa'avae (fa'atusa 64 bit faletusi e le fetaui ma le 32 bit platform ma vice versa).
Postsynth ma Post-layout Simulations Faʻaaogaina MSS ma SERDES Aʻo faʻatautaia faʻataʻitaʻiga postsynth o mamanu o loʻo i ai le poloka MSS poʻo faʻataʻitaʻiga faʻataʻitaʻiga o mamanu e faʻaaoga ai SERDES, e le aoga le BFM simulations pe a fai o le filifiliga -libmap e
e le'o fa'amaonia i le taimi o fa'amatalaga. E mafua ona i le taimi o faʻamatalaga, MSS e foia mai le faletusi o galuega (ona o le faaletonu o le fusifusia ma le worklib o le postsynth / post-layout) lea e naʻo se Galuega Faʻamau.
O le ncelab command e tatau ona tusia e pei ona faʻaalia i le poloka code nei e foia ai le MSS
poloka mai le SmartFusion2 faletusi ua uma ona tuufaatasia.

ncelab -libmap lib.map -libverbose -Savali -access +rwc cfg1
ma le lib.map file e tatau ona fa'apea:
config cfg1;
mamanu ;
Lisi fa'atonu smartfusion2 ;
endconfig
Ole mea lea e fofo ai so'o se sela ile faletusi SmartFusion2 a'o le'i va'ai ile faletusi galuega fa'atusa postsynth/post-layout.
O le filifiliga -libmap e mafai ona faʻaaogaina e ala i le faʻaogaina i le taimi o faʻamatalaga mo faʻataʻitaʻiga uma (presynth, postsynth, ma post-layout). Ole mea lea e 'alofia ai fa'afitauli fa'ata'ita'iga e mafua ona ole fa'amalieina o fa'ata'ita'iga mai faletusi.
ncelab: *F, INTERR: TU'OSA'AGA I totonu
O lenei mea faigaluega tuusaunoaga ncelab o se faʻatagaga mo mamanu o loʻo i ai le FDDR i SmartFusion 2 ma IGLOO 2 i le taimi o faʻataʻitaʻiga postsynth ma post-layout e faʻaaoga ai -libmap filifiliga.
Taua: Ua lipotia lenei mataupu i le vaega lagolago a Cadence (SAR 52113).

3.4 Sample Tcl ma Shell Script Files (Fai se Fesili)
O mea nei files o le faatulagaga files mana'omia mo le fa'atulagaina o le mamanu ma le atigi tusitusiga file mo le faʻatinoina o poloaiga NCSim.
Cds.lib
NE smartfusion2 /scratch/krydor/tmpspace/users/me/nc-vlog64/SmartFusion2
FAAMATALAGA COREAHBLITE_LIB ./COREAHBLITE_LIB
FAAMATALAGA presynth ./presynth

Hdl.var
FAAMATALAGA GALUEGA presynth
FA'AMANATU PROJECT_DIR /scratch/krydor/tmpspace/sqausers/me/3rd_party_simulators/Cadence/IGLOO2/
ENVM/M2GL050/envm_fic1_ser1_v/eNVM_fab_master
FAAMANATU LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/core/coreahblite_addrdec.v => COREAHBLITE_LIB )
FAAMANATU LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/core/coreahblite_defaultslavesm.v => COREAHBLITE_LIB )
FAAMANATU LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/core/coreahblite_masterstagev => COREAHBLITE_LIB )
FAAMANATU LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/core/coreahblite_slavearbiter.v => COREAHBLITE_LIB )
FAAMANATU LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/core/coreahblite_slavestagev => COREAHBLITE_LIB )
FAAMANATU LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/core/coreahblite_matrix2x16.v => COREAHBLITE_LIB )
FAAMANATU LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/core/coreahblite.v => COREAHBLITE_LIB )
FAAMANATU LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/component/work/SB/CCC_0/SB_CCC_0_FCCC.v =>
presynth)
FAAMANATU LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreConfigMaster/
2.0.101/rtl/vlog/core/coreconfigmaster.v => presynth )
FAAMANATU LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreConfigP/4.0.100/rtl/
vlog/core/coreconfigp.v => presynth )
FAAMANATU LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreResetP/5.0.103/rtl/
vlog/core/coreresetp_pcie_hotreset.v => presynth )
FAAMANATU LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreResetP/5.0.103/rtl/
vlog/core/coreresetp.v => presynth )
FAAMANATU LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/component/work/SB/FABOSC_0/SB_FABOSC_0_OSC.v =>
presynth)
FAAMANATU LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/component/work/SB_HPMS/SB_HPMS.v => presynth )
FAAMANATU LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/component/work/SB/SB.v => presynth )
FAAMANATU LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/vaega/galuega/SB_top/SERDES_IF_0/
SB_top_SERDES_IF_0_SERDES_IF.v => presynth )
FAAMANATU LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/component/work/SB_top/SB_top.v => presynth )
FAAMANATU LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/component/work/SB_top/testbench.v => presynth )
FAAMANATU LIB_MAP ($LIB_MAP, + => presynth )
Commands.csh
ncvlog +incdir+../../component/work/SB_top -cdslib ./cds.lib -hdlvar ./hdl.var -logfile
ncvlog.log -errormax 15 -update -linedebug
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite_addrdec.v
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/
coreahblite_defaultslavesm.v
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite_masterstagev
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite_slavearbiter.v
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite_slavestagev
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite_matrix2x16.v
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite.v
../../component/work/SB/CCC_0/SB_CCC_0_FCCC.v
../../component/Actel/DirectCore/CoreConfigMaster/2.0.101/rtl/vlog/core/coreconfigmaster.v
../../component/Actel/DirectCore/CoreConfigP/4.0.100/rtl/vlog/core/coreconfigp.v
../../component/Actel/DirectCore/CoreResetP/5.0.103/rtl/vlog/core/coreresetp_pcie_hotreset.v
../../component/Actel/DirectCore/CoreResetP/5.0.103/rtl/vlog/core/coreresetp.v
../../component/work/SB/FABOSC_0/SB_FABOSC_0_OSC.v ../../component/work/SB_HPMS/SB_HPMS.v
../../component/work/SB/SB.v ../../component/work/SB_top/SERDES_IF_0/
SB_TOP_SERDES_IF_0_SERDES_IF.v
../../component/work/SB_top/SB_top.v ../../component/work/SB_top/testbench.v
ncelab -Message -cdslib ./cds.lib -hdlvar ./hdl.var
-work presynth -logfile ncelab.log -errormax 15 -access +rwc -status presynth.testbench:module
ncsim -Message -batch -cdslib ./cds.lib -hdlvar ./
hdl.var -logfile ncsim.log -errormax 15 -status presynth.testbench:module

3.5 Otometi (Fai se Fesili)
O le mau lea file liliu le ModelSim run.do files i le faatulagaga files manaʻomia e faʻatautaia faʻataʻitaʻiga e faʻaaoga ai le NCSim.
Tusitala File Fa'aoga
perl cadence_parser.pl presynth_run.do postsynth_run.do
postlayout_run.do Microsemi_Family
Nofoaga_o_Cadence_Precompiled_libraries

Cadence_parser.pl
#!/usr/bin/perl -w

#################################################### ############################################
##################
#Fa'aoga: perl questa_parser.pl presynth_run.do postsynth_run.do postlayout_run.do
Microsemi_Family Precompiled_Libraries_location#

#################################################### ############################################
##################
fa'aaoga le POSIX;
fa'aoga sa'o;
la'u ($presynth, $postynth, $postlayout, $family, $lib_location) = @ARGV;
&questa_parser($presynth, $family, $lib_location);
&questa_parser($postsynth, $aiga, $lib_location);
&questa_parser ($postlayout, $aiga, $lib_location);
sub questa_parser {
la'u $ModelSim_run_do = $_[0];
lo'u $actel_family = $_[1];
la'u $lib_location = $_[2];
lo'u $setete;
afai (-e “$ModelSim_run_do” )
{
tatala (INFILE,”$ModelSim_run_do”);
la'u @ModelSim_run_do =FILE>;
la'u $line;
afai ($ModelSim_run_do =~ m/(presynth)/)
{
`mkdir QUESTA_PRESYNTH`;
tatala (FAIFILE,”>QUESTA_PRESYNTH/presynth_questa.do”);
$setete = $1;
} elsif ($ModelSim_run_do =~ m/(postsynth)/)
{
`mkdir QUESTA_POSTSYNTH`;
tatala (FAIFILE,”>QUESTA_POSTSYNTH/postsynth_questa.do”);
$setete = $1;
} elsif ($ModelSim_run_do =~ m/(postlayout)/ )
{
`mkdir QUESTA_POSTLAYOUT`;
tatala (FAIFILE,”>QUESTA_POSTLAYOUT/postlayout_questa.do”);
$setete = $1;
} isi
{
lolomi “Sese Inputs na tuuina atu i le file\n”;
lolomi “#Usage: perl questa_parser.pl presynth_run.do postsynth_run.do postlayout_run.do
\”Libraries_location\”\n”;
}
i luma $line (@ModelSim_run_do)
{
#O Galuega Lautele
$line =~ s/..\/designer.*simulation\///g;
$line =~ s/$state/$state\_questa/g;
# lolomi i fafoFILE “$line \n”;
afai ($line =~ m/vmap\s+.*($actel_family)/)
{
lolomi i fafoFILE “vmap $actel_family \”$lib_location\”\n”;
} elsif ($line =~ m/vmap\s+(.*._LIB)/)
{
$line =~ s/..\/component/..\/..\/component/g;
lolomi i fafoFILE “$line \n”;
} elsif ($line =~ m/vsim/)
{
$line =~ s/vsim/vsim -novopt/g;
lolomi i fafoFILE “$line \n”;
} isi
{
lolomi i fafoFILE “$line \n”;
}
}
latalata(INFILE);
tapuni(FAIFILE);
} isi {
lolomi "$ModelSim_run_do e le o iai. Toe fai fa'ata'ita'iga \n”;
}
}

Fa'atonu Xcelium Seti (Microchip Login)

E mana'omia ona e faia se tala file tutusa ma le ModelSim ME/ModelSim Pro ME run.do e faʻatautaia le Cadence Xcelium simulator. Mulimuli i laasaga nei ma fai tusitusiga file mo Xcelium poʻo le faʻaogaina o le tusitusiga file saunia e faaliliu le ModelSim ME/ModelSim Pro ME run.do files i le faatulagaga files manaʻomia e faʻatautaia faʻataʻitaʻiga e faʻaaoga ai le Xcelium.
4.1 Siosiomaga Fesuia'iga (Fai se Fesili)
Ina ia faʻatautaia le Cadence Xcelium, faʻapipiʻi suiga ole siosiomaga nei:

LM_LICENSE_FILE: e tatau ona aofia ai se faasinoala ile laisene file.
cds_root: e tatau ona faasino i le nofoaga o le lisi o fale o le Cadence Incisive Installation.
PATH: e tatau ona faasino i le nofoaga o talone i lalo o le lisi meafaigaluega e faasino i ai cds_root (ie
$cds_root/tools/bin/64bit (mo se masini 64 bit ma $cds_root/tools/bin mo se 32 bit
masini).

E tolu auala e faʻatulagaina ai le siosiomaga faʻataʻitaʻiga i le tulaga o se ki i le va o le 64-bit ma le 32-bit operating system:
Tulaga 1: FUAFUAGA PATH
seti ala = (install_dir/tools/bin/64bit $path) mo masini 64bit ma
seti ala = (install_dir/tools/bin $path) mo masini 32bit
Tulaga 2: Fa'aaoga le -64bit Command-line Filifiliga
I le laina faʻatonuga faʻamaonia -64bit filifiliga ina ia faʻaogaina le 64-bit executable.
Tulaga 3: Fa'atulaga le INCA_64BIT po'o le CDS_AUTO_64BIT Siosiomaga Su'esu'e
Ole suiga ole INCA_64BIT ole fa'atatau ole boolean. E mafai ona e setiina lenei fesuiaiga i soʻo se tau poʻo se null
manoa.
setenv INCA_64BIT

Taua: Le INCA_64BIT siosiomaga fesuiaiga e le afaina ai isi meafaigaluega Cadence, pei o meafaigaluega IC. Ae ui i lea, mo mea faigaluega Incisive, o le INCA_64BIT fesuiaiga e faʻamalo le faʻatulagaina mo le CDS_AUTO_64BIT fesuiaiga o le siosiomaga. Afai ole suiga ole siosiomaga INCA_64BIT et, o mea faigaluega uma a Incisive e tamo'e ile 64-bit mode.
setenv CDS_AUTO_64BIT FA'AMATALAGA:INCA
Taua: Le manoa INCA e tatau ona i le mataitusi tetele. O mea uma e mafai ona faʻatinoina e tatau ona faʻatautaia i le 2-bit mode poʻo le 64-bit mode, aua le setiina le fesuiaiga e aofia ai se tasi e mafai ona faʻatinoina, pei o mea nei:
setenv CDS_AUTO_64BIT INCLUDE:ncelab
O isi mea faigaluega Cadence, e pei o meafaigaluega IC, faʻaaoga foi le suiga ole siosiomaga CDS_AUTO_64BIT e pulea ai le filifiliga o le 32-bit poʻo le 64-bit executables. O le siata o loʻo i lalo o loʻo faʻaalia ai pe faʻapefea ona e setiina le CDS_AUTO_64BIT fesuiaiga e faʻatautaia ai meafaigaluega Incisive ma meafaigaluega IC i auala uma.

Laulau 4-1. CDS_AUTO_64BIT Fesuiaiga

CDS_AUTO_64BIT Fesuiaiga	Meafaigaluega fa'amalosi	Meafaigaluega IC
setenv CDS_AUTO_64BIT UMA	64-bit	64-bit
setenv CDS_AUTO_64BIT LEAI	32-bit	32-bit
setenv CDS_AUTO_64BIT FA'AVAE:ic_binary	64-bit	32-bit
setenv CDS_AUTO_64BIT SE'E FAAMATALAGA: INCA	32-bit	64-bit

Taua: O mea faigaluega uma e tatau ona faʻaogaina i le 32-bit mode poʻo le 64-bit mode, aua le faʻaogaina le EXCLUDE e faʻateʻaina ai se faʻatonuga faʻapitoa, pei o mea nei:
setenv CDS_AUTO_64BIT LE'A:ncelab
Afai e te setiina le fesuiaiga CDS_AUTO_64BIT e le aofia ai meafaigaluega Incisive (setenv
CDS_AUTO_64BIT EXCLUDE:INCA), o meafaigaluega uma Incisive o loʻo faʻaogaina i le 32-bit mode. Peitai, o le
-64bit filifiliga-laina filifiliga e faʻamalo le fesuiaiga o le siosiomaga.
O le fa'atulagaina lea files fesoasoani ia te oe e pulea au faʻamatalaga ma pulea le faʻaogaina o meafaigaluega faʻataʻitaʻi ma mea aoga:

Fa'afanua faletusi file (cds.lib) fa'amatalaina se igoa talafeagai mo le nofoaga o lau mamanu.
Faletusi ma fa'afeso'ota'i i igoa o fa'amaumauga fa'aletino.

Fuafuaga file (hdl.var) faʻamalamalamaina fesuiaiga e aʻafia ai le amio o meafaigaluega faʻataʻitaʻi ma mea aoga.

4.2 La'u mai le Faletusi Tu'ufa'atasi (Fai se Fesili)
La'u mai faletusi mo Cadence Xcelium mai Microsemi's webnofoaga.
4.3 Fausia le tusitusiga Xcelium file (Fai se Fesili)
A uma ona faia se kopi o le run.do files, fai laasaga nei e faʻatautaia ai lau faʻataʻitaʻiga e faʻaaoga ai le Xcelium script file.

Fausia se cds.lib file e fa'amatala ai po'o fea faletusi e mafai ona maua ma le mea o lo'o i ai.
O le file o lo'o i ai fa'amatalaga e fa'afanua igoa fa'atatau a le faletusi i a latou ala fa'asinotonu fa'aletino. Mo example, afai o loo e tamoe presynth simulation, le cds.lib file e mafai ona tusia e pei ona faʻaalia i le codeblock lea.
FAAMATALAGA presynth ./presynth
FAAMATALAGA COREAHBLITE_LIB ./COREAHBLITE_LIB
FA'AMANATU smartfusion2

Fausia se hdl.var file o se faatulagaga e filifili ai file o lo'o i ai fesuiaiga fetuutuunai, e fuafua ai pe fa'afefea ona fa'atulagaina lau siosiomaga mamanu. E aofia ai:
- Fuafuaga e faʻaaogaina e faʻamaonia ai le faletusi galuega lea e teu ai e le tagata faʻapipiʻi mea faʻapipiʻi ma isi faʻamaumauga.
- Mo Verilog, fesuiaiga (LIB_MAP, VIEW_MAP, GALUEGA) e faʻaaogaina e faʻamaonia ai faletusi ma views e su'esu'e pe a fo'ia e le fa'amatala fa'ata'ita'iga.
- Fuafuaga e mafai ai e oe ona faʻamatalaina le tuʻufaʻatasia, faʻamatalaga, ma le simulator filifiliga laina laina ma finauga.
I le tulaga o presynth simulation exampLe faʻaalia i luga, fai mai e 3 RTL files av, bv, ma testbench.v, lea e manaʻomia ona tuʻufaʻatasia i faletusi o le presynth, COREAHBLITE_LIB, ma le presynth. O le hdl.var file e mafai ona tusia e pei ona faʻaalia i le codeblock lea.
FAAMATALAGA GALUEGA presynth
FA'AMANATU POLOKALE_DIR files>
FAAMANATU LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/av => presynth )
FAAMANATU LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/bv => COREAHBLITE_LIB )
FAAMANATU LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/testbench.v => presynth )
FAAMANATU LIB_MAP ($LIB_MAP, + => presynth )
Tuufaatasia le mamanu files fa'aoga ncvlog filifiliga.
xmvlog +incdir+ –cdslib ./cds.lib –hdlvar ./hdl.var –logfile
ncvlog.log –update –linedebug av bv testbench.v
Fa'amatala le mamanu e fa'aaoga ai le ncelab. E fausia e le elaborator se fa'asologa o mamanu e fa'avae i luga o fa'amatalaga vave ma fa'asologa i totonu o le mamanu, fa'atūina le feso'ota'iga fa'ailo, ma fa'atatau muamua tau mo mea uma i totonu o le mamanu. O lo'o fa'aputuina le fa'asologa o fa'ata'ita'iga fa'ata'ita'iga, o le fa'atusa lea o lau fa'ata'ita'iga o lo'o fa'aogaina e le simulator e fa'atino ai le fa'ata'ita'iga.
Xcelium –Message –cdslib ./cds.lib –hdlvar ./hdl.var –logfile ncelab.log –errormax 15 –
avanoa +rwc –status worklib. : module
Fa'amatalaga I le taimi o le fa'ata'ita'iga Fa'ata'oto
I le tulaga o faʻataʻitaʻiga post-layout, muamua le SDF file e manaʻomia le tuʻufaʻatasia aʻo leʻi faʻamalamalamaina le faʻaaogaina o le ncsdfc poloaiga.
Xceliumfileigoa>.sdf –outputfileigoa>.sdf.X
I le taimi o faʻamatalaga faʻaaoga le SDF faʻapipiʻi faʻatasi ma -autosdf filifiliga e pei ona faʻaalia i le codeblock o loʻo mulimuli mai.
xmelab -autosdf –Message –cdslib ./cds.lib –hdlvar ./hdl.var –logfile ncelab.log –errormax
15 –access +rwc –status worklib. :module –sdf_cmd_file ./
sdf_cmd_file
Le sdf_cmd_file e tatau ona fa'aalia i le codeblock lea.
COMPILED_SDF_FILE = “ file>”

Fa'ata'ita'i fa'aaoga le Xcelium. A maeʻa le faʻamalamalamaina o se ata faʻataʻitaʻiga e faia lea e utaina e Xcelium mo faʻataʻitaʻiga. E mafai ona fa'atino i le fa'aputuga po'o le GUI.
xmsim –Message –batch/-gui –cdslib ./cds.lib –hdlvar ./hdl.var –logfile xmsim.log –
errormax 15 -status worklib. : module
Seti Xcelium Cadence
Taua: Uma o laasaga e tolu o loʻo i luga o le tuʻufaʻatasia, faʻamalamalamaga ma faʻataʻitaʻiga e mafai ona tuʻuina i totonu o se atigi tusitusiga file ma afua mai i le laina faʻatonu. Nai lo le faʻaaogaina o nei laasaga e tolu, e mafai ona faʻataʻitaʻiina le mamanu i le laasaga e tasi e faʻaaoga ai le ncverilog poʻo le xrun filifiliga e pei ona faʻaalia i le codeblock o loʻo mulimuli mai.
xmverilog +incdir+ -cdslib ./cds.lib –hdlvar ./hdl.var
files fa'aaogaina i le mamanu>
xrun +incdir+ -cdslib ./cds.lib –hdlvar ./hdl.var files
fa'aaogaina i le mamanu>

4.3.1 Fa'amatalaga Mata'utia (Fai se Fesili)
Fa'ata'ita'iga a le Testbench
O le faʻaaogaina o le faʻamatalaga o loʻo i lalo mo le faʻamaonia o le taimi o le uati i le suʻega suʻega na faia e le tagata faʻaoga poʻo le faʻaogaina o le suʻega suʻega na faia e Libero SoC e le galue ma Xcelium.
i taimi uma @(SYSCLK)
#(SYSCLK_PERIOD / 2.0) SYSCLK <= !SYSCLK;
Suia e pei ona taua i lalo e fai ai le fa'ata'ita'iga:
i taimi uma #(SYSCLK_PERIOD / 2.0) SYSCLK = ~SYSCLK;

Taua: O faletusi tu'ufa'atasia mo le Xcelium e fa'apitoa i luga ole laiga (fa'atusa, 64 bit faletusi e le fetaui ma le 32 bit platform ma le isi itu).
Postsynth ma Post-layout Simulations fa'aaoga MSS ma SERDES
Aʻo faʻataʻitaʻiina faʻataʻitaʻiga postsynth o mamanu o loʻo i ai poloka MSS, poʻo faʻataʻitaʻiga post-layout o mamanu e faʻaaoga ai SERDES, e le aoga le faʻataʻitaʻiga BFM pe afai e le o faʻamaonia le filifiliga -libmap i le taimi o faʻamatalaga. E mafua ona i le taimi o faʻamatalaga, MSS e faʻamalieina mai le faletusi galuega (ona o le faʻaogaina faʻaletonu ma le worklib o le postsynth / post-layout) lea e naʻo se Faʻatonuga Faʻatonu.
O le poloaiga ncelab e tatau ona tusia e pei ona faʻaalia i le poloka code nei e foia ai le poloka MSS mai le SmartFusion2 faletusi na tuʻufaʻatasia.
xmelab -libmap lib.map -libverbose -Savali -access +rwc cfg1
ma le lib.map file e tatau ona fa'apea:
config cfg1;
mamanu ;
Lisi fa'atonu smartfusion2 ;
endconfig
E tatau ona fo'ia so'o se sela i totonu o le faletusi SmartFusion2 a'o le'i va'ai i le faletusi galuega fa'atusa postsynth/post-layout.
O le filifiliga -libmap e mafai ona faʻaaogaina e ala i le faʻaogaina i le taimi o faʻamatalaga mo faʻataʻitaʻiga uma (presynth, postsynth ma post-layout). Ole mea lea e 'alofia ai fa'afitauli fa'ata'ita'iga e mafua ona ole fa'amalieina o fa'ata'ita'iga mai faletusi.
xmelab: *F, INTERR: TU'U'UGA I totonu
O lenei mea faigaluega tuusaunoaga ncelab o se faʻatagaga mo mamanu o loʻo i ai le FDDR i SmartFusion2 ma IGLOO2
i le taimi o faʻataʻitaʻiga postsynth ma post-layout e faʻaaoga ai le filifiliga -libmap.
Taua: Ua lipotia lenei mataupu i le vaega lagolago a Cadence (SAR 52113).

4.4 Sample Tcl ma atigi tusitusiga files (Fai se Fesili)
O mea nei files o le faatulagaga files mana'omia mo le fa'atulagaina o le mamanu ma le atigi tusitusiga file mo le faʻatinoina o poloaiga Xcelium.
Cds.lib
FA'AMANATU smartfusion2 /scratch/krydor/tmpspace/users/me/nc-vlog64/SmartFusion2
FAAMATALAGA COREAHBLITE_LIB ./COREAHBLITE_LIB
FAAMATALAGA presynth ./presynth
Hdl.var
FAAMATALAGA GALUEGA presynth
FA'AMANATU PROJECT_DIR /scratch/krydor/tmpspace/sqausers/me/3rd_party_simulators/Cadence/IGLOO2/
ENVM/M2GL050/envm_fic1_ser1_v/eNVM_fab_master
FAAMANATU LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/core/coreahblite_addrdec.v => COREAHBLITE_LIB )
FAAMANATU LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/core/coreahblite_defaultslavesm.v => COREAHBLITE_LIB )
FAAMANATU LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/core/coreahblite_masterstagev => COREAHBLITE_LIB )
FAAMANATU LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/core/coreahblite_slavearbiter.v => COREAHBLITE_LIB )
FAAMANATU LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/core/coreahblite_slavestagev => COREAHBLITE_LIB )
FAAMANATU LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/core/coreahblite_matrix2x16.v => COREAHBLITE_LIB )
FAAMANATU LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/core/coreahblite.v => COREAHBLITE_LIB )
FAAMANATU LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/component/work/SB/CCC_0/SB_CCC_0_FCCC.v =>
presynth)
FAAMANATU LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreConfigMaster/
2.0.101/rtl/vlog/core/coreconfigmaster.v => presynth )
FAAMANATU LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreConfigP/4.0.100/rtl/
vlog/core/coreconfigp.v => presynth )
FAAMANATU LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreResetP/5.0.103/rtl/
vlog/core/coreresetp_pcie_hotreset.v => presynth )
FAAMANATU LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreResetP/5.0.103/rtl/
vlog/core/coreresetp.v => presynth )
FAAMANATU LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/component/work/SB/FABOSC_0/SB_FABOSC_0_OSC.v =>
presynth)
FAAMANATU LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/component/work/SB_HPMS/SB_HPMS.v => presynth )
FAAMANATU LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/component/work/SB/SB.v => presynth )
FAAMANATU LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/vaega/galuega/SB_top/SERDES_IF_0/
SB_top_SERDES_IF_0_SERDES_IF.v => presynth )
FAAMANATU LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/component/work/SB_top/SB_top.v => presynth )
FAAMANATU LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/component/work/SB_top/testbench.v => presynth )
FAAMANATU LIB_MAP ($LIB_MAP, + => presynth )
Commands.csh
ncvlog +incdir+../../component/work/SB_top -cdslib ./cds.lib -hdlvar ./hdl.var -logfile
ncvlog.log -errormax 15 -update -linedebug
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite_addrdec.v
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/
coreahblite_defaultslavesm.v
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite_masterstagev
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite_slavearbiter.v
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite_slavestagev
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite_matrix2x16.v
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite.v
../../component/work/SB/CCC_0/SB_CCC_0_FCCC.v
../../component/Actel/DirectCore/CoreConfigMaster/2.0.101/rtl/vlog/core/coreconfigmaster.v
../../component/Actel/DirectCore/CoreConfigP/4.0.100/rtl/vlog/core/coreconfigp.v
../../component/Actel/DirectCore/CoreResetP/5.0.103/rtl/vlog/core/coreresetp_pcie_hotreset.v
../../component/Actel/DirectCore/CoreResetP/5.0.103/rtl/vlog/core/coreresetp.v
../../component/work/SB/FABOSC_0/SB_FABOSC_0_OSC.v ../../component/work/SB_HPMS/SB_HPMS.v
../../component/work/SB/SB.v ../../component/work/SB_top/SERDES_IF_0/
SB_TOP_SERDES_IF_0_SERDES_IF.v
../../component/work/SB_top/SB_top.v ../../component/work/SB_top/testbench.v
ncelab -Message -cdslib ./cds.lib -hdlvar ./hdl.var
-work presynth -logfile ncelab.log -errormax 15 -access +rwc -status presynth.testbench:module
ncsim -Message -batch -cdslib ./cds.lib -hdlvar ./
hdl.var -logfile ncsim.log -errormax 15 -status presynth.testbench:module

4.5 Otometi (Microchip Login)
O le mau lea file liliu ModelSim run.do files i le faatulagaga files manaʻomia e faʻatautaia faʻataʻitaʻiga e faʻaaoga ai le Xcelium.
Tusitala File Fa'aoga
perl cadence_parser.pl presynth_run.do postsynth_run.do
postlayout_run.do Microsemi_Family
Nofoaga_o_Cadence_Precompiled_libraries
Cadence_parser.pl
#!/usr/bin/perl -w

&questa_parser ($postlayout, $aiga, $lib_location);
sub questa_parser {
la'u $ModelSim_run_do = $_[0];
lo'u $actel_family = $_[1];
la'u $lib_location = $_[2];
lo'u $setete;
afai (-e “$ModelSim_run_do” )
{
tatala (INFILE,”$ModelSim_run_do”);
la'u @ModelSim_run_do =FILE>;
la'u $line;
afai ($ModelSim_run_do =~ m/(presynth)/)
{
`mkdir QUESTA_PRESYNTH`;
tatala (FAIFILE,”>QUESTA_PRESYNTH/presynth_questa.do”);
$setete = $1;
} elsif ($ModelSim_run_do =~ m/(postsynth)/)
{
`mkdir QUESTA_POSTSYNTH`;
tatala (FAIFILE,”>QUESTA_POSTSYNTH/postsynth_questa.do”);
$setete = $1;
} elsif ($ModelSim_run_do =~ m/(postlayout)/ )
{
`mkdir QUESTA_POSTLAYOUT`;
tatala (FAIFILE,”>QUESTA_POSTLAYOUT/postlayout_questa.do”);
$setete = $1;
} isi
{
lolomi “Sese Inputs na tuuina atu i le file\n”;
lolomi “#Usage: perl questa_parser.pl presynth_run.do postsynth_run.do postlayout_run.do
\”Libraries_location\”\n”;
}
i luma $line (@ModelSim_run_do)
{
#O Galuega Lautele
$line =~ s/..\/designer.*simulation\///g;
$line =~ s/$state/$state\_questa/g;
# lolomi i fafoFILE “$line \n”;
afai ($line =~ m/vmap\s+.*($actel_family)/)
{
lolomi i fafoFILE “vmap $actel_family \”$lib_location\”\n”;
} elsif ($line =~ m/vmap\s+(.*._LIB)/)
{
$line =~ s/..\/component/..\/..\/component/g;
lolomi i fafoFILE “$line \n”;
} elsif ($line =~ m/vsim/)
{
$line =~ s/vsim/vsim -novopt/g;
lolomi i fafoFILE “$line \n”;
} isi
{
lolomi i fafoFILE “$line \n”;
}
}
latalata(INFILE);
tapuni(FAIFILE);
} isi {
lolomi "$ModelSim_run_do e le o iai. Toe fai fa'ata'ita'iga \n”;
}
}

Siemens QuestaSim Setup/ModelSim Setup (Fai se Fesili)

O le tamoe.do files, faʻatupuina e le Libero SoC mo faʻataʻitaʻiga e faʻaaoga ai le ModelSim Microsemi Editions, e mafai ona faʻaogaina mo faʻataʻitaʻiga e faʻaaoga ai le QuestaSim / ModelSim SE / DE / PE ma se suiga e tasi. I le ModelSim ME/ModelSim Pro ME run.do file, e tatau ona suia le nofoaga o faletusi ua uma ona tuufaatasia.
Taua:
Ona o le le mafai, o le meafaigaluega faʻataʻitaʻiga e ese mai i le ModelSim Pro ME o loʻo faʻatinoina le faʻataʻitaʻiina o mamanu i le taimi o le faʻataʻitaʻiga lea e mafai ona aʻafia ai le vaʻaia i mea faʻataʻitaʻi faʻataʻitaʻiga e pei o mea mamanu ma mea faʻaosofia.
E masani ona fesoasoani lenei mea i le faʻaitiitia o le taimi faʻataʻitaʻiga mo faʻataʻitaʻiga lavelave, faʻaaogaina verbose, siaki suʻega a le tagata lava ia. Ae ui i lea, o faʻataʻitaʻiga faʻaletonu atonu e le talafeagai mo faʻataʻitaʻiga uma, aemaise lava i tulaga e te faʻamoemoe e suʻesuʻeina faʻataʻitaʻi faʻataʻitaʻiga iʻuga e faʻaaoga ai le faamalama o le galu.
Ina ia faʻatalanoaina faʻafitauli e mafua mai i lenei faʻataʻitaʻiga, e tatau ona e faʻaopoopoina tulafono talafeagai ma finauga faʻatatau i le taimi o faʻataʻitaʻiga e toe faʻafoʻi ai le vaʻaia i totonu o le mamanu. Mo faʻatonuga faʻapitoa meafaigaluega, vaʻai i faʻamaumauga o le simulator o loʻo faʻaaogaina.

5.1 Siosiomaga Fesuia'iga (Fai se Fesili)
O lo'o mulimuli mai suiga o le siosiomaga e mana'omia.

LM_LICENSE_FILE: e tatau ona aofia ai le ala i le laisene file.
MODEL_TECH: e tatau ona iloa le ala i le faletusi nofoaga o QuestaSim faʻapipiʻi.

PATH: e tatau ona fa'asino i le nofoaga fa'atino e fa'asino e MODEL_TECH.

5.2 Suia le run.do mo Mentor QuestaSim (Fai se Fesili)
O le tamoe.do files gaosia e Libero SoC mo faʻataʻitaʻiga e faʻaaoga ai le ModelSim Microsemi Editions e mafai ona faʻaogaina mo faʻataʻitaʻiga e faʻaaoga ai QuestaSim / ModelSim_SE ma se suiga e tasi.
Taua: Uma o mamanu o loʻo faʻaogaina e faʻaaoga ai QuestaSim e tatau ona aofia ai -novopt
filifiliga faʻatasi ma le vsim faʻatonuga i le run.do script files.
5.3 La'u mai le Faletusi Tu'ufa'atasi (Fai se Fesili)
La'u mai faletusi mo Mentor Graphics QuestaSim mai Microsemi's webnofoaga.

Seti VCS Synopsys (Fai se Fesili)

Ole tafega fautuaina e Microsemi e faʻalagolago ile Elaborate and Compile flow ile VCS. O lenei pepa e aofia ai se tusitusiga file lea e fa'aaoga ai le fa'asologa o le run.do files gaosia e Libero SoC ma fa'atupuina le seti files mana'omia mo VCS simulation. O le tusitusiga file fa'aaoga le run.do file e fai mea nei.

Fausia se faafanua faletusi file, lea e faia i le faʻaaogaina o le synopsys_sim.setup file o lo'o i totonu o le lisi lava lea o lo'o fa'agasolo ai le VCS simulation.
Fausia se tusitusiga atigi file e fa'alautele ma tu'ufa'atasia lau mamanu e fa'aaoga ai le VCS.

6.1 Siosiomaga Fesuia'iga (Fai se Fesili)
Seti suiga ole siosiomaga talafeagai mo VCS e fa'atatau i lau seti. O fesuiaiga o le siosiomaga e manaʻomia e tusa ai ma faʻamaumauga a le VCS o:

LM_LICENSE_FILE: e tatau ona aofia ai se faasinoala i le server laisene.
VCS_HOME: e tatau ona faasino i le nofoaga o le lisi o fale o le VCS faʻapipiʻi.
PATH: e tatau ona aofia ai se fa'asino ile talone i lalo ole lisi VCS_HOME.

6.2 La'u mai le Faletusi Tu'ufa'atasi (Fai se Fesili)
La'u mai faletusi mo Synopsys VCS mai Microsemi's webnofoaga.
6.3 VCS Simulation Script File (Fai se Fesili)
A maeʻa ona faʻatulagaina VCS ma fatuina le mamanu ma le eseʻese run.do files mai Libero SoC, e tatau ona e:

Fausia le faafanua o le faletusi file synopsys_sim.setup; lenei file o lo'o iai fa'ailoga i le nofoaga o faletusi uma e fa'aogaina e le mamanu.
Taua: Le file e le tatau ona suia le igoa ma e tatau ona tu i totonu o le lisi lava e tasi o loʻo faʻatautaia ai le faʻataʻitaʻiga. O se ex leaample mo sea file mo presynthesis simulation.
GALUEGA > EFAULT
SmartFusion2 :
presynth : ./presynth
FA'AALIGA : ./work
Fa'amatala le mamanu eseese files, e aofia ai le testbench, faʻaaoga le vlogan poloaiga i le VCS. O nei fa'atonuga e mafai ona aofia i totonu o se fa'amatalaga atigi file. O lo'o mulimuli mai se fa'atasiampLe o poloaiga e manaʻomia e faʻamalamalamaina ai se mamanu faʻamatalaina i le rtl.v faʻatasi ai ma lona faʻataʻitaʻiga faʻamatalaina i totonu
testbench.v.
vlogan +v2k -work presynth rtl.v
vlogan +v2k -work presynth testbench.v

Faʻapipiʻi le mamanu e faʻaaoga ai le VCS e faʻaaoga ai le poloaiga lenei.
vcs –sim_res=1fs presynth.testbench
Manatua: O le e tatau ona seti i le 1fs le fa'atulagaina ole taimi ole fa'ata'ita'iga mo fa'ata'ita'iga fa'atino sa'o.
A maeʻa loa ona tuʻufaʻatasia le mamanu, amata faʻataʻitaʻiga e faʻaaoga ai le poloaiga lenei.
./simv
Mo faʻataʻitaʻiga faʻamatalaga i tua, o le VCS poloaiga e tatau ona faʻaalia i le codeblock o loʻo mulimuli mai.
vcs postlayout.testbench –sim_res=1fs –sdf max: .
igoa>: file ala> –gui –l postlayout.log

6.4 Tapula'a/Tu'usaunoaga (Fai se Fesili)
O lo'o mulimuli mai tapula'a / tuusaunoaga o le Synopsys VCS setup.

VCS fa'ata'ita'iga e mafai ona fa'atino mo na'o galuega a Verilog a Libero SoC. O le VCS simulator o loʻo i ai le manaʻomia o le gagana VHDL e le o ausia e le Libero SoC faʻatupuina VHDL. files.
E tatau ona i ai sau faʻamatalaga $ maeʻa i le Verilog testbench e taofi ai le faʻataʻitaʻiga i soʻo se taimi e te manaʻo ai.
Taua: O afea faʻataʻitaʻiga o loʻo faʻatautaia i le GUI mode, taimi taʻavale e mafai ona faʻamaonia i le GUI.

6.5 Sample Tcl ma Shell Script Files (Fai se Fesili)
O le Perl o loʻo mulimuli mai e faʻaaogaina le gaosiga o le synopsys_sim.setup file fa'apea fo'i ma le tusitusiga atigi e fetaui files mana'omia e fa'alautele, fa'aopoopo, ma fa'atusa le mamanu.
Afai e fa'aogaina e le mamanu se MSS, kopi le test.vec file o loʻo i totonu o le pusa faʻataʻitaʻiga o le poloketi Libero SoC i totonu o le VCS simulation folder. O vaega nei o lo'o iai sample run.do files fa'atupuina e Libero SoC, e aofia ai le fa'afanua o le faletusi ma fa'amaumauga atigi files mana'omia mo VCS simulation.
6.5.1 mua'i fa'apipi'iina (Fai se Fesili)
Presynth_run.do
seti filemu ACTELLIBNAME SmartFusion2
seti filemu PROJECT_DIR "/sqa/users/me/VCS_Tests/Test_DFF"
afai {[file o lo'o iai presynth/_info]} {
echo "INFO: Simulation library presynth ua uma ona i ai"
} isi {
vlib presynth
}
vmap presynth presynth
vmap SmartFusion2 “/captures/lin/11_0_0_23_11prod/lib/ModelSim/precompiled/vlog/smartfusion2”
vlog -work presynth “${PROJECT_DIR}/component/work/SD1/SD1.v”
vlog “+incdir+${PROJECT_DIR}/stimulus” -work presynth “${PROJECT_DIR}/stimulus/SD1_TB1.v”
vsim -L SmartFusion2 -L presynth -t 1fs presynth.SD1_TB1
fa'aopoopo le galu /SD1_TB1/*
fa'aopoopo le log -r /*
tamoe 1000ns
presynth_main.csh
#!/bin/csh -f
seti PROJECT_DIR = "/sqa/users/Me/VCS_Tests/Test_DFF"
/cad_design/tools/vcs.dir/E-2011.03/bin/vlogan +v2k -work presynth “${PROJECT_DIR}/component/
galuega/SD1/SD1.v”
/cad_design/tools/vcs.dir/E-2011.03/bin/vlogan +v2k “+incdir+${PROJECT_DIR}/stimulus” -work
presynth “${PROJECT_DIR}/stimulus/SD1_TB1.v”
/cad_design/tools/vcs.dir/E-2011.03/bin/vcs -sim_res=1fs presynth.SD1_TB1 -l compile.log
./simv -l run.log
Synopsys_sim.setup
GALUEGA > TALA
SmartFusion2 : /VCS/SmartFusion2
presynth : ./presynth
FA'AALIGA : ./work

6.5.2 Fa'auma-fa'atasi (Fai se Fesili)
postsynth_run.do
seti filemu ACTELLIBNAME SmartFusion2
seti filemu PROJECT_DIR "/sqa/users/Me/VCS_Tests/Test_DFF"
afai {[file o lo'o iai postsynth/_info]} {
echo "INFO: Simulation library postsynth ua uma ona i ai"
} isi {
vlib postynth
}
vmap postsynth postsynth
vmap SmartFusion2 “//idm/captures/pc/11_0_1_12_g4x/Designer/lib/ModelSim/precompiled/vlog/
SmartFusion2”
vlog -work postsynth “${PROJECT_DIR}/synthesis/SD1.v”
vlog “+incdir+${PROJECT_DIR}/stimulus” -work postsynth “${PROJECT_DIR}/stimulus/SD1_TB1.v”
vsim -L SmartFusion2 -L postsynth -t 1fs postsynth.SD1_TB1
fa'aopoopo le galu /SD1_TB1/*
fa'aopoopo le log -r /*
tamoe 1000ns
fa'amaumauga SD1_TB1/*
ulufafo
Postsynth_main.csh
#!/bin/csh -f
seti PROJECT_DIR = "/sqa/users/Me/VCS_Tests/Test_DFF"
/cad_design/tools/vcs.dir/E-2011.03/bin/vlogan +v2k -work postsynth “${PROJECT_DIR}/synthesis/
SD1.v”
/cad_design/tools/vcs.dir/E-2011.03/bin/vlogan +v2k “+incdir+${PROJECT_DIR}/stimulus” -work
postsynth “${PROJECT_DIR}/stimulus/SD1_TB1.v”
/cad_design/tools/vcs.dir/E-2011.03/bin/vcs -sim_res=1fs postsynth.SD1_TB1 -l compile.log
./simv -l run.log
Synopsys_sim.setup
GALUEGA > TALA
SmartFusion2 : /VCS/SmartFusion2
postsynth : ./postsynth
FA'AALIGA : ./work
6.5.3 Fa'ata'atia uma (Fai se Fesili)
postlayout_run.do
seti filemu ACTELLIBNAME SmartFusion2
seti filemu PROJECT_DIR “E:/ModelSim_Work/Test_DFF”
afai {[file e iai ../designer/SD1/simulation/postlayout/_info]} {
si'uleo "INFO: Fa'ata'ita'iga faletusi ../designer/SD1/simulation/postlayout ua i ai"
} isi {
vlib ../designer/SD1/simulation/postlayout
}
vmap postlayout ../designer/SD1/simulation/postlayout
vmap SmartFusion2 “//idm/captures/pc/11_0_1_12_g4x/Designer/lib/ModelSim/precompiled/vlog/
SmartFusion2”
vlog -fa'atulagaina galuega fa'ata'atia “${PROJECT_DIR}/designer/SD1/SD1_ba.v”
vlog “+incdir+${PROJECT_DIR}/stimulus” -fa'atonu galuega fa'asolo "${PROJECT_DIR}/stimulus/SD1_TB1.v"
vsim -L SmartFusion2 -L postlayout -t 1fs -sdfmax /SD1_0=${PROJECT_DIR}/designer/SD1/
SD1_ba.sdf postlayout.SD1_TB1
fa'aopoopo le galu /SD1_TB1/*
fa'aopoopo le log -r /*
tamoe 1000ns
Postlayout_main.csh
#!/bin/csh -f
seti PROJECT_DIR = "/VCS_Tests/Test_DFF"
/cad_design/tools/vcs.dir/E-2011.03/bin/vlogan +v2k -faigaluega postlayout “${PROJECT_DIR}/
designer/SD1/SD1_ba.v”
/cad_design/tools/vcs.dir/E-2011.03/bin/vlogan +v2k “+incdir+${PROJECT_DIR}/stimulus” -work
fa'asologa o le meli “${PROJECT_DIR}/stimulus/SD1_TB1.v”
/cad_design/tools/vcs.dir/E-2011.03/bin/vcs -sim_res=1fs postlayout.SD1_TB1 -sdf

max:SD1_TB1.SD1_0:${PROJECT_DIR}/designer/SD1/SD1_ba.sdf -l compile.log
./simv -l run.log
Synopsys_sim.setup
GALUEGA > TALA
SmartFusion2 : /VCS/SmartFusion2
Postlayout : ./postlayout
FA'AALIGA : ./workVCS
6.6 Otometi (Fai se Fesili)
E mafai ona otometi le tafe e faʻaaoga ai le tusitusiga Perl o loʻo mulimuli mai file e faaliliu le ModelSim run.do files i totonu o le VCS e fetaui ma le atigi tusitusiga files, faia fa'atonuga talafeagai i totonu o le Libero SoC simulation directory, ona fa'atautaia lea o fa'ata'ita'iga.
Fa'asolo le tala file fa'aoga le syntax lea.
perl vcs_parse.pl presynth_run.do postsynth_run.do postlayout_run.do
Vcs_parse_pl
#!/usr/bin/perl -w
################################################## ############################
#
#Fa'aoga: perl vcs_parse.pl presynth_run.do postsynth_run.do postlayout_run.do
#
################################################## ##############################
la'u ($presynth, $postynth, $postlayout) = @ARGV;
afai (faiga ("mkdir VCS_Presynth")) {lomi "mkdir le manuia:\n";}
if(system(“mkdir VCS_Postsynth”)) {lomi “mkdir failed:\n”;}
afai (faiga ("mkdir VCS_Postlayout")) {lomi "mkdir le manuia:\n";}
chdir(VCS_Presynth);
`cp ../$ARGV[0] .` ;
&parse_do($presynth,”presynth”);
chdir (“../”);
chdir(VCS_Postsynth);
`cp ../$ARGV[1] .` ;
&parse_do($postsynth,”postsynth”);
chdir (“../”);
chdir(VCS_Postlayout);
`cp ../$ARGV[2] .` ;
&parse_do($postlayout,”postlayout”);
chdir (“../”);
sub parse_do {
la'u $vlog = “/cad_design/tools/vcs.dir/E-2011.03/bin/vlogan +v2k” ;
la'u %LIB = ();
la'u $file = $_[0] ;
la'u $setete = $_[1];
tatala(INFILE,”$file”) || oti “E le mafai ona tatala File Atonu o le:$!”;
pe afai ($state eq “presynth” )
{
tatala(OUT1,”>presynth_main.csh”) || oti “E le mafai ona faia Poloaiga File Atonu o le:$!”;
}
elsif ($state eq “postsynth” )
{
tatala(OUT1,”>postsynth_main.csh”) || oti “E le mafai ona faia Poloaiga File Atonu o le:$!”;
}
elsif ($state eq “postlayout” )
{
tatala(OUT1,”>postlayout_main.csh”) || oti “E le mafai ona faia Poloaiga File Atonu o le:$!”;
}
isi
{
lolomi “Ua misi le State Simulation \n” ;
}
tatala(OUT2,”>synopsys_sim.setup”) || oti “E le mafai ona faia Poloaiga File Atonu o le:$!”;
# .csh file
lolomi OUT1 “#!/bin/csh -f\n\n\n” ;
#SETI FILE
lolomi OUT2 “GALUEGA > LE TALA\n” ;
lolomi OUT2 “SmartFusion2 : /sqa/users/Aditya/VCS/SmartFusion2\n” ;
a o ($line =FILE>)
{

Synopsys VCS Setup

afai ($line =~ m/seti filemu PROJECT_DIR\s+\”(.*?)\”/)
{
lolomi OUT1 “set PROJECT_DIR = \”$1\”\n\n\n” ;
}
elsif ($line =~ m/vlog.*\.v\”/ )
{
afai ($ laina =~ m/\s+(\w*?)\_LIB/)
{
#print “\$1 =$1 \n” ;
$temp = “$1″.”_LIB”;
#print “Temp = $temp \n” ;
$LIB{$temp}++;
}
chomp($line);
$line =~ s/^vlog/$vlog/ ;
$line =~ s/ //g;
lolomi OUT1 “$line\n”;
}
elsif ( ($line =~ m/vsim.*presynth\.(.*)/) || ($line =~ m/vsim.*postsynth\.(.*)/) || ($line
=~ m/vsim.*postlayout\.(.*)/) )
{
$tb = $1 ;
$tb =~ s/ //g;
chomp($tb);
#print “Igoa TB : $tb \n”;
afai ($line =~ m/sdf(.*)\.sdf/)
{
chomp($line);
$line = $1 ;
#print “LINE : $line \n” ;
afai ($ laina =~ m/max/)
{
$line =~ s/max \/// ;
$line =~ s/=/:/;
lolomi OUT1 “\n\n/cad_design/tools/vcs.dir/E-2011.03/bin/vcs -sim_res=1fs postlayout.$tb -sdf
max:$tb.$line.sdf -l compile.log\n” ;
}
elsif ($line =~ m/min/)
{
$line =~ s/min \/// ;
$line =~ s/=/:/;
lolomi OUT1 “\n\n/cad_design/tools/vcs.dir/E-2011.03/bin/vcs -sim_res=1fs postlayout.$tb -sdf
min:$tb.$line.sdf -l compile.log\n” ;
}
elsif ($line =~ m/typ/)
{
$line =~ s/typ \/// ;
$line =~ s/=/:/;
lolomi OUT1 “\n\n/cad_design/tools/vcs.dir/E-2011.03/bin/vcs -sim_res=1fs postlayout.$tb -sdf
typ:$tb.$line.sdf -l compile.log\n” ;
}
#-sdfmax /M3_FIC32_0=${PROJECT_DIR}/designer/M3_FIC32/M3_FIC32_ba.sdf — ModelSim SDF format
#$sdf = “-sdf max:testbench.M3_FIC32_0:${PROJECT_DIR}/designer/M3_FIC32/M3_FIC32_ba.sdf”; -VCS
SDF faatulagaga
}
}
}
lolomi
OUT1 “\n\n”
;
if
($state eq “presynth”
)
{
lolomi
OUT2 “presynth
: ./presynth\n”
;
lolomi
OUT1 “/cad_design/tools/vcs.dir/E-2011.03/bin/vcs
-sim_res=1fs presynth.$tb -l
compile.log\n”
;
}
elsif
($state eq “postsynth”
)
{
lolomi
OUT2 “postsynth
: ./postsynth\n”
;
lolomi
OUT1 “/cad_design/tools/vcs.dir/E-2011.03/bin/vcs
-sim_res=1fs postsynth.$tb -l
compile.log\n”
;
}
elsif
($ state eq “postlayout”
)
{
lolomi OUT2 “postlayout : ./postlayout\n” ;
}
isi
{
lolomi “Ua misi le State Simulation \n” ;
}
mo $i ( ki %LIB)
{
#print “Ki : $i Taua : $LIB{$i} \n” ;
lolomi OUT2 “$i : ./$i\n” ;
}
lolomi OUT1 “\n\n” ;
lolomi OUT1 “./simv -l run.log\n” ;
lolomi OUT2 “DEFAULT : ./work\n” ;
tapunia INFILE;
tapuni OUT1;
tapuni OUT2;
}

Toe Iloilo Tala'aga (Microchip Login

O le tala fa'asolopito o lo'o fa'amatalaina suiga na fa'atinoina i le pepa. O suiga
o lo'o lisiina e ala i toe iloiloga, amata i le lomiga aupito lata mai.

Toe Iloiloga	Aso	Fa'amatalaga
A	12/2023	O suiga nei ua faia i lenei toe iloiloga: • Fa'aliliuina pepa i le mamanu Microchip. Toe Iloiloga Muamua. • Faʻafouina vaega 5. Siemens QuestaSim Setup / ModelSim Setup e aofia ai se faʻamatalaga fou e faʻamatalaina ai le aʻafiaga o le vaʻaia i le taimi o faʻataʻitaʻiga ma le faʻaleleia.

Microchip FPGA Lagolago
Microchip FPGA products group backs its products with various support services, including Customer Service, Customer Technical Support Center, a webnofoaga, ma ofisa faatau i le lalolagi atoa.
E fautuaina tagata fa'atau e asiasi i Microchip i luga ole laiga a'o le'i fa'afeso'ota'i le lagolago ona e foliga mai ua uma ona tali a latou fesili.
Fa'afeso'ota'i le Nofoaga Autu Lagolago Fa'apitoa e ala ile webnofoaga i www.microchip.com/support. Ta'u le numera o le Vaega o Meafaigaluega FPGA, filifili le vaega o mataupu talafeagai, ma fa'apipi'i le mamanu files a'o faia se mataupu lagolago fa'apitoa.
Fa'afeso'ota'i Auaunaga Fa'atau mo le lagolago o oloa e le fa'apitoa, e pei o le tau o oloa, fa'aleleia o oloa, fa'afouga fa'amatalaga, tulaga oka, ma le fa'atagaina.

Mai Amerika i Matu, valaau 800.262.1060
Mai le lalolagi atoa, valaau 650.318.4460

Fax, mai so'o se mea i le lalolagi, 650.318.8044

Microchip Fa'amatalaga
Le Microchip Webnofoaga
Microchip e maua le lagolago i luga ole laiga e ala i la matou webnofoaga i www.microchip.com/. Lenei web'upega tafa'ilagi e fa'aoga e fai ai files ma fa'amatalaga faigofie ona maua e tagata fa'atau. O nisi o mea e maua e aofia ai:

Lagolago oloa - Pepa faʻamatalaga ma mea sese, faʻamatalaga talosaga ma samppolokalame, punaoa mamanu, ta'iala a le tagata fa'aoga ma pepa lagolago mo meafaigaluega, fa'asalalauga fou fa'akomepiuta ma polokalama fa'amaumauga

Lagolago Faʻatekinisi Lautele - Fesili e masani ona fesiligia (FAQs), talosaga lagolago faʻapitoa, faʻasalalauga i luga ole laiga, Microchip design partner programme list
Pisinisi o Microchip - Faʻatau oloa ma taʻiala faʻatonu, faʻasalalauga lata mai a Microchip, lisi o semina ma mea na tutupu, lisi o ofisa faʻatau Microchip, tufatufaina ma sui fale gaosimea

Au'aunaga Fa'asilasilaga Suiga o Mea
O le auaunaga fa'asilasilaga suiga o oloa a Microchip e fesoasoani e fa'amautu ai tagata fa'atau i oloa Microchip. O le a maua e le au fai saofaga le faʻamatalaga imeli i soʻo se taimi e iai suiga, faʻafouga, toe teuteuga poʻo mea sese e fesoʻotaʻi ma se aiga o oloa faʻapitoa poʻo meafaigaluega atinaʻe e fiafia i ai.
Ina ia lesitala, alu i www.microchip.com/pcn ma mulimuli i faatonuga resitala.
Lagolago Tagata Fa'atau
O tagata fa'aoga o oloa Microchip e mafai ona maua fesoasoani e ala i le tele o auala:

Fa'asoa po'o le Sui
Ofisa Fa'atauga Fa'alotoifale
Embedded Solutions Engineer (ESE)

Lagolago Fa'atekinisi

E tatau i tagata fa'atau ona fa'afeso'ota'i le latou tufatufaina, sui po'o le ESE mo le lagolago. O loʻo avanoa foʻi ofisa faʻatau i le lotoifale e fesoasoani i tagata faʻatau. O lo'o iai se lisi o ofisa fa'atau ma nofoaga i totonu o lenei pepa.
E maua le lagolago fa'apitoa e ala ile webnofoaga i: www.microchip.com/support
Fa'ailoga Puipuiga o Fa'ailoga Fa'atonu a Microchip
Manatua faʻamatalaga o loʻo i lalo o le faʻaogaina o le puipuiga o tulafono i luga o oloa Microchip:

O oloa Microchip e fetaui ma faʻamatalaga o loʻo i totonu o la latou Pepa Faʻamatalaga Microchip.

E talitonu Microchip o lona aiga o oloa e saogalemu pe a faʻaaogaina i le auala faʻamoemoeina, i totonu o faʻamatalaga faʻaogaina, ma i lalo o tulaga masani.
Microchip fa'atauaina ma puipuia fa'amalosi ana aia tatau tau meatotino. O taumafaiga e soli le tulafono o le puipuiga o le oloa Microchip e matua fa'asaina ma e ono solia ai le Digital Millennium Copyright Act.
E le mafai e le Microchip poʻo se isi mea gaosi semiconductor ona faʻamaonia le saogalemu o lana tulafono. O le puipuiga o tulafono laiti e le o lona uiga o loʻo matou faʻamaonia le oloa e "le mafai ona motusia".
O le puipuiga o tulafono laiti o lo'o fa'asolosolo pea. Microchip ua tuuto atu i le faʻaauauina pea o le faʻaleleia atili o uiga puipuia o tulafono a tatou oloa.

Faasilasilaga Faaletulafono
O lenei lomiga ma faʻamatalaga o loʻo i totonu e mafai ona faʻaaogaina naʻo oloa Microchip, e aofia ai le mamanu, suʻega, ma tuʻufaʻatasia oloa Microchip ma lau talosaga. O le fa'aogaina o nei fa'amatalaga i so'o se isi lava faiga e solia ai nei aiaiga. O fa'amatalaga e uiga i le fa'aogaina o masini e tu'uina atu mo na'o lou fa'amalieina ma e ono suia i fa'afouga. O lau matafaioi le faʻamautinoa o lau talosaga e fetaui ma au faʻamatalaga. Fa'afeso'ota'i lou ofisa fa'atau Microchip fa'apitonu'u mo se lagolago fa'aopoopo pe, maua se lagolago fa'aopoopo ile www.microchip.com/en-us/support/design-help/client-support-services.
O LENEI FAʻAMATALAGA E TUUINA E MICROCHIP "AS IS". E LEAI FAIA e le MICROCHIP ni sui po'o se fa'amaoniga o so'o se ituaiga pe fa'aalia pe fa'aali, tusia pe tugutu, tulāfono po'o se isi mea, e feso'ota'i ma fa'amatalaga e aofia ai ae le tapula'a i so'o se fa'amaoniaga fa'amaonia, fa'amaonia, ma le fa'amaoniaina. FAAMOEMOEGA, POO WARRANTY E FAI I ONA TULAGA, TULAGA, POO LE FAIGALUEGA.
E LEAI SE MEA E TATAU AI MICROCHIP MO SO'O SE FA'AMATALAGA, FA'AMATALAGA, FA'ASA'OGA, FA'AMATALAGA, PO'O LE FA'A'ALI'AGA MA'U'U, FA'AFIA, TAU, PO'O LE TU'U'UINA O SO'O SE I'UGA SO'O SE FA'AIGA I LE FA'AMATALAGA POO LONA FA'A'OGA, PE'O LE MEA NA FA'AUPUNA'I, E tusa lava pe fa'aletonu. FA'ATONU POO LE FA'AFIA E FA'AVAEINA. I LE AGATOGA FA'AALIGA E LE TULAFONO, O LE UMA AOFA'IGA A MICROCHIP I TOTOGI UMA I SO'O SE AUALA E FA'AIGA I LE FA'AMATALAGA POO LONA FA'A'OGA E LE'A LOLOA I LE TOTOGI O TOTOGI, AFAI E IAI, NA E TOTOGI SA'O I LE MICROCHIP MO LE FA'AMATALAGA.
O le fa'aogaina o masini Microchip i le tausiga o le ola ma/po'o le saogalemu o lo'o i le tulaga lamatia o le tagata fa'atau, ma e malie le tagata fa'atau e puipuia, fa'aleaga ma taofia Microchip le afaina mai so'o se mea leaga, tagi, suti, po'o tupe alu e mafua mai i lea fa'aoga. E leai ni laisene e tu'uina atu, fa'aalia po'o se isi mea, i lalo o so'o se Microchip aia tatau tau le atamai se'i vagana ua ta'ua.
Fa'ailoga Fa'ailoga
Le igoa Microchip ma le logo, le Microchip logo, Adaptec, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, CryptoMemory, CryptoRF, dsPIC, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXStylus, maXTouch MediaLB, megaAVR, Microsemi, Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, PolarFire, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetricom , SyncServer, Tachyon, TimeSource, tinyAVR, UNI/O, Vectron, ma XMEGA o fa'ailoga fa'amaufa'ailoga a Microchip Technology Incorporated i Amerika ma isi atunu'u.
AgileSwitch, APT, ClockWorks, The Embedded Control Solutions Company, EtherSynch, Flashtec, Hyper Speed Control, HyperLight Load, Libero, motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet- Wire, SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub, TimePictra, TimeProvider, TrueTime, ma ZL o faʻailoga resitalaina o Microchip Technology Incorporated i Amerika.
Taofi Fa'aigoa Fa'atasi, AKS, Analog-mo-le-Digital Age, So'o se Capacitor, So'o se In, So'oOut, Suiga Fa'aopoopo, BlueSky, BodyCom, Clockstudio, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net Matching, Dynamic Average Matching , DAM, ECAN, Espresso T1S, EtherGREEN, GridTime, IdealBridge, In-Circuit Serial Programming, ICSP, INICnet, Intelligent Parallel, IntelliMOS, Inter-Chip Connectivity, JitterBlocker, Knob-on-Display, KoD, maxCrypto, maxView, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB Faʻamaonia logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net,
PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, RTAX, RTG4, SAMICE, Serial Quad I/O, simpleMAP, SimpliPHY, SmartBuffer, SmartHLS, SMART-IS, storClad, SQI, SuperSwitcher,
SuperSwitcher II, Switchtec, SynchroPHY, Aofa'i Tumau, Taimi Fa'alagolago, TSHARC, USBCheck, VariSense, VectorBlox, VeriPHY, ViewSpan, WiperLock, XpressConnect, ma ZENA o faʻailoga faʻailoga a Microchip Technology Incorporated
i Amerika ma isi atunuu.
SQTP ose fa'ailoga tautua a Microchip Technology Incorporated i Amerika
O le logo Adaptec, Frequency on Demand, Silicon Storage Technology, ma Symmcom o fa'ailoga fa'amaufa'ailoga a Microchip Technology Inc. i isi atunu'u.
GestIC ose fa'ailoga fa'amaufa'ailoga a Microchip Technology Germany II GmbH & Co. KG, ose lala o Microchip Technology Inc., i isi atunu'u.
O isi fa'ailoga tau fefa'ataua'iga uma o lo'o ta'ua ii o meatotino a latou kamupani.
© 2023, Microchip Technology Incorporated ma ona lala. Ua Taofia Aia Tatau Uma.
ISBN: 978-1-6683-3694-6
Faiga Fa'atonuga
Mo faʻamatalaga e uiga i Microchip's Quality Management Systems, faʻamolemole asiasi www.microchip.com/quality.

AMERIKA	ASIA/ PASIFIK	ASIA/ PASIFIK	Europa
Ofisa Autasi 2355 Sisifo Chandler Blvd. Chandler, AZ 85224-6199 Telefoni: 480-792-7200 Fax: 480-792-7277 Lagolago Fa'atekinisi: www.microchip.com/support Web tuatusi: www.microchip.com Atlanta Duluth, GA Telefoni: 678-957-9614 Fax: 678-957-1455 Austin, TX Telefoni: 512-257-3370 Boston Westborough, MA Telefoni: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Telefoni: 630-285-0071 Fax: 630-285-0075 Dallas Addison, TX Telefoni: 972-818-7423 Fax: 972-818-2924 Detroit Novi, MI Telefoni: 248-848-4000 Houston, TX Telefoni: 281-894-5983 Indianapolis Noblesville, IN Telefoni: 317-773-8323 Fax: 317-773-5453 Telefoni: 317-536-2380 Los Angeles Misiona Viejo, CA Telefoni: 949-462-9523 Fax: 949-462-9608 Telefoni: 951-273-7800 Raleigh, NC Telefoni: 919-844-7510 Niu Ioka, NY Telefoni: 631-435-6000 San Jose, CA Telefoni: 408-735-9110 Telefoni: 408-436-4270 Kanata - Toronto Telefoni: 905-695-1980 Fax: 905-695-2078	Ausetalia – Sini Telefoni: 61-2-9868-6733 Saina - Beijing Telefoni: 86-10-8569-7000 Saina – Chengdu Telefoni: 86-28-8665-5511 Saina – Chongqing Telefoni: 86-23-8980-9588 Saina – Dongguan Telefoni: 86-769-8702-9880 Saina – Guangzhou Telefoni: 86-20-8755-8029 Saina – Hangzhou Telefoni: 86-571-8792-8115 Saina - Hong Kong SAR Telefoni: 852-2943-5100 Saina – Nanjing Telefoni: 86-25-8473-2460 Saina – Qingdao Telefoni: 86-532-8502-7355 Saina – Shanghai Telefoni: 86-21-3326-8000 Saina – Shenyang Telefoni: 86-24-2334-2829 Saina – Shenzhen Telefoni: 86-755-8864-2200 Saina – Suzhou Telefoni: 86-186-6233-1526 Saina - Wuhan Telefoni: 86-27-5980-5300 Saina – Xian Telefoni: 86-29-8833-7252 Saina – Xiamen Telefoni: 86-592-2388138 Saina – Zhuhai Telefoni: 86-756-3210040	Initia – Bangalore Telefoni: 91-80-3090-4444 Initia – New Delhi Telefoni: 91-11-4160-8631 Initia - Pune Telefoni: 91-20-4121-0141 Iapani - Osaka Telefoni: 81-6-6152-7160 Iapani - Tokyo Telefoni: 81-3-6880-3770 Korea – Daegu Telefoni: 82-53-744-4301 Korea – Seoul Telefoni: 82-2-554-7200 Meleisia – Kuala Lumpur Telefoni: 60-3-7651-7906 Meleisia – Penang Telefoni: 60-4-227-8870 Filipaina – Manila Telefoni: 63-2-634-9065 Singapore Telefoni: 65-6334-8870 Taiuani – Hsin Chu Telefoni: 886-3-577-8366 Taiuani – Kaohsiung Telefoni: 886-7-213-7830 Taiuani – Taipei Telefoni: 886-2-2508-8600 Taialani – Bangkok Telefoni: 66-2-694-1351 Vietnam – Ho Chi Minh Telefoni: 84-28-5448-2100	Ausetalia – Uelese Telefoni: 43-7242-2244-39 Fax: 43-7242-2244-393 Tenimaka – Copenhagen Telefoni: 45-4485-5910 Fax: 45-4485-2829 Finelani – Espoo Telefoni: 358-9-4520-820 Farani – Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Siamani – Garching Telefoni: 49-8931-9700 Siamani – Haan Telefoni: 49-2129-3766400 Siamani – Heilbronn Telefoni: 49-7131-72400 Siamani – Karlsruhe Telefoni: 49-721-625370 Siamani – Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Siamani – Rosenheim Telefoni: 49-8031-354-560 Isaraelu – Ra’anana Telefoni: 972-9-744-7705 Italia – Milan Telefoni: 39-0331-742611 Fax: 39-0331-466781 Italia – Padova Telefoni: 39-049-7625286 Netherlands – Drunen Telefoni: 31-416-690399 Fax: 31-416-690340 Nouei – Trondheim Telefoni: 47-72884388 Polani – Warsaw Telefoni: 48-22-3325737 Romania – Bucharest Tel: 40-21-407-87-50 Sepania - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 Suetena – Gothenberg Tel: 46-31-704-60-40 Suetena - Stockholm Telefoni: 46-8-5090-4654 Peretania - Wokingham Telefoni: 44-118-921-5800 Fax: 44-118-921-5820

Pepa / Punaoa

MICROCHIP Libero SoC Simulation Library Software [pdf] Taiala mo Tagata Fa'aoga
DS50003627A, Libero SoC Simulation Library Software, SoC Simulation Library Software, Simulation Library Software, Library Software, Software

Fa'asinomaga

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