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Awọn akoonu tọju
1 Ọrọ Iṣaaju
2 Libero SoC Integration
3 Eto Aldec fun Active-HDL ati Riviera-Pro (Beere ibeere kan)
4 Eto Idaniloju Cadence (Beere Ibeere kan)
5 Eto Cadence Xcelium (Wọle Microchip)
6 Siemens QuestaSim Setup/AwoṣeSim Iṣeto (Beere ibeere kan)
7 Iṣeto VCS Synopsys (Beere Ibeere kan)
8 Itan Atunyẹwo (Wọle Microchip
9 Awọn iwe aṣẹ / Awọn orisun
9.1 Awọn itọkasi
10 jẹmọ Posts

Ọrọ Iṣaaju

(Beere ibeere kan)

Idi ti iwe yii ni lati ṣe apejuwe ilana lati ṣeto agbegbe kikopa nipa lilo iṣẹ akanṣe Libero SoC bi titẹ sii. Iwe yi ni ibamu si awọn ile-ikawe ti a ṣajọ tẹlẹ ti a pese fun lilo pẹlu Libero SoC v11.9 ati awọn idasilẹ sọfitiwia tuntun. Awọn ile-ikawe ti a pese ni akopọ fun Verilog. Awọn olumulo VHDL nilo iwe-aṣẹ gbigba kikopa ipo ipopọ.
Awọn ile-ikawe simulation ti a ṣe akojọpọ wa fun awọn irinṣẹ wọnyi:

  • Aldec Iroyin-HDL
  • Aldec Riviera-PRO
  • Cadence Incisive Idawọlẹ ati Xcelium
  • Siemens QuestaSim
  • Synopsys VCS

Lati beere ile-ikawe kan fun adaṣe oriṣiriṣi, kan si Microchip Technical Support.

Libero SoC Integration

(Beere ibeere kan)

Libero SoC ṣe atilẹyin kikopa nipa lilo ModelSim ME nipa ṣiṣẹda run.do file. Eyi file ModelSim ME/ModelSim Pro ME lo lati ṣeto ati ṣiṣẹ kikopa naa. Lati lo awọn irinṣẹ kikopa miiran, o le ṣe ina ModelSim ME/ModelSim Pro ME run.do ati yi iwe afọwọkọ Tcl pada file lati lo awọn aṣẹ ti o ni ibamu pẹlu simulator rẹ.
1.1 Libero SoC Tcl File Iran (Beere ibeere kan)
Lẹhin ṣiṣẹda ati ipilẹṣẹ apẹrẹ ni Libero SoC, bẹrẹ ModelSim ME/ModelSim Pro ME kikopa labẹ gbogbo awọn ipele apẹrẹ (presynth, postsynth, ati post-layout). Igbesẹ yii ṣe ipilẹṣẹ run.do file fun ModelSim ME / ModelSim Pro ME fun kọọkan oniru alakoso.
MICROCHIP Libero SoC Simulation Library Software - aami Pataki: Lẹhin ti o bẹrẹ ṣiṣe kikopa kọọkan, tunrukọ run.do ti ipilẹṣẹ laifọwọyi file labẹ itọsọna kikopa lati ṣe idiwọ Libero SoC lati kọkọ pe file. Fun example, awọn files le jẹ lorukọmii si presynth_run.do, postsynth_run.do ati postlayout_run.do.

Eto Aldec fun Active-HDL ati Riviera-Pro (Beere ibeere kan)

Ṣiṣe.ṣe file Lo nipasẹ ModelSim ME/ModelSim Pro ME le ṣe atunṣe ati lo fun kikopa nipa lilo awọn simulators Aldec.
2.1 Ayipada Ayika (Beere ibeere kan)
Ṣeto oniyipada ayika rẹ si iwe-aṣẹ rẹ file ibi:
LM_LICENSE_FILE: gbọdọ ni itọka si olupin iwe-aṣẹ.
2.2 Ṣe igbasilẹ Ile-ikawe Iṣakojọ (Beere ibeere kan)
Ṣe igbasilẹ awọn ile-ikawe fun Aldec Active-HDL ati Aldec Riviera-PRO lati Microchip webojula.
2.3 iyipada run.do fun kikopa Aldec (Beere ibeere kan)
Ṣiṣe.ṣe files ti ipilẹṣẹ nipasẹ Libero SoC fun awọn iṣeṣiro nipa lilo Active-HDL ati ọpa Riviera-Pro le ṣee lo fun awọn iṣeṣiro nipa lilo Active-HDL ati Riviera-Pro pẹlu iyipada kan. Tabili ti o tẹle ṣe atokọ awọn aṣẹ deede Aldec lati yipada ni ModelSim run.do file.
Table 2-1. Awọn aṣẹ deede Aldec

AwoṣeSim Nṣiṣẹ-HDL
vlog àgọ́
vcom acom
vlib alib
vsim asim
vmap maapu

Atẹle jẹ biample run.do jẹmọ si Aldec simulators.

  1. Ṣeto ipo ti itọsọna iṣẹ lọwọlọwọ.
    ṣeto dsn
  2. Ṣeto orukọ ile-ikawe ti n ṣiṣẹ, ṣe maapu ipo rẹ, lẹhinna ya aworan ipo ti idile Microchip FPGA
    awọn ile-ikawe ti a ti ṣajọ tẹlẹ (fun example, SmartFusion2) lori eyiti o nṣiṣẹ apẹrẹ rẹ.
    alib presynth
    amap presynth presynth
    maapu SmartFusion2
  3. Ṣe akopọ gbogbo HDL pataki files lo ninu awọn oniru pẹlu awọn ti a beere ìkàwé.
    alog –work presynth temp.v (fun Verilog)
    alog –work presynth testbench.v
    acom – iṣẹ presynth temp.vhd (fun Vhdl)
    acom – iṣẹ presynth testbench.vhd
  4. Ṣe afiwe apẹrẹ naa.
    asim –L SmartFusion2 –L presynth –t 1ps presynth.testbench
    ṣiṣe 10us

2.4 Awọn ọran ti a mọ (Beere ibeere kan)
Abala yii ṣe atokọ awọn ọran ti a mọ ati awọn idiwọn.

  • Awọn ile-ikawe ti a ṣe akojọpọ nipa lilo Riviera-PRO jẹ ipilẹ kan pato (ie awọn ile-ikawe 64-bit ko le ṣiṣẹ lori pẹpẹ 32-bit ati ni idakeji).
  • Fun awọn apẹrẹ ti o ni awọn SERDES/MDDR/FDDR, lo aṣayan atẹle ni run.do rẹ files lakoko ṣiṣe awọn iṣeṣiro lẹhin ti o ṣajọ awọn aṣa wọn:
    – Akitiyan-HDL: asim –o2
    - Riviera-PRO: asim –O2 (fun presynth ati awọn iṣeṣiro-ifiweranṣẹ) ati asim –O5 (fun awọn iṣeṣiro-ifiweranṣẹ)
    Eto Aldec fun Active-HDL ati Riviera-Pro ni awọn SAR isunmọtosi atẹle. Fun alaye siwaju sii, olubasọrọ Microchip Technical Support.
  • SAR 49908 – HDL ti nṣiṣe lọwọ: Aṣiṣe VHDL fun awọn iṣeṣiro Àkọsílẹ Math
  • SAR 50627 - Riviera-PRO 2013.02: Awọn aṣiṣe kikopa fun awọn aṣa SErdES
  • SAR 50461 – Riviera-PRO: asim -O2/-O5 aṣayan ni awọn iṣeṣiro

Eto Inisive Cadence (Beere ibeere kan)

O nilo lati ṣẹda iwe afọwọkọ file iru si ModelSim ME/ModelSim Pro ME run.do lati ṣiṣe awọn
Cadence Incisive labeabo. Tẹle awọn igbesẹ wọnyi ki o ṣẹda iwe afọwọkọ file fun NCSim tabi lo iwe afọwọkọ file
pese lati se iyipada ModelSim ME/ModelSim Pro ME run.do files sinu iṣeto ni files
nilo lati ṣiṣe awọn iṣeṣiro lilo NCsim.
MICROCHIP Libero SoC Simulation Library Software - aami Pataki: Cadence ti dẹkun idasilẹ awọn ẹya tuntun ti Idawọlẹ Inciive
simulator ati bẹrẹ atilẹyin simulator Xcelium.

3.1 Awọn iyipada Ayika (Beere ibeere kan)
Lati ṣiṣẹ simulator Cadence Incisive, tunto awọn oniyipada ayika wọnyi:

  1. LM_LICENSE_FILE: gbọdọ ni itọka si iwe-aṣẹ naa file.
  2. cds_root: gbọdọ tọka si ipo itọsọna ile ti fifi sori Cadence Incisive.
  3. PATH: gbọdọ tọka si ipo bin labẹ itọsọna irinṣẹ tokasi nipasẹ cds_root iyẹn ni,
    $ cds_root / awọn irinṣẹ / bin / 64bit (fun ẹrọ 64-bit ati $ cds_root / awọn irinṣẹ / bin fun ẹrọ 32-bit).
    Awọn ọna mẹta lo wa lati ṣeto agbegbe kikopa ni ọran ti yipada laarin awọn ọna ṣiṣe 64-bit ati 32-bit:

Ọran 1: PATH Ayipada
Ṣiṣe aṣẹ wọnyi:
ṣeto ona = (install_dir / irinṣẹ / bin / 64bit $ ona) fun 64bit ero ati
ṣeto ona = (install_dir / irinṣẹ / bin $ ona) fun 32bit ero
Ọran 2: Lilo aṣayan ila-aṣẹ -64bit
Ninu laini aṣẹ pato -64bit aṣayan lati pe 64bit ti o ṣiṣẹ.
Ọran 3: Ṣiṣeto INCA_64BIT tabi CDS_AUTO_64BIT Ayipada Ayika
Iyipada INCA_64BIT jẹ itọju bi boolean. O le ṣeto oniyipada yii si iye eyikeyi tabi si okun asan.
setenv INCA_64BIT

MICROCHIP Libero SoC Simulation Library Software - aami Pataki: Awọn INCA_64BIT oniyipada ayika ko kan awọn irinṣẹ Cadence miiran, gẹgẹbi awọn irinṣẹ IC. Bibẹẹkọ, fun awọn irinṣẹ Inisiive, oniyipada INCA_64BIT dojuti eto fun oniyipada ayika CDS_AUTO_64BIT. Ti a ba ṣeto oniyipada ayika INCA_64BIT, gbogbo awọn irinṣẹ Inisive nṣiṣẹ ni ipo 64-bit. setenv CDS_AUTO_64BIT PẸLU: INCA
MICROCHIP Libero SoC Simulation Library Software - aami Pataki: Awọn okun INCA gbọdọ wa ni oke nla. Gbogbo awọn iṣẹ ṣiṣe gbọdọ wa ni ṣiṣe ni boya ipo 32-bit tabi ni ipo 64-bit, maṣe ṣeto oniyipada lati pẹlu ọkan ti o ṣiṣẹ, bi ninu atẹle naa:
setenv CDS_AUTO_64BIT PẸLU:ncelab

Awọn irinṣẹ Cadence miiran, gẹgẹbi awọn irinṣẹ IC, tun lo CDS_AUTO_64BIT oniyipada ayika lati ṣakoso yiyan ti 32-bit tabi 64-bit executables. Tabili ti o tẹle fihan bi o ṣe le ṣeto oniyipada CDS_AUTO_64BIT lati ṣiṣẹ awọn irinṣẹ Inisive ati awọn irinṣẹ IC ni gbogbo awọn ipo.
Table 3-1. CDS_AUTO_64BIT Awọn iyipada

CDS_AUTO_64BIT Ayipada Awọn irinṣẹ Inisiive Awọn irinṣẹ IC
setenv CDS_AUTO_64BIT GBOGBO 64 die-die 64 die-die
setenv CDS_AUTO_64BIT KO 32 die-die 32 die-die
setenv CDS_AUTO_64BIT EXCLUDE:ic_alakomeji 64 die-die 32 die-die
setenv CDS_AUTO_64BIT EXCLUDE: INCA 32 die-die 64 die-die

MICROCHIP Libero SoC Simulation Library Software - aami Pataki: Gbogbo awọn irinṣẹ Inisiive gbọdọ wa ni ṣiṣe ni boya ipo 32-bit tabi ni ipo 64-bit, maṣe lo EXCLUDE lati yọkuro iṣẹ ṣiṣe kan pato, bi ninu atẹle yii: setenv CDS_AUTO_64BIT EXCLUDE:ncelab
Ti o ba ṣeto oniyipada CDS_AUTO_64BIT lati yọkuro awọn irinṣẹ Incisive (setenv CDS_AUTO_64BIT EXCLUDE:INCA), gbogbo awọn irinṣẹ Inisive ni a ṣiṣẹ ni ipo 32-bit. Bibẹẹkọ, aṣayan laini aṣẹ -64bit bori oniyipada ayika.
Awọn wọnyi iṣeto ni files ṣe iranlọwọ fun ọ lati ṣakoso data rẹ ati ṣakoso iṣẹ ti awọn irinṣẹ iṣeṣiro ati awọn ohun elo:

  • Iwe aworan agbaye file (cds.lib) — Ṣe alaye orukọ ọgbọn fun ipo ti apẹrẹ rẹ.
  • Awọn ile-ikawe ati ṣepọ wọn pẹlu awọn orukọ itọsọna ti ara.
  • Awọn oniyipada file (hdl.var) - Ṣe alaye awọn oniyipada ti o ni ipa lori ihuwasi ti awọn irinṣẹ iṣeṣiro ati awọn ohun elo.

3.2 Ṣe igbasilẹ Ile-ikawe Iṣakojọ (Beere ibeere kan)
Ṣe igbasilẹ awọn ile-ikawe fun Cadence Incisive lati Microsemi's webojula.
3.3 Ṣiṣẹda NCsim Script File (Beere ibeere kan)
Lẹhin ṣiṣẹda ẹda kan ti run.do files, ṣe awọn igbesẹ wọnyi lati ṣiṣẹ kikopa rẹ nipa lilo NCSim:

  1. Ṣẹda cds.lib file ti o asọye awọn ikawe ti o wa ni wiwọle ati ipo wọn. Awọn file ni awọn alaye ti o ya awọn orukọ ti oye ile-ikawe si awọn ọna itọsọna ti ara wọn. Fun example, ti o ba ti o ba ti wa ni nṣiṣẹ presynth kikopa, awọn cds.lib file ti kọ bi a ṣe han ninu koodu idinamọ atẹle.
    DEFINE presynth ./presynth
    Ṣe alaye COREAHBLITE_LIB ./COREAHBLITE_LIB
    SE alaye smartfusion2
  2. Ṣẹda hdl.var kan file, ohun iyan iṣeto ni file ti o ni awọn oniyipada atunto, ti o ipinnu bi o rẹ oniru ayika ni tunto. Awọn wọnyi ayípadà files wa ninu:
    - Awọn oniyipada ti a lo lati pato ile-ikawe iṣẹ nibiti olupilẹṣẹ ṣafipamọ awọn nkan ti a ṣajọ ati data miiran ti ari.
    - Fun Verilog, awọn oniyipada (LIB_MAP, VIEW_MAP, WORK) ti a lo lati pato awọn ile-ikawe ati views lati wa nigbati awọn elaborator resolves instances.
    - Awọn oniyipada ti o gba ọ laaye lati ṣalaye akopọ, onitumọ, ati awọn aṣayan laini aṣẹ simulator ati awọn ariyanjiyan.
    Ni irú ti presynth kikopa example han loke, wi a ni meta RTL files: av, bv, ati testbench.v, eyi ti o nilo lati ṣe akojọpọ si presynth, COREAHBLITE_LIB, ati awọn ile-ikawe presynth lẹsẹsẹ. hdl.var naa file le kọ bi o ṣe han ninu koodu idinamọ atẹle.
    Setumo Ise presynth
    SETU PROJECT_DIR files>
    DEFINE LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/av => presynth )
    DEFINE LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/bv => COREAHBLITE_LIB )
    DEFINE LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/testbench.v => presynth )
    DEFINE LIB_MAP ( $LIB_MAP, + => presynth )
  3. Ṣe akopọ apẹrẹ files lilo ncvlog aṣayan.
    ncvlog + incdir+ –cdslib ./cds.lib –hdlvar ./hdl.var –logfile
    ncvlog.log –imudojuiwọn –linedebug av bv testbench.v
  4. Ṣe alaye apẹrẹ nipa lilo celab. Oluṣeto n ṣe agbekalẹ awọn ilana apẹrẹ kan ti o da lori ese ati alaye iṣeto ni apẹrẹ, ṣe agbekalẹ asopọ ifihan, ati ṣe iṣiro awọn iye ibẹrẹ fun gbogbo awọn nkan inu apẹrẹ. Ilana apẹrẹ ti a ṣe alaye ti wa ni ipamọ ni aworan kikopa, eyiti o jẹ aṣoju apẹrẹ rẹ ti ẹrọ afọwọṣe nlo lati ṣiṣẹ kikopa naa.
    ncelab – Ifiranṣẹ –cdslib ./cds.lib –hdlvar ./hdl.var –logfile ncelab.log –aṣiṣe 15 –
    wiwọle +rwc –ipo worklib. : module
    Iṣalaye Lakoko kikopa Post-layout
    Ni ọran ti awọn iṣeṣiro-ifiweranṣẹ, akọkọ SDF file nilo lati ṣajọ ṣaaju ṣiṣe alaye nipa lilo pipaṣẹ ncsdfc.
    ncsdfcfileorukọ> .sdf -jadefileorukọ>.sdf.X
    Lakoko imudara lo iṣẹjade SDF ti a ṣajọpọ pẹlu aṣayan –autosdf bi o ṣe han ninu koodu block atẹle.
    ncelab -autosdf –Ifiranṣẹ –cdslib ./cds.lib –hdlvar ./hdl.var –logfile ncelab.log –errormax
    15 -wiwọle + rwc –ipo worklib. :module –sdf_cmd_file ./
    sdf_cmd_file
    Sdf_cmd_ naafile gbọdọ jẹ bi o ṣe han ninu koodu idinamọ atẹle.
    COPILED_SDF_FILE =" file>>
  5. Simulate lilo ncsim. Lẹhin ti alaye ni a ṣẹda aworan kikopa, eyiti o jẹ ti kojọpọ nipasẹ ncsim fun kikopa. O le ṣiṣẹ ni ipo ipele tabi ipo GUI.
    ncsim – Ifiranṣẹ –batch/-gui –cdslib ./cds.lib –hdlvar ./hdl.var –logfile ncsim.log –
    errormax 15 -ipo worklib. : module

MICROCHIP Libero SoC Simulation Library Software - aami Pataki: Gbogbo awọn igbesẹ mẹta ti o wa loke ti iṣakojọpọ, asọye, ati simulating ni a le fi sinu iwe afọwọkọ ikarahun kan file ati orisun lati laini aṣẹ. Dipo lilo awọn igbesẹ mẹta wọnyi, apẹrẹ le ṣe simulated ni igbesẹ kan nipa lilo ncverilog tabi aṣayan irun bi o ṣe han ni koodu block atẹle.
ncverilog + incdir + -cdslib ./cds.lib –hdlvar ./hdl.var
files lo ninu apẹrẹ>
irun + incdir+ -cdslib ./cds.lib –hdlvar ./hdl.var files
lo ninu apẹrẹ>

3.3.1 Awọn ọran ti a mọ (Beere ibeere kan)
Testbench Workaround
Lilo alaye atẹle fun asọye igbohunsafẹfẹ aago ni testbench ti ipilẹṣẹ nipasẹ olumulo, tabi testbench aiyipada ti ipilẹṣẹ nipasẹ Libero SoC ko ṣiṣẹ pẹlu NCsim.
nigbagbogbo @(SYSCLK)
#(SYSCLK_PERIOD / 2.0) SYSCLK <= !SYSCLK;
Ṣatunṣe bi atẹle lati ṣiṣẹ kikopa:
nigbagbogbo #(SYSCLK_PERIOD / 2.0) SYSCLK = ~ SYSCLK;
MICROCHIP Libero SoC Simulation Library Software - aami Pataki: Compiled awọn ile-ikawe fun NCSim jẹ pẹpẹ kan pato (ie awọn ile-ikawe 64 ko ni ibamu pẹlu pẹpẹ 32 bit ati ni idakeji).
Awọn iṣeṣiro Postsynth ati Ifilelẹ-lẹhin Lilo MSS ati SERDES Lakoko ti o nṣiṣẹ awọn iṣeṣiro postsynth ti awọn apẹrẹ ti o ni bulọọki MSS tabi awọn adaṣe ifiweranṣẹ-lẹhin ti awọn aṣa nipa lilo SERDES, awọn iṣeṣiro BFM ko ṣiṣẹ ti aṣayan –libmap ba jẹ
ko pato nigba elaboration. Eyi jẹ nitori lakoko iṣalaye, MSS jẹ ipinnu lati inu ile-ikawe iṣẹ (nitori abuda aiyipada ati pe worklib jẹ postsynth/post-layout) nibiti o jẹ Iṣẹ Ti o wa titi nikan.
Aṣẹ ncelab gbọdọ kọ bi o ṣe han ninu bulọọki koodu atẹle lati yanju MSS naa
dina lati SmartFusion2 ikawe ti a ti ṣajọ tẹlẹ.

ncelab -libmap lib.map -libverbose -Ifiranṣẹ -iwọle +rwc cfg1
ati lib.map file gbọdọ jẹ bi wọnyi:
konfigi cfg1;
oniru ;
aiyipada liblist smartfusion2 ;
endconfig
Eyi ṣe ipinnu sẹẹli eyikeyi ninu ile-ikawe SmartFusion2 ṣaaju ki o to wo inu ile-ikawe iṣẹ ie postsynth/ipilẹṣẹ ifiweranṣẹ.
Aṣayan –libmap le ṣee lo nipasẹ aiyipada lakoko imudara fun gbogbo kikopa (presynth, postsynth, ati igbekalẹ-lẹhin). Eyi yago fun awọn ọran kikopa ti o ṣẹlẹ nitori ipinnu awọn iṣẹlẹ lati awọn ile-ikawe.
ncelab: *F,INTERR: INU IYASO
Iyatọ ọpa ncelab yii jẹ akiyesi fun awọn apẹrẹ ti o ni FDDR ninu SmartFusion 2 ati IGLOO 2 lakoko awọn iṣeṣiro ifiweranṣẹ ati ifiweranṣẹ-lẹhin nipa lilo aṣayan –libmap.
MICROCHIP Libero SoC Simulation Library Software - aami Pataki: Ọrọ yii ti jẹ ijabọ si ẹgbẹ atilẹyin Cadence (SAR 52113).

Ọdun 3.4 Sample Tcl ati Shell akosile Files (Beere ibeere kan)
Atẹle naa files ni o wa iṣeto ni files nilo fun eto soke oniru ati ikarahun akosile file fun ṣiṣe awọn aṣẹ NCSim.
Cds.lib
NE smartfusion2 / scratch/krydor/tmpspace/users/me/nc-vlog64/SmartFusion2
Ṣe alaye COREAHBLITE_LIB ./COREAHBLITE_LIB
DEFINE presynth ./presynth

HDl.var
Setumo Ise presynth
DEFINE PROJECT_DIR / scratch/krydor/tmpspace/sqausers/mi/3rd_party_simulators/Cadence/IGLOO2/
ENVM/M2GL050/envm_fic1_ser1_v/eNVM_fab_master
DEFINE LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBlite/4.0.100/rtl/
vlog/core/coreahblite_addrdec.v => COREAHBLITE_LIB )
DEFINE LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBlite/4.0.100/rtl/
vlog/core/coreahblite_defaultslavesm.v => COREAHBLITE_LIB )
DEFINE LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBlite/4.0.100/rtl/
vlog / mojuto / coreahblite_masterstagev => COREAHBLITE_LIB )
DEFINE LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBlite/4.0.100/rtl/
vlog/core/coreahblite_slavearbiter.v => COREAHBLITE_LIB )
DEFINE LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBlite/4.0.100/rtl/
vlog / mojuto / coreahblite_slavestagev => COREAHBLITE_LIB )
DEFINE LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBlite/4.0.100/rtl/
vlog/core/coreahblite_matrix2x16.v => COREAHBLITE_LIB )
DEFINE LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBlite/4.0.100/rtl/
vlog/core/coreahblite.v => COREAHBLITE_LIB )
DEFINE LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB/CCC_0/SB_CCC_0_FCCC.v =>
presynth)
DEFINE LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreConfigMaster/
2.0.101/rtl/vlog/core/coreconfigmaster.v => presynth )
DEFINE LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreConfigP/4.0.100/rtl/
vlog/core/coreconfigp.v => presynth )
DEFINE LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreResetP/5.0.103/rtl/
vlog/core/coreresetp_pcie_hotreset.v => presynth )
DEFINE LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreResetP/5.0.103/rtl/
vlog/core/coreresetp.v => presynth )
DEFINE LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB/FABOSC_0/SB_FABOSC_0_OSC.v =>
presynth)
DEFINE LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB_HPMS/SB_HPMS.v => presynth )
DEFINE LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB/SB.v => presynth )
DEFINE LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB_top/SERDES_IF_0/
SB_top_SERDES_IF_0_SERDES_IF.v => presynth )
DEFINE LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB_top/SB_top.v => presynth )
DEFINE LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB_top/testbench.v => presynth )
DEFINE LIB_MAP ( $LIB_MAP, + => presynth )
Awọn aṣẹ.csh
ncvlog + incdir+.../../component/work/SB_top -cdslib ./cds.lib -hdlvar ./hdl.var -logfile
ncvlog.log -errormax 15 -update -linedebug
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite_addrdec.v
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/
coreahblite_defaultslavesm.v
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite_masterstagev
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite_slavearbiter.v
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite_slavestagev
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite_matrix2x16.v
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite.v
../../component/ise/SB/CCC_0/SB_CCC_0_FCCC.v
../../component/Actel/DirectCore/CoreConfigMaster/2.0.101/rtl/vlog/core/coreconfigmaster.v
../../component/Actel/DirectCore/CoreConfigP/4.0.100/rtl/vlog/core/coreconfigp.v
.
../../component/Actel/DirectCore/CoreResetP/5.0.103/rtl/vlog/core/coreresetp.v
../../component/ise/SB/FABOSC_0/SB_FABOSC_0_OSC.v ../../component/work/SB_HPMS/SB_HPMS.v
../../component/iṣẹ/SB/SB.v ../../component/work/SB_top/SERDES_IF_0/
SB_oke_SERDES_IF_0_SERDES_IF.v
../../component/ise/SB_top/SB_top.v ../../component/work/SB_top/testbench.v
ncelab -Ifọrọranṣẹ -cdslib ./cds.lib -hdlvar ./hdl.var
-iṣẹ presynth -logfile ncelab.log -errormax 15 -wccess +rwc -status presynth.testbench:module
ncsim -Ifiranṣẹ -batch -cdslib ./cds.lib -hdlvar ./
hdl.var -logfile ncsim.log -errormax 15 -ipo presynth.testbench:module

3.5 adaṣe (Beere ibeere kan)
Awọn wọnyi akosile file iyipada ModelSim run.do files sinu iṣeto ni files nilo lati ṣiṣe awọn iṣeṣiro lilo NCsim.
Iwe afọwọkọ File Lilo
perl cadence_parser.pl presynth_run.do postsynth_run.do
postlayout_run.do Microsemi_Family
Ibi_ti_Cadence_Precompiled_libraries

Cadence_parser.pl
#!/usr/bin/perl -w

################################################### #####################################
################
#Lilo: perl questa_parser.pl presynth_run.do postsynth_run.do postlayout_run.do
Microsemi_Family Precompiled_Libraries_location#

################################################### #####################################
################
lo POSIX;
lo ti o muna;
mi ($presynth, $postsynth, $ postlayout, $ ebi, $ lib_location) = @ARGV;
&questa_parser ($ presynth, $ ebi, $ lib_location);
&questa_parser ($ postsynth, $ ebi, $ lib_location);
&questa_parser ($ postlayout, $ ebi, $ lib_location);
sub questa_parser {
mi $ModelSim_run_do = $_[0];
$actel_family mi = $_[1];
mi $ lib_location = $ _ [2];
ipinle $ mi;
ti (-e “$ModelSim_run_do”)
{
ṣii (INFILE, "$ ModelSim_run_do");
mi @ModelSim_run_do =FILE>;
ila $ mi;
ti ($ModelSim_run_do =~ m/(presynth)/)
{
`mkdir QUESTA_PRESYNTH';
ṣii (OUTFILE,”>QUESTA_PRESYNTH/presynth_questa.do”);
ipinle = $1;
} elsif ( $ModelSim_run_do =~ m/(postsynth)/)
{
`mkdir QUESTA_POSTSYNTH`;
ṣii (OUTFILE,”>QUESTA_POSTSYNTH/postsynth_questa.do”);
ipinle = $1;
} elsif ( $ModelSim_run_do =~ m/(ifiweranṣẹ)/)
{
`mkdir QUESTA_POSTLAYOUT`;
ṣii (OUTFILE,”>QUESTA_POSTLAYOUT/postlayout_questa.do”);
ipinle = $1;
} miiran
{
tẹjade “Awọn igbewọle ti ko tọ ti a fi fun awọn file\n";
sita "#Usage: perl questa_parser.pl presynth_run.do postsynth_run.do postlayout_run.do
\"Ibi_Ibi ikawe \"\n";
}
ila $iwaju (@ModelSim_run_do)
{
# Awọn iṣẹ gbogbogbo
$ ila = ~ s / .. \/ onise. * Simulation \ /// g;
$ila =~ s/$ipinlẹ/$ipinlẹ _questa/g;
#tẹ jadeFILE "$ila \n";
ti o ba jẹ ($ ila = ~ m/vmap\s+.*($actel_family)/)
{
tẹ jadeFILE "vmap $actel_family \"$lib_location\"\n";
} elsif ($ila =~ m/vmap\s+(.*._LIB)/)
{
$ ila = ~ s / .. \ / paati / .. \ / .. \ / paati / g;
tẹ jadeFILE "$ila \n";
} elsif ($ila =~ m/vsim/)
{
$ila =~ s/vsim/vsim -novopt/g;
tẹ jadeFILE "$ila \n";
} miiran
{
tẹ jadeFILE "$ila \n";
}
}
sunmọ (INFILE);
sunmọ (OUTFILE);
} miran {
tẹjade “$ModelSim_run_do ko si. Atunse kikopa lẹẹkansi \n";
}
}

Eto Cadence Xcelium (Microchip Wọle)

O nilo lati ṣẹda iwe afọwọkọ file iru si ModelSim ME/ModelSim Pro ME run.do lati ṣiṣẹ simulator Cadence Xcelium. Tẹle awọn igbesẹ wọnyi ki o ṣẹda iwe afọwọkọ file fun Xcelium tabi lo iwe afọwọkọ file pese lati se iyipada ModelSim ME/ModelSim Pro ME run.do files sinu iṣeto ni files nilo lati ṣiṣẹ awọn iṣeṣiro nipa lilo Xcelium.
4.1 Awọn iyipada Ayika (Beere ibeere kan)
Lati ṣiṣẹ Cadence Xcelium, tunto awọn oniyipada ayika wọnyi:

  1. LM_LICENSE_FILE: gbọdọ ni itọka si iwe-aṣẹ naa file.
  2. cds_root: gbọdọ tọka si ipo itọsọna ile ti fifi sori Cadence Incisive.
  3. PATH: gbọdọ tọka si ipo bin labẹ itọsọna irinṣẹ tokasi nipasẹ cds_root (ie
    $ cds_root / awọn irinṣẹ / bin / 64bit (fun ẹrọ 64 bit ati $ cds_root / awọn irinṣẹ / bin fun 32 bit
    ẹrọ).

Awọn ọna mẹta lo wa lati ṣeto agbegbe kikopa ni ọran ti yipada laarin awọn ọna ṣiṣe 64-bit ati 32-bit:
Ọran 1: PATH Ayipada
ṣeto ona = (install_dir / irinṣẹ / bin / 64bit $ ona) fun 64bit ero ati
ṣeto ona = (install_dir / irinṣẹ / bin $ ona) fun 32bit ero
Ọran 2: Lilo aṣayan ila-aṣẹ -64bit
Ninu laini aṣẹ pato -64bit aṣayan lati le pe 64-bit ti o ṣiṣẹ.
Ọran 3: Ṣiṣeto INCA_64BIT tabi CDS_AUTO_64BIT Ayipada Ayika
Iyipada INCA_64BIT jẹ itọju bi boolean. O le ṣeto oniyipada yii si iye eyikeyi tabi si asan
okun.
setenv INCA_64BIT

MICROCHIP Libero SoC Simulation Library Software - aami Pataki: Awọn INCA_64BIT oniyipada ayika ko kan awọn irinṣẹ Cadence miiran, gẹgẹbi awọn irinṣẹ IC. Bibẹẹkọ, fun awọn irinṣẹ Inisiive, oniyipada INCA_64BIT dojuti eto fun oniyipada ayika CDS_AUTO_64BIT. Ti o ba jẹ pe oniyipada ayika INCA_64BIT jẹ et, gbogbo awọn irinṣẹ Inisiive nṣiṣẹ ni ipo 64-bit.
setenv CDS_AUTO_64BIT PẸLU: INCA
MICROCHIP Libero SoC Simulation Library Software - aami Pataki: Awọn okun INCA gbọdọ wa ni oke nla. Gbogbo awọn iṣẹ ṣiṣe gbọdọ wa ni ṣiṣe ni boya ipo 2-bit tabi ni ipo 64-bit, maṣe ṣeto oniyipada lati pẹlu ọkan ti o ṣiṣẹ, bi ninu atẹle naa:
setenv CDS_AUTO_64BIT PẸLU:ncelab
Awọn irinṣẹ Cadence miiran, gẹgẹbi awọn irinṣẹ IC, tun lo CDS_AUTO_64BIT oniyipada ayika lati ṣakoso yiyan ti 32-bit tabi 64-bit executables. Tabili ti o tẹle fihan bi o ṣe le ṣeto oniyipada CDS_AUTO_64BIT lati ṣiṣẹ awọn irinṣẹ Inisive ati awọn irinṣẹ IC ni gbogbo awọn ipo.

Table 4-1. CDS_AUTO_64BIT Awọn iyipada

CDS_AUTO_64BIT Ayipada Awọn irinṣẹ Inisiive Awọn irinṣẹ IC
setenv CDS_AUTO_64BIT GBOGBO 64-bit 64-bit
setenv CDS_AUTO_64BIT KO 32-bit 32-bit
setenv CDS_AUTO_64BIT
EXCLUDE: ic_binary		 64-bit 32-bit
setenv CDS_AUTO_64BIT EXCLUDE: INCA 32-bit 64-bit

MICROCHIP Libero SoC Simulation Library Software - aami Pataki: Gbogbo awọn irinṣẹ Insiive gbọdọ wa ni ṣiṣe ni boya ipo 32-bit tabi ni ipo 64-bit, maṣe lo EXCLUDE lati yọkuro iṣẹ ṣiṣe kan pato, bi ninu atẹle:
setenv CDS_AUTO_64BIT EXCLUDE:ncelab
Ti o ba ṣeto oniyipada CDS_AUTO_64BIT lati yọkuro awọn irinṣẹ Inisive (setenv)
CDS_AUTO_64BIT EXCLUDE:INCA), gbogbo awọn irinṣẹ Inisiive ti wa ni ṣiṣe ni ipo 32-bit. Sibẹsibẹ, awọn
-64bit-ila aṣayan pipaṣẹ idojuk oniyipada ayika.
Awọn wọnyi iṣeto ni files ṣe iranlọwọ fun ọ lati ṣakoso data rẹ ati ṣakoso iṣẹ ti awọn irinṣẹ iṣeṣiro ati awọn ohun elo:

  • Iwe aworan agbaye file (cds.lib) n ṣalaye orukọ ọgbọn fun ipo ti apẹrẹ rẹ.
  • Awọn ile-ikawe ati ṣepọ wọn pẹlu awọn orukọ itọsọna ti ara.
  • Awọn oniyipada file (hdl.var) n ṣalaye awọn oniyipada ti o ni ipa lori ihuwasi awọn irinṣẹ adaṣe ati awọn ohun elo.

4.2 Ṣe igbasilẹ Ile-ikawe Iṣakojọ (Beere ibeere kan)
Ṣe igbasilẹ awọn ile-ikawe fun Cadence Xcelium lati Microsemi's webojula.
4.3 Ṣiṣẹda Xcelium iwe afọwọkọ file (Beere ibeere kan)
Lẹhin ṣiṣẹda ẹda kan ti run.do files, ṣe awọn igbesẹ wọnyi lati ṣiṣẹ kikopa rẹ nipa lilo iwe afọwọkọ Xcelium file.

  1. Ṣẹda cds.lib file ti o asọye eyi ti ikawe wa ni wiwọle ati ibi ti won ti wa ni be.
    Awọn file ni awọn alaye ti o ya awọn orukọ ti oye ile-ikawe si awọn ọna itọsọna ti ara wọn. Fun example, ti o ba ti o ba ti wa ni nṣiṣẹ presynth kikopa, awọn cds.lib file le kọ bi o ṣe han ninu koodu idinamọ atẹle.
    DEFINE presynth ./presynth
    Ṣe alaye COREAHBLITE_LIB ./COREAHBLITE_LIB
    SE alaye smartfusion2
  2. Ṣẹda hdl.var kan file eyi ti o jẹ ẹya iyan iṣeto ni file ti o ni awọn oniyipada atunto, ti o ipinnu bi o rẹ oniru ayika ni tunto. Iwọnyi pẹlu:
    - Awọn oniyipada ti a lo lati pato ile-ikawe iṣẹ nibiti olupilẹṣẹ ṣafipamọ awọn nkan ti a ṣajọ ati data miiran ti ari.
    - Fun Verilog, awọn oniyipada (LIB_MAP, VIEW_MAP, WORK) ti a lo lati pato awọn ile-ikawe ati views lati wa nigbati awọn elaborator resolves instances.
    - Awọn oniyipada ti o gba ọ laaye lati ṣalaye akopọ, onitumọ, ati awọn aṣayan laini aṣẹ simulator ati awọn ariyanjiyan.
    Ni irú ti presynth kikopa example han loke, wi a ni 3 RTL files av, bv, ati testbench.v, eyi ti o nilo lati ṣe akojọpọ si presynth, COREAHBLITE_LIB, ati awọn ile-ikawe presynth lẹsẹsẹ. hdl.var naa file le kọ bi o ṣe han ninu koodu idinamọ atẹle.
    Setumo Ise presynth
    SETU PROJECT_DIR files>
    DEFINE LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/av => presynth )
    DEFINE LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/bv => COREAHBLITE_LIB )
    DEFINE LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/testbench.v => presynth )
    DEFINE LIB_MAP ( $LIB_MAP, + => presynth )
  3. Ṣe akopọ apẹrẹ files lilo ncvlog aṣayan.
    xmvlog + incdir+ –cdslib ./cds.lib –hdlvar ./hdl.var –logfile
    ncvlog.log –imudojuiwọn –linedebug av bv testbench.v
  4. Ṣe alaye apẹrẹ nipa lilo celab. Oluṣeto n ṣe agbekalẹ awọn ilana apẹrẹ kan ti o da lori ese ati alaye iṣeto ni apẹrẹ, ṣe agbekalẹ asopọ ifihan, ati ṣe iṣiro awọn iye ibẹrẹ fun gbogbo awọn nkan inu apẹrẹ. Ilana apẹrẹ ti a ṣe alaye ti wa ni ipamọ ni aworan kikopa, eyiti o jẹ aṣoju apẹrẹ rẹ ti ẹrọ afọwọṣe nlo lati ṣiṣẹ kikopa naa.
    Xcelium – Ifiranṣẹ –cdslib ./cds.lib –hdlvar ./hdl.var –logfile ncelab.log –aṣiṣe 15 –
    wiwọle +rwc –ipo worklib. : module
    Iṣalaye Lakoko kikopa Post-layout
    Ni ọran ti awọn iṣeṣiro-ifiweranṣẹ, akọkọ SDF file nilo lati ṣajọ ṣaaju ṣiṣe alaye nipa lilo pipaṣẹ ncsdfc.
    Xceliumfileorukọ> .sdf -jadefileorukọ>.sdf.X
    Lakoko imudara lo iṣẹjade SDF ti a ṣajọpọ pẹlu aṣayan –autosdf bi o ṣe han ninu koodu block atẹle.
    xmelab -autosdf –Ifiranṣẹ –cdslib ./cds.lib –hdlvar ./hdl.var –logfile ncelab.log –errormax
    15 -wiwọle + rwc –ipo worklib. :module –sdf_cmd_file ./
    sdf_cmd_file
    Sdf_cmd_ naafile gbọdọ jẹ bi o ṣe han ninu koodu idinamọ atẹle.
    COPILED_SDF_FILE =" file>>
  5. Ṣe afarawe nipa lilo Xcelium. Lẹhin ti alaye ni a ṣẹda aworan kikopa ti o jẹ ti kojọpọ nipasẹ Xcelium fun kikopa. Eyi le ṣee ṣiṣẹ ni ipo ipele tabi ipo GUI.
    xmsim – Ifiranṣẹ –batch/-gui –cdslib ./cds.lib –hdlvar ./hdl.var –logfile xmsim.log –
    errormax 15 -ipo worklib. : module
    Cadence Xcelium Oṣo
    MICROCHIP Libero SoC Simulation Library Software - aami Pataki: Gbogbo awọn igbesẹ mẹta ti o wa loke ti iṣakojọpọ, asọye ati simulating ni a le fi sinu iwe afọwọkọ ikarahun kan file ati orisun lati laini aṣẹ. Dipo lilo awọn igbesẹ mẹta wọnyi, apẹrẹ le ṣe simulated ni igbesẹ kan nipa lilo ncverilog tabi aṣayan xrun bi o ṣe han ni koodu block atẹle.
    xmverilog + incdir+ -cdslib ./cds.lib –hdlvar ./hdl.var
    files lo ninu apẹrẹ>
    xrun + incdir+ -cdslib ./cds.lib –hdlvar ./hdl.var files
    lo ninu apẹrẹ>

4.3.1 Awọn ọran ti a mọ (Beere ibeere kan)
Testbench Workaround
Lilo alaye atẹle fun asọye igbohunsafẹfẹ aago ni testbench ti ipilẹṣẹ nipasẹ olumulo tabi testbench aiyipada ti ipilẹṣẹ nipasẹ Libero SoC ko ṣiṣẹ pẹlu Xcelium.
nigbagbogbo @(SYSCLK)
#(SYSCLK_PERIOD / 2.0) SYSCLK <= !SYSCLK;
Ṣatunṣe bi atẹle lati ṣiṣẹ kikopa:
nigbagbogbo #(SYSCLK_PERIOD / 2.0) SYSCLK = ~ SYSCLK;

MICROCHIP Libero SoC Simulation Library Software - aami Pataki: Awọn ile-ikawe ti a ṣajọpọ fun Xcelium jẹ ipilẹ kan pato (ie awọn ile-ikawe 64 ko ni ibamu pẹlu pẹpẹ 32 bit ati ni idakeji).
Postsynth ati Awọn iṣeṣiro igbekalẹ-lẹhin ni lilo MSS ati SERDES
Lakoko ti o nṣiṣẹ awọn iṣeṣiro postsynth ti awọn apẹrẹ ti o ni idiwọ MSS, tabi awọn iṣeṣiro-lẹhin ti awọn apẹrẹ ti awọn aṣa nipa lilo SERDES, awọn iṣeṣiro BFM ko ṣiṣẹ ti aṣayan –libmap ko ba ni pato lakoko imudara. Eyi jẹ nitori lakoko iṣalaye, MSS jẹ ipinnu lati inu ile-ikawe iṣẹ (nitori abuda aiyipada ati pe worklib jẹ postsynth/post-layout) nibiti o jẹ Iṣẹ Ti o wa titi nikan.
Aṣẹ ncelab gbọdọ wa ni kikọ bi o ṣe han ninu bulọọki koodu atẹle lati yanju bulọọki MSS lati inu ikawe ti a ti ṣajọ tẹlẹ SmartFusion2.
xmelab -libmap lib.map -libverbose -Ifiranṣẹ -iwọle +rwc cfg1
ati lib.map file gbọdọ jẹ bi wọnyi:
konfigi cfg1;
oniru ;
aiyipada liblist smartfusion2 ;
endconfig
Eyi gbọdọ yanju eyikeyi sẹẹli ninu ile-ikawe SmartFusion2 ṣaaju ki o to wo inu ile-ikawe iṣẹ ie postsynth/post-layout.
Aṣayan –libmap le ṣee lo nipasẹ aiyipada lakoko imudara fun gbogbo kikopa (presynth, postsynth ati igbekalẹ-lẹhin). Eyi yago fun awọn ọran kikopa ti o ṣẹlẹ nitori ipinnu awọn iṣẹlẹ lati awọn ile-ikawe.
xmelab: *F,INTERR: IYASO ti inu
Iyatọ ọpa ncelab yii jẹ akiyesi fun awọn apẹrẹ ti o ni FDDR ninu SmartFusion2 ati IGLOO2
lakoko postsynth ati awọn iṣeṣiro ipilẹ-lẹhin nipa lilo aṣayan –libmap.
MICROCHIP Libero SoC Simulation Library Software - aami Pataki: Ọrọ yii ti jẹ ijabọ si ẹgbẹ atilẹyin Cadence (SAR 52113).

Ọdun 4.4 Sample Tcl ati ikarahun akosile files (Beere ibeere kan)
Atẹle naa files ni o wa iṣeto ni files nilo fun eto soke oniru ati ikarahun akosile file fun ṣiṣe awọn pipaṣẹ Xcelium.
Cds.lib
DEFINE smartfusion2 / scratch/krydor/tmpspace/users/me/nc-vlog64/SmartFusion2
Ṣe alaye COREAHBLITE_LIB ./COREAHBLITE_LIB
DEFINE presynth ./presynth
HDl.var
Setumo Ise presynth
DEFINE PROJECT_DIR / scratch/krydor/tmpspace/sqausers/mi/3rd_party_simulators/Cadence/IGLOO2/
ENVM/M2GL050/envm_fic1_ser1_v/eNVM_fab_master
DEFINE LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBlite/4.0.100/rtl/
vlog/core/coreahblite_addrdec.v => COREAHBLITE_LIB )
DEFINE LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBlite/4.0.100/rtl/
vlog/core/coreahblite_defaultslavesm.v => COREAHBLITE_LIB )
DEFINE LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBlite/4.0.100/rtl/
vlog / mojuto / coreahblite_masterstagev => COREAHBLITE_LIB )
DEFINE LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBlite/4.0.100/rtl/
vlog/core/coreahblite_slavearbiter.v => COREAHBLITE_LIB )
DEFINE LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBlite/4.0.100/rtl/
vlog / mojuto / coreahblite_slavestagev => COREAHBLITE_LIB )
DEFINE LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBlite/4.0.100/rtl/
vlog/core/coreahblite_matrix2x16.v => COREAHBLITE_LIB )
DEFINE LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBlite/4.0.100/rtl/
vlog/core/coreahblite.v => COREAHBLITE_LIB )
DEFINE LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB/CCC_0/SB_CCC_0_FCCC.v =>
presynth)
DEFINE LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreConfigMaster/
2.0.101/rtl/vlog/core/coreconfigmaster.v => presynth )
DEFINE LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreConfigP/4.0.100/rtl/
vlog/core/coreconfigp.v => presynth )
DEFINE LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreResetP/5.0.103/rtl/
vlog/core/coreresetp_pcie_hotreset.v => presynth )
DEFINE LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreResetP/5.0.103/rtl/
vlog/core/coreresetp.v => presynth )
DEFINE LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB/FABOSC_0/SB_FABOSC_0_OSC.v =>
presynth)
DEFINE LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB_HPMS/SB_HPMS.v => presynth )
DEFINE LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB/SB.v => presynth )
DEFINE LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB_top/SERDES_IF_0/
SB_top_SERDES_IF_0_SERDES_IF.v => presynth )
DEFINE LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB_top/SB_top.v => presynth )
DEFINE LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB_top/testbench.v => presynth )
DEFINE LIB_MAP ( $LIB_MAP, + => presynth )
Awọn aṣẹ.csh
ncvlog + incdir+.../../component/work/SB_top -cdslib ./cds.lib -hdlvar ./hdl.var -logfile
ncvlog.log -errormax 15 -update -linedebug
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite_addrdec.v
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/
coreahblite_defaultslavesm.v
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite_masterstagev
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite_slavearbiter.v
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite_slavestagev
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite_matrix2x16.v
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite.v
../../component/ise/SB/CCC_0/SB_CCC_0_FCCC.v
../../component/Actel/DirectCore/CoreConfigMaster/2.0.101/rtl/vlog/core/coreconfigmaster.v
../../component/Actel/DirectCore/CoreConfigP/4.0.100/rtl/vlog/core/coreconfigp.v
.
../../component/Actel/DirectCore/CoreResetP/5.0.103/rtl/vlog/core/coreresetp.v
../../component/ise/SB/FABOSC_0/SB_FABOSC_0_OSC.v ../../component/work/SB_HPMS/SB_HPMS.v
../../component/iṣẹ/SB/SB.v ../../component/work/SB_top/SERDES_IF_0/
SB_oke_SERDES_IF_0_SERDES_IF.v
../../component/ise/SB_top/SB_top.v ../../component/work/SB_top/testbench.v
ncelab -Ifọrọranṣẹ -cdslib ./cds.lib -hdlvar ./hdl.var
-iṣẹ presynth -logfile ncelab.log -errormax 15 -wccess +rwc -status presynth.testbench:module
ncsim -Ifiranṣẹ -batch -cdslib ./cds.lib -hdlvar ./
hdl.var -logfile ncsim.log -errormax 15 -ipo presynth.testbench:module

4.5 adaṣe (Microchip Wọle)
Awọn wọnyi akosile file iyipada ModelSim run.do files sinu iṣeto ni files nilo lati ṣiṣẹ awọn iṣeṣiro nipa lilo Xcelium.
Iwe afọwọkọ File Lilo
perl cadence_parser.pl presynth_run.do postsynth_run.do
postlayout_run.do Microsemi_Family
Ibi_ti_Cadence_Precompiled_libraries
Cadence_parser.pl
#!/usr/bin/perl -w

################################################### #####################################
################
#Lilo: perl questa_parser.pl presynth_run.do postsynth_run.do postlayout_run.do
Microsemi_Family Precompiled_Libraries_location#

################################################### #####################################
################
lo POSIX;
lo ti o muna;
mi ($presynth, $postsynth, $ postlayout, $ ebi, $ lib_location) = @ARGV;
&questa_parser ($ presynth, $ ebi, $ lib_location);
&questa_parser ($ postsynth, $ ebi, $ lib_location);

&questa_parser ($ postlayout, $ ebi, $ lib_location);
sub questa_parser {
mi $ModelSim_run_do = $_[0];
$actel_family mi = $_[1];
mi $ lib_location = $ _ [2];
ipinle $ mi;
ti (-e “$ModelSim_run_do”)
{
ṣii (INFILE, "$ ModelSim_run_do");
mi @ModelSim_run_do =FILE>;
ila $ mi;
ti ($ModelSim_run_do =~ m/(presynth)/)
{
`mkdir QUESTA_PRESYNTH';
ṣii (OUTFILE,”>QUESTA_PRESYNTH/presynth_questa.do”);
ipinle = $1;
} elsif ( $ModelSim_run_do =~ m/(postsynth)/)
{
`mkdir QUESTA_POSTSYNTH`;
ṣii (OUTFILE,”>QUESTA_POSTSYNTH/postsynth_questa.do”);
ipinle = $1;
} elsif ( $ModelSim_run_do =~ m/(ifiweranṣẹ)/)
{
`mkdir QUESTA_POSTLAYOUT`;
ṣii (OUTFILE,”>QUESTA_POSTLAYOUT/postlayout_questa.do”);
ipinle = $1;
} miiran
{
tẹjade “Awọn igbewọle ti ko tọ ti a fi fun awọn file\n";
sita "#Usage: perl questa_parser.pl presynth_run.do postsynth_run.do postlayout_run.do
\"Ibi_Ibi ikawe \"\n";
}
ila $iwaju (@ModelSim_run_do)
{
# Awọn iṣẹ gbogbogbo
$ ila = ~ s / .. \/ onise. * Simulation \ /// g;
$ila =~ s/$ipinlẹ/$ipinlẹ _questa/g;
#tẹ jadeFILE "$ila \n";
ti o ba jẹ ($ ila = ~ m/vmap\s+.*($actel_family)/)
{
tẹ jadeFILE "vmap $actel_family \"$lib_location\"\n";
} elsif ($ila =~ m/vmap\s+(.*._LIB)/)
{
$ ila = ~ s / .. \ / paati / .. \ / .. \ / paati / g;
tẹ jadeFILE "$ila \n";
} elsif ($ila =~ m/vsim/)
{
$ila =~ s/vsim/vsim -novopt/g;
tẹ jadeFILE "$ila \n";
} miiran
{
tẹ jadeFILE "$ila \n";
}
}
sunmọ (INFILE);
sunmọ (OUTFILE);
} miran {
tẹjade “$ModelSim_run_do ko si. Atunse kikopa lẹẹkansi \n";
}
}

Eto Siemens QuestaSim/ Iṣeto SimdelBeere ibeere kan)

Ṣiṣe.ṣe files, ti ipilẹṣẹ nipasẹ Libero SoC fun awọn iṣeṣiro nipa lilo ModelSim Microsemi Editions, le ṣee lo fun awọn iṣeṣiro nipa lilo QuestaSim/ModelSim SE/DE/PE pẹlu iyipada kan. Ni ModelSim ME/ModelSim Pro ME run.do file, ipo ile-ikawe ti a ti ṣajọ tẹlẹ nilo lati yipada.
MICROCHIP Libero SoC Simulation Library Software - aami Pataki: 
Nipa aiyipada, ohun elo simulation miiran ju ModelSim Pro ME ṣe iṣapeye apẹrẹ lakoko simulation ti o le ni ipa hihan sinu awọn ohun-ọṣọ simulation gẹgẹbi awọn nkan apẹrẹ ati iwuri titẹ sii.
Eyi ṣe iranlọwọ ni igbagbogbo ni idinku akoko ṣiṣe iṣeṣiro fun awọn iṣeṣiro ti o nipọn, ni lilo ọrọ-ọrọ, awọn benches idanwo ti ara ẹni. Bibẹẹkọ, awọn iṣapeye aiyipada le ma ṣe deede fun gbogbo awọn iṣeṣiro, pataki ni awọn ọran nibiti o nireti lati ṣayẹwo ni ayaworan awọn abajade iṣeṣiro nipa lilo ferese igbi.
Lati koju awọn ọran ti o ṣẹlẹ nipasẹ iṣapeye yii, o gbọdọ ṣafikun awọn aṣẹ ti o yẹ ati awọn ariyanjiyan ti o jọmọ lakoko simulation lati mu pada hihan sinu apẹrẹ. Fun awọn aṣẹ irinṣẹ-pato, wo iwe ti ẹrọ simulator ni lilo.

5.1 Awọn iyipada Ayika (Beere ibeere kan)
Atẹle ni awọn oniyipada ayika ti a beere.

  • LM_LICENSE_FILE: gbọdọ ni ọna si iwe-aṣẹ file.
  • MODEL_TECH: gbọdọ ṣe idanimọ ọna si ipo ilana ile ti fifi sori QuestaSim.
  • PATH: gbọdọ tọka si ipo iṣẹ ṣiṣe ti MODEL_TECH tọka si.

5.2 Yiyipada run.do fun Mentor QuestaSim (Beere ibeere kan)
Ṣiṣe.ṣe files ti ipilẹṣẹ nipasẹ Libero SoC fun awọn iṣeṣiro lilo ModelSim Microsemi Editions le ṣee lo fun awọn iṣeṣiro nipa lilo QuestaSim/ModelSim_SE pẹlu iyipada kan.
MICROCHIP Libero SoC Simulation Library Software - aami Pataki: Gbogbo awọn apẹrẹ ti a ṣe simulated nipa lilo QuestaSim gbọdọ pẹlu -novopt
aṣayan pẹlu aṣẹ vsim ni iwe afọwọkọ run.do files.
5.3 Ṣe igbasilẹ Ile-ikawe Iṣakojọ (Beere ibeere kan)
Ṣe igbasilẹ awọn ile-ikawe fun Mentor Graphics QuestaSim lati Microsemi's webojula.

Iṣeto VCS Synopsys (Beere ibeere kan)

Sisan ti a ṣeduro nipasẹ Microsemi gbarale ṣiṣan Elaborate ati Compile ni VCS. Iwe yii pẹlu iwe afọwọkọ kan file ti o nlo run.do akosile files ti ipilẹṣẹ nipasẹ Libero SoC ati ipilẹṣẹ iṣeto files nilo fun kikopa VCS. Iwe afọwọkọ naa file nlo run.do file lati ṣe awọn wọnyi.

  • Ṣẹda aworan agbaye file, eyi ti o ti ṣe nipa lilo synopsys_sim.setup file be ni kanna liana ibi ti VCS kikopa ti wa ni nṣiṣẹ.
  • Ṣẹda iwe afọwọkọ ikarahun file lati ṣe alaye ati ṣajọ apẹrẹ rẹ nipa lilo VCS.

6.1 Awọn iyipada Ayika (Beere ibeere kan)
Ṣeto awọn oniyipada ayika ti o yẹ fun VCS da lori iṣeto rẹ. Awọn oniyipada ayika nilo gẹgẹ bi iwe VCS jẹ:

  • LM_LICENSE_FILE: gbọdọ ni itọka si olupin iwe-aṣẹ.
  • VCS_HOME: gbọdọ tọka si ipo itọsọna ile ti fifi sori VCS.
  • PATH: gbọdọ ni itọka si iwe-ilana bin ni isalẹ itọsọna VCS_HOME.

6.2 Ṣe igbasilẹ Ile-ikawe Iṣakojọ (Beere ibeere kan)
Ṣe igbasilẹ awọn ile-ikawe fun Synopsys VCS lati Microsemi's webojula.
6.3 VCS Simulation akosile File (Beere ibeere kan)
Lẹhin ti ṣeto VCS ati ipilẹṣẹ apẹrẹ ati ṣiṣe oriṣiriṣi.do files lati Libero SoC, o gbọdọ:

  1. Ṣẹda aworan agbaye file synopsys_sim.setup; eyi file ni awọn itọka si ipo ti gbogbo awọn ile-ikawe lati ṣee lo nipasẹ apẹrẹ.
    MICROCHIP Libero SoC Simulation Library Software - aami  Pataki: Awọn file orukọ ko gbọdọ yipada ati pe o gbọdọ wa ni itọsọna kanna nibiti kikopa nṣiṣẹ. Eyi jẹ ẹya Mofiample fun iru a file fun kikopa presynthesis.
    IṢẸ > AṢẸ
    SmartFusion2:
    presynth: ./presynth
    DEFAUT: ./iṣẹ
  2. Ṣe alaye apẹrẹ ti o yatọ files, pẹlu testbench, lilo vlogan pipaṣẹ ni VCS. Awọn aṣẹ wọnyi le wa ninu iwe afọwọkọ ikarahun kan file. Atẹle jẹ ẹya Mofiample ti awọn ofin ti o nilo lati ṣe alaye asọye apẹrẹ kan ni rtl.v pẹlu testbench rẹ ti ṣalaye ni
    testbench.v.
    vlogan + v2k -iṣẹ presynth rtl.v
    vlogan + v2k -iṣẹ presynth testbench.v
  3. Ṣe akopọ apẹrẹ nipa lilo VCS nipa lilo pipaṣẹ atẹle.
    vcs –sim_res=1fs presynth.testbench
    Akiyesi: Awọn ipinnu akoko ti kikopa gbọdọ wa ni ṣeto si 1fs fun kikopa iṣẹ ṣiṣe ti o tọ.
  4. Ni kete ti a ti ṣajọ apẹrẹ naa, bẹrẹ kikopa nipa lilo pipaṣẹ atẹle.
    ./simv
  5. Fun kikopa ti a ṣe alaye-pada, aṣẹ VCS gbọdọ jẹ bi o ṣe han ninu koodu idilọwọ atẹle.
    vcs postlayout.testbench –sim_res=1fs –sdf max: .
    orukọ >: file ona> –gui –l postlayout.log

6.4 Awọn idiwọn / Awọn imukuro (Beere ibeere kan)
Atẹle ni awọn idiwọn/awọn imukuro ti iṣeto Synopsys VCS.

  • Awọn iṣeṣiro VCS le ṣee ṣiṣẹ nikan fun awọn iṣẹ akanṣe Verilog ti Libero SoC. Simulator VCS ni awọn ibeere ede VHDL ti o muna ti ko ni ibamu nipasẹ Libero SoC ti ipilẹṣẹ VHDL adaṣe files.
  • O gbọdọ ni alaye ipari $ ni Verilog testbench lati da simulation naa duro nigbakugba ti o ba fẹ.
    MICROCHIP Libero SoC Simulation Library Software - aami Pataki: Nigbawo iṣeṣiro ti wa ni ṣiṣe ni GUI mode, run akoko le ti wa ni pato ninu awọn GUI.

Ọdun 6.5 Sample Tcl ati Shell akosile Files (Beere ibeere kan)
Awọn wọnyi Perl automates awọn iran ti synopsys_sim.setup file bakanna bi iwe afọwọkọ ikarahun ti o baamu files nilo lati ṣe alaye lẹkunrẹrẹ, ṣajọ, ati ṣe adaṣe apẹrẹ naa.
Ti apẹrẹ ba nlo MSS, daakọ test.vec file ti o wa ninu folda kikopa ti iṣẹ akanṣe Libero SoC sinu folda kikopa VCS. Awọn apakan atẹle ni awọn s ninuample run.do files ti ipilẹṣẹ nipasẹ Libero SoC, pẹlu awọn ti o baamu ìkàwé maapu ati ikarahun akosile files nilo fun kikopa VCS.
6.5.1 Iṣaaju iṣaju (Beere ibeere kan)
Presynth_run.do
laiparuwo ṣeto ACTELLIBNAME SmartFusion2
ni idakẹjẹ ṣeto PROJECT_DIR "/sqa/users/me/VCS_Tests/Test_DFF"
ti {[file presynth/_info wa]} {
iwoyi “INFO: Presynth ikawe Simulation ti wa tẹlẹ”
} miran {
vlib presynth
}
vmap presynth presynth
vmap SmartFusion2 “/captures/lin/11_0_0_23_11prod/lib/ModelSim/precompiled/vlog/smartfusion2”
vlog -work presynth "${PROJECT_DIR}/component/work/SD1/SD1.v"
vlog “+incdir+${PROJECT_DIR}/ikunra” -iṣẹ presynth “${PROJECT_DIR}/stimulus/SD1_TB1.v”
vsim -L SmartFusion2 -L presynth -t 1fs presynth.SD1_TB1
fi igbi kun / SD1_TB1/*
fi log -r /*
ṣiṣe 1000ns
presynth_main.csh
#!/bin/csh -f
ṣeto PROJECT_DIR = "/sqa/users/Me/VCS_Tests/Test_DFF"
/cad_design/tools/vcs.dir/E-2011.03/bin/vlogan +v2k -iṣẹ presynth “${PROJECT_DIR}/component/
iṣẹ/SD1/SD1.v”
/cad_design/tools/vcs.dir/E-2011.03/bin/vlogan +v2k “+incdir+${PROJECT_DIR}/stimulus” -iṣẹ
presynth “${PROJECT_DIR}/stimulus/SD1_TB1.v”
/cad_design/tools/vcs.dir/E-2011.03/bin/vcs -sim_res=1fs presynth.SD1_TB1 -l compile.log
./simv -l run.log
Synopsys_sim.setup
IṢẸ> ALAIKỌ
SmartFusion2: /VCS/SmartFusion2
presynth: ./presynth
DEFAUT: ./iṣẹ

6.5.2 Lẹhin-sọpọ (Beere ibeere kan)
postsynth_run.do
laiparuwo ṣeto ACTELLIBNAME SmartFusion2
ni idakẹjẹ ṣeto PROJECT_DIR "/sqa/users/Me/VCS_Tests/Test_DFF"
ti {[file wa postsynth/_info]} {
iwoyi "INFO: Awọn iwe-ikawe Simulation postsynth ti wa tẹlẹ"
} miran {
vlib postsynth
}
vmap postsynth postsynth
vmap SmartFusion2 “//idm/captures/pc/11_0_1_12_g4x/Designer/lib/ModelSim/precompiled/vlog/
SmartFusion2”
vlog -work postsynth "${PROJECT_DIR}/synthesis/SD1.v"
vlog “+incdir+${PROJECT_DIR}/atunkun” -work postsynth “${PROJECT_DIR}/stimulus/SD1_TB1.v”
vsim -L SmartFusion2 -L postsynth -t 1fs postsynth.SD1_TB1
fi igbi kun / SD1_TB1/*
fi log -r /*
ṣiṣe 1000ns
wọle SD1_TB1/*
Jade
Postsynth_main.csh
#!/bin/csh -f
ṣeto PROJECT_DIR = "/sqa/users/Me/VCS_Tests/Test_DFF"
/cad_design/tools/vcs.dir/E-2011.03/bin/vlogan +v2k -work postsynth “${PROJECT_DIR}/synthesis/
SD1.v”
/cad_design/tools/vcs.dir/E-2011.03/bin/vlogan +v2k “+incdir+${PROJECT_DIR}/stimulus” -iṣẹ
postsynth "${PROJECT_DIR}/stimulus/SD1_TB1.v"
/cad_design/tools/vcs.dir/E-2011.03/bin/vcs -sim_res=1fs postsynth.SD1_TB1 -l compile.log
./simv -l run.log
Synopsys_sim.setup
IṢẸ> ALAIKỌ
SmartFusion2: /VCS/SmartFusion2
postsynth: ./postsynth
DEFAUT: ./iṣẹ
6.5.3 Ifilelẹ-lẹhin (Beere ibeere kan)
postlayout_run.do
laiparuwo ṣeto ACTELLIBNAME SmartFusion2
ni idakẹjẹ ṣeto PROJECT_DIR "E:/ModelSim_Work/Test_DFF"
ti {[file wa ../designer/SD1/simulation/postlayout/_info]} {
iwoyi “INFO: Ile-ikawe Simulation ../Designer/SD1/simulation/postlayout tẹlẹ wa”
} miran {
vlib ../ onise/SD1/simulation/postlayout
}
vmap postlayout ../ onise/SD1/simulation/postlayout
vmap SmartFusion2 “//idm/captures/pc/11_0_1_12_g4x/Designer/lib/ModelSim/precompiled/vlog/
SmartFusion2”
vlog -iṣẹ ifiweranṣẹ “${PROJECT_DIR}/apẹrẹ/SD1/SD1_ba.v”
vlog “+incdir+${PROJECT_DIR}/ikunju” -ipinjade iṣẹ “${PROJECT_DIR}/stimulus/SD1_TB1.v”
vsim -L SmartFusion2 -L postlayout -t 1fs -sdfmax /SD1_0=${PROJECT_DIR}/designer/SD1/
SD1_ba.sdf postlayout.SD1_TB1
fi igbi kun / SD1_TB1/*
fi log -r /*
ṣiṣe 1000ns
Postlayout_main.csh
#!/bin/csh -f
ṣeto PROJECT_DIR = "/VCS_Tests/Test_DFF"
/cad_design/tools/vcs.dir/E-2011.03/bin/vlogan +v2k -work postlayout “${PROJECT_DIR}/
onise/SD1/SD1_ba.v”
/cad_design/tools/vcs.dir/E-2011.03/bin/vlogan +v2k “+incdir+${PROJECT_DIR}/stimulus” -iṣẹ
postlayout “${PROJECT_DIR}/stimulus/SD1_TB1.v”
/cad_design/tools/vcs.dir/E-2011.03/bin/vcs -sim_res=1fs postlayout.SD1_TB1 -sdf

max:SD1_TB1.SD1_0:${PROJECT_DIR}/designer/SD1/SD1_ba.sdf -l compile.log
./simv -l run.log
Synopsys_sim.setup
IṢẸ> ALAIKỌ
SmartFusion2: /VCS/SmartFusion2
postlayout: ./postlayout
DEFAULT: ./workVCS
6.6 adaṣe (Beere ibeere kan)
Awọn sisan le ti wa ni aládàáṣiṣẹ lilo awọn wọnyi Perl akosile file lati yi ModelSim run.do pada files sinu iwe afọwọkọ ikarahun ibaramu VCS files, ṣẹda awọn ilana to dara inu iwe ilana kikopa Libero SoC, ati lẹhinna ṣiṣe awọn iṣeṣiro.
Ṣiṣe awọn akosile file lilo awọn wọnyi sintasi.
perl vcs_parse.pl presynth_run.do postsynth_run.do postlayout_run.do
Vcs_parse_pl
#!/usr/bin/perl -w
################################################### ########################
#
#Lilo: perl vcs_parse.pl presynth_run.do postsynth_run.do postlayout_run.do
#
################################################### #########################
mi ($presynth, $postsynth, $ postlayout) = @ARGV;
ti (eto ("mkdir VCS_Presynth")) {titẹ sita "mkdir kuna:\n";}
ti (eto ("mkdir VCS_Postsynth")) {titẹ sita "mkdir kuna:\n";}
ti (eto ("mkdir VCS_Postlayout")) {titẹ sita "mkdir kuna:\n";}
chdir (VCS_Presynth);
`cp ../$ARGV[0] .` ;
&parse_do ($ presynth,” presynth”);
chdir ("../");
chdir (VCS_Postsynth);
`cp ../$ARGV[1] .` ;
&parse_do ($ postsynth,” postsynth”);
chdir ("../");
chdir (VCS_Postlayout);
`cp ../$ARGV[2] .` ;
&parse_do ($ postlayout,” postlayout”);
chdir ("../");
abala parse_do {
my $vlog = "/cad_design/tools/vcs.dir/E-2011.03/bin/vlogan +v2k";
mi% LIB = ();
mi $file = $__[0];
ipinle $ mi = $_[1];
ṣii (INFILE,”$file”) || kú “Ko le ṣii File Idi le jẹ:$!";
ti ($state eq “presynth”)
{
ṣii (OUT1,”>presynth_main.csh”) || kú “Ko le ṣẹda pipaṣẹ File Idi le jẹ:$!";
}
elsif ($state eq “postsynth”)
{
ṣii (OUT1,”> postsynth_main.csh”) || kú “Ko le ṣẹda pipaṣẹ File Idi le jẹ:$!";
}
elsif ($state eq “ipinjade ifiweranṣẹ”)
{
ṣii (OUT1,”> postlayout_main.csh”) || kú “Ko le ṣẹda pipaṣẹ File Idi le jẹ:$!";
}
miiran
{
tẹjade “Ipinlẹ Simulation ti nsọnu \n” ;
}
ìmọ (OUT2,”> synopsys_sim.setup”) || kú “Ko le ṣẹda pipaṣẹ File Idi le jẹ:$!";
# .csh file
sita OUT1 "#!/bin/csh -f\n\n\n" ;
#ṢETO FILE
tẹjade OUT2 “IṢẸ > DEFAULT\n” ;
tẹjade OUT2 “SmartFusion2: /sqa/users/Aditya/VCS/SmartFusion2\n”;
nigba ($ ila =FILE>)
{

Synopsys VCS Oṣo

ti o ba ti ($ ila =~ m/dakẹjẹ ṣeto PROJECT_DIR\s+\"(.*?)\"/)
{
print OUT1 “set PROJECT_DIR = \”$1\”\n\n\n” ;
}
elsif ( $ila =~ m/vlog.*\.v\”/)
{
ti o ba jẹ ($ ila =~ m/\s+(\ w*?) \ _LIB/)
{
#tẹ̀wé “\$1 =$1 \n” ;
$temp = "$1″."_LIB";
# tẹjade "Temp = $temp \n" ;
$LIB{$temp}++;
}
chomp($ila);
$ila =~ s/^vlog/$vlog/ ;
$ila =~ s/ //g;
tẹjade OUT1 “$ila\n”;
}
elsif ( ($ ila =~ m/vsim. * presynth \. (.*)/) || ($ ila =~ m/vsim.*postsynth \ . (.*)/) || ($ ila
=~ m/vsim.*jade postlayout\.(.*)/) )
{
$tb = $1;
$tb = ~ s/ // g;
chomp($tb);
#tẹ̀wé “Orúkọ TB : $tb \n”;
ti ($ila =~ m/sdf(.*)\.sdf/)
{
chomp($ila);
$ila = $1;
#tẹ̀wé “LINE : $line \n” ;
ti o ba jẹ ($ ila = ~ m/max/)
{
$ila =~ s/max \/// ;
$ila =~ s/=/:/;
sita OUT1 "\n\n/cad_design/tools/vcs.dir/E-2011.03/bin/vcs -sim_res=1fs postlayout.$tb -sdf
max:$tb.$line.sdf -l compile.log\n” ;
}
elsif ($ila =~ m/min/)
{
$ila =~ s/min \/// ;
$ila =~ s/=/:/;
sita OUT1 "\n\n/cad_design/tools/vcs.dir/E-2011.03/bin/vcs -sim_res=1fs postlayout.$tb -sdf
min:$tb.$line.sdf -l compile.log\n” ;
}
elsif ($ila =~ m/type/)
{
$ila =~ s/type \/// ;
$ila =~ s/=/:/;
sita OUT1 "\n\n/cad_design/tools/vcs.dir/E-2011.03/bin/vcs -sim_res=1fs postlayout.$tb -sdf
tẹ:$tb.$line.sdf -l compile.log\n” ;
}
#-sdfmax /M3_FIC32_0=${PROJECT_DIR}/apẹrẹ/M3_FIC32/M3_FIC32_ba.sdf — AwoṣeSim SDF
#$sdf = "-sdf max: testbench.M3_FIC32_0:${PROJECT_DIR}/designer/M3_FIC32/M3_FIC32_ba.sdf"; -VCS
SDF kika
}
}
}
titẹ sita
OUT1 "\n\n"
;
if
($state eq “presynth”
)
{
titẹ sita
OUT2 “presynth
: ./presynth\n”
;
titẹ sita
OUT1 “/cad_design/tools/vcs.dir/E-2011.03/bin/vcs
-sim_res=1fs presynth.$tb -l
compile.log\n”
;
}
elsif
($state eq “postsynth”
)
{
titẹ sita
OUT2 “postsynth
: ./postsynth\n”
;
titẹ sita
OUT1 “/cad_design/tools/vcs.dir/E-2011.03/bin/vcs
-sim_res=1fs postsynth.$tb -l
compile.log\n”
;
}
elsif
($state eq “ipinjade ifiweranṣẹ”
)
{
sita OUT2 “postlayout: ./postlayout\n”;
}
miiran
{
tẹjade “Ipinlẹ Simulation ti nsọnu \n” ;
}
ṣaaju $i (awọn bọtini %LIB)
{
#tẹ̀wé "Kọ́kọ́rọ́ : $i Iye: $LIB{$i} \n" ;
tẹjade OUT2 “$i : ./$i\n” ;
}
tẹjade OUT1 “\n\n” ;
tẹjade OUT1 “./simv -l run.log\n” ;
sita OUT2 "DEFAULT : ./work\n" ;
sunmọ INFILE;
sunmọ OUT1;
sunmọ OUT2;
}

Itan Atunyẹwo (Microchip Wọle

Itan atunyẹwo ṣe apejuwe awọn iyipada ti a ṣe imuse ninu iwe-ipamọ naa. Awọn iyipada
ti wa ni akojọ nipasẹ àtúnyẹwò, ti o bere pẹlu awọn julọ lọwọlọwọ atejade.

Àtúnyẹwò Ọjọ Apejuwe
A 12/2023 Awọn ayipada wọnyi ni a ṣe ninu atunyẹwo yii:
• Iwe iyipada si awoṣe Microchip. Atunyẹwo akọkọ.
• Abala imudojuiwọn 5. Siemens QuestaSim Setup/ModelSim Setup lati ni akọsilẹ titun kan ti o ṣe alaye ipa lori hihan lakoko kikopa ati iṣapeye.

Microchip FPGA Support
Ẹgbẹ awọn ọja Microchip FPGA ṣe atilẹyin awọn ọja rẹ pẹlu ọpọlọpọ awọn iṣẹ atilẹyin, pẹlu Iṣẹ alabara, Ile-iṣẹ Atilẹyin Imọ-ẹrọ Onibara, a webojula, ati ni agbaye tita ifiweranṣẹ.
A daba awọn alabara lati ṣabẹwo si awọn orisun ori ayelujara Microchip ṣaaju kikan si atilẹyin nitori o ṣee ṣe pupọ pe awọn ibeere wọn ti ni idahun tẹlẹ.
Kan si Technical Support Center nipasẹ awọn webojula ni www.microchip.com/support. Darukọ nọmba Apakan Ẹrọ FPGA, yan ẹka ọran ti o yẹ, ati apẹrẹ ikojọpọ files lakoko ṣiṣẹda ọran atilẹyin imọ-ẹrọ.
Kan si Iṣẹ Onibara fun atilẹyin ọja ti kii ṣe imọ-ẹrọ, gẹgẹbi idiyele ọja, awọn iṣagbega ọja, alaye imudojuiwọn, ipo aṣẹ, ati aṣẹ.

  • Lati North America, pe 800.262.1060
  • Lati iyoku agbaye, pe 650.318.4460
  • Faksi, lati nibikibi ninu aye, 650.318.8044

Microchip Alaye
Microchip naa Webojula
Microchip pese atilẹyin ori ayelujara nipasẹ wa webojula ni www.microchip.com/. Eyi webojula ti wa ni lo lati ṣe files ati alaye awọn iṣọrọ wa si awọn onibara. Diẹ ninu akoonu ti o wa pẹlu:

  • Atilẹyin Ọja – Awọn iwe data ati errata, awọn akọsilẹ ohun elo ati sample eto, oniru oro, olumulo ká itọsọna ati hardware support awọn iwe aṣẹ, titun software tu ati ki o gbepamo software
  • Atilẹyin Imọ-ẹrọ Gbogbogbo - Awọn ibeere ti a beere nigbagbogbo (Awọn FAQ), awọn ibeere atilẹyin imọ-ẹrọ, awọn ẹgbẹ ijiroro lori ayelujara, atokọ awọn ọmọ ẹgbẹ eto alabaṣepọ apẹrẹ Microchip
  • Iṣowo ti Microchip - Aṣayan ọja ati awọn itọsọna aṣẹ, awọn idasilẹ atẹjade Microchip tuntun, atokọ ti awọn apejọ ati awọn iṣẹlẹ, awọn atokọ ti awọn ọfiisi tita Microchip, awọn olupin kaakiri ati awọn aṣoju ile-iṣẹ

Ọja Change iwifunni Service
Iṣẹ ifitonileti iyipada ọja Microchip ṣe iranlọwọ lati jẹ ki awọn alabara wa lọwọlọwọ lori awọn ọja Microchip. Awọn alabapin yoo gba ifitonileti imeeli nigbakugba ti awọn ayipada ba wa, awọn imudojuiwọn, awọn atunyẹwo tabi errata ti o ni ibatan si ẹbi ọja kan tabi ohun elo idagbasoke ti iwulo.
Lati forukọsilẹ, lọ si www.microchip.com/pcn ati tẹle awọn ilana iforukọsilẹ.
Onibara Support
Awọn olumulo ti awọn ọja Microchip le gba iranlọwọ nipasẹ awọn ikanni pupọ:

  • Olupin tabi Aṣoju
  • Agbegbe Sales Office
  • Onimọ-ẹrọ Awọn ojutu ti a fi sii (ESE)
  • Oluranlowo lati tun nkan se

Awọn onibara yẹ ki o kan si olupin wọn, aṣoju tabi ESE fun atilẹyin. Awọn ọfiisi tita agbegbe tun wa lati ṣe iranlọwọ fun awọn alabara. Atokọ ti awọn ọfiisi tita ati awọn ipo wa ninu iwe yii.
Imọ support wa nipasẹ awọn webojula ni: www.microchip.com/support
Ẹya Idaabobo koodu Awọn ẹrọ Microchip
Ṣe akiyesi awọn alaye atẹle ti ẹya aabo koodu lori awọn ọja Microchip:

  • Awọn ọja Microchip pade awọn pato ti o wa ninu Iwe Data Microchip pato wọn.
  • Microchip gbagbọ pe ẹbi ti awọn ọja wa ni aabo nigba lilo ni ọna ti a pinnu, laarin awọn pato iṣẹ, ati labẹ awọn ipo deede.
  • Awọn iye Microchip ati ibinu ṣe aabo awọn ẹtọ ohun-ini ọgbọn rẹ. Awọn igbiyanju lati irufin awọn ẹya aabo koodu ti ọja Microchip jẹ eewọ muna ati pe o le rú Ofin Aṣẹ-lori Ẹgbẹrun Ọdun Digital.
  • Bẹni Microchip tabi eyikeyi olupese semikondokito miiran le ṣe iṣeduro aabo koodu rẹ. Idaabobo koodu ko tumọ si pe a n ṣe iṣeduro ọja naa jẹ “aibikita”.
    Idaabobo koodu ti wa ni idagbasoke nigbagbogbo. Microchip ti pinnu lati ni ilọsiwaju nigbagbogbo awọn ẹya aabo koodu ti awọn ọja wa.

Ofin Akiyesi
Atẹjade yii ati alaye ti o wa ninu rẹ le ṣee lo pẹlu awọn ọja Microchip nikan, pẹlu lati ṣe apẹrẹ, idanwo, ati ṣepọ awọn ọja Microchip pẹlu ohun elo rẹ. Lilo alaye yii ni ọna miiran ti o lodi si awọn ofin wọnyi. Alaye nipa awọn ohun elo ẹrọ ti pese fun irọrun rẹ nikan ati pe o le rọpo nipasẹ awọn imudojuiwọn. O jẹ ojuṣe rẹ lati rii daju pe ohun elo rẹ ni ibamu pẹlu awọn pato rẹ. Kan si ọfiisi tita Microchip agbegbe rẹ fun atilẹyin afikun tabi, gba atilẹyin afikun ni www.microchip.com/en-us/support/design-help/client-support-services.
ALAYE YI NI MICROCHIP “BI O SE WA”. MICROCHIP KO SE Aṣoju TABI ATILẸYIN ỌJA TI IRU KANKAN BOYA KIAKIA TABI TỌRỌ, KỌ TABI ẹnu, Ilana tabi Bibẹkọkọ, ti o jọmọ ALAYE NAA SUGBON KO NI LOPIN SI KANKAN, LATI IKILỌ ỌRỌ, ÀTI IFỌRỌWỌRỌ FUN IDI PATAKI, TABI ATILẸYIN ỌJA TO JEmọ MAJEMU, Didara, TABI Iṣe Rẹ.
LAISI iṣẹlẹ ti yoo ṣe oniduro fun eyikeyi aiṣedeede, PATAKI, ijiya, ijamba, tabi ipadanu, bibajẹ, iye owo, tabi inawo ti eyikeyi iru ohunkohun ti o jọmọ si awọn alaye tabi ti o ti gba, ti o ba ti lo, Ti a gbaniyanju nipa Seese TABI awọn bibajẹ ni o wa tẹlẹ. SI AWỌN NIPA NIPA NIPA TI OFIN, LAPAPA LAPAPO MICROCHIP LORI Gbogbo awọn ẹtọ ni eyikeyi ọna ti o jọmọ ALAYE TABI LILO RE KO NI JU OPO ỌWỌ, TI O BA KAN, PE O TI ṢAN NIPA TODAJU SIROMỌ.
Lilo awọn ẹrọ Microchip ni atilẹyin igbesi aye ati/tabi awọn ohun elo aabo jẹ patapata ni ewu olura, ati pe olura gba lati daabobo, ṣe idalẹbi ati dimu Microchip ti ko lewu lati eyikeyi ati gbogbo awọn bibajẹ, awọn ẹtọ, awọn ipele, tabi awọn inawo ti o waye lati iru lilo. Ko si awọn iwe-aṣẹ ti a gbe lọ, laisọtọ tabi bibẹẹkọ, labẹ eyikeyi awọn ẹtọ ohun-ini imọ Microchip ayafi bibẹẹkọ ti sọ.
Awọn aami-išowo
Orukọ Microchip ati aami, aami Microchip, Adaptec, AVR, AVR logo, AVR Freaks, BestTime, BitCloud, CryptoMemory, CryptoRF, dsPIC, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXSty MediaLB, megaAVR, Microsemi, Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, logo PIC32, PolarFire, Prochip Designer, QTouch, SAM-BA, Segenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetricom , SyncServer, Tachyon, TimeSource, tinyAVR, UNI/O, Vectron, ati XMEGA jẹ aami-išowo ti a forukọsilẹ ti Microchip Technology Incorporated ni AMẸRIKA ati awọn orilẹ-ede miiran.
AgileSwitch, APT, ClockWorks, Ile-iṣẹ Awọn Solusan Iṣakoso ti a fi sinu, EtherSynch, Flashtec, Iṣakoso Iyara Hyper, Load HyperLight, Libero, motorBench, mTouch, Powermite 3, Edge Precision, ProASIC, ProASIC Plus, ProASIC Plus logo, Idakẹjẹ- Waya, SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub, TimePictra, TimeProvider, TrueTime, ati ZL jẹ aami-išowo ti a forukọsilẹ ti Microchip Technology Incorporated ni AMẸRIKA
Imukuro Bọtini nitosi, AKS, Analog-fun-The-Digital Age, Eyikeyi Kapasito, AnyIn, AnyOut, Yipada Augmented, BlueSky, BodyCom, Clockstudio, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM Average, Matching Nẹtiwọọki. , DAM, ECAN, Espresso T1S, EtherGREEN, GridTime, IdealBridge, In-Circuit Serial Programming, ICSP, INICnet, Intelligent Paralleling, IntelliMOS, Inter-Chip Asopọmọra, JitterBlocker, Knob-on-Display, KoD, maxCrypto, maxView, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB aami ifọwọsi, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net,
PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, GIDI yinyin, Ripple Blocker, RTAX, RTG4, SAMICE, Serial Quad I/O, simpleMAP, SimpliPHY, SmartBuffer, SmartHLS, SMART-IS, storClad, SQI, SuperSwitcher,
SuperSwitcher II, Switchtec, SynchroPHY, Apapọ Ifarada, Akoko igbẹkẹle, TSHARC, USBCheck, VariSense, VectorBlox, VeriPHY, ViewSpan, WiperLock, XpressConnect, ati ZENA jẹ aami-iṣowo ti Microchip Technology Incorporated
ni AMẸRIKA ati awọn orilẹ-ede miiran.
SQTP jẹ aami iṣẹ ti Microchip Technology Incorporated ni AMẸRIKA
Aami Adaptec, Igbohunsafẹfẹ lori Ibeere, Imọ-ẹrọ Ibi ipamọ Silicon, ati Symmcom jẹ aami-išowo ti a forukọsilẹ ti Microchip Technology Inc. ni awọn orilẹ-ede miiran.
GestIC jẹ aami-iṣowo ti a forukọsilẹ ti Microchip Technology Germany II GmbH & Co.KG, oniranlọwọ ti Microchip Technology Inc., ni awọn orilẹ-ede miiran.
Gbogbo awọn aami-iṣowo miiran ti a mẹnuba ninu rẹ jẹ ohun-ini ti awọn ile-iṣẹ wọn.
© 2023, Microchip Technology Incorporated ati awọn ẹka rẹ. Gbogbo awọn ẹtọ wa ni ipamọ.
ISBN: 978-1-6683-3694-6
Didara Management System
Fun alaye nipa Awọn ọna iṣakoso Didara Microchip, jọwọ ṣabẹwo www.microchip.com/quality.

AMERIKA ASIA/PACIFIC ASIA/PACIFIC EUROPE
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www.microchip.com
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MICROCHIP Libero SoC Simulation Library Software [pdf] Itọsọna olumulo
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