Libero SoC Simulation
Ntuziaka nhazi ụlọ akwụkwọ

Okwu mmalite

(Jụọ ajụjụ)

Ebumnuche nke akwụkwọ a bụ ịkọwa usoro iji guzobe gburugburu ịme anwansị site na iji ọrụ Libero SoC dị ka ntinye. Akwụkwọ a dabara na ọba akwụkwọ achịkọtaburu ewepụtara maka ojiji ya na Libero SoC v11.9 na mwepụta sọftụwia ọhụrụ. Achịkọtara ọba akwụkwọ ndị enyere maka Verilog. Ndị ọrụ VHDL chọrọ ikikere na-enye ohere ịme simulụ agwakọta.
Ọbá akwụkwọ simulation achịkọtara dị maka ngwaọrụ ndị a:

• Aldec Active-HDL
• Aldec Riviera-PRO
• Cadence Incisive Enterprise na Xcelium
• Siemens QuestaSim
• Akụkọ ihe mere eme nke VCS

Iji rịọ ụlọ akwụkwọ maka simulator dị iche, kpọtụrụ Nkwado nka na ụzụ Microchip.

Njikọ nke Libero SoC

(Jụọ ajụjụ)

Libero SoC na-akwado ịme anwansị iji ModelSim ME site na ịmepụta run.do file. Nke a file A na-eji ModelSim ME/ModelSim Pro ME hazie ma mee ihe ngosi ahụ. Iji jiri ngwaọrụ ịme anwansị ndị ọzọ, ị nwere ike ịmepụta ModelSim ME/ModelSim Pro ME run.do wee gbanwee edemede Tcl. file iji iwu dakọtara na simulator gị.
1.1 Libero SoC Tcl File Ọgbọ (Jụọ ajụjụ)
Mgbe imepụtachara na imepụta imewe na Libero SoC, bido simulation ModelSim ME/ModelSim Pro ME n'okpuru usoro nhazi niile (presynth, postsynth, na post-layout). Nzọụkwụ a na-ebute run.do file maka ModelSim ME / ModelSim Pro ME maka usoro nhazi ọ bụla.
Ihe dị mkpa: Mgbe ịmalitere ọsọ simulation ọ bụla, nyegharịa run.do nke emepụtara onwe ya aha file n'okpuru ndekọ simulation iji gbochie Libero SoC idegharị nke ahụ file. Maka example, ndị fileEnwere ike ịnyegharị s ka ọ bụrụ presynth_run.do, postsynth_run.do na postlayout_run.do.

Ntọala Aldec maka Active-HDL na Riviera-Pro (Jụọ ajụjụ)

The ọsọ.do file ModelSim ME/ModelSim Pro ME nke ModelSim ME/ModelSim Pro ME na-eji nwere ike gbanwee ma jiri ya mee ihe n'iji simulators Aldec.
2.1 gburugburu gburugburu (Jụọ ajụjụ)
Tọọ mgbanwe gburugburu gị na ikike gị file ebe:
LM_LICENSE_FILE: ga-etinyerịrị ntụnye aka na ihe nkesa ikike.
2.2 Budata ọba akwụkwọ chịkọtara (Jụọ ajụjụ)
Budata ọba akwụkwọ maka Aldec Active-HDL na Aldec Riviera-PRO site na Microchip websaịtị.
2.3 na-atụgharị run.do maka ịme anwansị Aldec (Jụọ ajụjụ)
The ọsọ.do files nke Libero SoC na-emepụta maka ịme anwansị iji Active-HDL na ngwá ọrụ Riviera-Pro nwere ike iji mee ihe ngosi site na iji Active-HDL na Riviera-Pro na otu mgbanwe. Tebụlụ na-esote depụtara iwu Aldec dakọtara iji gbanwee na ModelSim run.do file.
Isiokwu 2-1. Iwu Aldec Dakọtara

ModelSim	Arụ ọrụ-HDL
vlog	alog
vcom	acom
vlib	alib
vsim	asim
vmap	amap

Na-esonụ bụ dị kaample run.do metụtara Aldec simulators.

1. Tọọ ebe akwụkwọ ndekọ aha na-arụ ọrụ ugbu a.
   tọọ dsn
2. Tọọ aha ọba akwụkwọ na-arụ ọrụ, mapụta ebe ọ nọ, wee mapụta ebe ezinụlọ Microchip FPGA nọ
   ọba akwụkwọ achịkọtagoro (maka example, SmartFusion2) nke ị na-eme atụmatụ gị.
   alib presynth
   amap presynth presynth
   amap SmartFusion2
3. Chịkọta HDL niile dị mkpa files eji na imewe na achọrọ ọbá akwụkwọ.
   alog –work presynth temp.v (maka Verilog)
   alog – ọrụ presynth testbench.v
   acom –work presynth temp.vhd (maka Vhdl)
   acom – ọrụ presynth testbench.vhd
4. Mepụta atụmatụ ahụ.
   asim –L SmartFusion2 –L presynth –t 1ps presynth.testbench
   agba 10us

2.4 Okwu ndị ama ama (Jụọ ajụjụ)
Nkebi a na-edepụta ihe ama ama ama.

• Ọbá akwụkwọ achịkọtara site na iji Riviera-PRO bụ ikpo okwu akọwapụtara (ya bụ, ọba akwụkwọ 64-bit enweghị ike ịgba ọsọ n'elu ikpo okwu 32-bit yana ọzọ).
• Maka atụmatụ nwere SERDES/MDDR/FDDR, jiri nhọrọ a na run.do gị files ka ha na-eme simulations mgbe ha chịkọtachara atụmatụ ha:
  – HDL arụ ọrụ: asim –o2
  – Riviera-PRO: asim –O2 (maka presynth na post-layout simulations) na asim –O5 (maka simulations post- okirikiri nhọrọ ukwuu)
  Ntọala Aldec maka Active-HDL na Riviera-Pro nwere SAR ndị a na-echere. Maka ozi ndị ọzọ, kpọtụrụ Nkwado nka na ụzụ Microchip.
• SAR 49908 - HDL na-arụ ọrụ: Njehie VHDL maka ịme anwansị mgbochi mgbakọ na mwepụ
• SAR 50627 - Riviera-PRO 2013.02: Njehie ịme anwansị maka atụmatụ SErdES
• SAR 50461 – Riviera-PRO: asim -O2/-O5 nhọrọ na simulations.

Ntọala mkpali Cadence (Jụọ ajụjụ)

Ịkwesịrị ịmepụta edemede file yiri ModelSim ME/ModelSim Pro ME run.do iji na-agba ọsọ
Cadence Incisive simulator. Soro usoro ndị a wee mepụta edemede file maka NCSim ma ọ bụ jiri edemede file
enyere iji tọghata ModelSim ME/ModelSim Pro ME run.do files n'ime nhazi files
achọrọ iji NCsim mee ihe ngosi ahụ.
Ihe dị mkpa:  Cadence akwụsịla iwepụta ụdịdị Insiive Enterprise ọhụrụ
simulator wee malite ịkwado simulator Xcelium.

3.1 Mgbanwe gburugburuJụọ ajụjụ)
Iji mee simulator Cadence Incisive, hazie mgbanwe gburugburu ebe a:

1. LM_LICENSE_FILE: ga-etinyerịrị ntụnye aka na ikikere file.
2. cds_root: ga-arụtụ aka na ebe ndekọ ụlọ nke nwụnye Cadence Incisive.
3. PATH: ga-arụtụ aka na ebe a na-edebe ihe n'okpuru akwụkwọ ndekọ aha nke cds_root rụtụrụ aka ya bụ,
   $cds_root/ngwaọrụ/bin/64bit (maka igwe 64-bit na $cds_root/ngwaọrụ/bin maka igwe 32-bit).
   Enwere ụzọ atọ iji melite gburugburu ịme anwansị ma ọ bụrụ na mgbanwe n'etiti sistemụ arụmọrụ 64-bit na 32-bit:

Ikpe 1: PATH mgbanwe
Gbaa iwu a:
set ụzọ = (install_dir / ngwaọrụ / bin / 64bit $ ụzọ) maka 64bit igwe na
set ụzọ = (install_dir / ngwaọrụ / bin $ ụzọ) maka 32bit igwe
Ikpe 2: Iji -64bit Command-line Nhọrọ
N'ahịrị iwu ezipụta -64bit nhọrọ iji kpọọ 64bit executable.
Ikpe 3: Ịtọ ntọala INCA_64BIT ma ọ bụ CDS_AUTO_64BIT Gburugburu
A na-emeso mgbanwe INCA_64BIT dị ka onye na-agba ọsọ. Ị nwere ike ịtọ mgbanwe a na uru ọ bụla ma ọ bụ na eriri efu.
setenv INCA_64BIT

Ihe dị mkpa: INCA_64BIT mgbanwe gburugburu anaghị emetụta ngwaọrụ Cadence ndị ọzọ, dị ka ngwaọrụ IC. Agbanyeghị, maka ngwaọrụ Incisiive, mgbanwe INCA_64BIT na-ewepụ ntọala maka mgbanwe gburugburu CDS_AUTO_64BIT. Ọ bụrụ na edobere INCA_64BIT mgbanwe gburugburu ebe obibi, ngwaọrụ Insiive niile na-agba na ọnọdụ 64-bit. setenv CDS_AUTO_64BIT gụnyere:INCA
Ihe dị mkpa: eriri INCA ga-abụrịrị na mkpụrụedemede ukwu. A ga-emerịrị ihe omume niile n'ụdị 32-bit ma ọ bụ na ọnọdụ 64-bit, etinyela mgbanwe ahụ ka ọ tinye otu executable, dị ka ndị a:
setenv CDS_AUTO_64BIT gụnyere:ncelab

Ngwa Cadence ndị ọzọ, dị ka ngwaọrụ IC, na-ejikwa CDS_AUTO_64BIT mgbanwe gburugburu ebe obibi iji jikwaa nhọrọ nke 32-bit ma ọ bụ 64-bit executables. Tebụlụ na-esonụ na-egosi otu ị ga-esi tọọ mgbanwe CDS_AUTO_64BIT iji mee ngwa ngwa Insiive na ngwaọrụ IC n'ụdị niile.
Isiokwu 3-1. CDS_AUTO_64BIT mgbanwe

CDS_AUTO_64BIT dị iche iche	Ngwa ngwa ngwa	Ngwa IC
setenv CDS_AUTO_64BIT niile	64 bit	64 bit
setenv CDS_AUTO_64BIT Ọ BỤGHỊ	32 bit	32 bit
setenv CDS_AUTO_64BIT EXCLUDE:ic_binary	64 bit	32 bit
setenv CDS_AUTO_64BIT EXCLUDE:INCA	32 bit	64 bit

Ihe dị mkpa: Ngwa mkpali niile ga-agbarịrị n'ụdị 32-bit ma ọ bụ na ọnọdụ 64-bit, ejila EXCLUDE wepụ otu arụrụ arụ ọrụ, dịka na nke a: setenv CDS_AUTO_64BIT EXCLUDE:ncelab
Ọ bụrụ na ịtọọ mgbanwe CDS_AUTO_64BIT ka ewepu ngwa ọrụ Insiive (setenv CDS_AUTO_64BIT EXCLUDE:INCA), ngwaọrụ mkpado niile na-agba na ọnọdụ 32-bit. Agbanyeghị, nhọrọ ahịrị iwu -64bit na-ewepụ mgbanwe gburugburu ebe obibi.
Nhazi na-esonụ fileỌ na-enyere gị aka ijikwa data gị ma jikwaa ọrụ nke ngwa simulation na akụrụngwa:

• Maapụ ụlọ akwụkwọ file (cds.lib)—Na-akọwapụta aha ezi uche dị na ya maka ebe imewe gị.
• Ọbá akwụkwọ na-ejikọta ha na aha ndekọ anụ ahụ.
• Mgbanwe file (hdl.var) - Akọwapụta mgbanwe ndị na-emetụta omume nke ngwa simulation na akụrụngwa.

3.2 Budata ọba akwụkwọ chịkọtara (Jụọ ajụjụ)
Budata ọba akwụkwọ maka Cadence Incisive site na Microsemi's websaịtị.
3.3 Mepụta Ederede NCSim File (Jụọ ajụjụ)
Mgbe ịmepụtara otu nke run.do files, mee usoro ndị a iji jiri NCsim mee simulation gị:

1. Mepụta cds.lib file nke na-akọwa ọba akwụkwọ ndị a na-enweta na ebe ha nọ. Nke file nwere nkwupụta ndị na-edepụta aha ndị ezi uche dị na ya n'ụzọ akwụkwọ ndekọ aha ha. Maka example, ọ bụrụ na ị na-agba presynth simulation, na cds.lib file Edere dị ka egosiri na ngọngọ koodu na-esonụ.
   Kọwaa presynth ./presynth
   Kọwaa COREAHBLITE_LIB ./COREAHBLITE_LIB
   Kọwaa smartfusion2
2. Mepụta hdl.var file, nhazi nhọrọ file nke nwere mgbanwe nhazi, nke na-ekpebi ka esi ahazi gburugburu imewe gị. Ndị na-agbanwe agbanwe files gụnyere:
   - Mgbanwe ndị a na-eji akọwapụta ọbá akwụkwọ ọrụ ebe ndị nchịkọta na-echekwa ihe achịkọtara na data ndị ọzọ ewepụtara.
   - Maka Verilog, mgbanwe (LIB_MAP, VIEW_MAP, WORK) nke a na-eji akọwapụta ọba akwụkwọ na views ka ịchọọ mgbe onye nkwuwa okwu na-edozi okwu.
   - Mgbanwe nke na-enye gị ohere ịkọwapụta nhọrọ na arụmụka iwu-achịkọta, onye na-akọwa ihe na simulator.
   N'ihe banyere simulation presynth example egosiri n'elu, sị na anyị nwere RTL atọ files: a.v, b.v, na testbench.v, nke kwesiri ka achịkọta ya na presynth, COREAHBLITE_LIB, na ọba akwụkwọ presynth n'otu n'otu. hdl.var file enwere ike dee dị ka egosiri na koodu ngọngọ na-esote.
   Kọwaa ọrụ presynth
   DEFINE PROJECT_DIR <ebe ndị files>
   DEFINE LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/av => presynth )
   Kọwaa LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/b.v => COREAHBLITE_LIB )
   DEFINE LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/testbench.v => presynth )
   Kọwaa LIB_MAP ( $LIB_MAP, + => presynth )
3. Chịkọta imewe files iji ncvlog nhọrọ.
   ncvlog +incdir+ –cdslib ./cds.lib –hdlvar ./hdl.var –logfile
   ncvlog.log –update –linedebug av bv testbench.v
4. Jiri celab kọwapụta nhazi ahụ. Onye na-akọwapụta ihe na-ewulite usoro nhazi nke dabere na ozi nzizi na nhazi n'ime nhazi ahụ, guzobe njikọ mgbaàmà, ma na-agbakọ ụkpụrụ mbụ maka ihe niile dị na nhazi ahụ. A na-echekwa usoro nhazi a kọwapụtara na foto simulation, nke bụ ihe nnọchianya nke imewe gị nke simulator na-eji na-eme simulation ahụ.
   ncelab – Ozi –cdslib ./cds.lib –hdlvar ./hdl.var –logfile celab.log –errormax 15 –
   access +rwc –status worklib.:modul
   Nkọwa n'oge ịme anwansị post-layout
   N'ihe gbasara ịme anwansị post-layout, buru ụzọ nweta SDF file kwesiri ka achịkọta ya tupu akọwapụta ya site na iji iwu ncsdfc.
   ncsdfcfileaha> .sdf - mmepụta <fileaha>.sdf.X
   Mgbe a na-akọwapụta, jiri mmepụta SDF chịkọtara yana nhọrọ –autosdf dị ka egosiri na koodu ngọngọ na-esonụ.
   ncelab -autosdf –Ozi –cdslib ./cds.lib –hdlvar ./hdl.var –logfile ncelab.log -errormax
   15 – nweta +rwc –status worklib.:modul –sdf_cmd_file ./
   sdf_cmd_file
   sdf_cmd_file ga-adị ka egosiri na koodu ngọngọ na-esonụ.
   COPILED_SDF_FILE = " <Ebe e si achịkọta SDF file>”
5. Simulate iji ncsim. Ka emechara nkọwapụta, a na-emepụta onyonyo simulation, nke ncsim kwajuru maka simulation. Ị nwere ike na-agba ọsọ na batch mode ma ọ bụ GUI mode.
   ncsim – Ozi –batch/-gui –cdslib ./cds.lib –hdlvar ./hdl.var –logfile ncsim.log –
   errormax 15 –status worklib.:modul

Ihe dị mkpa: Enwere ike itinye usoro atọ ndị a niile nke ịchịkọta, ịkọwapụta na ịme anwansị n'ime edemede shei file wee nweta site na ahịrị iwu. Kama iji usoro atọ ndị a, enwere ike ịmebe imewe n'otu nzọụkwụ site na iji ncverilog ma ọ bụ ntutu nhọrọ dị ka egosiri na codeblock na-esonụ.
ncverilog +incdir+ -cdslib ./cds.lib –hdlvar ./hdl.var < RTL niile
files eji emewe>
irun +incdir+ -cdslib ./cds.lib –hdlvar ./hdl.var <all RTL files
eji na imewe>

3.3.1 Okwu ndị ama ama (Jụọ ajụjụ)
Testbench Workaround
Iji nkwupụta na-esonụ maka ịkọwapụta ugboro elekere na testbench nke onye ọrụ mepụtara, ma ọ bụ testbench ndabara nke Libero SoC mepụtara anaghị arụ ọrụ na NCsim.
mgbe niile @(SYSCLK)
#(SYSCLK_PERIOD / 2.0) SYSCLK <= !SYSCLK;
Gbanwee dị ka ndị a ka ịme simulation:
mgbe niile #(SYSCLK_PERIOD / 2.0) SYSCLK = ~ SYSCLK;
Ihe dị mkpa: Achịkọtara ọba akwụkwọ maka NCsim bụ ikpo okwu akọwapụtara (ya bụ, ọba akwụkwọ 64 adabereghị na ikpo okwu 32 bit yana ọzọ).
Ihe ngosi Postsynth na Post-layout Iji MSS na SERDES Ka ị na-eme simulations postsynth nke atụmatụ nwere ngọngọ MSS ma ọ bụ ihe ngosi post-layout nke eserese site na iji SERDES, simulations BFM anaghị arụ ọrụ ma ọ bụrụ na nhọrọ –libmap bụ.
akọwapụtaghị ya n'oge nkọwa. Nke a bụ n'ihi na n'oge nkọwa, a na-edozi MSS site n'ọbá akwụkwọ ọrụ (n'ihi na ndabara njide na worklib bụ postsynth/post-layout) ebe ọ bụ naanị arụrụ arụrụ arụ.
A ga-ederịrị iwu ncelab dịka egosiri na ngọngọ koodu a iji dozie MSS
gbochie n'ọbá akwụkwọ SmartFusion2 agbakọkọtara.

ncelab -libmap lib.map -libverbose -Message -access +rwc cfg1
na lib.map file ga-adị ka ndị a:
nhazi cfg1;
imewe ;
liblist smartfusion2 ;
endconfig
Nke a na-edozi cell ọ bụla n'ọbá akwụkwọ SmartFusion2 tupu i lee anya n'ọbá akwụkwọ ọrụ ya bụ postsynth/ post-layout.
Enwere ike iji nhọrọ –libmap na ndabara n'oge nkọwa maka simulation ọ bụla (presynth, postsynth, na post-layout). Nke a na-ezere nsogbu ịme anwansị na-akpata n'ihi mkpebi ikpe sitere na ụlọ akwụkwọ.
ncelab: *F,INTERR: EXECEPTION ENTERNAL
Ewepụ ngwá ọrụ ncelab a bụ ihe nhụsianya maka atụmatụ nwere FDDR na SmartFusion 2 na IGLOO 2 n'oge simulations postsynth na post-layout site na iji -libmap nhọrọ.
Ihe dị mkpa: A kọsarala ndị otu nkwado Cadence okwu a (SAR 52113).

3.4 Sample Tcl na Shell Script Files (Jụọ ajụjụ)
Ndị a files bụ nhazi files mkpa maka ịtọlite ​​imewe na shei script file maka ịgba ọsọ NCsim iwu.
Cds.lib
NE smartfusion2 / scratch/krydor/tmpspace/users/me/nc-vlog64/SmartFusion2
Kọwaa COREAHBLITE_LIB ./COREAHBLITE_LIB
Kọwaa presynth ./presynth

HDl.var
Kọwaa ọrụ presynth
Kọwaa PROJECT_DIR / scratch/krydor/tmpspace/sqausers/me/3rd_party_simulators/Cadence/IGLOO2/
ENVM/M2GL050/envm_fic1_ser1_v/eNVM_fab_master
Kọwaa LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBlite/4.0.100/rtl/
vlog/core/coreahblite_addrdec.v => COREAHBLITE_LIB )
Kọwaa LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBlite/4.0.100/rtl/
vlog/core/coreahblite_defaultslavesm.v => COREAHBLITE_LIB )
Kọwaa LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBlite/4.0.100/rtl/
vlog/core/coreahblite_masterstagev => COREAHBLITE_LIB )
Kọwaa LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBlite/4.0.100/rtl/
vlog/core/coreahblite_slavearbiter.v => COREAHBLITE_LIB )
Kọwaa LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBlite/4.0.100/rtl/
vlog/core/coreahblite_slavestagev => COREAHBLITE_LIB )
Kọwaa LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBlite/4.0.100/rtl/
vlog/core/coreahblite_matrix2x16.v => COREAHBLITE_LIB )
Kọwaa LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBlite/4.0.100/rtl/
vlog/core/coreahblite.v => COREAHBLITE_LIB )
DEFINE LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB/CCC_0/SB_CCC_0_FCCC.v =>
presynth)
Kọwaa LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreConfigMaster/
2.0.101/rtl/vlog/core/coreconfigmaster.v => presynth )
Kọwaa LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreConfigP/4.0.100/rtl/
vlog/core/coreconfigp.v => presynth )
Kọwaa LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreResetP/5.0.103/rtl/
vlog/core/coreresetp_pcie_hotreset.v => presynth )
Kọwaa LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreResetP/5.0.103/rtl/
vlog/core/coreresetp.v => presynth )
DEFINE LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB/FABOSC_0/SB_FABOSC_0_OSC.v =>
presynth)
DEFINE LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB_HPMS/SB_HPMS.v => presynth )
Kọwaa LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB/SB.v => presynth )
Kọwaa LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB_top/SERDES_IF_0/
SB_top_SERDES_IF_0_SERDES_IF.v => presynth )
DEFINE LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB_top/SB_top.v => presynth )
DEFINE LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB_top/testbench.v => presynth )
Kọwaa LIB_MAP ( $LIB_MAP, + => presynth )
Iwu.csh
ncvlog +incdir+.../../component/work/SB_top -cdslib ./cds.lib -hdlvar ./hdl.var -logfile
ncvlog.log -errormax 15 -update -linedebug
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite_addrdec.v
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/
coreahblite_defaultslavesm.v
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite_masterstagev
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite_slavearbiter.v
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite_slavestagev
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite_matrix2x16.v
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite.v
../../component/work/SB/CCC_0/SB_CCC_0_FCCC.v
../../component/Actel/DirectCore/CoreConfigMaster/2.0.101/rtl/vlog/core/coreconfigmaster.v
../../component/Actel/DirectCore/CoreConfigP/4.0.100/rtl/vlog/core/coreconfigp.v
../../component/Actel/DirectCore/CoreResetP/5.0.103/rtl/vlog/core/coreresetp_pcie_hotreset.v
../../component/Actel/DirectCore/CoreResetP/5.0.103/rtl/vlog/core/coreresetp.v
../../component/work/SB/FABOSC_0/SB_FABOSC_0_OSC.v ../../component/work/SB_HPMS/SB_HPMS.v
../../component/work/SB/SB.v ../../component/work/SB_top/SERDES_IF_0/
SB_top_SERDES_IF_0_SERDES_IF.v
../../component/work/SB_top/SB_top.v ../../component/work/SB_top/testbench.v
ncelab -Message -cdslib ./cds.lib -hdlvar ./hdl.var
-arụ ọrụ presynth -logfile ncelab.log -errormax 15 -access +rwc -status presynth.testbench:modul
ncsim -Message -batch -cdslib ./cds.lib -hdlvar ./
hdl.var - ndekọfile ncsim.log -errormax 15 -status presynth.testbench:modul

3.5 akpaaka (Jụọ ajụjụ)
Edemede na-esonụ file na-atụgharị ModelSim run.do files n'ime nhazi files mkpa iji NCsim mee simulations.
Ederede File Ojiji
perl cadence_parser.pl presynth_run.do postsynth_run.do
postlayout_run.do Microsemi_Family
Ebe_nke_Cadence_ụlọ ọbaakwụkwọ agbakọgoro

Cadence_parser.pl
#!/usr/bin/perl -w

################################################ #####################################
##############
#Ojiji: perl questa_parser.pl presynth_run.do postsynth_run.do postlayout_run.do
Microsemi_Family achịkọtagoro_ụlọ ọba akwụkwọ #

################################################ #####################################
##############
jiri POSIX;
jiri nlezianya mee ihe;
m ($presynth, $postsynth, $postlayout, $ezinụlọ, $lib_location) = @ARGV;
&questa_parser($presynth, $ezinụlọ, $lib_location);
&questa_parser($postsynth, $ezinụlọ, $lib_location);
&questa_parser ($ postlayout, $ ezinụlọ, $ lib_location);
sub questa_parser {
m $ModelSim_run_do = $_[0];
my $actel_family = $_[1];
m $lib_location = $_[2];
steeti m;
ọ bụrụ na (-e “$ModelSim_run_do”)
{
mepere (INFILE, "$ ModelSim_run_do");
m @ModelSim_run_do = <INFILE>;
ahịrị $m;
ọ bụrụ na ( $ ModelSim_run_do = ~ m / (presynth) /)
{
'mkdir QUESTA_PRESYNTH';
mepere (OUTFILE,”>QUESTA_PRESYNTH/presynth_questa.do”);
steeti = $1;
} elsif ( $ModelSim_run_do =~ m/(postsynth)/)
{
'mkdir QUESTA_POSTSYNTH';
mepere (OUTFILE,”>QUESTA_POSTSYNTH/postsynth_questa.do”);
steeti = $1;
} elsif ( $ModelSim_run_do =~ m/(postlayout)/ )
{
'mkdir QUESTA_POSTLAYOUT';
mepere (OUTFILE,”>QUESTA_POSTLAYOUT/postlayout_questa.do”);
steeti = $1;
} ọzọ
{
bipụta “Ntụnye ezighi ezi enyere ndị file\n";
ebipụta "#Usage: perl questa_parser.pl presynth_run.do postsynth_run.do postlayout_run.do
\"Ebe_ụlọ ọba akwụkwọ\n";
}
ahịrị $ (@ModelSim_run_do)
{
# Ọrụ izugbe
$ akara = ~ s / .. \/ designer. * simulation \///g;
$ akara = ~ s/$state/$state\_questa/g;
#bipụtaFILE "$akara \n";
ọ bụrụ ($ akara = ~ m/vmap\s+.*($actel_family)/)
{
bipụtaFILE "vmap $actel_family \"$lib_location\"\n";
} elsif ($ ahịrị =~ m/vmap\s+(.*._LIB)/)
{
$ akara = ~ s/ .. \/component/.. \/..\/component/g;
bipụtaFILE "$akara \n";
} elsif ($ ahịrị = ~ m/vsim/)
{
$ akara = ~ s/vsim/vsim -novopt/g;
bipụtaFILE "$akara \n";
} ọzọ
{
bipụtaFILE "$akara \n";
}
}
nso (INFILE);
nso (OUTFILE);
} ọzọ {
ebipụta "$ModelSim_run_do adịghị adị. Tinyegharịa ịme anwansị ọzọ \n";
}
}

Ntọala Cadence Xcelium (Nbanye Microchip)

Ịkwesịrị ịmepụta edemede file yiri ModelSim ME/ModelSim Pro ME run.do iji mee simulator Cadence Xcelium. Soro usoro ndị a wee mepụta edemede file maka Xcelium ma ọ bụ jiri edemede file enyere iji tọghata ModelSim ME/ModelSim Pro ME run.do files n'ime nhazi files chọrọ iji Xcelium mee simulations.
4.1 Mgbanwe gburugburuJụọ ajụjụ)
Iji mee Cadence Xcelium, hazie mgbanwe gburugburu ebe a:

1. LM_LICENSE_FILE: ga-etinyerịrị ntụnye aka na ikikere file.
2. cds_root: ga-arụtụ aka na ebe ndekọ ụlọ nke Cadence Incisive Installation.
3. PATH: ga-arụtụ aka na ebe a na-edebe ihe n'okpuru akwụkwọ ndekọ aha nke cds_root rụtụrụ aka (ya bụ.
   $ cds_root / ngwaọrụ / bin / 64bit (maka igwe 64 bit na $ cds_root / ngwaọrụ / bin maka 32 bit
   igwe).

Enwere ụzọ atọ iji melite gburugburu ịme anwansị ma ọ bụrụ na mgbanwe n'etiti sistemụ arụmọrụ 64-bit na 32-bit:
Ikpe 1: PATH mgbanwe
set ụzọ = (install_dir / ngwaọrụ / bin / 64bit $ ụzọ) maka 64bit igwe na
set ụzọ = (install_dir / ngwaọrụ / bin $ ụzọ) maka 32bit igwe
Ikpe 2: Iji -64bit Command-line Nhọrọ
N'ahịrị iwu ezipụta -64bit nhọrọ iji kpọọ 64-bit executable.
Ikpe 3: Ịtọ ntọala INCA_64BIT ma ọ bụ CDS_AUTO_64BIT Gburugburu
A na-emeso mgbanwe INCA_64BIT dị ka onye na-agba ọsọ. Ị nwere ike ịtọ mgbanwe a na uru ọ bụla ma ọ bụ na efu
eriri.
setenv INCA_64BIT

Ihe dị mkpa: INCA_64BIT mgbanwe gburugburu anaghị emetụta ngwaọrụ Cadence ndị ọzọ, dị ka ngwaọrụ IC. Agbanyeghị, maka ngwaọrụ Incisiive, mgbanwe INCA_64BIT na-ewepụ ntọala maka mgbanwe gburugburu CDS_AUTO_64BIT. Ọ bụrụ na ọnọdụ INCA_64BIT na-agbanwe agbanwe bụ et, ngwaọrụ mkpali niile na-agba na ọnọdụ 64-bit.
setenv CDS_AUTO_64BIT gụnyere:INCA
Ihe dị mkpa: eriri INCA ga-abụrịrị na mkpụrụedemede ukwu. A ga-emerịrị ihe omume niile n'ụdị 2-bit ma ọ bụ na ọnọdụ 64-bit, etinyela mgbanwe ahụ ka ọ tinye otu executable, dị ka ndị a:
setenv CDS_AUTO_64BIT gụnyere:ncelab
Ngwa Cadence ndị ọzọ, dị ka ngwaọrụ IC, na-ejikwa CDS_AUTO_64BIT mgbanwe gburugburu ebe obibi iji jikwaa nhọrọ nke 32-bit ma ọ bụ 64-bit executables. Tebụlụ na-esonụ na-egosi otu ị ga-esi tọọ mgbanwe CDS_AUTO_64BIT iji mee ngwa ngwa Insiive na ngwaọrụ IC n'ụdị niile.

Isiokwu 4-1. CDS_AUTO_64BIT mgbanwe

CDS_AUTO_64BIT dị iche iche	Ngwa ngwa ngwa	Ngwa IC
setenv CDS_AUTO_64BIT niile	64-bit	64-bit
setenv CDS_AUTO_64BIT Ọ BỤGHỊ	32-bit	32-bit
setenv CDS_AUTO_64BIT EXCLUDE:ic_binary	64-bit	32-bit
setenv CDS_AUTO_64BIT EXCLUDE:INCA	32-bit	64-bit

Ihe dị mkpa: Ngwa ngwa mkpali niile ga-agbarịrị n'ụdị 32-bit ma ọ bụ na ọnọdụ 64-bit, ejila EXCLUDE wepụ otu ihe arụrụ arụ, dị ka ndị a:
setenv CDS_AUTO_64BIT EXCLUDE:ncelab
Ọ bụrụ na ịtọọ mgbanwe CDS_AUTO_64BIT iji wepu ngwaọrụ mkparị (setenv)
CDS_AUTO_64BIT EXCLUDE:INCA), a na-agba ngwa ngwa niile n'ụdị 32-bit. Otú ọ dị, ndị
-64bit nhọrọ ahịrị iwu na-ewepụ mgbanwe gburugburu ebe obibi.
Nhazi na-esonụ fileỌ na-enyere gị aka ijikwa data gị ma jikwaa ọrụ nke ngwa simulation na akụrụngwa:

• Maapụ ụlọ akwụkwọ file (cds.lib) na-akọwa aha ezi uche dị na ya maka ebe imewe gị.
• Ọbá akwụkwọ na-ejikọta ha na aha ndekọ anụ ahụ.
• Mgbanwe file (hdl.var) na-akọwapụta mgbanwe ndị na-emetụta omume nke ngwa simulation na akụrụngwa.

4.2 Budata ọba akwụkwọ chịkọtara (Jụọ ajụjụ)
Budata ọba akwụkwọ maka Cadence Xcelium site na Microsemi's websaịtị.
4.3 Ịmepụta edemede Xcelium file (Jụọ ajụjụ)
Mgbe ịmepụtara otu nke run.do files, mee usoro ndị a iji mee simulation gị site na iji script Xcelium file.

1. Mepụta cds.lib file nke na-akọwa ụlọ akwụkwọ ndị a na-enweta na ebe ha dị.
   Nke file nwere nkwupụta ndị na-edepụta aha ndị ezi uche dị na ya n'ụzọ akwụkwọ ndekọ aha ha. Maka example, ọ bụrụ na ị na-agba presynth simulation, na cds.lib file enwere ike dee dị ka egosiri na koodu ngọngọ na-esote.
   Kọwaa presynth ./presynth
   Kọwaa COREAHBLITE_LIB ./COREAHBLITE_LIB
   Kọwaa smartfusion2
2. Mepụta hdl.var file nke bụ nhazi nhọrọ file nke nwere mgbanwe nhazi, nke na-ekpebi ka esi ahazi gburugburu imewe gị. Ndị a gụnyere:
   - Mgbanwe ndị a na-eji akọwapụta ọbá akwụkwọ ọrụ ebe ndị nchịkọta na-echekwa ihe achịkọtara na data ndị ọzọ ewepụtara.
   - Maka Verilog, mgbanwe (LIB_MAP, VIEW_MAP, WORK) nke a na-eji akọwapụta ọba akwụkwọ na views ka ịchọọ mgbe onye nkwuwa okwu na-edozi okwu.
   - Mgbanwe nke na-enye gị ohere ịkọwapụta nhọrọ na arụmụka iwu-achịkọta, onye na-akọwa ihe na simulator.
   N'ihe banyere simulation presynth example egosiri n'elu, kwuo na anyị nwere 3 RTL files a.v, b.v, na testbench.v, nke kwesịrị ịchịkọta ya na presynth, COREAHBLITE_LIB, na ụlọ akwụkwọ presynth n'otu n'otu. hdl.var file enwere ike dee dị ka egosiri na koodu ngọngọ na-esote.
   Kọwaa ọrụ presynth
   DEFINE PROJECT_DIR <ebe ndị files>
   DEFINE LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/av => presynth )
   Kọwaa LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/b.v => COREAHBLITE_LIB )
   DEFINE LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/testbench.v => presynth )
   Kọwaa LIB_MAP ( $LIB_MAP, + => presynth )
3. Chịkọta imewe files iji ncvlog nhọrọ.
   xmvlog +incdir+ –cdslib ./cds.lib –hdlvar ./hdl.var –logfile
   ncvlog.log –update –linedebug av bv testbench.v
4. Jiri celab kọwapụta nhazi ahụ. Onye na-akọwapụta ihe na-ewulite usoro nhazi nke dabere na ozi nzizi na nhazi n'ime nhazi ahụ, guzobe njikọ mgbaàmà, ma na-agbakọ ụkpụrụ mbụ maka ihe niile dị na nhazi ahụ. A na-echekwa usoro nhazi a kọwapụtara na foto simulation, nke bụ ihe nnọchianya nke imewe gị nke simulator na-eji na-eme simulation ahụ.
   Xcelium – Ozi –cdslib ./cds.lib –hdlvar ./hdl.var –logfile celab.log –errormax 15 –
   access +rwc –status worklib.:modul
   Nkọwa n'oge ịme anwansị post-layout
   N'ihe gbasara ịme anwansị post-layout, buru ụzọ nweta SDF file kwesiri ka achịkọta ya tupu akọwapụta ya site na iji iwu ncsdfc.
   Xceliumfileaha> .sdf - mmepụta <fileaha>.sdf.X
   Mgbe a na-akọwapụta, jiri mmepụta SDF chịkọtara yana nhọrọ –autosdf dị ka egosiri na koodu ngọngọ na-esonụ.
   xmelab -autosdf –Ozi –cdslib ./cds.lib –hdlvar ./hdl.var –logfile ncelab.log -errormax
   15 – nweta +rwc –status worklib.:modul –sdf_cmd_file ./
   sdf_cmd_file
   sdf_cmd_file ga-adị ka egosiri na koodu ngọngọ na-esonụ.
   COPILED_SDF_FILE = " <Ebe e si achịkọta SDF file>”
5. Simulate iji Xcelium. Ka emechara nkọwapụta, a na-emepụta foto simulation nke Xcelium kwajuru maka ịme anwansị. Enwere ike ịme nke a na ọnọdụ batch ma ọ bụ ọnọdụ GUI.
   xmsim – Ozi –batch/-gui –cdslib ./cds.lib –hdlvar ./hdl.var –logfile xmsim.log –
   errormax 15 –status worklib.:modul
   Ntọala Xcelium Cadence
   Ihe dị mkpa:   niile Enwere ike itinye nzọụkwụ atọ dị n'elu nke nchịkọta, ịkọwapụta na ịme ngosi n'ime edemede shei file wee nweta site na ahịrị iwu. Kama iji usoro atọ ndị a, enwere ike ịmebe imewe n'otu nzọụkwụ site na iji ncverilog ma ọ bụ xrun nhọrọ dị ka egosiri na codeblock na-esonụ.
   xmverilog +incdir+ -cdslib ./cds.lib –hdlvar ./hdl.var < RTL niile
   files eji emewe>
   xrun +incdir+ -cdslib ./cds.lib –hdlvar ./hdl.var < RTL niile files
   eji na imewe>

4.3.1 Okwu ndị ama ama (Jụọ ajụjụ)
Testbench Workaround
Iji nkwupụta na-esonụ maka ịkọwapụta ugboro elekere na testbench nke onye ọrụ mepụtara ma ọ bụ testbench ndabara nke Libero SoC mepụtara anaghị arụ ọrụ na Xcelium.
mgbe niile @(SYSCLK)
#(SYSCLK_PERIOD / 2.0) SYSCLK <= !SYSCLK;
Gbanwee dị ka ndị a ka ịme simulation:
mgbe niile #(SYSCLK_PERIOD / 2.0) SYSCLK = ~ SYSCLK;

Ihe dị mkpa: Ọbá akwụkwọ achịkọtara maka Xcelium bụ ikpo okwu akọwapụtara (ya bụ, ọba akwụkwọ 64 adabereghị na ikpo okwu 32 bit yana ọzọ).
Ihe ngosi Postsynth na Post-layout na-eji MSS na SERDES
Ka ị na-eme simulations postsynth nke atụmatụ nwere MSS ngọngọ, ma ọ bụ simulations post-layout nke atụmatụ site na iji SERDES, ịme anwansị BFM anaghị arụ ọrụ ma ọ bụrụ na-akọwapụtaghị nhọrọ libmap n'oge nkọwa. Nke a bụ n'ihi na n'oge nkọwa, a na-edozi MSS site n'ọbá akwụkwọ ọrụ (n'ihi na ndabara njide na worklib bụ postsynth/post-layout) ebe ọ bụ naanị arụrụ arụrụ arụ.
A ga-ederịrị iwu ncelab dịka egosiri na ngọngọ koodu a iji dozie ngọngọ MSS site na ọbaakwụkwọ achịkọtara achịkọtaburu.
xmelab -libmap lib.map -libverbose -Ozi - nweta +rwc cfg1
na lib.map file ga-adị ka ndị a:
nhazi cfg1;
imewe ;
liblist smartfusion2 ;
endconfig
Nke a ga-edozi cell ọ bụla n'ọbá akwụkwọ SmartFusion2 tupu i lee anya n'ọbá akwụkwọ ọrụ ya bụ postsynth/post-layout.
Enwere ike iji nhọrọ –libmap na ndabara n'oge nkọwa maka simulation ọ bụla (presynth, postsynth na post-layout). Nke a na-ezere nsogbu ịme anwansị na-akpata n'ihi mkpebi ikpe sitere na ụlọ akwụkwọ.
xmelab: *F,INTERR: Ewezuga n'ime
Mwepu ngwá ọrụ celab a bụ ihe ịma aka maka atụmatụ nwere FDDR na SmartFusion2 na IGLOO2
n'oge simulations postsynth na post-layout site na iji nhọrọ –libmap.
Ihe dị mkpa: A kọsarala ndị otu nkwado Cadence okwu a (SAR 52113).

4.4 Sample Tcl na shei script files (Jụọ ajụjụ)
Ndị a files bụ nhazi files mkpa maka ịtọlite ​​imewe na shei script file maka ịgba ọsọ iwu Xcelium.
Cds.lib
Kọwaa smartfusion2 / scratch/krydor/tmpspace/users/me/nc-vlog64/SmartFusion2
Kọwaa COREAHBLITE_LIB ./COREAHBLITE_LIB
Kọwaa presynth ./presynth
HDl.var
Kọwaa ọrụ presynth
Kọwaa PROJECT_DIR / scratch/krydor/tmpspace/sqausers/me/3rd_party_simulators/Cadence/IGLOO2/
ENVM/M2GL050/envm_fic1_ser1_v/eNVM_fab_master
Kọwaa LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBlite/4.0.100/rtl/
vlog/core/coreahblite_addrdec.v => COREAHBLITE_LIB )
Kọwaa LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBlite/4.0.100/rtl/
vlog/core/coreahblite_defaultslavesm.v => COREAHBLITE_LIB )
Kọwaa LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBlite/4.0.100/rtl/
vlog/core/coreahblite_masterstagev => COREAHBLITE_LIB )
Kọwaa LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBlite/4.0.100/rtl/
vlog/core/coreahblite_slavearbiter.v => COREAHBLITE_LIB )
Kọwaa LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBlite/4.0.100/rtl/
vlog/core/coreahblite_slavestagev => COREAHBLITE_LIB )
Kọwaa LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBlite/4.0.100/rtl/
vlog/core/coreahblite_matrix2x16.v => COREAHBLITE_LIB )
Kọwaa LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBlite/4.0.100/rtl/
vlog/core/coreahblite.v => COREAHBLITE_LIB )
DEFINE LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB/CCC_0/SB_CCC_0_FCCC.v =>
presynth)
Kọwaa LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreConfigMaster/
2.0.101/rtl/vlog/core/coreconfigmaster.v => presynth )
Kọwaa LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreConfigP/4.0.100/rtl/
vlog/core/coreconfigp.v => presynth )
Kọwaa LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreResetP/5.0.103/rtl/
vlog/core/coreresetp_pcie_hotreset.v => presynth )
Kọwaa LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreResetP/5.0.103/rtl/
vlog/core/coreresetp.v => presynth )
DEFINE LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB/FABOSC_0/SB_FABOSC_0_OSC.v =>
presynth)
DEFINE LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB_HPMS/SB_HPMS.v => presynth )
Kọwaa LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB/SB.v => presynth )
Kọwaa LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB_top/SERDES_IF_0/
SB_top_SERDES_IF_0_SERDES_IF.v => presynth )
DEFINE LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB_top/SB_top.v => presynth )
DEFINE LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB_top/testbench.v => presynth )
Kọwaa LIB_MAP ( $LIB_MAP, + => presynth )
Iwu.csh
ncvlog +incdir+.../../component/work/SB_top -cdslib ./cds.lib -hdlvar ./hdl.var -logfile
ncvlog.log -errormax 15 -update -linedebug
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite_addrdec.v
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/
coreahblite_defaultslavesm.v
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite_masterstagev
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite_slavearbiter.v
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite_slavestagev
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite_matrix2x16.v
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite.v
../../component/work/SB/CCC_0/SB_CCC_0_FCCC.v
../../component/Actel/DirectCore/CoreConfigMaster/2.0.101/rtl/vlog/core/coreconfigmaster.v
../../component/Actel/DirectCore/CoreConfigP/4.0.100/rtl/vlog/core/coreconfigp.v
../../component/Actel/DirectCore/CoreResetP/5.0.103/rtl/vlog/core/coreresetp_pcie_hotreset.v
../../component/Actel/DirectCore/CoreResetP/5.0.103/rtl/vlog/core/coreresetp.v
../../component/work/SB/FABOSC_0/SB_FABOSC_0_OSC.v ../../component/work/SB_HPMS/SB_HPMS.v
../../component/work/SB/SB.v ../../component/work/SB_top/SERDES_IF_0/
SB_top_SERDES_IF_0_SERDES_IF.v
../../component/work/SB_top/SB_top.v ../../component/work/SB_top/testbench.v
ncelab -Message -cdslib ./cds.lib -hdlvar ./hdl.var
-arụ ọrụ presynth -logfile ncelab.log -errormax 15 -access +rwc -status presynth.testbench:modul
ncsim -Message -batch -cdslib ./cds.lib -hdlvar ./
hdl.var - ndekọfile ncsim.log -errormax 15 -status presynth.testbench:modul

4.5 akpaaka (Nbanye Microchip)
Edemede na-esonụ file na-atụgharị ModelSim run.do files n'ime nhazi files chọrọ iji Xcelium mee simulations.
Ederede File Ojiji
perl cadence_parser.pl presynth_run.do postsynth_run.do
postlayout_run.do Microsemi_Family
Ebe_nke_Cadence_ụlọ ọbaakwụkwọ agbakọgoro
Cadence_parser.pl
#!/usr/bin/perl -w

################################################ #####################################
##############
#Ojiji: perl questa_parser.pl presynth_run.do postsynth_run.do postlayout_run.do
Microsemi_Family achịkọtagoro_ụlọ ọba akwụkwọ #

################################################ #####################################
##############
jiri POSIX;
jiri nlezianya mee ihe;
m ($presynth, $postsynth, $postlayout, $ezinụlọ, $lib_location) = @ARGV;
&questa_parser($presynth, $ezinụlọ, $lib_location);
&questa_parser($postsynth, $ezinụlọ, $lib_location);

&questa_parser ($ postlayout, $ ezinụlọ, $ lib_location);
sub questa_parser {
m $ModelSim_run_do = $_[0];
my $actel_family = $_[1];
m $lib_location = $_[2];
steeti m;
ọ bụrụ na (-e “$ModelSim_run_do”)
{
mepere (INFILE, "$ ModelSim_run_do");
m @ModelSim_run_do = <INFILE>;
ahịrị $m;
ọ bụrụ na ( $ ModelSim_run_do = ~ m / (presynth) /)
{
'mkdir QUESTA_PRESYNTH';
mepere (OUTFILE,”>QUESTA_PRESYNTH/presynth_questa.do”);
steeti = $1;
} elsif ( $ModelSim_run_do =~ m/(postsynth)/)
{
'mkdir QUESTA_POSTSYNTH';
mepere (OUTFILE,”>QUESTA_POSTSYNTH/postsynth_questa.do”);
steeti = $1;
} elsif ( $ModelSim_run_do =~ m/(postlayout)/ )
{
'mkdir QUESTA_POSTLAYOUT';
mepere (OUTFILE,”>QUESTA_POSTLAYOUT/postlayout_questa.do”);
steeti = $1;
} ọzọ
{
bipụta “Ntụnye ezighi ezi enyere ndị file\n";
ebipụta "#Usage: perl questa_parser.pl presynth_run.do postsynth_run.do postlayout_run.do
\"Ebe_ụlọ ọba akwụkwọ\n";
}
ahịrị $ (@ModelSim_run_do)
{
# Ọrụ izugbe
$ akara = ~ s / .. \/ designer. * simulation \///g;
$ akara = ~ s/$state/$state\_questa/g;
#bipụtaFILE "$akara \n";
ọ bụrụ ($ akara = ~ m/vmap\s+.*($actel_family)/)
{
bipụtaFILE "vmap $actel_family \"$lib_location\"\n";
} elsif ($ ahịrị =~ m/vmap\s+(.*._LIB)/)
{
$ akara = ~ s/ .. \/component/.. \/..\/component/g;
bipụtaFILE "$akara \n";
} elsif ($ ahịrị = ~ m/vsim/)
{
$ akara = ~ s/vsim/vsim -novopt/g;
bipụtaFILE "$akara \n";
} ọzọ
{
bipụtaFILE "$akara \n";
}
}
nso (INFILE);
nso (OUTFILE);
} ọzọ {
ebipụta "$ModelSim_run_do adịghị adị. Tinyegharịa ịme anwansị ọzọ \n";
}
}

Siemens QuestaSim Ntọala/Ntọala Sim (ModelSim Setup)Jụọ ajụjụ)

The ọsọ.do files, nke Libero SoC mere maka ịme anwansị iji ModelSim Microsemi Editions, enwere ike iji mee ihe ngosi site na iji QuestaSim/ModelSim SE/DE/PE nwere otu mgbanwe. Na ModelSim ME/ModelSim Pro ME run.do file, ọ dị mkpa ka emegharịa ọnọdụ ọba akwụkwọ achịkọtaburu.
Ihe dị mkpa: 
Site na ndabara, ngwá ọrụ ịme anwansị na-abụghị ModelSim Pro ME na-arụ ọrụ njikarịcha n'oge ịme anwansị nke nwere ike imetụta visibiliti n'ime ihe ngosi simulation dị ka ihe imewe na ihe mkpali ntinye.
Nke a na-enyekarị aka n'ibelata oge ịme anwansị maka ịme anwansị ndị dị mgbagwoju anya, na-eji verbose, nlele ule onwe. Agbanyeghị, njikarịcha ndabara nwere ike ọ gaghị adị mma maka ịme anwansị niile, ọkachasị n'ọnọdụ ebe ị na-atụ anya iji mpio ebili mmiri nyochaa nsonaazụ simulation.
Iji dozie nsogbu ndị sitere na njikarịcha a kpatara, ị ga-agbakwunyerịrị iwu kwesịrị ekwesị na arụmụka metụtara n'oge ịme anwansị iji weghachi visibiliti n'ime nhazi ahụ. Maka iwu akọwapụtara ngwa, hụ akwụkwọ nke simulator in-eji.

5.1 Mgbanwe gburugburuJụọ ajụjụ)
Ndị a bụ mgbanwe gburugburu ebe achọrọ.

• LM_LICENSE_FILE: ga-agụnye ụzọ akwụkwọ ikike file.
• MODEL_TECH: ga-achọpụtarịrị ụzọ ebe nrụnye QuestaSim ga-esi na ndekọ ụlọ.
• ỤZỌ: ga-atụrịrị aka na ebe enwere ike ime nke MODEL_TECH rụtụrụ aka.

5.2 na-atụgharị run.do maka Mentor QuestaSim (Jụọ ajụjụ)
The ọsọ.do files nke Libero SoC mere maka ịme anwansị iji ModelSim Microsemi Edition nwere ike iji mee ihe ngosi site na iji QuestaSim/ModelSim_SE nwere otu mgbanwe.
Ihe dị mkpa:   niile Nhazi nke ejiri QuestaSim simulated ga-agụnye -novopt
nhọrọ yana iwu vsim na run.do script files.
5.3 Budata ọbá akwụkwọ agbakọtara (Jụọ ajụjụ)
Budata ọba akwụkwọ maka Mentor Graphics QuestaSim site na Microsemi's websaịtị.

Nchịkọta VCS Synopsys (Jụọ ajụjụ)

Ọsọ nke Microsemi kwadoro na-adabere na mgbawa Elaborate na Compile na VCS. Akwụkwọ a gụnyere edemede file nke na-eji script run.do files nke Libero SoC mebere wee wepụta ntọlite ​​​​ fileachọrọ maka ịme anwansị VCS. Edemede file na-eji ọsọ ọsọ.do file ime ihe ndia.

• Mepụta eserese ọbá akwụkwọ file, nke a na-eme site na iji synopsys_sim.setup file dị n'otu akwụkwọ ndekọ aha ebe ịme anwansị VCS na-agba.
• Mepụta edemede shei file iji VCS kọwapụta ma chịkọta atụmatụ gị.

6.1 Mgbanwe gburugburuJụọ ajụjụ)
Tọọ mgbanwe gburugburu ebe kwesịrị ekwesị maka VCS dabere na ntọala gị. Ụdị mgbanwe gburugburu ebe obibi achọrọ dị ka akwụkwọ VCS si dị bụ:

• LM_LICENSE_FILE: ga-etinyerịrị ntụnye aka na ihe nkesa ikike.
• VCS_HOME: ga-arụtụ aka na ebe ndekọ ụlọ nke nrụnye VCS.
• PATH: ga-etinyerịrị ntụnye n'akwụkwọ ndekọ aha n'okpuru ndekọ VCS_HOME.

6.2 Budata ọba akwụkwọ chịkọtara (Jụọ ajụjụ)
Budata ọba akwụkwọ maka Synopsys VCS site na Microsemi's websaịtị.
6.3 VCS simulation Script File (Jụọ ajụjụ)
Mgbe ịtọlitechara VCS na ịmepụta imewe na ọsọ dị iche iche.do files sitere na Libero SoC, ị ghaghị:

1. Mepụta maapụ ọba akwụkwọ file synopsys_sim.setup; nke a file nwere ntụnye aka na ebe ụlọ akwụkwọ niile a ga-eji mee ihe.
     Ihe dị mkpa: file aha agaghị agbanwe ma ọ ga-adị n'otu akwụkwọ ndekọ aha ebe simulation na-agba ọsọ. Nke a bụ example maka nke a file maka presynthesis simulation.
   ỌRỤ> MARA
   SmartFusion2 :
   presynth : ./presynth
   ezighi ezi: ./ọrụ
2. Kọwaa ihe dị iche iche imewe files, gụnyere testbench, na-eji iwu vlogan na VCS. Enwere ike itinye iwu ndị a na edemede shei file. Ndị na-esonụ bụ example nke iwu ndị achọrọ iji kọwapụta atụmatụ akọwapụtara na rtl.v yana testbench ya akọwapụtara na
   testbench.v.
   vlogan + v2k -ọrụ presynth rtl.v
   vlogan +v2k -ọrụ presynth testbench.v
3. Jiri VCS chịkọta nhazi ahụ site na iji iwu na-esonụ.
   vcs –sim_res=1fs presynth.testbench
   Rịba ama:  The Ekwesịrị ịtọ mkpebi oge nke ịme anwansị ka ọ bụrụ 1fs maka ịme anwansị arụ ọrụ ziri ezi.
4. Ozugbo achịkọtara imewe ahụ, malite ịme anwansị site na iji iwu a.
   ./simv
5. Maka ịme anwansị nkọwapụta azụ, iwu VCS ga-abụrịrị dị ka egosiri na ngọngọ koodu a.
   vcs postlayout.testbench –sim_res=1fs –sdf max:.<DUT atụ
   aha >: <sdf file ụzọ > –gui –l postlayout.log

6.4 Oke/iche (iche)Jụọ ajụjụ)
Ndị na-esonụ bụ mmachi/wepụ na ntọala Synopsys VCS.

• Enwere ike ịme ihe ngosi VCS naanị maka ọrụ Verilog nke Libero SoC. Ihe simulator VCS nwere ihe chọrọ asụsụ VHDL siri ike nke Libero SoC mebere VHDL na-emezughị. files.
• Ị ga-enwerịrị nkwupụta ngwụcha $ na Verilog testbench iji kwụsị ịme anwansị ahụ mgbe ọ bụla ịchọrọ.
  Ihe dị mkpa:   Mgbe A na-agba ọsọ simulations na ọnọdụ GUI, enwere ike ịkọwa oge ịgba ọsọ na GUI.

6.5 Sample Tcl na Shell Script Files (Jụọ ajụjụ)
Perl na-esote na-akpaghị aka ọgbọ nke synopsys_sim.setup file yana edemede shei kwekọrọ files mkpa iji kọwapụta, chịkọta, na ime ka imewe ahụ.
Ọ bụrụ na imewe ahụ na-eji MSS, detuo test.vec file dị na nchekwa simulation nke ọrụ Libero SoC n'ime folda ịme anwansị VCS. Akụkụ ndị a nwere sample ọsọ.do filenke Libero SoC mebere, gụnyere maapụ ọba akwụkwọ kwekọrọ na edemede shei fileachọrọ maka ịme anwansị VCS.
6.5.1 tupu njikọ (Jụọ ajụjụ)
Presynth_run.do
jiri nwayọ tọọ ACTELLIBNAME SmartFusion2
jiri nwayọ tọọ PROJECT_DIR "/sqa/users/me/VCS_Tests/Test_DFF"
ọ bụrụ {[file dị presynth/_info]} {
kwughachi "INFO: presynth ụlọ akwụkwọ simulation adịlarị"
} ọzọ {
vlib presynth
}
vmap presynth presynth
vmap SmartFusion2 “/captures/lin/11_0_0_23_11prod/lib/ModelSim/precompiled/vlog/smartfusion2”
vlog -work presynth "${PROJECT_DIR}/component/work/SD1/SD1.v"
vlog “+incdir+${PROJECT_DIR}/ mkpali” -ọrụ presynth “${PROJECT_DIR}/stimulus/SD1_TB1.v”
vsim -L SmartFusion2 -L presynth -t 1fs presynth.SD1_TB1
tinye ife / SD1_TB1/*
tinye log -r /*
agba 1000ns
presynth_main.csh
#!/bin/csh -f
tọọ PROJECT_DIR = "/sqa/users/Me/VCS_Tests/Test_DFF"
/cad_design/tools/vcs.dir/E-2011.03/bin/vlogan +v2k -work presynth “${PROJECT_DIR}/component/
arụ ọrụ/SD1/SD1.v”
/cad_design/tools/vcs.dir/E-2011.03/bin/vlogan +v2k “+incdir+${PROJECT_DIR}/stimulus” -ọrụ
presynth "${PROJECT_DIR}/stimulus/SD1_TB1.v"
/cad_design/tools/vcs.dir/E-2011.03/bin/vcs -sim_res=1fs presynth.SD1_TB1 -l compile.log
./simv -l run.log
Synopsys_sim.setup
ỌRỤ> ỌZỌ
SmartFusion2: /VCS/SmartFusion2
presynth : ./presynth
ezighi ezi: ./ọrụ

6.5.2 Mgbasa ozi (Jụọ ajụjụ)
postsynth_run.do
jiri nwayọ tọọ ACTELLIBNAME SmartFusion2
jiri nwayọ tọọ PROJECT_DIR "/sqa/users/Me/VCS_Tests/Test_DFF"
ọ bụrụ {[file dị postsynth/_info]} {
kwughachi "INFO: postsynth ọbá akwụkwọ ịme anwansị adịlarị"
} ọzọ {
vlib postsynth
}
vmap postsynth postsynth
vmap SmartFusion2 “//idm/captures/pc/11_0_1_12_g4x/Designer/lib/ModelSim/precompiled/vlog/
SmartFusion2”
vlog -work postsynth "${PROJECT_DIR}/synthesis/SD1.v"
vlog “+incdir+${PROJECT_DIR}/ mkpali” -work postsynth “${PROJECT_DIR}/stimulus/SD1_TB1.v”
vsim -L SmartFusion2 -L postsynth -t 1fs postsynth.SD1_TB1
tinye ife / SD1_TB1/*
tinye log -r /*
agba 1000ns
ndekọ SD1_TB1/*
Ụzọ ọpụpụ
Postsynth_main.csh
#!/bin/csh -f
tọọ PROJECT_DIR = "/sqa/users/Me/VCS_Tests/Test_DFF"
/cad_design/tools/vcs.dir/E-2011.03/bin/vlogan +v2k -work postsynth “${PROJECT_DIR}/synthesis/
SD1.v”
/cad_design/tools/vcs.dir/E-2011.03/bin/vlogan +v2k “+incdir+${PROJECT_DIR}/stimulus” -ọrụ
postsynth "${PROJECT_DIR}/stimulus/SD1_TB1.v"
/cad_design/tools/vcs.dir/E-2011.03/bin/vcs -sim_res=1fs postsynth.SD1_TB1 -l compile.log
./simv -l run.log
Synopsys_sim.setup
ỌRỤ> ỌZỌ
SmartFusion2: /VCS/SmartFusion2
postsynth: ./postsynth
ezighi ezi: ./ọrụ
6.5.3 nhazi ọkwa (Jụọ ajụjụ)
postlayout_run.do
jiri nwayọ tọọ ACTELLIBNAME SmartFusion2
jiri nwayọ tọọ PROJECT_DIR "E:/ModelSim_Work/Test_DFF"
ọ bụrụ {[file dị ../designer/SD1/simulation/postlayout/_info]} {
kwughachi "INFO: Ọbá akwụkwọ Simulation ../designer/SD1/simulation/postlayout adịlarị"
} ọzọ {
vlib ../designer/SD1/simulation/postlayout
}
vmap postlayout ../designer/SD1/simulation/postlayout
vmap SmartFusion2 “//idm/captures/pc/11_0_1_12_g4x/Designer/lib/ModelSim/precompiled/vlog/
SmartFusion2”
vlog -ọrụ postlayout "${PROJECT_DIR}/designer/SD1/SD1_ba.v"
vlog “+incdir+${PROJECT_DIR}/ mkpali” -ọrụ postlayout "${PROJECT_DIR}/stimulus/SD1_TB1.v"
vsim -L SmartFusion2 -L postlayout -t 1fs -sdfmax /SD1_0=${PROJECT_DIR}/designer/SD1/
SD1_ba.sdf postlayout.SD1_TB1
tinye ife / SD1_TB1/*
tinye log -r /*
agba 1000ns
Postlayout_main.csh
#!/bin/csh -f
tọọ PROJECT_DIR = "/ VCS_Tests/Test_DFF"
/cad_design/tools/vcs.dir/E-2011.03/bin/vlogan +v2k -work postlayout “${PROJECT_DIR}/
mmebe/SD1/SD1_ba.v”
/cad_design/tools/vcs.dir/E-2011.03/bin/vlogan +v2k “+incdir+${PROJECT_DIR}/stimulus” -ọrụ
nzigharị "${PROJECT_DIR}/stimulus/SD1_TB1.v"
/cad_design/tools/vcs.dir/E-2011.03/bin/vcs -sim_res=1fs postlayout.SD1_TB1 -sdf

max:SD1_TB1.SD1_0:${PROJECT_DIR}/designer/SD1/SD1_ba.sdf -l compile.log
./simv -l run.log
Synopsys_sim.setup
ỌRỤ> ỌZỌ
SmartFusion2: /VCS/SmartFusion2
postlayout: ./postlayout
ezighi ezi: ./workVCS
6.6 akpaaka (Jụọ ajụjụ)
Enwere ike ịmegharị ọsọ ahụ site na iji edemede Perl a file iji tọghata ModelSim run.do filebanye VCS edemede shei dakọtara files, mepụta akwụkwọ ndekọ aha kwesịrị ekwesị n'ime akwụkwọ ndekọ simulation Libero SoC, wee mee ihe ngosi.
Gbaa edemede ahụ file iji syntax na-esonụ.
perl vcs_parse.pl presynth_run.do postsynth_run.do postlayout_run.do
Vcs_parse_pl
#!/usr/bin/perl -w
################################################ ######################
#
#Ojiji: perl vcs_parse.pl presynth_run.do postsynth_run.do postlayout_run.do
#
################################################ #########################
m ($presynth, $postsynth, $postlayout) = @ARGV;
ọ bụrụ (sistemu ("mkdir VCS_Presynth")) {bipụta "mkdir dara:\n";}
ọ bụrụ (sistemu ("mkdir VCS_Postsynth")) {bipụta "mkdir dara:\n";}
ọ bụrụ (sistemu ("mkdir VCS_Postlayout")) {bipụta "mkdir dara:\n";}
chdir (VCS_Presynth);
`cp ../$ARGV[0] .`;
&parse_do ($ presynth, "presynth");
chdir ("../");
chdir (VCS_Postsynth);
`cp ../$ARGV[1] .`;
&parse_do($postsynth,”postsynth));
chdir ("../");
chdir (VCS_Postlayout);
`cp ../$ARGV[2] .`;
&parse_do ($ postlayout,” postlayout”);
chdir ("../");
sub parse_do {
my $vlog = "/cad_design/tools/vcs.dir/E-2011.03/bin/vlogan +v2k" ;
m%LIB = ();
m $file = $__[0];
steeti m = $_[1];
meghere (INFILE,”$file”) || anwụ “Enweghị ike imeghe File Ihe kpatara ya nwere ike ịbụ:$!";
ọ bụrụ na ($state eq “presynth”)
{
mepere (OUT1,”>presynth_main.csh”) || anwụ “Enweghị ike imepụta iwu File Ihe kpatara ya nwere ike ịbụ:$!";
}
elsif ($state eq “postsynth”)
{
mepere (OUT1,”>postsynth_main.csh”) || anwụ “Enweghị ike imepụta iwu File Ihe kpatara ya nwere ike ịbụ:$!";
}
elsif ($state eq “postlayout”)
{
mepere (OUT1,”> postlayout_main.csh”) || anwụ “Enweghị ike imepụta iwu File Ihe kpatara ya nwere ike ịbụ:$!";
}
ọzọ
{
ebipụta "Semulation State na-efu \n" ;
}
mepere (OUT2,”> synopsys_sim.setup”) || anwụ “Enweghị ike imepụta iwu File Ihe kpatara ya nwere ike ịbụ:$!";
# .csh file
ebipụta OUT1 "#!/bin/csh -f\n\n\n" ;
#MELITE FILE
bipụta OUT2 "ỌRỤ > DEFAULT\n" ;
ebipụta OUT2 "SmartFusion2: /sqa/users/Aditya/VCS/SmartFusion2\n" ;
mgbe ($ akara = <INFILE>)
{

Synopsys VCS Mbido

ma ọ bụrụ ($ akara = ~ m/dobe nwayọọ PROJECT_DIR\s+"(.*?)\"/)
{
ebipụta OUT1 "set PROJECT_DIR = \"$1"\n\n\n" ;
}
elsif ( $ahịrị =~ m/vlog.*\.v\”/ )
{
ma ọ bụrụ ($ akara = ~ m/\s+(\ w*?) \ _LIB/)
{
#bipụta "\$1 =$1 \n" ;
$temp = "$1″."_LIB";
#ebipụta "Temp = $temp \n" ;
$LIB{$temp}++;
}
chomp($akara);
$ akara = ~ s / ^ vlog / $ vlog / ;
$akara =~ s///g;
bipụta OUT1 "$ ahịrị\n";
}
elsif ( ($ akara = ~ m/vsim. * presynth \. (.*)/) || ($ akara = ~ m/vsim. * postsynth \ . (.*)/) || ($ ahịrị).
=~ m/vsim.* postlayout\.(.*)/) )
{
$tb = $1 ;
$tb = ~ s/ //g;
chomp($tb);
#bipụta "Aha TB: $tb \n";
ma ọ bụrụ ($ akara = ~ m/sdf(.*)\.sdf/)
{
chomp($akara);
$akara = $1 ;
#bipụta "LINE : $ahịrị \n" ;
ma ọ bụrụ ($ akara = ~ m / max /)
{
$akara =~ s/max \/// ;
$akara =~ s/=/:/;
ebipụta OUT1 "\n\n/cad_design/tools/vcs.dir/E-2011.03/bin/vcs -sim_res=1fs postlayout.$tb -sdf
max:$tb.$line.sdf -l compile.log\n" ;
}
elsif ($ ahịrị = ~ m/min/)
{
$ akara = ~ s/min \/// ;
$akara =~ s/=/:/;
ebipụta OUT1 "\n\n/cad_design/tools/vcs.dir/E-2011.03/bin/vcs -sim_res=1fs postlayout.$tb -sdf
min:$tb.$line.sdf -l compile.log\n” ;
}
elsif ($ ahịrị = ~ m/typ/)
{
$ akara = ~ s/ụdị \/// ;
$akara =~ s/=/:/;
ebipụta OUT1 "\n\n/cad_design/tools/vcs.dir/E-2011.03/bin/vcs -sim_res=1fs postlayout.$tb -sdf
ụdị:$tb.$line.sdf -l compile.log\n" ;
}
#-sdfmax /M3_FIC32_0=${PROJECT_DIR}/designer/M3_FIC32/M3_FIC32_ba.sdf — Ụdị Sim SDF
#$sdf = "-sdf max: testbench.M3_FIC32_0:${PROJECT_DIR}/designer/M3_FIC32/M3_FIC32_ba.sdf"; -VCS
Ụdị SDF
}
}
}
ebipụta
Mpụga 1 "\n\n"
;
if
($state eq "presynth"
)
{
ebipụta
OUT2 “presynth
: ./presynth\n"
;
ebipụta
OUT1 "/cad_design/tools/vcs.dir/E-2011.03/bin/vcs
-sim_res=1fs presynth.$tb -l
nchịkọta.log\n"
;
}
elsif
($state eq "postsynth"
)
{
ebipụta
OUT2 “postsynth
: ./postsynth\n"
;
ebipụta
OUT1 "/cad_design/tools/vcs.dir/E-2011.03/bin/vcs
-sim_res=1fs postsynth.$tb -l
nchịkọta.log\n"
;
}
elsif
($state eq "postlayout"
)
{
bipụta OUT2 “postlayout: ./postlayout\n”;
}
ọzọ
{
ebipụta "Semulation State na-efu \n" ;
}
foreach $i ( igodo %LIB)
{
#bipụta "Igodo: $i Uru: $LIB{$i} \n" ;
ebipụta OUT2 "$i : ./$i\n" ;
}
ebipụta OUT1 "\n\n" ;
ebipụta OUT1 "./simv -l run.log\n" ;
bipụta OUT2 “DEFAULT: ./work\n”;
nso INFILE;
mechie OUT1;
mechie OUT2;
}

Akụkọ ngbanwe (Nbanye Microchip

Akụkọ ngbanwe ahụ na-akọwa mgbanwe ndị etinyere na akwụkwọ ahụ. Mgbanwe ndị ahụ
E depụtara ya site na ntughari, malite na mbipụta kachasị ugbu a.

Ndozigharị	Ụbọchị	Nkọwa
A	12/2023	A na-eme mgbanwe ndị a na ngbanwe a: • Atụgharịrị akwụkwọ ka ọ bụrụ ndebiri Microchip. Ndozigharị izizi. • Emelitere ngalaba 5. Siemens QuestaSim Setup/ModelSim Setup iji tinye ndetu ọhụrụ nke na-akọwa mmetụta dị na visibiliti n'oge simulation na njikarịcha.

Nkwado FPGA Microchip
Otu ngwaahịa Microchip FPGA na-eji ọrụ nkwado dị iche iche kwado ngwaahịa ya, gụnyere Ọrụ Ndị Ahịa, Ụlọ Ọrụ Nkwado nka na ụzụ Ndị Ahịa, a websaịtị, na ụlọ ahịa ahịa zuru ụwa ọnụ.
A na-atụ aro ka ndị ahịa gaa leta akụrụngwa Microchip n'ịntanetị tupu ha akpọtụrụ nkwado n'ihi na o yikarịrị ka azalarị ajụjụ ha.
Kpọtụrụ Ụlọ Ọrụ Nkwado nka na ụzụ site na websaịtị na www.microchip.com/support. Kwuo nọmba akụkụ ngwaọrụ FPGA, họrọ udi ikpe dabara adaba, wee bulite imewe files mgbe ị na-ekepụta ikpe nkwado teknụzụ.
Kpọtụrụ ọrụ ndị ahịa maka nkwado ngwaahịa na-abụghị teknụzụ, dị ka ọnụahịa ngwaahịa, nkwalite ngwaahịa, mmelite ozi, ọkwa ịtụ na ikike.

• Site na North America, kpọọ 800.262.1060
• Site na ụwa ndị ọzọ, kpọọ 650.318.4460
• Fax, si n'ebe ọ bụla n'ụwa, 650.318.8044

Ozi Microchip
Microchip Websaịtị
Microchip na-enye nkwado ntanetị site na anyị websaịtị na www.microchip.com/. Nke a weba na-eji saịtị eme ihe files na ozi dị mfe maka ndị ahịa. Ụfọdụ ọdịnaya dị gụnyere:

• Nkwado ngwaahịa – Ibé akwụkwọ data na errata, ndetu ngwa na sampmmemme, akụrụngwa imewe, ntuziaka onye ọrụ na akwụkwọ nkwado ngwaike, ewepụtara sọftụwia kacha ọhụrụ yana sọftụwia echekwara
• Nkwado nka na ụzụ izugbe - Ajuju a na-ajụkarị (FAQ), arịrịọ nkwado teknụzụ, otu mkparịta ụka n'ịntanetị, ndepụta ndị otu mmemme mmebe Microchip
• Azụmahịa nke Microchip – ntuziaka onye na-ahọpụta ngwaahịa na ịtụ iwu, mbipụta akwụkwọ akụkọ Microchip kacha ọhụrụ, ndepụta nke nzukọ ọmụmụ na mmemme, ndepụta nke ụlọ ahịa Microchip, ndị nkesa na ndị nnọchi anya ụlọ ọrụ mmepụta ihe.

Ọrụ ngosi mgbanwe ngwaahịa
Ọrụ ngosi mgbanwe ngwaahịa Microchip na-enyere ndị ahịa aka ugbu a na ngwaahịa Microchip. Ndị debanyere aha ga-enweta ọkwa email mgbe ọ bụla enwere mgbanwe, mmelite, nlegharị anya ma ọ bụ errata metụtara ezinụlọ ngwaahịa akọwapụtara ma ọ bụ ngwa mmepe nke mmasị.
Iji debanye aha, gaa na www.microchip.com/pcn ma soro ntuziaka ndebanye aha.
Nkwado ndị ahịa
Ndị na-eji ngwaahịa Microchip nwere ike ịnweta enyemaka site na ọtụtụ ọwa:

• Onye nkesa ma ọ bụ onye nnọchi anya
• Ụlọ ọrụ ire ahịa mpaghara
• Injinia Ngwọta agbakwunyere (ESE)
• Nkwado ndị teknuzu

Ndị ahịa kwesịrị ịkpọtụrụ onye nkesa ha, onye nnọchi anya ma ọ bụ ESE maka nkwado. Ọfịs ahịa mpaghara dịkwa maka inyere ndị ahịa aka. Agụnyere ndepụta ụlọ ọrụ ahịa na ebe n'ime akwụkwọ a.
Nkwado nka na ụzụ dị site na websaịtị na: www.microchip.com/support
Njirimara Nchekwa Koodu Ngwaọrụ Microchip
Rịba ama nkọwa ndị a nke njirimara nchedo koodu na ngwaahịa Microchip:

• Ngwaahịa Microchip na-ezute nkọwapụta dị na mpempe data Microchip ha.
• Microchip kwenyere na ezinaụlọ nke ngwaahịa ya nwere nchekwa mgbe ejiri ya n'ụzọ achọrọ, n'ime nkọwapụta ọrụ yana n'okpuru ọnọdụ nkịtị.
• Ụkpụrụ Microchip na-eji ike na-echebe ikike ikike ọgụgụ isi ya. Mgbalị imebi njirimara nchedo koodu nke ngwaahịa Microchip bụ nke amachibidoro nke ọma ma nwee ike imebi iwu nwebiisinka nke Millennium Digital.
• Ma Microchip ma ọ bụ ndị nrụpụta semiconductor ọ bụla enweghị ike ikwe nkwa nchekwa nke koodu ya. Nchedo koodu apụtaghị na anyị na-ekwe nkwa na ngwaahịa a "enweghị ike imebi".
  Nchekwa koodu na-agbanwe mgbe niile. Microchip agba mbọ na-aga n'ihu na-emeziwanye njirimara nchedo koodu nke ngwaahịa anyị.

Akwụkwọ Ozi Iwu
Enwere ike iji akwụkwọ a na ozi dị n'ime ya naanị site na ngwaahịa Microchip, gụnyere iji chepụta, nwalee ma jikọta ngwaahịa Microchip na ngwa gị. Iji ozi a n'ụzọ ọ bụla ọzọ mebiri usoro ndị a. A na-enye ozi gbasara ngwa ngwaọrụ naanị maka ịdị mma gị yana mmelite nwere ike dochie ya. Ọ bụ ọrụ gị ịhụ na ngwa gị dabara na nkọwapụta gị. Kpọtụrụ ụlọ ọrụ ịre ahịa Microchip mpaghara gị maka nkwado ọzọ ma ọ bụ nweta nkwado ọzọ na www.microchip.com/en-us/support/design-help/client-support-services.
Ozi a bụ MICROCHIP “DỊ KA Ọ BỤ”. MICROCHIP emeghị nnochite anya ma ọ bụ akwụkwọ ikike n'ụdị ọ bụla ma ekwupụta ma ọ bụ kwupụta ya, edere ma ọ bụ n'ọnụ, usoro iwu ma ọ bụ ọzọ, metụtara ozi ahụ gụnyere mana ọnweghị oke n'iwu ọ bụla na-akwadoghị, iwu na-akwadoghị. NA ahụ dị mma maka ebumnuche pụrụ iche, ma ọ bụ akwụkwọ ikike metụtara ọnọdụ ya, ogo ya, ma ọ bụ arụmọrụ ya.
Ọ BỤGHỊ ỌMỤNỤ Ọ BỤGHỊ MICROCHIP GA-AKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỌ Ọ BỤLA OZI Ọ BỤ Ọ BỤ Ọ BỤLA. AKWỤKWỌ NDỊ NDỊ DỊ MMADỤ N'ỤRỤ IKE MA Ọ BỤ NDỊ MMADỤ AHỤ. Ruo n'ụzọ zuru ezu iwu kwadoro, MICROCHIP'S TOTAL IBLIability na ebubo niile n'ụzọ ọ bụla metụtara ozi ahụ ma ọ bụ ojiji ya agaghị agafe ego nke ụgwọ, ma ọ bụrụ na ọ bụla, na ị kwụrụ ozugbo na-agwa ya.
Iji ngwaọrụ Microchip na nkwado ndụ yana/ma ọ bụ ngwa nchekwa bụ kpamkpam n'ihe ize ndụ nke onye zụrụ ya, onye na-azụ ya kwenyere ịgbachitere, kwụọ ụgwọ ma jide Microchip na-adịghị emerụ ahụ site na mmebi ọ bụla, nkwuputa, uwe, ma ọ bụ mmefu sitere na ụdị ojiji ahụ. Ọnweghị ikike ebugara, n'ezoghị ọnụ ma ọ bụ n'ụzọ ọzọ, n'okpuru ikike ikike ọgụgụ isi Microchip ọ gwụla ma ekwuputaghị ya.
Akara ụghalaahia
Aha Microchip na akara ngosi, akara Microchip, Adaptec, AVR, akara AVR, AVR Freaks, BestTime, BitCloud, CryptoMemory, CryptoRF, dsPIC, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXXSty MediaLB, megaAVR, Microsemi, Microsemi logo, Kasị, akara kacha, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, akara PIC32, PolarFire, Prochip Designer,  QTouch, SAM-BA, Sengenuity, SpyNIC, SST, SST Logo, SuperFlash, , SyncServer, Tachyon, TimeSource, tinyAVR, UNI/O, Vectron, na XMEGA bụ ụghalaahịa edenyere n'akwụkwọ ikikere nke Microchip Technology Incorporated na U.S.A. na obodo ndị ọzọ.
AgileSwitch, APT, ClockWorks, The agbakwunyere Control Solutions Company, EtherSynch, Flashtec, Hyper Speed ​​Control, HyperLight Load, Libero, motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet- Waya, SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub, TimePictra, TimeProvider, TrueTime, na ZL bụ ụghalaahịa edenyere n'akwụkwọ ikikere nke Microchip Technology Incorporated na USA.
Nkwụsị igodo dị n'akụkụ, AKS, Analog-maka-Digital Age, Capacitor ọ bụla, AnyIn, AnyOut, Augmented Switching, BlueSky, BodyCom, Clockstudio, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM Average Net , DAM, ECAN, Espresso T1S, EtherGREEN, GridTime, IdealBridge, In-Circuit Serial Programming, ICSP, INICnet, Intelligent Paralleling, IntelliMOS, Inter-Chip Connectivity, JitterBlocker, Knob-on-Display, KoD, maxCrypto, maxView, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB Asambodo akara, MPLIB, MPLINK, MultiTRAK, NetDetach, Usoro Ọgbọ Omniscient, PICDEM, PICDEM.net,
PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, RTAX, RTG4, SAMICE, Serial Quad I/O, simpleMAP, SimpliPHY, SmartBuffer, SmartHLS, SMART-IS., storClad, SQI, SuperSwitcher,
SuperSwitcher II, Switchtec, SynchroPHY, ngụkọta ntachi obi, oge ntụkwasị obi, TSHARC, USBCheck, VariSense, VectorBlox, VeriPHY, ViewSpan, WiperLock, XpressConnect, na ZENA bụ ụghalaahịa nke Microchip Technology Incorporated.
na U.S.A. na obodo ndi ozo.
SQTP bụ akara ọrụ Microchip Technology Incorporated na USA
Akara Adaptec, Frequency on Demand, Silicon Storage Technology, na Symmcom bụ ụghalaahịa edenyere n'akwụkwọ ikikere nke Microchip Technology Inc. na obodo ndị ọzọ.
GestIC bụ ụghalaahịa edenyere n'akwụkwọ ikikere nke Microchip Technology Germany II GmbH & Co.KG, onye enyemaka Microchip Technology Inc., na mba ndị ọzọ.
ụghalaahịa ndị ọzọ niile a kpọtụrụ aha n'ime ebe a bụ akụ nke ụlọ ọrụ ha.
© 2023, Microchip Technology Incorporated na ndị enyemaka ya. Ikike niile echekwabara.
ISBN: 978-1-6683-3694-6
Sistemụ Njikwa Ogo
Maka ozi gbasara Sistemụ Njikwa Ogo nke Microchip, biko gaa na www.microchip.com/quality.

AMERIKA	ASIA/PACIFIC	ASIA/PACIFIC	EUROPE
Ụlọ ọrụ ụlọ ọrụ 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Nkwado ndị teknuzu: www.microchip.com/support Web adreesị: www.microchip.com Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Austin, TX Tel: 512-257-3370 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Novi, MI Tel: 248-848-4000 Houston, TX Tel: 281-894-5983 Indianapolis Noblesville, IN Tel: 317-773-8323 Fax: 317-773-5453 Tel: 317-536-2380 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Tel: 951-273-7800 Raleigh, NC Tel: 919-844-7510 New York, NY Tel: 631-435-6000 San Jose, CA Tel: 408-735-9110 Tel: 408-436-4270 Canada - Toronto Tel: 905-695-1980 Fax: 905-695-2078	Australia - Sydney Nọmba ekwentị: 61-2-9868-6733 China - Beijing Nọmba ekwentị: 86-10-8569-7000 China - Chengdu Nọmba ekwentị: 86-28-8665-5511 China - Chongqing Nọmba ekwentị: 86-23-8980-9588 China - Dongguan Nọmba ekwentị: 86-769-8702-9880 China - Guangzhou Nọmba ekwentị: 86-20-8755-8029 China - Hangzhou Nọmba ekwentị: 86-571-8792-8115 China - Hong Kong SAR Tel: 852-2943-5100 China - Nanjing Nọmba ekwentị: 86-25-8473-2460 China - Qingdao Nọmba ekwentị: 86-532-8502-7355 China - Shanghai Nọmba ekwentị: 86-21-3326-8000 China - Shenyang Nọmba ekwentị: 86-24-2334-2829 China - Shenzhen Nọmba ekwentị: 86-755-8864-2200 China - Suzhou Nọmba ekwentị: 86-186-6233-1526 China - Wuhan Nọmba ekwentị: 86-27-5980-5300 China - Xian Nọmba ekwentị: 86-29-8833-7252 China - Xiamen Tel: 86-592-2388138 China - Zhuhai Tel: 86-756-3210040	India - Bangalore Nọmba ekwentị: 91-80-3090-4444 India - New Delhi Nọmba ekwentị: 91-11-4160-8631 India - Pune Nọmba ekwentị: 91-20-4121-0141 Japan - Osaka Nọmba ekwentị: 81-6-6152-7160 Japan - Tokyo Nọmba ekwentị: 81-3-6880-3770 Korea - Daegu Nọmba ekwentị: 82-53-744-4301 Korea - Seoul Nọmba ekwentị: 82-2-554-7200 Malaysia - Kuala Lumpur Nọmba ekwentị: 60-3-7651-7906 Malaysia - Penang Nọmba ekwentị: 60-4-227-8870 Philippines - Manila Nọmba ekwentị: 63-2-634-9065 Singapore Tel: 65-6334-8870 Taiwan - Hsin Chu Nọmba ekwentị: 886-3-577-8366 Taiwan - Kaohsiung Nọmba ekwentị: 886-7-213-7830 Taiwan - Taipei Nọmba ekwentị: 886-2-2508-8600 Thailand - Bangkok Nọmba ekwentị: 66-2-694-1351 Vietnam - Ho Chi Minh Nọmba ekwentị: 84-28-5448-2100	Austria – Wels Nọmba ekwentị: 43-7242-2244-39 Faksị: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4485-5910 Faksị: 45-4485-2829 Finland - Espoo Nọmba ekwentị: 358-9-4520-820 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany - na-agba ọsọ Tel: 49-8931-9700 Germany - Haan Tel: 49-2129-3766400 Germany - Heilbronn Tel: 49-7131-72400 Germany - Karlsruhe Tel: 49-721-625370 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Germany - Rosenheim Nọmba ekwentị: 49-8031-354-560 Israel - Ra'anana Nọmba ekwentị: 972-9-744-7705 Ịtali - Milan Tel: 39-0331-742611 Faksị: 39-0331-466781 Ịtali - Padova Tel: 39-049-7625286 Netherlands - mmanya Tel: 31-416-690399 Faksị: 31-416-690340 Norway - Trondheim Nọmba ekwentị: 47-72884388 Poland - Warsaw Tel: 48-22-3325737 Romania - Bucharest Tel: 40-21-407-87-50 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 Sweden - Gothenberg Tel: 46-31-704-60-40 Sweden - Stockholm Nọmba ekwentị: 46-8-5090-4654 UK - Wokingham Nọmba ekwentị: 44-118-921-5800 Faksị: 44-118-921-5820

© 2023 Microchip Technology Inc. na ndị enyemaka ya
DS50003627A -

Akwụkwọ / akụrụngwa

MICROCHIP Libero SoC Simulation Library Software [pdf] Ntuziaka onye ọrụ DS50003627A, Libero SoC Simulation Library Software, SoC Simulation Library Software, Simulation Library Software, Library Software, Software

Ntụaka

• Akwụkwọ ntuziaka onye ọrụ