Libero SoC Ukulinganisa
Imiyalelo yokuSeta iThala leeNcwadi
Intshayelelo
Injongo yolu xwebhu kukuchaza inkqubo yokuseka indawo yokulinganisa usebenzisa iprojekthi yeLibero SoC njengegalelo. Olu xwebhu luhambelana namathala eencwadi ahlanganiswe kwangaphambili anikezelwe ukusetyenziswa kunye neLibero SoC v11.9 kunye nokukhutshwa kwesoftware entsha. Amathala eencwadi abonelelweyo aqulunqelwe iVerilog. Abasebenzisi beVHDL bafuna ilayisenisi evumela ukulinganisa okuxubileyo.
Amathala eencwadi okulinganisa ahlanganisiweyo ayafumaneka kwezi zixhobo zilandelayo:
- I-Aldec Active-HDL
- Aldec Riviera-PRO
- I-Cadence Incisive Enterprise kunye ne-Xcelium
- Siemens QuestaSim
- Iisinopsy VCS
Ukucela ilayibrari yesifanisi esahlukileyo, qhagamshelana INkxaso yobuGcisa beMicrochip.
ILibero SoC Integration
I-Libero SoC ixhasa ukulinganisa usebenzisa i-ModelSim ME ngokuvelisa i-run.do file. Oku file isetyenziswa yi ModelSim ME/ModelSim Pro ME ukuseta kunye nokuqhuba ukulinganisa. Ukusebenzisa ezinye izixhobo zokulinganisa, unokuvelisa iModelSim ME/ModelSim Pro ME run.do kwaye ulungise umbhalo weTcl file ukusebenzisa imiyalelo ehambelana nesifanisi sakho.
1.1 Libero SoC Tcl File Isizukulwana (Buza umbuzo)
Emva kokudala kunye nokuvelisa uyilo kwi-Libero SoC, qalisa i-ModelSim ME / i-ModelSim Pro ME ukulinganisa phantsi kwazo zonke izigaba zoyilo (i-presynth, i-postsynth, kunye ne-post-layout). Eli nyathelo livelisa i-run.do file yeModelSim ME/ModelSim Pro ME kwisigaba ngasinye soyilo.
Kubalulekile: Emva kokuqaliswa kokwenziwa kokulinganisa ngakunye, yithiya ngokutsha i-run.do eyenziwe ngokuzenzekelayo file phantsi kolawulo lokulinganisa ukukhusela i-Libero SoC ekubhaleni ngaphezulu oko file. Umzekeloample, ifayile ye- files inokuphinda ithiywe kwakhona ku-presynth_run.do, postsynth_run.do kunye ne-postlayout_run.do.
Ukuseta i-Aldec ye-Active-HDL kunye ne-Riviera-Pro (Buza umbuzo)
I run.do file isetyenziswe yi-ModelSim ME / ModelSim Pro ME inokuguqulwa kwaye isetyenziselwe ukulinganisa usebenzisa i-simulators ye-Aldec.
2.1 Ukuguquguquka kokusingqongileyo (Buza umbuzo)
Seta ukuguquguquka kwendawo yakho kwilayisensi yakho file indawo:
LM_LICENSE_FILE: kufuneka ibandakanye isalathisi kumncedisi welayisensi.
2.2 Khuphela Ithala Leencwadi Elihlanganisiweyo (Buza umbuzo)
Khuphela amathala eencwadi eAldec Active-HDL kunye neAldec Riviera-PRO evela kwiMicrochip webindawo.
2.3 Ukuguqula i-run.do ye-Aldec simulation (Buza umbuzo)
I run.do files eyenziwe yi-Libero SoC yokulinganisa usebenzisa i-Active-HDL kunye ne-Riviera-Pro isixhobo ingasetyenziselwa ukulinganisa usebenzisa i-Active-HDL kunye ne-Riviera-Pro kunye noshintsho olulodwa. Le theyibhile ilandelayo idwelisa imiyalelo elinganayo yeAldec yokuguqula iModelSim run.do file.
Uluhlu 2-1. Imiyalelo ye-Aldec Equivalent
| ImodeliSim | Esebenzayo-HDL |
| vlog | Alog |
| vcom | acom |
| vlib | alib |
| vsim | asim |
| vmap | amap |
Okulandelayo kunjeample run.do enxulumene ne-Aldec simulators.
- Cwangcisa indawo yolawulo lwangoku olusebenzayo.
seta dsn - Cwangcisa igama lethala leencwadi elisebenzayo, imephu yendawo yalo, kwaye emva koko imephu yendawo ye-Microchip FPGA yosapho
amathala eencwadi aqulunqwe kwangaphambili (umzekeloample, SmartFusion2) apho usebenzisa uyilo lwakho.
alib presynth
amap presynth presynth
amap SmartFusion2 - Qokelela zonke ii-HDL eziyimfuneko files isetyenziswe kuyilo kunye nethala leencwadi elifunekayo.
ialog -work presynth temp.v (yeVerilog)
ialog –work presynth testbench.v
acom -work presynth temp.vhd (yeVhdl)
acom –work presynth testbench.vhd - Xelisa uyilo.
i-asim –L SmartFusion2 –L presynth –t 1ps presynth.testbench
baleka 10us
2.4 Imiba eyaziwayo (Buza umbuzo)
Eli candelo lidwelisa imiba eyaziwayo kunye nemida.
- Amathala eencwadi aqulunqwe kusetyenziswa iRiviera-PRO angqamene neqonga (oko kukuthi amathala eencwadi angama-64 akanakuqhutywa kwiqonga leebhithi ezingama-32 kwaye ngokuphendululekileyo).
- Kuyilo oluqulathe iSERDES/MDDR/FDDR, sebenzisa olu khetho lulandelayo kwi run.do yakho files ngelixa uqhuba ukulinganisa emva kokwenza uyilo lwazo:
– Active-HDL: asim –o2
- I-Riviera-PRO: i-asim -O2 (ye-presynth kunye ne-post-layout simulations ) kunye ne-asim -O5 (ye-post- layout simulations)
Ukuseta i-Aldec ye-Active-HDL kunye ne-Riviera-Pro inala ma-SAR alandelayo alindileyo. Ngolwazi oluthe vetshe, qhagamshelana INkxaso yobuGcisa beMicrochip. - I-SAR 49908 -I-HDL esebenzayo: Impazamo ye-VHDL yokulinganisa ibhloko yeMathematika
- I-SAR 50627-Riviera-PRO 2013.02: Iimpazamo zokulinganisa kuyilo lwe-SERDES
- I-SAR 50461-Riviera-PRO: i-asim -O2/-O5 ukhetho kukulinganisa
Cadence Incisive Setup (Buza umbuzo)
Kufuneka wenze iskripthi file iyafana ne ModelSim ME/ModelSim Pro ME run.do ukuqhuba i
I-Cadence Incisive simulator. Landela la manyathelo kwaye wenze iskripthi file yeNCSim okanye sebenzisa iscript file
kunikezelwe ukuguqula iModelSim ME/ModelSim Pro ME run.do files kuqwalaselo files
efunekayo ukuqhuba ukulinganisa usebenzisa i-NCSim.
Kubalulekile: Cadence iyekile ukukhupha iinguqulelo ezintsha ze-Incisive Enterprise
simulator kwaye waqala ukuxhasa iXcelium simulator.
3.1 Izinto eziguquguqukayo zokusingqongileyo (Buza umbuzo)
Ukusebenzisa iCadence Incisive simulator, qwalasela oku kuguquguquka kwemekobume kulandelayo:
- LM_LICENSE_FILE: kufuneka ibandakanye isalathisi kwilayisensi file.
- cds_root: kufuneka yalathe kuvimba weefayili wasekhaya weCadence Incisive Installation.
- UMENDO: kufuneka yalathe kwindawo yomgqomo phantsi kolawulo lwezixhobo oluphawulwe yi cds_root ethi,
$ cds_root/tools/bin/64bit (ye-64-bit machine kunye ne $cds_root/tools/bin for a 32-bit machine).
Kukho iindlela ezintathu zokuseta imeko-bume yokulinganisa kwimeko yokutshintsha phakathi kwe-64-bit kunye ne-32-bit yeenkqubo zokusebenza:
Imeko 1: UMENDO Oguquguqukayo
Yenza lo myalelo ulandelayo:
cwangcisa indlela = (install_dir/tools/bin/64bit $path) kumatshini we64bit kunye
misela indlela = (install_dir/tools/bin $path) kumatshini we-32bit
Ityala lesi-2: Ukusebenzisa i -64bit Umyalelo woKhetho lomgca womyalelo
Kumgca womyalelo ucacise -64bit ukhetho ukuze ubize i-64bit ephunyeziweyo.
Imeko 3: Ukucwangcisa iINCA_64BIT okanye iCDS_AUTO_64BIT eguquguqukayo
I-INCA_64BIT eguquguqukayo iphathwa njenge boolean. Ungacwangcisa oku kuguquguquka kulo naliphi na ixabiso okanye kumtya ongenanto.
setenv INCA_64BIT
Kubalulekile: I INCA_64BIT ukuguquguquka kwemekobume azizichaphazeli ezinye izixhobo zeCadence, njengezixhobo ze-IC. Nangona kunjalo, kwi-Incisive tools, i-INCA_64BIT eguquguqukayo ibeka ngaphezulu kwesicwangciso seCDS_AUTO_64BIT eguquguqukayo. Ukuba i-INCA_64BIT imo eguquguqukayo iseti, zonke izixhobo ze-Incisive zisebenza kwimowudi ye-64-bit. setenv CDS_AUTO_64BIT IBUKA:INCA
Kubalulekile: I umtya INCA kufuneka ibe ngoonobumba abakhulu. Zonke izinto eziphunyeziweyo maziqhutywe nokuba yi-32-bit mode okanye kwi-64-bit mode, musa ukuseta ukuguquguquka ukubandakanya enye ephunyeziweyo, njengokulandelayo:
setenv CDS_AUTO_64BIT IBANDAKANYA:ncelab
Ezinye izixhobo zeCadence, ezifana nezixhobo ze-IC, nazo zisebenzisa i-CDS_AUTO_64BIT eguquguqukayo yemo engqongileyo ukulawula ukhetho lwe-32-bit okanye i-64-bit ephunyeziweyo. Itheyibhile ilandelayo ibonisa ukuba unokuseta njani iCDS_AUTO_64BIT eguquguqukayo ukuze usebenzise izixhobo ze-Incisive kunye nezixhobo ze-IC kuzo zonke iindlela.
Uluhlu 3-1. CDS_AUTO_64BIT izinto ezahlukeneyo
| CDS_AUTO_64BIT eguquguqukayo | Izixhobo ezikhawulezayo | Izixhobo ze-IC |
| setenv CDS_AUTO_64BIT ZONKE | 64 bit | 64 bit |
| setenv CDS_AUTO_64BIT NONE | 32 bit | 32 bit |
| setenv CDS_AUTO_64BIT AKAHLANGANISI:ic_binary | 64 bit | 32 bit |
| setenv CDS_AUTO_64BIT ABANGAPHAMBILI:INCA | 32 bit | 64 bit |
Kubalulekile: Zonke izixhobo ze-Incisive kufuneka ziqhutywe nokuba yi-32-bit mode okanye kwi-64-bit mode, musa ukusebenzisa EXCLUDE ukungabandakanyi ukuphunyezwa okuthile, njengoko kulandelayo: setenv CDS_AUTO_64BIT EXCLUDE:ncelab
Ukuba ngaba umisela iCDS_AUTO_64BIT eguquguqukayo ukuba ingabandakanyi izixhobo ze-Incisive (setenv CDS_AUTO_64BIT EXCLUDE:INCA), zonke izixhobo ze-Incisive ziqhutywa kwimowudi ye-32-bit. Nangona kunjalo, i -64bit yomyalelo we-line yomyalelo ikhetha ngaphezulu kokuguquguquka kokusingqongileyo.
Olu qwalaselo lulandelayo files kukunceda ulawule idatha yakho kwaye ulawule ukusebenza kwezixhobo zokulinganisa kunye nezinto eziluncedo:
- Imephu yethala leencwadi file (cds.lib)—Ichaza igama elinengqiqo lendawo yoyilo lwakho.
- Amathala eencwadi kwaye uwanxulumanise namagama olawulo lwendawo.
- Izinto eziguquguqukayo file (hdl.var) -Ichaza izinto eziguquguqukayo ezichaphazela ukuziphatha kwezixhobo zokulinganisa kunye nezixhobo.
3.2 Khuphela Ithala Leencwadi Elihlanganisiweyo (Buza umbuzo)
Khuphela amathala eencwadi eCadence Incisive kwaMicrosemi's webindawo.
3.3 Ukwenza i-NCSim Script File (Buza umbuzo)
Emva kokudala ikopi ye run.do files, yenza la manyathelo ukuqhuba ukulinganisa kwakho usebenzisa i-NCSim:
- Yenza i-cds.lib file echaza amathala eencwadi afikelelekayo kunye nendawo yawo. I file iqulethe iinkcazelo ezenza imaphu yamagama elayibrari anengqiqo kwiindlela zabo zolawulo lwendawo. UmzekeloampLe, ukuba usebenzisa i-presynth simulation, i cds.lib file ibhaliwe njengoko kubonisiwe kwikhowudi yekhowudi elandelayo.
CHAZA i-presynth ./presynth
DEFINE COREAHBLITE_LIB ./COREAHBLITE_LIB
CHAZA i-smartfusion2 - Yenza i-hdl.var file, uqwalaselo olukhethwayo file equlathe uqwalaselo oluguquguqukayo, olumisela ukuba imekobume yakho yoyilo iqwalaselwe njani. Olu tshintsho lulandelayo files zibandakanyiwe:
- Iinguqu ezisetyenziselwa ukucacisa ilayibrari yomsebenzi apho umqokeleli ugcina izinto eziqulunqiweyo kunye nezinye iinkcukacha ezifunyenweyo.
- KwiVerilog, izinto ezahlukeneyo (LIB_MAP, VIEW_MAP, UMSEBENZI) ezisetyenziselwa ukukhankanya amathala eencwadi kunye views ukukhangela xa umaluleki elungisa iimeko.
-Iiguquguquko ezikuvumela ukuba uchaze umqokeleli, i-elaborator, kunye ne-simulator ukhetho lomgca womyalelo kunye neengxoxo.
Kwimeko yokulinganisa i-presynth exampLe iboniswe ngasentla, yithi sine-RTL ezintathu files: av, bv, kunye testbench.v, ekufuneka idityaniswe ibe presynth, COREAHBLITE_LIB, kunye presynth amathala eencwadi ngokulandelelanayo. I-hdl.var file ingabhalwa njengoko kubonisiwe kwikhowudi yekhowudi elandelayo.
CINGA UMSEBENZI presynth
CHAZA IPROJEKTHI_DIR files>
CHAZA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/av => presynth )
CHAZA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/bv => COREAHBLITE_LIB )
CHAZA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/testbench.v => presynth )
CHAZA LIB_MAP ( $LIB_MAP, + => presynth ) - Qokelela uyilo files usebenzisa i-ncvlog ukhetho.
ncvlog +incdir+ –cdslib ./cds.lib –hdlvar ./hdl.var –logfile
ncvlog.log –uhlaziyo –linedebug av bv testbench.v - Cacisa uyilo usebenzisa i-ncelab. I-elaborator yakha i-hierarchy yoyilo esekelwe kwi-instantiation kunye nolwazi loqwalaselo kuyilo, iseka uxhulumaniso lwesignali, kwaye ibala ixabiso lokuqala kuzo zonke izinto ezikuyilo. Ubume boyilo obunabileyo bugcinwe kwisnapshot yokulinganisa, eluphawu loyilo lwakho olusetyenziswa sisilingisi ukuqhuba ukulinganisa.
ncelab –Umyalezo –cdslib ./cds.lib –hdlvar ./hdl.var –logfile celab.log -errormax 15 -
ukufikelela ku-+rwc-imo yokusebenza. :modyuli
Ukucaciswa Ngexesha lokulinganisa kwePost-layout
Kwimeko ye-post-layout simulations, kuqala i-SDF file ifuna ukuqokelelwa phambi kobalo kusetyenziswa umyalelo wencsdfc.
ncdfcfileigama>.sdf –imvelisofileigama>.sdf.X
Ngexesha lokucacisa sebenzisa imveliso yeSDF ehlanganisiweyo nge-autosdf ukhetho njengoko kubonisiwe kwikhowudi yekhowudi elandelayo.
ncelab -autosdf –Umyalezo –cdslib ./cds.lib –hdlvar ./hdl.var –logfile ncelab.log –errormax
I-15 -ufikelelo +rwc -isimo somsebenzi. :imodyuli -sdf_cmd_file ./
sdf_cmd_file
I sdf_cmd_file kufuneka kube njengoko kubonisiwe kwikhowudi yekhowudi elandelayo.
COMPILED_SDF_FILE = " file>” - Ukulinganisa usebenzisa i-ncsim. Emva kokucaciswa kwesnapshot yokulinganisa yenziwa, elayishwa yincsim yokulinganisa. Unokubaleka kwimowudi yebhetshi okanye imowudi yeGUI.
ncsim –Umyalezo –batch/-gui –cdslib ./cds.lib –hdlvar ./hdl.var –logfile ncsim.log -
errormax 15 -status worklib. :modyuli
Kubalulekile: Onke la manyathelo mathathu angasentla okuqulunqa, ukucacisa, kunye nokulinganisa anokufakwa kwiskripthi seqokobhe file kwaye ithathwe kumgca womyalelo. Endaweni yokusebenzisa la manyathelo mathathu, uyilo lunokulinganisa kwinqanaba elinye usebenzisa i-ncverilog okanye irun ukhetho njengoko kubonisiwe kwikhowudi yekhowudi elandelayo.
ncverilog +incdir+ -cdslib ./cds.lib –hdlvar ./hdl.var
files isetyenziswe kuyilo>
irun +incdir+ -cdslib ./cds.lib –hdlvar ./hdl.var files
isetyenziswe kuyilo>
3.3.1 Imiba eyaziwayo (Buza umbuzo)
Testbench Workaround
Ukusebenzisa le nkcazo elandelayo ukucacisa i-clock frequency kwi-testbench eyenziwe ngumsebenzisi, okanye i-testbench engagqibekanga eyenziwa yi-Libero SoC ayisebenzi kunye ne-NCSim.
rhoqo @(SYSCLK)
#(SYSCLK_PERIOD / 2.0) SYSCLK <= !SYSCLK;
Lungisa ngolu hlobo lulandelayo ukuqhuba ukulinganisa:
rhoqo #(SYSCLK_PERIOD / 2.0) SYSCLK = ~SYSCLK;
Kubalulekile: Ihlanganiswe amathala eencwadi e-NCSim angqamene neqonga (oko kukuthi amathala eencwadi angama-64 awahambelani neqonga lamasuntswana angama-32 kwaye ngokuphendululekileyo).
I-Postsynth kunye ne-Post-layout Ukulinganisa usebenzisa i-MSS kunye ne-SERDES Ngelixa usebenzisa ukulinganisa kwe-postsynth yoyilo oluqulathe ibhloko ye-MSS okanye ukulinganisa emva koyilo loyilo usebenzisa i-SERDES, ukulinganisa kwe-BFM akusebenzi ukuba ukhetho lwe -libmap luyi.
ayichazwanga ngexesha lokucaciswa. Oku kungenxa yokuba ngexesha lokucaciswa, i-MSS isonjululwe kwilayibrari yomsebenzi (ngenxa yesibophelelo esingagqibekanga kunye nencwadi yokusebenza ibe yi-postsynth/post-layout) apho inguMsebenzi oMiselweyo nje.
Umyalelo we-ncelab kufuneka ubhalwe njengoko kubonisiwe kwibhloko yekhowudi elandelayo ukusombulula i-MSS
ibhlokhi kwithala leencwadi leSmartFusion2 esele liqulunqwe.
ncelab -libmap lib.map -libverbose -ufikelelo lomyalezo +rwc cfg1
kunye ne-lib.map file kufuneka ibe ngolu hlobo lulandelayo:
uqwalaselo cfg1;
uyilo ;
uluhlu olusisiseko smartfusion2 ;
endconfig
Oku kusombulula nayiphi na iseli kwithala leencwadi leSmartFusion2 phambi kokujonga kwithala leencwadi okt postsynth/ post-layout.
Ukhetho lwe-libmap lunokusetyenziswa ngokungagqibekanga ngexesha lokucaciswa kwayo yonke imilinganiso (i-presynth, i-postsynth, kunye ne-post-layout). Oku kuthintela imiba yokulinganisa ebangelwa kukulungiswa kweemeko ezivela kumathala eencwadi.
ncelab: *F,I-INTERR: UKWEHLUKA NGAPHAKATHI
Esi sixhobo se-ncelab ngaphandle kwe-caveat yoyilo oluqukethe i-FDDR kwi-SmartFusion 2 kunye ne-IGLOO 2 ngexesha le-postsynth kunye ne-post-layout simulations usebenzisa i-libmap inketho.
Kubalulekile: Lo mbandela uxelwe kwiqela lenkxaso yeCadence (SAR 52113).
3.4Sample Tcl kunye neShell Script Files (Buza umbuzo)
Ezilandelayo files luqwalaselo files ezifunekayo ukuseta uyilo kunye neskripthi seqokobhe file ukwenza imiyalelo ye-NCSim.
Cds.lib
NE smartfusion2 /scratch/krydor/tmpspace/users/me/nc-vlog64/SmartFusion2
DEFINE COREAHBLITE_LIB ./COREAHBLITE_LIB
CHAZA i-presynth ./presynth
Hdl.var
CINGA UMSEBENZI presynth
CHAZA IPROJEKTHI_DIR /scratch/krydor/tmpspace/sqausers/me/3rd_party_simulators/Cadence/IGLOO2/
ENVM/M2GL050/envm_fic1_ser1_v/eNVM_fab_master
CHAZA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/core/coreahblite_addrdec.v => COREAHBLITE_LIB )
CHAZA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/core/coreahblite_defaultslavesm.v => COREAHBLITE_LIB )
CHAZA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/core/coreahblite_masterstagev => COREAHBLITE_LIB )
CHAZA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/core/coreahblite_slavearbiter.v => COREAHBLITE_LIB )
CHAZA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/core/coreahblite_slavestagev => COREAHBLITE_LIB )
CHAZA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/core/coreahblite_matrix2x16.v => COREAHBLITE_LIB )
CHAZA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/core/coreahblite.v => COREAHBLITE_LIB )
CHAZA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB/CCC_0/SB_CCC_0_FCC.v =>
presynth )
CHAZA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreConfigMaster/
2.0.101/rtl/vlog/core/coreconfigmaster.v => presynth )
CHAZA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreConfigP/4.0.100/rtl/
vlog/core/coreconfigp.v => presynth )
CHAZA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreResetP/5.0.103/rtl/
vlog/core/coresetp_pcie_hotreset.v => presynth )
CHAZA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreResetP/5.0.103/rtl/
vlog/core/coresetp.v => presynth )
CHAZA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB/FABOSC_0/SB_FABOSC_0_OSC.v =>
presynth )
CHAZA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB_HPMS/SB_HPMS.v => presynth )
CHAZA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB/SB.v => presynth )
CHAZA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB_top/SERDES_IF_0/
SB_top_SERDES_IF_0_SERDES_IF.v => presynth )
CHAZA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB_top/SB_top.v => presynth)
CHAZA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB_top/testbench.v => presynth)
CHAZA LIB_MAP ( $LIB_MAP, + => presynth )
Imiyalelo.csh
ncvlog +incdir+../../component/work/SB_top -cdslib ./cds.lib -hdlvar ./hdl.var -logfile
ncvlog.log -errormax 15 -uhlaziyo -linedebug
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite_addrdec.v
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/
coreahblite_defaultslavesm.v
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite_masterstagev
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite_slavearbiter.v
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite_slavestagev
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite_matrix2x16.v
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite.v
../../component/work/SB/CCC_0/SB_CCC_0_FCCC.v
../../component/Actel/DirectCore/CoreConfigMaster/2.0.101/rtl/vlog/core/coreconfigmaster.v
../../component/Actel/DirectCore/CoreConfigP/4.0.100/rtl/vlog/core/coreconfigp.v
../../component/Actel/DirectCore/CoreResetP/5.0.103/rtl/vlog/core/coreresetp_pcie_hotreset.v
../../component/Actel/DirectCore/CoreResetP/5.0.103/rtl/vlog/core/coreresetp.v
../../component/work/SB/FABOSC_0/SB_FABOSC_0_OSC.v ../../component/work/SB_HPMS/SB_HPMS.v
../../component/work/SB/SB.v ../../component/work/SB_top/SERDES_IF_0/
SB_top_SERDES_IF_0_SERDES_IF.v
../../component/work/SB_top/SB_top.v ../../component/work/SB_top/testbench.v
ncelab -Umyalezo -cdslib ./cds.lib -hdlvar ./hdl.var
-work presynth -logfile ncelab.log -errormax 15 -access +rwc -status presynth.testbench:modyuli
ncsim -Ibhetshi yomyalezo -cdslib ./cds.lib -hdlvar ./
hdl.var -logfile ncsim.log -errormax 15 -status presynth.testbench:modyuli
3.5 Ukuzenzela (Buza umbuzo)
Umbhalo olandelayo file iguqula iModelSim run.do files kuqwalaselo files efunekayo ukuqhuba ukulinganisa usebenzisa i-NCSim.
Ushicilelo File Ukusetyenziswa
perl cadence_parser.pl presynth_run.do postsynth_run.do
postlayout_run.do Microsemi_Family
Indawo_ye-Cadence_Ilayibrari_eQinisekisiweyo
Cadence_parser.pl
#!/usr/bin/perl -w
##################################################### ############################################
###################
#Ukusetyenziswa: perl questa_parser.pl presynth_run.do postsynth_run.do postlayout_run.do
Microsemi_Family Precompiled_Libraries_location#
##################################################### ############################################
###################
sebenzisa iPOSIX;
sebenzisa ngqongqo;
yam ($ presynth, $ postsynth, $ postlayout, $ family, $ lib_location) = @ARGV;
&questa_parser($ presynth, $family, $lib_location);
&questa_parser($ postsynth, $family, $lib_location);
& questa_parser($ postlayout, $family, $lib_location);
i-questa_parser {
my $ModelSim_run_do = $_[0];
my $ actel_family = $_[1];
my $ lib_location = $_[2];
imeko yam ye-$;
ukuba (-e “$ModelSim_run_do” )
{
vula (INFILE,”$ModelSim_run_do”);
yam @ModelSim_run_do =FILE>;
umgca wam we-$;
ukuba ( $ModelSim_run_do =~ m/(presynth)/)
{
`mkdir QUESTA_PRESYNTH`;
vula (OUTFILE,”>QUESTA_PRESYNTH/presynth_questa.do”);
I-$ yelizwe = $ 1;
} elsif ( $ModelSim_run_do =~ m/(postsynth)/)
{
`mkdir QUESTA_POSTSYNTH`;
vula (OUTFILE,”>QUESTA_POSTSYNTH/postsynth_questa.do”);
I-$ yelizwe = $ 1;
} elsif ( $ModelSim_run_do =~ m/(uyilo lokuposa)/ )
{
`mkdir QUESTA_POSTLAYOUT`;
vula (OUTFILE,”>QUESTA_POSTLAYOUT/postlayout_questa.do”);
I-$ yelizwe = $ 1;
} Omnye
{
print “Iingeniso ezingalunganga ezinikwe kwi file\n";
shicilela “#Usetyenziso: perl questa_parser.pl presynth_run.do postsynth_run.do postlayout_run.do
\”Indawo_yethala leencwadi\”\n”;
}
i-foreach $line (@ModelSim_run_do)
{
#Imisebenzi gabalala
$line =~ s/..\/designer.*ukulinganisa\///g;
Umgca we-$ =~ s/$state/$state\_questa/g;
#Shicilela iphumeFILE “$line \n”;
ukuba ($line =~ m/vmap\s+.*($actel_family)/)
{
Shicilela iphumeFILE “vmap $actel_family \”$lib_location\”\n”;
} elsif (umgca we-$ =~ m/vmap\s+(.*._LIB)/)
{
$line =~ s/..\/component/..\/..\/component/g;
Shicilela iphumeFILE “$line \n”;
} i-elsif (umgca we-$ =~ m/vsim/)
{
$ umgca =~ s/vsim/vsim -novopt/g;
Shicilela iphumeFILE “$line \n”;
} Omnye
{
Shicilela iphumeFILE “$line \n”;
}
}
vala (INFILE);
ivalelwe ngaphandleFILE);
} enye {
printa “$ModelSim_run_do ayikho. Phinda wenze ukulinganisa kwakhona \n”;
}
}
Ukusekwa kweCadence Xcelium (Microchip Ngena)
Kufuneka wenze iskripthi file iyafana neModelSim ME/ModelSim Pro ME run.do ukuqhuba iCadence Xcelium simulator. Landela la manyathelo kwaye wenze iskripthi file yeXcelium okanye sebenzisa iscript file kunikezelwe ukuguqula iModelSim ME/ModelSim Pro ME run.do files kuqwalaselo files efunekayo ukuqhuba ukulinganisa usebenzisa i-Xcelium.
4.1 Izinto eziguquguqukayo zokusingqongileyo (Buza umbuzo)
Ukusebenzisa iCadence Xcelium, qwalasela iimeko-bume eziguquguqukayo zilandelayo:
- LM_LICENSE_FILE: kufuneka ibandakanye isalathisi kwilayisensi file.
- cds_root: kufuneka yalathe kuvimba weefayili wasekhaya weCadence Incisive Installation.
- UMENDO: kufuneka yalathe kwindawo yomgqomo phantsi kolawulo lwezixhobo oluphawulwe yi-cds_root (okt
$cds_root/tools/bin/64bit (ye-bit machine 64 kwaye $cds_root/tools/bin for a 32 bit
umatshini).
Kukho iindlela ezintathu zokuseta imeko-bume yokulinganisa kwimeko yokutshintsha phakathi kwe-64-bit kunye ne-32-bit yeenkqubo zokusebenza:
Imeko 1: UMENDO Oguquguqukayo
cwangcisa indlela = (install_dir/tools/bin/64bit $path) kumatshini we64bit kunye
misela indlela = (install_dir/tools/bin $path) kumatshini we-32bit
Ityala lesi-2: Ukusebenzisa i -64bit Umyalelo woKhetho lomgca womyalelo
Kumgca womyalelo cacisa -64bit ukhetho ukuze ubize i-64-bit ephunyeziweyo.
Imeko 3: Ukucwangcisa iINCA_64BIT okanye iCDS_AUTO_64BIT eguquguqukayo
I-INCA_64BIT eguquguqukayo iphathwa njenge boolean. Ungacwangcisa oku kuguquguquka kulo naliphi na ixabiso okanye kwi-null
umtya.
setenv INCA_64BIT
Kubalulekile: I INCA_64BIT ukuguquguquka kwemekobume azizichaphazeli ezinye izixhobo zeCadence, njengezixhobo ze-IC. Nangona kunjalo, kwi-Incisive tools, i-INCA_64BIT eguquguqukayo ibeka ngaphezulu kwesicwangciso seCDS_AUTO_64BIT eguquguqukayo. Ukuba i-INCA_64BIT imo eguquguqukayo i-et, zonke izixhobo ze-Incisive zisebenza kwimowudi ye-64-bit.
setenv CDS_AUTO_64BIT IBUKA:INCA
Kubalulekile: I umtya INCA kufuneka ibe ngoonobumba abakhulu. Zonke izinto eziphunyeziweyo maziqhutywe nokuba yi-2-bit mode okanye kwi-64-bit mode, musa ukuseta ukuguquguquka ukubandakanya enye ephunyeziweyo, njengokulandelayo:
setenv CDS_AUTO_64BIT IBANDAKANYA:ncelab
Ezinye izixhobo zeCadence, ezifana nezixhobo ze-IC, nazo zisebenzisa i-CDS_AUTO_64BIT eguquguqukayo yemo engqongileyo ukulawula ukhetho lwe-32-bit okanye i-64-bit ephunyeziweyo. Itheyibhile ilandelayo ibonisa ukuba unokuseta njani iCDS_AUTO_64BIT eguquguqukayo ukuze usebenzise izixhobo ze-Incisive kunye nezixhobo ze-IC kuzo zonke iindlela.
Uluhlu 4-1. CDS_AUTO_64BIT izinto ezahlukeneyo
| CDS_AUTO_64BIT eguquguqukayo | Izixhobo ezikhawulezayo | Izixhobo ze-IC |
| setenv CDS_AUTO_64BIT ZONKE | 64-bit | 64-bit |
| setenv CDS_AUTO_64BIT NONE | 32-bit | 32-bit |
| setenv CDS_AUTO_64BIT QAPHELA:ic_binary |
64-bit | 32-bit |
| setenv CDS_AUTO_64BIT ABANGAPHAMBILI:INCA | 32-bit | 64-bit |
Kubalulekile: Zonke izixhobo ze-Incisive kufuneka ziqhutywe nokuba yi-32-bit mode okanye kwi-64-bit mode, musa ukusebenzisa EXCLUDE ukungabandakanyi into ethile ephunyezwayo, njengoko kulandelayo:
setenv CDS_AUTO_64BIT ABANGAPHAMBILI:ncelab
Ukuba ucwangcisa i CDS_AUTO_64BIT eguquguqukayo ukukhuphela ngaphandle izixhobo eziIncisive (setenv
CDS_AUTO_64BIT EXCLUDE:INCA), zonke izixhobo ze-Incisive ziqhutywa kwimowudi ye-32-bit. Nangona kunjalo, i
-64bit inketho yomgca womyalelo ingaphezulu kokuguquguquka kokusingqongileyo.
Olu qwalaselo lulandelayo files kukunceda ulawule idatha yakho kwaye ulawule ukusebenza kwezixhobo zokulinganisa kunye nezinto eziluncedo:
- Imephu yethala leencwadi file (cds.lib) ichaza igama elinengqiqo lendawo yoyilo lwakho.
- Amathala eencwadi kwaye uwanxulumanise namagama olawulo lwendawo.
- Izinto eziguquguqukayo file (i-hdl.var) ichaza iinguqu ezichaphazela ukuziphatha kwezixhobo zokulinganisa kunye nezinto eziluncedo.
4.2 Khuphela Ithala Leencwadi Elihlanganisiweyo (Buza umbuzo)
Khuphela amathala eencwadi eCadence Xcelium evela kwiMicrosemi's webindawo.
4.3 Ukwenza iscript seXcelium file (Buza umbuzo)
Emva kokudala ikopi ye run.do files, yenza la manyathelo alandelayo ukuqhuba ukulinganisa kwakho usebenzisa i-Xcelium script file.
- Yenza i-cds.lib file echaza ukuba ngawaphi amathala eencwadi afikelelekayo nalapho akhoyo.
I file iqulethe iinkcazelo ezenza imaphu yamagama elayibrari anengqiqo kwiindlela zabo zolawulo lwendawo. UmzekeloampLe, ukuba usebenzisa i-presynth simulation, i cds.lib file ingabhalwa njengoko kubonisiwe kwikhowudi yekhowudi elandelayo.
CHAZA i-presynth ./presynth
DEFINE COREAHBLITE_LIB ./COREAHBLITE_LIB
CHAZA i-smartfusion2 - Yenza i-hdl.var file oluluqwalaselo olukhethwayo file equlathe uqwalaselo oluguquguqukayo, olumisela ukuba imekobume yakho yoyilo iqwalaselwe njani. Ezi ziquka:
- Iinguqu ezisetyenziselwa ukucacisa ilayibrari yomsebenzi apho umqokeleli ugcina izinto eziqulunqiweyo kunye nezinye iinkcukacha ezifunyenweyo.
- KwiVerilog, izinto ezahlukeneyo (LIB_MAP, VIEW_MAP, UMSEBENZI) ezisetyenziselwa ukukhankanya amathala eencwadi kunye views ukukhangela xa umaluleki elungisa iimeko.
-Iiguquguquko ezikuvumela ukuba uchaze umqokeleli, i-elaborator, kunye ne-simulator ukhetho lomgca womyalelo kunye neengxoxo.
Kwimeko yokulinganisa i-presynth exampLe iboniswe ngasentla, yithi sine-3 RTL files av, bv, kunye ne-testbench.v, ekufuneka iqokelelwe ibe yipresynth, COREAHBLITE_LIB, kunye namathala eencwadi epresynth ngokulandelelanayo. I-hdl.var file ingabhalwa njengoko kubonisiwe kwikhowudi yekhowudi elandelayo.
CINGA UMSEBENZI presynth
CHAZA IPROJEKTHI_DIR files>
CHAZA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/av => presynth )
CHAZA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/bv => COREAHBLITE_LIB )
CHAZA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/testbench.v => presynth )
CHAZA LIB_MAP ( $LIB_MAP, + => presynth ) - Qokelela uyilo files usebenzisa i-ncvlog ukhetho.
xmvlog +incdir+ –cdslib ./cds.lib –hdlvar ./hdl.var –logfile
ncvlog.log –uhlaziyo –linedebug av bv testbench.v - Cacisa uyilo usebenzisa i-ncelab. I-elaborator yakha i-hierarchy yoyilo esekelwe kwi-instantiation kunye nolwazi loqwalaselo kuyilo, iseka uxhulumaniso lwesignali, kwaye ibala ixabiso lokuqala kuzo zonke izinto ezikuyilo. Ubume boyilo obunabileyo bugcinwe kwisnapshot yokulinganisa, eluphawu loyilo lwakho olusetyenziswa sisilingisi ukuqhuba ukulinganisa.
Xcelium –Umyalezo –cdslib ./cds.lib –hdlvar ./hdl.var –logfile celab.log -errormax 15 -
ukufikelela ku-+rwc-imo yokusebenza. :modyuli
Ukucaciswa Ngexesha lokulinganisa kwePost-layout
Kwimeko ye-post-layout simulations, kuqala i-SDF file ifuna ukuqokelelwa phambi kobalo kusetyenziswa umyalelo wencsdfc.
Xceliumfileigama>.sdf –imvelisofileigama>.sdf.X
Ngexesha lokucacisa sebenzisa imveliso yeSDF ehlanganisiweyo nge-autosdf ukhetho njengoko kubonisiwe kwikhowudi yekhowudi elandelayo.
xmelab -autosdf –Umyalezo –cdslib ./cds.lib –hdlvar ./hdl.var –logfile ncelab.log –errormax
I-15 -ufikelelo +rwc -isimo somsebenzi. :imodyuli -sdf_cmd_file ./
sdf_cmd_file
I sdf_cmd_file kufuneka kube njengoko kubonisiwe kwikhowudi yekhowudi elandelayo.
COMPILED_SDF_FILE = " file>” - Xelisa usebenzisa i-Xcelium. Emva kokucaciswa kwe-snapshot yokulinganisa yenziwa elayishwe yi-Xcelium yokulinganisa. Oku kunokuqhutywa kwimo yebhetshi okanye kwimo ye-GUI.
xmsim –Umyalezo –batch/-gui –cdslib ./cds.lib –hdlvar ./hdl.var –logfile xmsim.log -
errormax 15 -status worklib. :modyuli
Ukusekwa kweCadence Xcelium
Kubalulekile: Konke la manyathelo mathathu angasentla okuqulunqa, ukucacisa kunye nokulinganisa anokufakwa kwiskripthi seqokobhe file kwaye ithathwe kumgca womyalelo. Endaweni yokusebenzisa la manyathelo mathathu, uyilo lunokulinganisa kwinqanaba elinye usebenzisa i-ncverilog okanye i-xrun ukhetho njengoko kubonisiwe kwikhowudi yekhowudi elandelayo.
xmverilog +incdir+ -cdslib ./cds.lib –hdlvar ./hdl.var
files isetyenziswe kuyilo>
xrun +incdir+ -cdslib ./cds.lib –hdlvar ./hdl.var files
isetyenziswe kuyilo>
4.3.1 Imiba eyaziwayo (Buza umbuzo)
Testbench Workaround
Ukusebenzisa le nkcazo elandelayo ukucacisa i-clock frequency kwi-testbench eyenziwe ngumsebenzisi okanye i-testbench engagqibekanga eyenziwa yi-Libero SoC ayisebenzi kunye ne-Xcelium.
rhoqo @(SYSCLK)
#(SYSCLK_PERIOD / 2.0) SYSCLK <= !SYSCLK;
Lungisa ngolu hlobo lulandelayo ukuqhuba ukulinganisa:
rhoqo #(SYSCLK_PERIOD / 2.0) SYSCLK = ~SYSCLK;
Kubalulekile: Amathala eencwadi aqokelelweyo e-Xcelium angqamene neqonga (oko kukuthi, amathala eencwadi angama-64 awahambelani neqonga lamasuntswana angama-32 kwaye ngokuphendululekileyo).
I-Possynth kunye ne-Post-layout Ukulinganisa usebenzisa i-MSS kunye ne-SERDES
Ngelixa uqhuba ukulinganisa kwe-postsynth yoyilo oluqulethe ibhloko ye-MSS, okanye ukulinganisa emva koyilo lwezakhiwo usebenzisa i-SERDES, ukulinganisa kwe-BFM akusebenzi ukuba i-libmap inketho ayichazwanga ngexesha lokuchazwa. Oku kungenxa yokuba ngexesha lokucaciswa, i-MSS isonjululwe kwilayibrari yomsebenzi (ngenxa yesibophelelo esingagqibekanga kunye nencwadi yokusebenza ibe yi-postsynth/post-layout) apho inguMsebenzi oMiselweyo nje.
Umyalelo we-ncelab kufuneka ubhalwe njengoko kubonisiwe kwibhloko yekhowudi elandelayo ukusombulula ibhloko ye-MSS evela kwilayibrari esele yenziwe i-SmartFusion2.
xmelab -libmap lib.map -libverbose -ufikelelo lomyalezo +rwc cfg1
kunye ne-lib.map file kufuneka ibe ngolu hlobo lulandelayo:
uqwalaselo cfg1;
uyilo ;
uluhlu olusisiseko smartfusion2 ;
endconfig
Oku kufuneka kusonjululwe nayiphi na iseli kwithala leencwadi le-SmartFusion2 phambi kokujonga kwithala leencwadi okt postsynth/post-layout.
Ukhetho lwe-libmap lunokusetyenziswa ngokungagqibekanga ngexesha lokucaciswa kwayo yonke into yokulinganisa (i-presynth, i-postsynth kunye ne-post-layout). Oku kuthintela imiba yokulinganisa ebangelwa kukulungiswa kweemeko ezivela kumathala eencwadi.
xmelab: *F,INTERR: UKUNGAMTHETHO NGAPHAKATHI
Esi sixhobo se-ncelab ngaphandle kwe-caveat yoyilo oluqulathe i-FDDR kwi-SmartFusion2 kunye ne-IGLOO2
ngexesha le-postsynth kunye ne-post-layout simulations usebenzisa i-libmap ukhetho.
Kubalulekile: Lo mbandela uxelwe kwiqela lenkxaso yeCadence (SAR 52113).
4.4Sample Tcl kunye neskripthi seqokobhe files (Buza umbuzo)
Ezilandelayo files luqwalaselo files ezifunekayo ukuseta uyilo kunye neskripthi seqokobhe file ukwenza imiyalelo ye-Xcelium.
Cds.lib
CHAZA i-smartfusion2 /scratch/krydor/tmpspace/users/me/nc-vlog64/SmartFusion2
DEFINE COREAHBLITE_LIB ./COREAHBLITE_LIB
CHAZA i-presynth ./presynth
Hdl.var
CINGA UMSEBENZI presynth
CHAZA IPROJEKTHI_DIR /scratch/krydor/tmpspace/sqausers/me/3rd_party_simulators/Cadence/IGLOO2/
ENVM/M2GL050/envm_fic1_ser1_v/eNVM_fab_master
CHAZA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/core/coreahblite_addrdec.v => COREAHBLITE_LIB )
CHAZA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/core/coreahblite_defaultslavesm.v => COREAHBLITE_LIB )
CHAZA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/core/coreahblite_masterstagev => COREAHBLITE_LIB )
CHAZA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/core/coreahblite_slavearbiter.v => COREAHBLITE_LIB )
CHAZA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/core/coreahblite_slavestagev => COREAHBLITE_LIB )
CHAZA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/core/coreahblite_matrix2x16.v => COREAHBLITE_LIB )
CHAZA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/core/coreahblite.v => COREAHBLITE_LIB )
CHAZA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB/CCC_0/SB_CCC_0_FCC.v =>
presynth )
CHAZA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreConfigMaster/
2.0.101/rtl/vlog/core/coreconfigmaster.v => presynth )
CHAZA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreConfigP/4.0.100/rtl/
vlog/core/coreconfigp.v => presynth )
CHAZA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreResetP/5.0.103/rtl/
vlog/core/coresetp_pcie_hotreset.v => presynth )
CHAZA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreResetP/5.0.103/rtl/
vlog/core/coresetp.v => presynth )
CHAZA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB/FABOSC_0/SB_FABOSC_0_OSC.v =>
presynth )
CHAZA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB_HPMS/SB_HPMS.v => presynth )
CHAZA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB/SB.v => presynth )
CHAZA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB_top/SERDES_IF_0/
SB_top_SERDES_IF_0_SERDES_IF.v => presynth )
CHAZA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB_top/SB_top.v => presynth)
CHAZA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB_top/testbench.v => presynth)
CHAZA LIB_MAP ( $LIB_MAP, + => presynth )
Imiyalelo.csh
ncvlog +incdir+../../component/work/SB_top -cdslib ./cds.lib -hdlvar ./hdl.var -logfile
ncvlog.log -errormax 15 -uhlaziyo -linedebug
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite_addrdec.v
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/
coreahblite_defaultslavesm.v
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite_masterstagev
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite_slavearbiter.v
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite_slavestagev
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite_matrix2x16.v
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite.v
../../component/work/SB/CCC_0/SB_CCC_0_FCCC.v
../../component/Actel/DirectCore/CoreConfigMaster/2.0.101/rtl/vlog/core/coreconfigmaster.v
../../component/Actel/DirectCore/CoreConfigP/4.0.100/rtl/vlog/core/coreconfigp.v
../../component/Actel/DirectCore/CoreResetP/5.0.103/rtl/vlog/core/coreresetp_pcie_hotreset.v
../../component/Actel/DirectCore/CoreResetP/5.0.103/rtl/vlog/core/coreresetp.v
../../component/work/SB/FABOSC_0/SB_FABOSC_0_OSC.v ../../component/work/SB_HPMS/SB_HPMS.v
../../component/work/SB/SB.v ../../component/work/SB_top/SERDES_IF_0/
SB_top_SERDES_IF_0_SERDES_IF.v
../../component/work/SB_top/SB_top.v ../../component/work/SB_top/testbench.v
ncelab -Umyalezo -cdslib ./cds.lib -hdlvar ./hdl.var
-work presynth -logfile ncelab.log -errormax 15 -access +rwc -status presynth.testbench:modyuli
ncsim -Ibhetshi yomyalezo -cdslib ./cds.lib -hdlvar ./
hdl.var -logfile ncsim.log -errormax 15 -status presynth.testbench:modyuli
4.5 Ukuzenzela (Microchip Ngena)
Umbhalo olandelayo file iguqula iModelSim run.do files kuqwalaselo files efunekayo ukuqhuba ukulinganisa usebenzisa i-Xcelium.
Ushicilelo File Ukusetyenziswa
perl cadence_parser.pl presynth_run.do postsynth_run.do
postlayout_run.do Microsemi_Family
Indawo_ye-Cadence_Ilayibrari_eQinisekisiweyo
Cadence_parser.pl
#!/usr/bin/perl -w
##################################################### ############################################
###################
#Ukusetyenziswa: perl questa_parser.pl presynth_run.do postsynth_run.do postlayout_run.do
Microsemi_Family Precompiled_Libraries_location#
##################################################### ############################################
###################
sebenzisa iPOSIX;
sebenzisa ngqongqo;
yam ($ presynth, $ postsynth, $ postlayout, $ family, $ lib_location) = @ARGV;
&questa_parser($ presynth, $family, $lib_location);
&questa_parser($ postsynth, $family, $lib_location);
& questa_parser($ postlayout, $family, $lib_location);
i-questa_parser {
my $ModelSim_run_do = $_[0];
my $ actel_family = $_[1];
my $ lib_location = $_[2];
imeko yam ye-$;
ukuba (-e “$ModelSim_run_do” )
{
vula (INFILE,”$ModelSim_run_do”);
yam @ModelSim_run_do =FILE>;
umgca wam we-$;
ukuba ( $ModelSim_run_do =~ m/(presynth)/)
{
`mkdir QUESTA_PRESYNTH`;
vula (OUTFILE,”>QUESTA_PRESYNTH/presynth_questa.do”);
I-$ yelizwe = $ 1;
} elsif ( $ModelSim_run_do =~ m/(postsynth)/)
{
`mkdir QUESTA_POSTSYNTH`;
vula (OUTFILE,”>QUESTA_POSTSYNTH/postsynth_questa.do”);
I-$ yelizwe = $ 1;
} elsif ( $ModelSim_run_do =~ m/(uyilo lokuposa)/ )
{
`mkdir QUESTA_POSTLAYOUT`;
vula (OUTFILE,”>QUESTA_POSTLAYOUT/postlayout_questa.do”);
I-$ yelizwe = $ 1;
} Omnye
{
print “Iingeniso ezingalunganga ezinikwe kwi file\n";
shicilela “#Usetyenziso: perl questa_parser.pl presynth_run.do postsynth_run.do postlayout_run.do
\”Indawo_yethala leencwadi\”\n”;
}
i-foreach $line (@ModelSim_run_do)
{
#Imisebenzi gabalala
$line =~ s/..\/designer.*ukulinganisa\///g;
Umgca we-$ =~ s/$state/$state\_questa/g;
#Shicilela iphumeFILE “$line \n”;
ukuba ($line =~ m/vmap\s+.*($actel_family)/)
{
Shicilela iphumeFILE “vmap $actel_family \”$lib_location\”\n”;
} elsif (umgca we-$ =~ m/vmap\s+(.*._LIB)/)
{
$line =~ s/..\/component/..\/..\/component/g;
Shicilela iphumeFILE “$line \n”;
} i-elsif (umgca we-$ =~ m/vsim/)
{
$ umgca =~ s/vsim/vsim -novopt/g;
Shicilela iphumeFILE “$line \n”;
} Omnye
{
Shicilela iphumeFILE “$line \n”;
}
}
vala (INFILE);
ivalelwe ngaphandleFILE);
} enye {
printa “$ModelSim_run_do ayikho. Phinda wenze ukulinganisa kwakhona \n”;
}
}
ISiemens QuestaSim Setup/ModelSim Setup (Buza umbuzo)
I run.do files, eveliswa yi-Libero SoC yokulinganisa usebenzisa i-ModelSim Microsemi Editions, ingasetyenziselwa ukulinganisa usebenzisa i-QuestaSim / ModelSim SE / DE / PE kunye noshintsho olulodwa. KwiModelSim ME/ModelSim Pro ME run.do file, indawo yamathala eencwadi esele iqokelelwe ifuna ukulungiswa.
Kubalulekile:
Ngokungagqibekanga, isixhobo sokulinganisa ngaphandle kwe-ModelSim Pro ME senza ukulungiswa koyilo ngexesha lokulinganisa elinokuthi libe nefuthe lokubonakala kwizinto zokulinganisa ezifana nezinto zokuyila kunye ne-input stimulus.
Oku kudla ngokuba luncedo ekunciphiseni ukulinganisa ixesha lokusebenzisa ukulinganisa okuntsokothileyo, usebenzisa i-verbose, iibhentshi zokuzijonga. Nangona kunjalo, ulungiselelo olungagqibekanga lusenokungalungeli lonke ufaniso, ngakumbi kwiimeko apho ulindele ukujonga iziphumo zokulinganisa usebenzisa ifestile yamaza.
Ukujongana nemiba ebangelwa koku kulungiswa, kufuneka ungeze imiyalelo efanelekileyo kunye neengxabano ezinxulumeneyo ngexesha lokulinganisa ukubuyisela ukubonakala kuyilo. Ngemiyalelo ethe ngqo kwisixhobo, bona uxwebhu lwesifanisi esisetyenziswayo.
5.1 Izinto eziguquguqukayo zokusingqongileyo (Buza umbuzo)
Okulandelayo ziinguqu ezifunekayo zokusingqongileyo.
- LM_LICENSE_FILE: mayibandakanye indlela eya kwilayisenisi file.
- MODEL_TECH: kufuneka ichonge indlela eya kulawulo lwasekhaya lofakelo lwe QuestaSim.
- UMENDO: kufuneka yalathe kwindawo ephunyezwayo ekhonjwe yi-MODEL_TECH.
5.2 Ukuguqula i-run.do ye-Mentor QuestaSim (Buza umbuzo)
I run.do files eveliswe yi-Libero SoC yokulinganisa usebenzisa i-ModelSim Microsemi Editions ingasetyenziselwa ukulinganisa usebenzisa i-QuestaSim / ModelSim_SE kunye noshintsho olulodwa.
Kubalulekile: Konke Uyilo oluye lwenziwa kusetyenziswa i-QuestaSim kufuneka lubandakanye -novopt
ukhetho kunye nomyalelo we-vsim kwi-run.do script files.
5.3 Khuphela iThala leeNcwadi elihlanganisiweyo (Buza umbuzo)
Khuphela amathala eencwadi eMentor Graphics QuestaSim evela kwiMicrosemi's webindawo.
Umiselo lwe-Synopsy VCS (Buza umbuzo)
Ukuhamba okucetyisiweyo yi-Microsemi kuxhomekeke kwi-Elaborate and Compile flow kwi-VCS. Olu xwebhu lubandakanya iscript file esebenzisa i run.do script files eveliswe nguLibero SoC kwaye ivelisa ukuseta files ezifunekayo ukuze VCS ukulinganisa. Iskripthi file isebenzisa run.do file ukwenza oku kulandelayo.
- Yenza imaphu yethala leencwadi file, eyenziwa kusetyenziswa i synopsys_sim.setup file ibekwe kulawulo olufanayo apho ukulinganisa kweVCS kuqhuba.
- Yenza umbhalo weqokobhe file ukucacisa kunye nokuqokelela uyilo lwakho usebenzisa iVCS.
6.1 Izinto eziguquguqukayo zokusingqongileyo (Buza umbuzo)
Cwangcisa iinguqu ezifanelekileyo zemeko-bume yeVCS ngokusekelwe kucwangciso lwakho. Iinguqu zemo engqongileyo ezifunekayo ngokoxwebhu lweVCS zezi:
- LM_LICENSE_FILE: kufuneka ibandakanye isalathisi kumncedisi welayisensi.
- VCS_HOME: kufuneka yalathe kuvimba weefayili wasekhaya wofakelo lweVCS.
- UMENDO: mayibandakanye isalathisi kulawulo lomgqomo ongezantsi koluhlu lweVCS_HOME.
6.2 Khuphela Ithala Leencwadi Elihlanganisiweyo (Buza umbuzo)
Khuphela amathala eencwadi e-Synopsy VCS kwa-Microsemi's webindawo.
6.3 ISikripthi sokulinganisa seVCS File (Buza umbuzo)
Emva kokumisela i-VCS kunye nokuvelisa uyilo kunye ne-run.do eyahlukileyo files ukusuka kwiLibero SoC, kufuneka:
- Yenza imaphu yethala leencwadi file synopsys_sim.setup; oku file iqulethe izalathisi kwindawo yawo onke amathala eencwadi aza kusetyenziswa luyilo.
Kubalulekile: I file Igama akufuneki litshintshe kwaye kufuneka libekwe kulawulo olufanayo apho ukulinganisa kuqhuba. Nantsi i-example ngenxa enjalo file ukulinganisa i-presynthesis.
UMSEBENZI > UMSEBENZI
SmartFusion2 :
presynth : ./presynth
UMHLABA : ./work - Cacisa uyilo olwahlukileyo files, kuquka testbench, usebenzisa vlogan umyalelo kwiVCS. Le miyalelo inokuqukwa kwiskripthi seqokobhe file. Okulandelayo yi example yemiyalelo efunekayo ukucacisa uyilo oluchazwe kwi-rtl.v kunye nebhentshi yovavanyo echazwe kwi
testbench.v.
vlogan +v2k -sebenza presynth rtl.v
vlogan +v2k -work presynth testbench.v - Qokelela uyilo usebenzisa iVCS usebenzisa lo myalelo ulandelayo.
vcs –sim_res=1fs presynth.testbench
Qaphela: I Isisombululo sexesha sokulinganisa kufuneka simiselwe kwi-1fs yokulinganisa okuchanekileyo okusebenzayo. - Nje ukuba uyilo luqokelelwe, qalisa ukulinganisa usebenzisa lo myalelo ulandelayo.
./simv - Ukulinganisa i-back-annotated, umyalelo weVCS kufuneka ube njengoko kubonisiwe kwi-codeblock elandelayo.
vcs postlayout.testbench -sim_res=1fs -sdf max: .
igama>: file indlela> -gui -l postlayout.log
6.4 Imida/IziCawe (Buza umbuzo)
Okulandelayo yimida / ngaphandle kokusekwa kwe-Synopsys VCS.
- Ukulinganisa kweVCS kunokuqhutywa kuphela kwiiprojekthi zeVerilog zeLibero SoC. I-VCS simulator ineemfuno ezingqongqo zolwimi lweVHDL ezingahlangatyezwanga yiLibero SoC eyenziwe ngokuzenzekelayo yeVHDL. files.
- Kufuneka ube nengxelo yokugqiba i-$ kwi-testbench ye-Verilog ukumisa ukulinganisa nanini na xa ufuna.
Kubalulekile: Nini Ukulinganisa kuqhutywa kwimo ye-GUI, ixesha lokuqhuba lingachazwa kwi-GUI.
6.5Sample Tcl kunye neShell Script Files (Buza umbuzo)
Le ilandelayo iPerl yenza ngokuzenzekelayo ukuveliswa kwe synopsys_sim.setup file kunye nombhalo weqokobhe ohambelanayo files ezifunekayo ukucacisa, ukuqulunqa, kunye nokulinganisa uyilo.
Ukuba uyilo lusebenzisa i-MSS, khuphela uvavanyo.vec file ibekwe kwifolda yokulinganisa yeprojekthi yeLibero SoC kwifolda yokulinganisa yeVCS. La macandelo alandelayo aqulathe sample run.do files eveliswe nguLibero SoC, kubandakanywa imephu yelayibrari ehambelanayo kunye neskripthi seqokobhe files ezifunekayo ukuze VCS ukulinganisa.
6.5.1 Ukuhlanganiswa kwangaphambili (Buza umbuzo)
Presynth_run.do
cwaka usete ACTELLIBNAME SmartFusion2
Cwaka ukusetha i-PROJECT_DIR "/sqa/users/me/VCS_Tests/Test_DFF"
ukuba {[file ikhona presynth/_info]} {
echo "INFO: Ukulinganisa ilayibrari presynth sele ikhona"
} enye {
vlib presynth
}
vmap presynth presynth
vmap SmartFusion2 “/captures/lin/11_0_0_23_11prod/lib/ModelSim/precompiled/vlog/smartfusion2”
vlog -work presynth "${PROJECT_DIR}/component/work/SD1/SD1.v"
vlog "+ incdir+${PROJECT_DIR}/uvuselelo" -presynth "${PROJECT_DIR}/stimulus/SD1_TB1.v"
vsim -L SmartFusion2 -L presynth -t 1fs presynth.SD1_TB1
yongeza amaza /SD1_TB1/*
yongeza ilog -r /*
baleka i-1000ns
presynth_main.csh
#!/umgqomo/csh -f
seta iPROJECT_DIR = "/sqa/users/Me/VCS_Tests/Test_DFF"
/cad_design/tools/vcs.dir/E-2011.03/bin/vlogan +v2k -work presynth “${PROJECT_DIR}/component/
umsebenzi/SD1/SD1.v”
/cad_design/tools/vcs.dir/E-2011.03/bin/vlogan +v2k “+incdir+${PROJECT_DIR}/stimulus” -sebenza
presynth “${PROJECT_DIR}/sivuseleli/SD1_TB1.v”
/cad_design/tools/vcs.dir/E-2011.03/bin/vcs -sim_res=1fs presynth.SD1_TB1 -l compile.log
./simv -l run.log
Synopsys_sim.setup
SEBENZA > UMHLAWULO
SmartFusion2 : /VCS/SmartFusion2
presynth : ./presynth
UMHLABA : ./work
6.5.2 Emva kokudibanisa (Buza umbuzo)
postsynth_run.do
cwaka usete ACTELLIBNAME SmartFusion2
Cwangcisa cwangcisa iPROJECT_DIR "/sqa/users/Me/VCS_Tests/Test_DFF"
ukuba {[file ikhona postsynth/_info]} {
echo "INFO: Ukulinganisa ilayibrari postsynth sele ikhona"
} enye {
vlib postsynth
}
vmap postsynth postsynth
vmap SmartFusion2 “//idm/captures/pc/11_0_1_12_g4x/Designer/lib/ModelSim/precompiled/vlog/
SmartFusion2”
vlog -work postsynth "${PROJECT_DIR}/synthesis/SD1.v"
vlog "+ incdir+${PROJECT_DIR}/isivuseleli" -sebenza postsynth "${PROJECT_DIR}/stimulus/SD1_TB1.v"
vsim -L SmartFusion2 -L postsynth -t 1fs postsynth.SD1_TB1
yongeza amaza /SD1_TB1/*
yongeza ilog -r /*
baleka i-1000ns
log SD1_TB1/*
Phuma
Postsynth_main.csh
#!/umgqomo/csh -f
seta iPROJECT_DIR = "/sqa/users/Me/VCS_Tests/Test_DFF"
/cad_design/tools/vcs.dir/E-2011.03/bin/vlogan +v2k -work postsynth “${PROJECT_DIR}/synthesis/
SD1.v”
/cad_design/tools/vcs.dir/E-2011.03/bin/vlogan +v2k “+incdir+${PROJECT_DIR}/stimulus” -sebenza
postsynth “${PROJECT_DIR}/isivuseleli/SD1_TB1.v”
/cad_design/tools/vcs.dir/E-2011.03/bin/vcs -sim_res=1fs postsynth.SD1_TB1 -l compile.log
./simv -l run.log
Synopsys_sim.setup
SEBENZA > UMHLAWULO
SmartFusion2 : /VCS/SmartFusion2
postsynth : ./postsynth
UMHLABA : ./work
6.5.3 Uyilo lwasemva (Buza umbuzo)
postlayout_run.do
cwaka usete ACTELLIBNAME SmartFusion2
ngokuzolileyo seta i-PROJECT_DIR “E:/ModelSim_Work/Test_DFF”
ukuba {[file ikhona ../designer/SD1/simulation/postlayout/_info]} {
echo "INFO: Ithala leencwadi lokulinganisa ../designer/SD1/simulation/postlayout sele ikhona"
} enye {
vlib ../designer/SD1/simulation/postlayout
}
vmap postlayout ../designer/SD1/simulation/postlayout
vmap SmartFusion2 “//idm/captures/pc/11_0_1_12_g4x/Designer/lib/ModelSim/precompiled/vlog/
SmartFusion2”
vlog -umsebenzi wokumiselwa kweposi "${PROJECT_DIR}/designer/SD1/SD1_ba.v"
vlog "+ incdir+${PROJECT_DIR}/isivuseleli" -ulungiselelo lokuposa lomsebenzi "${PROJECT_DIR}/stimulus/SD1_TB1.v"
vsim -L SmartFusion2 -L postlayout -t 1fs -sdfmax /SD1_0=${PROJECT_DIR}/designer/SD1/
SD1_ba.sdf postlayout.SD1_TB1
yongeza amaza /SD1_TB1/*
yongeza ilog -r /*
baleka i-1000ns
I-Postlayout_main.csh
#!/umgqomo/csh -f
seta PROJECT_DIR = "/VCS_Test/Test_DFF"
/cad_design/tools/vcs.dir/E-2011.03/bin/vlogan +v2k -umsebenzi wokumiselwa kwesithuba “${PROJECT_DIR}/
umyili/SD1/SD1_ba.v”
/cad_design/tools/vcs.dir/E-2011.03/bin/vlogan +v2k “+incdir+${PROJECT_DIR}/stimulus” -sebenza
Uyilo lwesithuba “${PROJECT_DIR}/isivuseleli/SD1_TB1.v”
/cad_design/tools/vcs.dir/E-2011.03/bin/vcs -sim_res=1fs postlayout.SD1_TB1 -sdf
max:SD1_TB1.SD1_0:${PROJECT_DIR}/designer/SD1/SD1_ba.sdf -l compile.log
./simv -l run.log
Synopsys_sim.setup
SEBENZA > UMHLAWULO
SmartFusion2 : /VCS/SmartFusion2
uyilo lwasemva : ./postlayout
OKWENZEKAYO : ./workVCS
6.6 Ukuzenzela (Buza umbuzo)
Ukuhamba kungenziwa ngokuzenzekelayo usebenzisa i-Perl script elandelayo file ukuguqula iModelSim run.do files kwi-VCS ehambelana neskripthi seqokobhe files, yenza abalawuli abafanelekileyo ngaphakathi kweLibero SoC yokulinganisa ulawulo, kwaye emva koko uqhube ukulinganisa.
Qhuba isikripthi file usebenzisa le syntax ilandelayo.
perl vcs_parse.pl presynth_run.do postynth_run.do postlayout_run.do
Vcs_parse_pl
#!/usr/bin/perl -w
##################################################### #############################
#
#Ukusetyenziswa: perl vcs_parse.pl presynth_run.do postsynth_run.do postlayout_run.do
#
##################################################### ##############################
yam ($ presynth, $ postsynth, $ postlayout) = @ARGV;
ukuba(inkqubo(“mkdir VCS_Presynth”)) {print “mkdir ayiphumelelanga:\n”;}
ukuba(inkqubo(“mkdir VCS_Postsynth”)) {print “mkdir ayiphumelelanga:\n”;}
ukuba(inkqubo(“mkdir VCS_Postlayout”)) {print “mkdir ayiphumelelanga:\n”;}
chdir(VCS_Presynth);
`cp ../$ARGV[0] .` ;
&parse_do($presynth,"presynth");
chdir (“../”);
chdir(VCS_Postsynth);
`cp ../$ARGV[1] .` ;
&parse_do($postsynth,"postsynth");
chdir (“../”);
chdir(VCS_Postlayout);
`cp ../$ARGV[2] .` ;
&parse_do($postlayout,"uyilo lwasemva");
chdir (“../”);
cahlula_yenza {
my $ vlog = "/cad_design/tools/vcs.dir/E-2011.03/bin/vlogan +v2k" ;
eyam i-%LIB = ();
yam $file = $_[0] ;
my $state = $_[1];
vula(INFILE,”$file”) || fa “Ayinakuvuleka File Isizathu sisenokuba:$!”;
ukuba ( $state eq “presynth” )
{
open(OUT1,”>presynth_main.csh”) || fa “Awukwazi ukwenza uMyalelo File Isizathu sisenokuba:$!”;
}
elsif ( $state eq “postsynth” )
{
vula(OUT1,”>postsynth_main.csh”) || fa “Awukwazi ukwenza uMyalelo File Isizathu sisenokuba:$!”;
}
elsif ( $state eq “postlayout” )
{
vula(OUT1,”>postlayout_main.csh”) || fa “Awukwazi ukwenza uMyalelo File Isizathu sisenokuba:$!”;
}
enye into
{
shicilela “Imeko yokulinganisa ayikho \n” ;
}
open(OUT2,”>synopsys_sim.setup”) || fa “Awukwazi ukwenza uMyalelo File Isizathu sisenokuba:$!”;
# .csh file
printa OUT1 “#!/bin/csh -f\n\n\n” ;
#MISELA FILE
printa OUT2 “UMSEBENZI > OKWENZEKAYO\n” ;
printa OUT2 “SmartFusion2 : /sqa/users/Aditya/VCS/SmartFusion2\n” ;
ngelixa (umgca we-$ =FILE>)
{
Ukusekwa kwe-Synopsy VCS
ukuba (umgca we-$ =~ m/uthe cwaka cwangcisa PROJECT_DIR\s+\”(.*?)\”/)
{
print OUT1 “seta PROJECT_DIR = \”$1\”\n\n\n” ;
}
elsif ( $line =~ m/vlog.*\.v\”/ )
{
ukuba ($line =~ m/\s+(\w*?)\_LIB/)
{
#print “\$1 =$1 \n” ;
i-$ Temp = “$1″.”_LIB”;
#print "Temp = $ temp \n" ;
$LIB{$temp}++;
}
chomp (umgca we-$);
Umgca we-$ =~ s/^vlog/$vlog/ ;
$umgca =~ s/ //g;
printa OUT1 “$line\n”;
}
elsif ( ($line =~ m/vsim.*presynth\.(.*)/) || ($line =~ m/vsim.*postsynth\.(.*)/) || ($line
=~ m/vsim.*uyilo lwasemva\.(.*)/) )
{
$tb = $1 ;
$tb =~ s/ //g;
chomp($tb);
#print “TB Name : $tb \n”;
ukuba ( $line =~ m/sdf(.*)\.sdf/)
{
chomp (umgca we-$);
Umgca we-$ = $ 1;
#print "UMLINE : $line \n" ;
ukuba ($line =~ m/max/)
{
Umgca we-$ =~ s/max \/// ;
$umgca =~ s/=/:/;
print OUT1 “\n\n/cad_design/tools/vcs.dir/E-2011.03/bin/vcs -sim_res=1fs postlayout.$tb -sdf
max:$tb.$line.sdf -l compile.log\n” ;
}
elsif (umgca we-$ =~ m/min/)
{
$ umgca =~ s/min \/// ;
$umgca =~ s/=/:/;
print OUT1 “\n\n/cad_design/tools/vcs.dir/E-2011.03/bin/vcs -sim_res=1fs postlayout.$tb -sdf
umz:$tb.$line.sdf -l compile.log\n” ;
}
elsif ($line =~ m/typ/)
{
$ umgca =~ s/typ \/// ;
$umgca =~ s/=/:/;
print OUT1 “\n\n/cad_design/tools/vcs.dir/E-2011.03/bin/vcs -sim_res=1fs postlayout.$tb -sdf
chwetheza:$tb.$line.sdf -l compile.log\n” ;
}
#-sdfmax /M3_FIC32_0=${PROJECT_DIR}/designer/M3_FIC32/M3_FIC32_ba.sdf — iModelSim SDF ifomathi
#$sdf = “-sdf max:testbench.M3_FIC32_0:${PROJECT_DIR}/designer/M3_FIC32/M3_FIC32_ba.sdf”; -VCS
ifomathi yeSDF
}
}
}
shicilela
OUT1 “\n\n”
;
if
($state eq “presynth”
)
{
shicilela
OUT2 “presynth
: ./presynth\n”
;
shicilela
OUT1 “/cad_design/tools/vcs.dir/E-2011.03/bin/vcs
-sim_res=1fs presynth.$tb -l
compile.log\n”
;
}
elsif
($state eq “postsynth”
)
{
shicilela
OUT2 “postsynth
: ./postsynth\n”
;
shicilela
OUT1 “/cad_design/tools/vcs.dir/E-2011.03/bin/vcs
-sim_res=1fs postsynth.$tb -l
compile.log\n”
;
}
elsif
($state eq "postlayout"
)
{
print OUT2 “uyilo lwasemva : ./postlayout\n” ;
}
enye into
{
shicilela “Imeko yokulinganisa ayikho \n” ;
}
icala $i (izitshixo %LIB)
{
#print "Isitshixo : $i Ixabiso : $LIB{$i} \n" ;
printa OUT2 “$i : ./$i\n” ;
}
printa OUT1 “\n\n” ;
printa OUT1 “./simv -l run.log\n” ;
printa OUT2 “DEFAULT : ./work\n” ;
vala INFILE;
vala i-OUT1;
vala i-OUT2;
}
Imbali yohlaziyo (Microchip Ngena
Imbali yohlaziyo ichaza utshintsho oluthe lwaphunyezwa kuxwebhu. Iinguqu
zidweliswe ngohlaziyo, kuqalwa ngeyona mpapasho yakutshanje.
| Uhlaziyo | Umhla | Inkcazo |
| A | 12/2023 | Olu tshintsho lulandelayo lwenziwa kolu hlaziyo: • Uxwebhu luguqulelwe kwitemplate yeMicrochip. Uhlaziyo lokuqala. • Icandelo elihlaziyiweyo 5. I-Siemens QuestaSim Setup/ModelSim Setup ukubandakanya inqaku elitsha elichaza impembelelo yokubonakala ngexesha lokulinganisa kunye nokuphucula. |
Microchip FPGA Inkxaso
Iqela leemveliso zeMicrochip FPGA libuyisela iimveliso zalo ngeenkonzo ezahlukeneyo zenkxaso, kubandakanya iNkonzo yabaThengi, iZiko leNkxaso yobuGcisa yabaThengi, a webindawo, kunye neeofisi zokuthengisa zehlabathi.
Abathengi bayacetyiswa ukuba bandwendwele iMicrochip imithombo ye-intanethi phambi kokuqhagamshelana nenkxaso njengoko kunokwenzeka ukuba imibuzo yabo sele iphendulwe.
Qhagamshelana neZiko leNkxaso yobuGcisa nge webindawo kwi www.microchip.com/support. Khankanya inombolo yeCandelo leSixhobo seFPGA, khetha udidi lwetyala elifanelekileyo, kwaye uyilo lokulayisha files ngelixa usenza imeko yenkxaso yobugcisa.
Qhagamshelana neNkonzo yabaThengi ngenkxaso yemveliso engeyiyo eyobugcisa, njengamaxabiso emveliso, ukuphuculwa kwemveliso, ulwazi lokuhlaziya, isimo somyalelo kunye nokugunyaziswa.
- Ukusuka eMntla Melika, fowunela 800.262.1060
- Ukusuka kwihlabathi liphela, fowunela 650.318.4460
- Ifeksi, naphi na ehlabathini, 650.318.8044
Ulwazi lweMicrochip
I Microchip Webindawo
I-Microchip ibonelela ngenkxaso ye-intanethi ngokusebenzisa yethu webindawo kwi www.microchip.com/. Oku webindawo isetyenziselwa ukwenza files kunye nolwazi olufumaneka lula kubathengi. Eminye imixholo ekhoyo iquka:
- Inkxaso yeMveliso - Amaxwebhu eDatha kunye neerrata, amanqaku esicelo kunye ne-sampiinkqubo, izixhobo zoyilo, izikhokelo zabasebenzisi kunye namaxwebhu enkxaso yehardware, ukukhutshwa kwesoftware yamva nje kunye nesoftware egciniweyo
- Inkxaso yezobuGcisa ngokuBanzi-Imibuzo eQhwayo (FAQs), izicelo zenkxaso yobugcisa, amaqela eengxoxo kwi-intanethi, uluhlu lwamalungu enkqubo yoyilo lweMicrochip
- Ishishini leMicrochip - Umkhethi weMveliso kunye nezikhokelo zokuodola, ushicilelo lwamva nje lweMicrochip, uluhlu lweesemina kunye nemisitho, uluhlu lweeofisi zentengiso yeMicrochip, abasasazi kunye nabameli befektri.
Inkonzo yesaziso soTshintsho kwimveliso
Inkonzo yesaziso yokutshintsha imveliso yeMicrochip inceda ukugcina abathengi bangoku kwiimveliso zeMicrochip. Ababhalisi baya kufumana isaziso se-imeyile nanini na kukho utshintsho, uhlaziyo, uhlaziyo okanye iimpazamo ezinxulumene nosapho lwemveliso ethile okanye isixhobo sophuhliso esinomdla.
Ukubhalisa, yiya ku www.microchip.com/pcn kwaye ulandele imiyalelo yobhaliso.
Uxhaso lwabathengi
Abasebenzisi beemveliso zeMicrochip banokufumana uncedo ngeendlela ezininzi:
- Umsasazi okanye uMmeli
- I-Ofisi yoThengiso yasekuhlaleni
- Embedded Solutions Engineer (ESE)
- Uxhaso lobuchwepheshe
Abathengi kufuneka baqhagamshelane nomthengisi wabo, ummeli okanye i-ESE ngenkxaso. Iiofisi zeentengiso zasekuhlaleni zikwafumaneka ukunceda abathengi. Uluhlu lweeofisi zokuthengisa kunye neendawo zibandakanyiwe kolu xwebhu.
Inkxaso yobugcisa ifumaneka nge webindawo e: www.microchip.com/support
Microchip Devices Code Protection Feature
Qaphela ezi nkcukacha zilandelayo zenqaku lokhuseleko lwekhowudi kwiimveliso zeMicrochip:
- Iimveliso zeMicrochip ziyahlangabezana nemigaqo equlethwe kwiMicrochip Data Sheet yazo.
- IMicrochip ikholelwa ukuba usapho lwayo lweemveliso lukhuselekile xa lusetyenziswa ngendlela ecetywayo, ngokwemigaqo yokusebenza, naphantsi kweemeko eziqhelekileyo.
- Ixabiso leMicrochip kwaye likhusela ngokungqongqo amalungelo epropathi enomgangatho ophezulu wokuqonda. Iinzame zokwaphula ikhowudi yokukhusela iimpawu zeMicrochip zithintelwe ngokungqongqo kwaye zinokwaphula umthetho weDigital Millennium Copyright Act.
- Ayikho i-Microchip okanye nawuphi na umenzi we-semiconductor onokuqinisekisa ukhuseleko lwekhowudi yayo. Ukukhuselwa kwekhowudi akuthethi ukuba siqinisekisa ukuba imveliso "ayinakwaphulwa".
Ukhuseleko lwekhowudi luhlala luvela. I-Microchip izinikele ekuphuculeni ngokuqhubekayo iimpawu zokukhusela ikhowudi kwiimveliso zethu.
Isaziso soMthetho
Olu papasho kunye nolwazi olulapha lunokusetyenziswa kuphela ngeemveliso zeMicrochip, kubandakanywa ukuyila, ukuvavanya, kunye nokudibanisa iimveliso zeMicrochip kunye nesicelo sakho. Ukusetyenziswa kolu lwazi ngayo nayiphi na enye indlela kwaphula le migaqo. Ulwazi malunga nosetyenziso lwesixhobo lunikezelwa kuphela ukulungiselela wena kwaye lunokuthi luthathelwe indawo luhlaziyo. Luxanduva lwakho ukuqinisekisa ukuba isicelo sakho siyadibana neenkcukacha zakho. Qhagamshelana neofisi yakho yentengiso yeMicrochip yengingqi ngenkxaso eyongezelelweyo okanye, ufumane inkxaso eyongezelelweyo kwi www.microchip.com/en-us/support/design-help/client-support-services.
OLU LWAZI LUBONWA NGE-MICROCHIP “NJENGOKO ZINJALO”. I-MICROCHIP AYENZA Mmeli OKANYE IZIQINISEKISO ZALO NALUPHI UHLOBO, OKANYE INGCACILEYO OKANYE IYATHENWA, IYABHALWA OKANYE NGOMLOMO, NGOMTHETHO OKANYE NGOLUNYE, ENXULUMENE NOLWAZI KUBANDAKANYA KODWA AYIMDALWA KUSO NAsiphi na ISIQINISEKISO SOKUBANISWA, UKUFANELEKILEYO NGENJONGO ETHILE, OKANYE IZIQINISEKISO EZINXULUMENE NEMEKO, UMGANGATHO, OKANYE UKUSEBENZA KWAYO.
AKUKHO SIGANEKO IYA KUTHWATHWA NALUPHI NA I-MICROCHIP ESIYA KUTHWALA NGALO NALUPHI NA ULWAZI, OLUKHETHEKILEYO, LWESOHLWAYO, NGESIGANEKO, OKANYE OKUPHUMELELE Ilahleko, UMONAKALO, IINDLEKO, OKANYE INKCITHO YALO NOLUPHI NA UHLOBO ELUYANXULUMENE NOLWAZI OKANYE UKUSETYENZISWA KWALO, NANGONA INGCACISO, NANGENZWENI. OKUSEKO OKANYE UMONAKALO UYABONAKALA. NGOKUPHELELEYO UXANDUVA LUVUMELEKILEYO NGOMTHETHO, UXANDUVA LWONKE LE-MICROCHIP KULONKE AMABANGO NGAYO NAYIPHI NA IINDLELA EZINXULUMENE NOLWAZI OKANYE UKUSETYENZISWA KWALO AKUYI KUGQIBELA ISIXA SOMRHUMO, UKUBA NAKHO, OWUHLAWULE NGQO UKUBA ULWAZI LWAZI.
Ukusetyenziswa kwezixhobo zeMicrochip kwinkxaso yobomi kunye / okanye izicelo zokhuseleko ngokupheleleyo kumngcipheko womthengi, kwaye umthengi uyavuma ukukhusela, ukuhlawulela kwaye ubambe iMicrochip engenabungozi kuyo nayiphi na kunye nawo wonke umonakalo, amabango, iisuti, okanye iindleko ezibangelwa kukusetyenziswa okunjalo. Akukho zilayisenisi zigqithiswayo, ngokungafihlisiyo okanye ngenye indlela, phantsi kwawo nawaphi na amalungelo epropathi yemveliso yeMicrochip ngaphandle kokuba kuchazwe ngenye indlela.
Iimpawu zokuthengisa
Igama leMicrochip kunye nelogo, ilogo yeMicrochip, iAdaptec, iAVR, ilogo yeAVR, iAVR Freaks, iBesTime, iBitCloud, iCryptoMemory, iCryptoRF, dsPIC, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXStylus MediaLB, megaAVR, Microsemi, Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, PolarFire, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetri , SyncServer, Tachyon, TimeSource, tinyAVR, UNI/O, Vectron, kunye neXMEGA ziimpawu zorhwebo ezibhalisiweyo zeMicrochip Technology Incorporated e-USA nakwamanye amazwe.
I-AgileSwitch, i-APT, i-ClockWorks, i-Embedded Control Solutions Company, i-EtherSynch, i-Flashtec, i-Speed Speed Control, i-HyperLight Load, i-Libero, i-motorBench, i-mTouch, i-Powermite 3, i-Precision Edge, i-ProASIC, i-ProASIC Plus, i-logo ye-ProASIC Plus, i-Quiet-Wire, i-SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub, TimePictra, TimeProvider, TrueTime, kunye neZL ziimpawu zorhwebo ezibhalisiweyo zeMicrochip Technology Incorporated e-USA.
Uxinzelelo oluphambili olusondeleyo, i-AKS, i-Analog-for-the-Digital Age, nayiphi na i-Capacitor, i-AnyIn, i-AnyOut, i-Augmented Switching, i-BlueSky, i-BodyCom, i-Clockstudio, i-CodeGuard, i-CryptoAuthentication, i-CryptoAutomotive, i-CryptoCompanion, i-CryptoController, i-dsPICDEM, i-dsPICDEMEverage, i-DSPICDEMverage. , DAM, ECAN, Espresso T1S, EtherGREEN, GridTime, IdealBridge, In-Circuit Serial Programming, ICSP, INICnet, Intelligent Paralleling, IntelliMOS, Inter-Chip Connectivity, JitterBlocker, Knob-on-Display, KoD, maxCrypto, maxView, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net,
PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, RTAX, RTG4, SAMICE, Serial Quad I/O, simpleMAP, SimpliPHY, SmartBuffer, SmartHLS, SMART-IS, storClad, SQI, SuperSwitcher,
SuperSwitcher II, Switchtec, SynchroPHY, Unyamezelo lulonke, ixesha elithenjiweyo, TSHARC, USBCheck, VariSense, VectorBlox, VeriPHY, ViewSpan, WiperLock, XpressConnect, kunye ne ZENA ziimpawu zorhwebo zeMicrochip Technology Incorporated
e-USA nakwamanye amazwe.
I-SQTP luphawu lwenkonzo ye-Microchip Technology Incorporated e-USA
Ilogo ye-Adaptec, Frequency on Demand, Silicon Storage Technology, kunye ne Symmcom ziimpawu zorhwebo ezibhalisiweyo ze Microchip Technology Inc. kwamanye amazwe.
I-GestIC luphawu lwentengiso olubhalisiweyo lwe-Microchip Technology Germany II GmbH & Co. KG, i-subsidiary ye-Microchip Technology Inc., kwamanye amazwe.
Zonke ezinye iimpawu zorhwebo ezikhankanywe apha ziyipropathi yeenkampani zabo.
© 2023, Microchip Technology Incorporated kunye nenkxaso yayo. Onke Amalungelo Agciniwe.
ISBN: 978-1-6683-3694-6
Inkqubo yoLawulo loMgangatho
Ngolwazi malunga neMicrochip's Quality Management Systems, nceda undwendwele www.microchip.com/quality.
| AMAMERIKA | I-ASIA/PACIFIC | I-ASIA/PACIFIC | I-YUROYA |
| IOfisi yoShishino 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Umnxeba: 480-792-7200 Ifeksi: 480-792-7277 Uxhaso lobuchwepheshe: www.microchip.com/support Web Idilesi: www.microchip.com eAtlanta Duluth, GA Umnxeba: 678-957-9614 Ifeksi: 678-957-1455 Austin, TX Umnxeba: 512-257-3370 eBoston Westborough, MA Umnxeba: 774-760-0087 Ifeksi: 774-760-0088 eChicago Itasca, IL Umnxeba: 630-285-0071 Ifeksi: 630-285-0075 eDallas Ukudibanisa, TX Umnxeba: 972-818-7423 Ifeksi: 972-818-2924 eDetroit Novi, MI Umnxeba: 248-848-4000 eHouston, TX Umnxeba: 281-894-5983 Indianapolis Noblesville, IN Umnxeba: 317-773-8323 Ifeksi: 317-773-5453 Umnxeba: 317-536-2380 Ilos angeles UMthunywa Viejo, CA Umnxeba: 949-462-9523 Ifeksi: 949-462-9608 Umnxeba: 951-273-7800 Raleigh, NC Umnxeba: 919-844-7510 ENew York, NY Umnxeba: 631-435-6000 San Jose, CA Umnxeba: 408-735-9110 Umnxeba: 408-436-4270 Canada - Toronto Umnxeba: 905-695-1980 Ifeksi: 905-695-2078 |
EOstreliya - eSydney Umnxeba: 61-2-9868-6733 China-Beijing Umnxeba: 86-10-8569-7000 China-Chengdu Umnxeba: 86-28-8665-5511 China - Chongqing Umnxeba: 86-23-8980-9588 China-Dongguan Umnxeba: 86-769-8702-9880 China - Guangzhou Umnxeba: 86-20-8755-8029 China-Hangzhou Umnxeba: 86-571-8792-8115 China-Hong Kong SAR Umnxeba: 852-2943-5100 China-Nanjing Umnxeba: 86-25-8473-2460 China - Qingdao Umnxeba: 86-532-8502-7355 China - Shanghai Umnxeba: 86-21-3326-8000 China – Shenyang Umnxeba: 86-24-2334-2829 China-Shenzhen Umnxeba: 86-755-8864-2200 China - Suzhou Umnxeba: 86-186-6233-1526 China - Wuhan Umnxeba: 86-27-5980-5300 China - Xian Umnxeba: 86-29-8833-7252 China - Xiamen Umnxeba: 86-592-2388138 China - Zhuhai Umnxeba: 86-756-3210040 |
EIndiya-Bangalore Umnxeba: 91-80-3090-4444 EIndiya-eNew Delhi Umnxeba: 91-11-4160-8631 Indiya-IPune Umnxeba: 91-20-4121-0141 Japan - Osaka Umnxeba: 81-6-6152-7160 EJapan - eTokyo Umnxeba: 81-3-6880-3770 Korea - Daegu Umnxeba: 82-53-744-4301 Korea - Seoul Umnxeba: 82-2-554-7200 IMalaysia-Kuala Lumpur Umnxeba: 60-3-7651-7906 EMalaysia - ePenang Umnxeba: 60-4-227-8870 IiPhilippines - eManila Umnxeba: 63-2-634-9065 Singapho Umnxeba: 65-6334-8870 ITaiwan-Hsin Chu Umnxeba: 886-3-577-8366 ITaiwan-Kaohsiung Umnxeba: 886-7-213-7830 ITaiwan-iTaipei Umnxeba: 886-2-2508-8600 EThailand - eBangkok Umnxeba: 66-2-694-1351 IVietnam - iHo Chi Minh Umnxeba: 84-28-5448-2100 |
EOstriya-Wels Umnxeba: 43-7242-2244-39 Ifeksi: 43-7242-2244-393 EDenmark - eCopenhagen Umnxeba: 45-4485-5910 Ifeksi: 45-4485-2829 EFinland - Espoo Umnxeba: 358-9-4520-820 EFransi - eParis Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 EJamani - Ukutya Umnxeba: 49-8931-9700 EJamani-Haan Umnxeba: 49-2129-3766400 EJamani - Heilbronn Umnxeba: 49-7131-72400 EJamani-Karlsruhe Umnxeba: 49-721-625370 EJamani-Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 EJamani - iRosenheim Umnxeba: 49-8031-354-560 USirayeli - Ra'anana Umnxeba: 972-9-744-7705 EItali - eMilan Umnxeba: 39-0331-742611 Ifeksi: 39-0331-466781 EItali - ePadova Umnxeba: 39-049-7625286 ENetherlands – Drunen Umnxeba: 31-416-690399 Ifeksi: 31-416-690340 INorway - iTrondheim Umnxeba: 47-72884388 Poland - Warsaw Umnxeba: 48-22-3325737 I-Romania-Bucharest Tel: 40-21-407-87-50 Spain -Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 eSweden-Gothenberg Tel: 46-31-704-60-40 eSweden-Stockholm Umnxeba: 46-8-5090-4654 E-UK-Wokingham Umnxeba: 44-118-921-5800 Ifeksi: 44-118-921-5820 |
© 2023 iMicrochip Technology Inc. kunye nenkxaso-mali yayo
DS50003627A-
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MICROCHIP Libero SoC Ukulinganisa iSoftware yeThala leeNcwadi [pdf] Isikhokelo somsebenzisi I-DS50003627A, iSoftware yeThala lokulinganisa iLibero SoC, iSoftware yeThala lokulinganisa iSoC, iSoftware yeThala lokulinganisa, iSoftware yeThala leeNcwadi, iSoftware |
