Libero SoC Simulation
Malangizo Okhazikitsa Laibulale
Mawu Oyamba
Cholinga cha chikalatachi ndikulongosola njira yokhazikitsira malo oyerekeza pogwiritsa ntchito pulojekiti ya Libero SoC monga chothandizira. Zolemba izi zimagwirizana ndi malaibulale omwe adasanjidwa kale omwe amaperekedwa kuti agwiritsidwe ntchito ndi Libero SoC v11.9 komanso kutulutsa kwatsopano kwa mapulogalamu. Ma library omwe aperekedwa amapangidwa ku Verilog. Ogwiritsa ntchito VHDL amafunikira chilolezo chololeza kuyerekezera kosakanikirana.
Ma library ofananira omwe adapangidwa ali ndi zida zotsatirazi:
- Aldec Active-HDL
- Aldec Riviera-PRO
- Cadence Incisive Enterprise ndi Xcelium
- Siemens QuestaSim
- Zithunzi za VCS
Kuti mupemphe laibulale yopangira makina ena oyeserera, funsani Microchip Technical Support.
Libero SoC Integration
Libero SoC imathandizira kuyerekezera pogwiritsa ntchito ModelSim ME popanga run.do file. Izi file imagwiritsidwa ntchito ndi ModelSim ME/ModelSim Pro ME kukhazikitsa ndi kuyendetsa kayeseleledwe. Kuti mugwiritse ntchito zida zina zofananira, mutha kupanga ModelSim ME/ModelSim Pro ME run.do ndikusintha zolemba za Tcl. file kugwiritsa ntchito malamulo omwe amagwirizana ndi simulator yanu.
1.1 Libero SoC Tcl File M'badwo (Funsani Funso)
Pambuyo popanga ndi kupanga mapangidwe mu Libero SoC, yambani kuyerekezera kwa ModelSim ME/ModelSim Pro ME pansi pa magawo onse apangidwe (presynth, postsynth, ndi post-layout). Gawo ili limapanga run.do file kwa ModelSim ME/ModelSim Pro ME pagawo lililonse la mapangidwe.
Zofunika: Mukayamba kuthamanga kulikonse, sinthani dzina lopangidwa ndi auto-generated run.do file pansi pa chikwatu choyerekeza kuti muteteze Libero SoC kuti isalembenso file. Za example, ndi files ikhoza kusinthidwa kukhala presynth_run.do, postsynth_run.do ndi postlayout_run.do.
Kukhazikitsa kwa Aldec kwa Active-HDL ndi Riviera-Pro (Funsani Funso)
The run.do file zogwiritsidwa ntchito ndi ModelSim ME/ModelSim Pro ME zitha kusinthidwa ndi kugwiritsidwa ntchito kuyerekezera pogwiritsa ntchito zoyeserera za Aldec.
2.1 Kusintha kwa chilengedwe (Funsani Funso)
Khazikitsani kusintha kwa chilengedwe ku chiphaso chanu file malo:
LM_LICENSE_FILE: iyenera kuphatikiza cholozera ku seva yalayisensi.
2.2 Tsitsani Library Yophatikizidwa (Funsani Funso)
Tsitsani malaibulale a Aldec Active-HDL ndi Aldec Riviera-PRO kuchokera ku Microchip. webmalo.
2.3 Kutembenuza run.do kwa Aldec simulation (Funsani Funso)
The run.do files yopangidwa ndi Libero SoC yofananira pogwiritsa ntchito chida cha Active-HDL ndi Riviera-Pro chingagwiritsidwe ntchito poyerekezera pogwiritsa ntchito Active-HDL ndi Riviera-Pro ndi kusintha kumodzi. Gome lotsatirali likulemba malamulo ofanana ndi Aldec kuti asinthe mu ModelSim run.do file.
Gulu 2-1. Aldec Equivalent Commands
| ModelSim | Active-HDL |
| vlog | alogi |
| vcom | acom |
| vlib | alib |
| vsim | asim |
| vmap | amap |
Zotsatirazi ndi mongaample run.do yokhudzana ndi ma simulators a Aldec.
- Khazikitsani malo a chikwatu chomwe chikugwira ntchito pano.
set dsn - Khazikitsani dzina laibulale yomwe ikugwira ntchito, jambulani malo ake, kenako ndikujambulani komwe kuli banja la Microchip FPGA
malaibulale opangidwa kale (mwachitsanzoample, SmartFusion2) pomwe mukuyendetsa mapangidwe anu.
alib presynth
amap presynth presynth
amap SmartFusion2 - Phatikizani zonse zofunika HDL files amagwiritsidwa ntchito popanga ndi laibulale yofunikira.
alog -work presynth temp.v (ya Verilog)
alogi -work presynth testbench.v
acom -work presynth temp.vhd (ya Vhdl)
acom -work presynth testbench.vhd - Tsanzirani mapangidwe.
asim -L SmartFusion2 -L presynth -t 1ps presynth.testbench
kuthamanga 10us
2.4 Nkhani Zodziwika (Funsani Funso)
Gawoli likulemba zomwe zimadziwika komanso zolepheretsa.
- Ma library opangidwa pogwiritsa ntchito Riviera-PRO ndi okhazikika papulatifomu (ie malaibulale a 64-bit sangathe kuyendetsedwa papulatifomu ya 32-bit ndi mosemphanitsa).
- Pamapangidwe okhala ndi SEDES/MDDR/FDDR, gwiritsani ntchito njira iyi mu run.do yanu files poyendetsa zoyerekeza pambuyo popanga mapangidwe awo:
- Active-HDL: asim -o2
- Riviera-PRO: asim -O2 (zofananira za presynth ndi post-layout ) ndi asim -O5 (zoyerekeza zapambuyo)
Kukonzekera kwa Aldec kwa Active-HDL ndi Riviera-Pro kuli ndi ma SAR otsatirawa. Kuti mudziwe zambiri, lemberani Microchip Technical Support. - SAR 49908 - Active-HDL: Vuto la VHDL pamayesero a Math block
- SAR 50627 - Riviera-PRO 2013.02: Zolakwika zofananira pamapangidwe a SEDES
- SAR 50461 - Riviera-PRO: njira ya asim -O2/-O5 poyerekezera
Kukhazikitsa kwa Cadence Incisive (Funsani Funso)
Muyenera kupanga script file zofanana ndi ModelSim ME/ModelSim Pro ME run.do kuti mugwiritse ntchito
Cadence Incisive simulator. Tsatirani izi ndikupanga script file kwa NCSim kapena gwiritsani ntchito script file
amaperekedwa kuti asinthe ModelSim ME/ModelSim Pro ME run.do files mu kasinthidwe files
zofunikira kuyendetsa zoyeserera pogwiritsa ntchito NCSim.
Chofunika: Cadence yasiya kutulutsa mitundu yatsopano ya Incisive Enterprise
simulator ndikuyamba kuthandizira Xcelium simulator.
3.1 Zosintha Zachilengedwe (Funsani Funso)
Kuti mugwiritse ntchito Cadence Incisive simulator, konzani zosintha zotsatirazi:
- LM_LICENSE_FILE: iyenera kuphatikiza cholozera ku chilolezo file.
- cds_root: ikuyenera kuloza komwe kuli chikwatu chakunyumba kwa Cadence Incisive Installation.
- NTCHITO: iyenera kuloza ku malo a bin pansi pa bukhu la zida zomwe zatchulidwa ndi cds_root ndiko kuti,
$cds_root/tools/bin/64bit (kwa makina a 64-bit ndi $cds_root/tools/bin for a 32-bit machine).
Pali njira zitatu zokhazikitsira malo oyeserera ngati kusinthana pakati pa makina a 64-bit ndi 32-bit:
Mlandu 1: PATH Variable
Yendetsani lamulo ili:
set njira = (install_dir/tools/bin/64bit $njira) yamakina a 64bit ndi
set path = (install_dir/tools/bin $path) pamakina a 32bit
Mlandu 2: Kugwiritsa ntchito -64bit Command-line Option
Mu mzere wolamula tchulani -64bit njira kuti mupemphe 64bit yomwe ingathe kuchitidwa.
Mlandu 3: Kukhazikitsa INCA_64BIT kapena CDS_AUTO_64BIT Zosintha Zachilengedwe
Kusiyana kwa INCA_64BIT kumatengedwa ngati boolean. Mutha kuyika kusinthaku kumtengo uliwonse kapena chingwe chopanda pake.
setenv INCA_64BIT
Chofunika: The INCA_64BIT kusintha kwa chilengedwe sikukhudza zida zina za Cadence, monga zida za IC. Komabe, pazida za Incisive, zosintha za INCA_64BIT zimaposa makonzedwe a CDS_AUTO_64BIT chilengedwe. Ngati kusintha kwa chilengedwe kwa INCA_64BIT kukhazikitsidwa, zida zonse za Incisive zimayenda mu 64-bit mode. setenv CDS_AUTO_64BIT KUPHATIKIRA:INCA
Chofunika: The chingwe INCA iyenera kukhala ya zilembo zazikulu. Zonse zomwe zikuyenera kuchitika ziyenera kuyendetsedwa munjira ya 32-bit kapena 64-bit mode, musakhazikitse zosinthika kuti ziphatikizepo chimodzi chotheka, monga izi:
setenv CDS_AUTO_64BIT KUPHATIKIRA:ncelab
Zida zina za Cadence, monga zida za IC, zimagwiritsanso ntchito CDS_AUTO_64BIT kusintha kwa chilengedwe kuwongolera kusankha kwa 32-bit kapena 64-bit executable. Gome lotsatirali likuwonetsa momwe mungakhazikitsire ma CDS_AUTO_64BIT kuti mugwiritse ntchito zida za Incisive ndi zida za IC m'njira zonse.
Gulu 3-1. Zithunzi za CDS_AUTO_64BIT
| CDS_AUTO_64BIT Zosintha | Incisive Zida | Zida za IC |
| setenv CDS_AUTO_64BIT ZONSE | 64 pang'ono | 64 pang'ono |
| setenv CDS_AUTO_64BIT NONE | 32 pang'ono | 32 pang'ono |
| setenv CDS_AUTO_64BIT KUCHOKERA:ic_binary | 64 pang'ono | 32 pang'ono |
| setenv CDS_AUTO_64BIT KUCHOKERA:INCA | 32 pang'ono | 64 pang'ono |
Zofunika: Zida zonse za Incisive ziyenera kuyendetsedwa munjira ya 32-bit kapena 64-bit mode, osagwiritsa ntchito EXCLUDE kusaphatikiza zomwe zikuyenera kuchitika, monga izi: setenv CDS_AUTO_64BIT EXCLUDE:ncelab
Mukakhazikitsa CDS_AUTO_64BIT yosiyana kuti isaphatikize zida za Incisive (setenv CDS_AUTO_64BIT EXCLUDE:INCA), zida zonse za Incisive zimayendetsedwa munjira ya 32-bit. Komabe, njira ya -64bit-line-line imaposa kusintha kwa chilengedwe.
Kukonzekera kotsatiraku files imakuthandizani kuyang'anira deta yanu ndikuwongolera magwiridwe antchito a zida zoyeserera ndi zofunikira:
- Mapu a library file (cds.lib)—Imatanthawuza dzina lomveka la malo omwe mwapanga.
- Ma library ndikuwagwirizanitsa ndi mayina a zolemba zenizeni.
- Zosintha file (hdl.var) -Imatanthauzira zosintha zomwe zimakhudza machitidwe a zida zofananira ndi zofunikira.
3.2 Tsitsani Library Yophatikizidwa (Funsani Funso)
Tsitsani malaibulale a Cadence Incisive kuchokera ku Microsemi's webmalo.
3.3 Kupanga NCSim Script File (Funsani Funso)
Pambuyo popanga kopi ya run.do files, chitani izi kuti mugwiritse ntchito NCSim:
- Pangani cds.lib file zomwe zimatanthawuza malaibulale omwe akupezeka komanso malo awo. The file ili ndi mawu omwe amalemba mayina omveka a library kumayendedwe awo enieni. Za example, ngati mukuyendetsa presynth simulation, cds.lib file yalembedwa monga momwe ikusonyezera mu codeblock yotsatira.
TASINDIKIRANI presynth ./presynth
DEFINE COREAHBLITE_LIB ./COREAHBLITE_LIB
TULUKANSO smartfusion2 - Pangani hdl.var file, kasinthidwe kosankha file yomwe ili ndi masinthidwe osinthika, omwe amatsimikizira momwe chilengedwe chanu chimapangidwira. Zosintha zotsatirazi files akuphatikizidwa:
- Zosintha zomwe zimagwiritsidwa ntchito pofotokoza laibulale yantchito komwe wopanga amasunga zinthu zophatikizidwa ndi zina zotengedwa.
- Kwa Verilog, zosintha (LIB_MAP, VIEW_MAP, NTCHITO) zomwe zimagwiritsidwa ntchito kutchula malaibulale ndi views kufufuza pamene wofotokozerayo athetsa zochitika.
- Zosintha zomwe zimakupatsani mwayi wofotokozera zosankha ndi mikangano yamawu opangira, ofotokozera, ndi zoyeserera.
Pankhani ya presynth kayeseleledwe exampzomwe zawonetsedwa pamwambapa, tinene kuti tili ndi ma RTL atatu files: a.v, b.v, ndi testbench.v, zomwe ziyenera kuphatikizidwa kukhala presynth, COREAHBLITE_LIB, ndi malaibulale a presynth motsatana. hdl.var file ikhoza kulembedwa monga momwe iliri mu codeblock yotsatira.
TANTHAUZIRA NTCHITO presynth
DEFINE PROJECT_DIR <malo a files>
TANKHANI LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/a.v => presynth )
TAFOTANI LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/b.v => COREAHBLITE_LIB )
TANZANI LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/testbench.v => presynth )
TASINDIKIRANI LIB_MAP ( $LIB_MAP, + => presynth) - Lembani mapangidwe files pogwiritsa ntchito njira ya ncvlog.
ncvlog + incdir+ -cdslib ./cds.lib -hdlvar ./hdl.var -logfile
ncvlog.log -update -linedebug a.v b.v testbench.v - Konzani mapangidwe pogwiritsa ntchito ncelab. Wopangayo amapanga mawonekedwe owongolera potengera zomwe zachitika komanso kasinthidwe pamapangidwewo, amakhazikitsa kulumikizana kwazizindikiro, ndikuwerengera zoyambira zazinthu zonse zomwe zimapangidwira. Mapangidwe apamwamba amasungidwa mu chithunzi choyerekeza, chomwe ndi chithunzi cha mapangidwe anu omwe oyeserera amagwiritsa ntchito poyeserera.
ncelab -Uthenga -cdslib ./cds.lib -hdlvar ./hdl.var -logfile ncelab.log -errormax 15 -
kupeza +rwc -status worklib.:module
Kufotokozera Pamafaniziro a Post-layout
Ngati mafanizidwe apangidwe pambuyo pake, choyamba SDF file ziyenera kuphatikizidwa musanafotokozere bwino pogwiritsa ntchito lamulo la ncsdfc.
ncdfcfilename>.sdf -output <filedzina>.sdf.X
Pakuwunikira gwiritsani ntchito zotulutsa za SDF zomwe zidapangidwa ndi -autosdf monga zikuwonetsedwa mu codeblock yotsatira.
ncelab -autosdf -Uthenga -cdslib ./cds.lib -hdlvar ./hdl.var -logfile ncelab.log -errormax
15 -access +rwc -status worklib. : module -sdf_cmd_file ./
sdf_cmd_file
sdf_cmd_file ziyenera kukhala monga momwe ziliri mu codeblock yotsatira.
COMPILED_SDF_FILE = "<malo a SDF yophatikizidwa file>” - Yezetsani kugwiritsa ntchito ncsim. Pambuyo pofotokozera chithunzithunzi chofananira chimapangidwa, chomwe chimayikidwa ndi ncsim kuti chiyesedwe. Mutha kuthamanga mu batch mode kapena GUI mode.
ncsim -Uthenga -batch/-gui -cdslib ./cds.lib -hdlvar ./hdl.var -logfile ncsim.log -
errormax 15 -status worklib. : module
Zofunika: Masitepe onse atatu omwe ali pamwambawa akukonzekera, kulongosola, ndi kuyerekezera akhoza kuikidwa mu chipolopolo file ndipo amachokera ku mzere wolamula. M'malo mogwiritsa ntchito masitepe atatuwa, mapangidwe amatha kufananizidwa mu gawo limodzi pogwiritsa ntchito njira ya ncverilog kapena irun monga momwe zilili mu codeblock yotsatira.
ncverilog + incdir+ -cdslib ./cds.lib –hdlvar ./hdl.var <all RTL
files amagwiritsidwa ntchito pakupanga>
irun +incdir+ -cdslib ./cds.lib –hdlvar ./hdl.var <all RTL files
amagwiritsidwa ntchito pakupanga>
3.3.1 Nkhani Zodziwika (Funsani Funso)
Testbench Workaround
Kugwiritsa ntchito mawu otsatirawa pofotokoza mafupipafupi a wotchi mu testbench yopangidwa ndi wogwiritsa ntchito, kapena testbench yokhazikika yopangidwa ndi Libero SoC sigwira ntchito ndi NCSim.
nthawi zonse @(SYSCLK)
#(SYSCLK_PERIOD / 2.0) SYSCLK <= !SYSCLK;
Sinthani motere kuti muyesere:
nthawi zonse #(SYSCLK_PERIOD / 2.0) SYSCLK = ~SYSCLK;
Zofunika: Zophatikizidwa malaibulale a NCSim ndi a pulatifomu (mwachitsanzo, malaibulale 64 sagwirizana ndi nsanja ya 32 ndi mosemphanitsa).
Mafanizidwe a Postsynth ndi Post-layout Pogwiritsa Ntchito MSS ndi SERDES Pamene mukuyendetsa zofananira za postsynth zamapangidwe omwe ali ndi chipika cha MSS kapena mafanizidwe opangidwa pambuyo pake pogwiritsa ntchito SERDES, zofananira za BFM sizigwira ntchito ngati njira ya -libmap ili
sichinatchulidwe panthawi yofotokozera. Izi zili choncho chifukwa panthawi yofotokozera, MSS imathetsedwa kuchokera ku laibulale ya ntchito (chifukwa chakumangirira kosasintha ndi worklib kukhala postsynth / post-layout) kumene ndi Ntchito Yokhazikika.
Lamulo la ncelab liyenera kulembedwa monga momwe zasonyezedwera mu code block kuti athetse MSS
block kuchokera ku laibulale yopangidwa ndi SmartFusion2.
ncelab -libmap lib.map -libverbose -Message -access +rwc cfg1
ndi lib.map file ziyenera kukhala motere:
sintha cfg1;
kupanga ;
kusakhulupirika liblist smartfusion2 ;
endconfig
Izi zimathetsa selo iliyonse mulaibulale ya SmartFusion2 musanayang'ane mulaibulale yantchito mwachitsanzo postsynth/ post-layout.
Njira ya -libmap ingagwiritsidwe ntchito mwachisawawa panthawi yofotokozera zonse (presynth, postsynth, ndi post-layout). Izi zimapewa zovuta zongoyerekeza zomwe zimachitika chifukwa cha kuwongolera zochitika kuchokera kuma library.
ncelab: *F, INTERR: KUSINTHA KWAMKATI
Kupatulapo chida cha ncelab ichi ndi chenjezo la mapangidwe omwe ali ndi FDDR mu SmartFusion 2 ndi IGLOO 2 panthawi ya postsynth ndi post-layout zoyerekeza pogwiritsa ntchito -libmap njira.
Zofunika: Nkhaniyi idanenedwa ku gulu lothandizira la Cadence (SAR 52113).
3.4 Sample Tcl ndi Shell Script Files (Funsani Funso)
Zotsatirazi files ndi kasinthidwe files zofunika kukhazikitsa mapangidwe ndi chipolopolo script file poyendetsa malamulo a NCSim.
Cds.lib
NE smartfusion2 /scratch/krydor/tmpspace/users/me/nc-vlog64/SmartFusion2
DEFINE COREAHBLITE_LIB ./COREAHBLITE_LIB
TASINDIKIRANI presynth ./presynth
Hdl.var
TANTHAUZIRA NTCHITO presynth
TANTHAUZA PROJECT_DIR /scratch/krydor/tmpspace/sqausers/me/3rd_party_simulators/Cadence/IGLOO2/
ENVM/M2GL050/envm_fic1_ser1_v/eNVM_fab_master
TAFOTANI LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/core/coreahblite_addrdec.v => COREAHBLITE_LIB )
TAFOTANI LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/core/coreahblite_defaultslavesm.v => COREAHBLITE_LIB )
TAFOTANI LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/core/coreahblite_masterstagev => COREAHBLITE_LIB )
TAFOTANI LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/core/coreahblite_slavearbiter.v => COREAHBLITE_LIB )
TAFOTANI LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/core/coreahblite_slavestagev => COREAHBLITE_LIB )
TAFOTANI LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/core/coreahblite_matrix2x16.v => COREAHBLITE_LIB )
TAFOTANI LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/core/coreahblite.v => COREAHBLITE_LIB )
TAFOTANI LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB/CCC_0/SB_CCC_0_FCC.v =>
presynth)
TATULANI LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreConfigMaster/
2.0.101/rtl/vlog/core/coreconfigmaster.v => presynth )
TAFOTANI LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreConfigP/4.0.100/rtl/
vlog/core/coreconfigp.v => presynth)
TATULANI LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreResetP/5.0.103/rtl/
vlog/core/coresetp_pcie_hotreset.v => presynth)
TATULANI LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreResetP/5.0.103/rtl/
vlog/core/coresetp.v => presynth)
TAFOTANI LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB/FABOSC_0/SB_FABOSC_0_OSC.v =>
presynth)
TANZANI LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB_HPMS/SB_HPMS.v => presynth )
TAFOTANI LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB/SB.v => presynth )
TAFOTENGANI LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB_top/SERDES_IF_0/
SB_top_SERDES_IF_0_SERDES_IF.v => presynth )
TAFOTSANI LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB_top/SB_top.v => presynth )
TAFOTSANI LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB_top/testbench.v => presynth )
TASINDIKIRANI LIB_MAP ( $LIB_MAP, + => presynth)
Commands.csh
ncvlog +incdir+../../component/work/SB_top -cdslib ./cds.lib -hdlvar ./hdl.var -logfile
ncvlog.log -errormax 15 -update -linedebug
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite_addrdec.v
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/
coreahblite_defaultslavesm.v
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite_masterstagev
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite_slavearbiter.v
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite_slavestagev
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite_matrix2x16.v
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite.v
../../component/work/SB/CCC_0/SB_CCC_0_FCCC.v
../../component/Actel/DirectCore/CoreConfigMaster/2.0.101/rtl/vlog/core/coreconfigmaster.v
../../component/Actel/DirectCore/CoreConfigP/4.0.100/rtl/vlog/core/coreconfigp.v
../../component/Actel/DirectCore/CoreResetP/5.0.103/rtl/vlog/core/coreresetp_pcie_hotreset.v
../../component/Actel/DirectCore/CoreResetP/5.0.103/rtl/vlog/core/coreresetp.v
../../component/work/SB/FABOSC_0/SB_FABOSC_0_OSC.v ../../component/work/SB_HPMS/SB_HPMS.v
../../component/work/SB/SB.v ../../component/work/SB_top/SERDES_IF_0/
SB_top_SERDES_IF_0_SERDES_IF.v
../../component/work/SB_top/SB_top.v ../../component/work/SB_top/testbench.v
ncelab -Message -cdslib ./cds.lib -hdlvar ./hdl.var
-work presynth -logfile ncelab.log -errormax 15 -access +rwc -status presynth.testbench: module
ncsim -Message -batch -cdslib ./cds.lib -hdlvar ./
hdl.var -logfile ncsim.log -errormax 15 -status presynth.testbench: gawo
3.5 Zochita zokha (Funsani Funso)
Zolemba zotsatirazi file imatembenuza ModelSim run.do files mu kasinthidwe files amafunikira kuyendetsa zofananira pogwiritsa ntchito NCSim.
Zolemba File Kugwiritsa ntchito
perl cadence_parser.pl presynth_run.do postsynth_run.do
postlayout_run.do Microsemi_Family
Location_of_Cadence_Precompiled_libraries
Cadence_parser.pl
#!/usr/bin/perl -w
######################################################## ###############################################
####################
#Kagwiritsidwe: perl questa_parser.pl presynth_run.do postsynth_run.do postlayout_run.do
Microsemi_Family Precompiled_Libraries_location#
######################################################## ###############################################
####################
gwiritsani ntchito POSIX;
gwiritsani ntchito mwamphamvu;
wanga ($presynth, $postsynth, $postlayout, $family, $lib_location) = @ARGV;
&questa_parser($presynth, $family, $lib_location);
&questa_parser($postsynth, $family, $lib_location);
&questa_parser($postlayout, $family, $lib_location);
questa_parser {
wanga $ModelSim_run_do = $_[0];
my $actel_family = $_[1];
wanga $lib_location = $_[2];
dziko langa la $;
ngati (-e "$ModelSim_run_do")
{
open (INFILE,"$ModelSim_run_do");
wanga @ModelSim_run_do = <INFILE>;
mzere wanga $;
ngati ( $ModelSim_run_do =~ m/(presynth)/)
{
`mkdir QUESTA_PRESYNTH`;
open (OUTFILE,”>QUESTA_PRESYNTH/presynth_questa.do”);
$ dziko = $ 1;
} elsif ( $ModelSim_run_do =~ m/(postsynth)/)
{
`mkdir QUESTA_POSTSYNTH`;
open (OUTFILE,”>QUESTA_POSTSYNTH/postsynth_questa.do”);
$ dziko = $ 1;
} elsif ( $ModelSim_run_do =~ m/(postlayout)/ )
{
`mkdir QUESTA_POSTLAYOUT`;
open (OUTFILE,”>QUESTA_POSTLAYOUT/postlayout_questa.do”);
$ dziko = $ 1;
} wina
{
print “Zolemba Zolakwika Zoperekedwa kwa a file\n";
sindikizani "#Usage: perl questa_parser.pl presynth_run.do postsynth_run.do postlayout_run.do
\"Libraries_location\"\n";
}
foreach $line (@ModelSim_run_do)
{
# General Operations
$line =~ s/..\/designer.*kuyerekezera\///g;
$line =~ s/$state/$state\_questa/g;
#SINDIKIZANIFILE "$line \n";
ngati ($line =~ m/vmap\s+.*($actel_family)/)
{
SINDIKIZANIFILE "vmap $actel_family \"$lib_location\"\n";
} elsif ($line =~ m/vmap\s+(.*._LIB)/)
{
$line =~ s/..\/component/..\/..\/component/g;
SINDIKIZANIFILE "$line \n";
} elsif ($line =~ m/vsim/)
{
$ mzere =~ s/vsim/vsim -novopt/g;
SINDIKIZANIFILE "$line \n";
} wina
{
SINDIKIZANIFILE "$line \n";
}
}
pafupi (INFILE);
kutseka (OUTFILE);
} zina {
sindikizani "$ModelSim_run_do kulibe. Yambitsaninso kayeseleledwe katsopano \n";
}
}
Kukhazikitsa kwa Cadence Xcelium (Kulowa kwa Microchip)
Muyenera kupanga script file zofanana ndi ModelSim ME/ModelSim Pro ME run.do kuyendetsa Cadence Xcelium simulator. Tsatirani izi ndikupanga script file kwa Xcelium kapena gwiritsani ntchito script file amaperekedwa kuti asinthe ModelSim ME/ModelSim Pro ME run.do files mu kasinthidwe files amafunikira kuyendetsa zoyeserera pogwiritsa ntchito Xcelium.
4.1 Zosintha Zachilengedwe (Funsani Funso)
Kuti muyendetse Cadence Xcelium, konzani zosintha zotsatirazi:
- LM_LICENSE_FILE: iyenera kuphatikiza cholozera ku chilolezo file.
- cds_root: iyenera kuloza ku chikwatu chakunyumba komwe kuli Cadence Incisive Installation.
- PATH: iyenera kuloza komwe kuli bin pansi pa zida zolozera ndi cds_root (ie.
$cds_root/tools/bin/64bit (kwa makina 64-bit ndi $cds_root/tools/bin kwa 32 bit
makina).
Pali njira zitatu zokhazikitsira malo oyeserera ngati kusinthana pakati pa makina a 64-bit ndi 32-bit:
Mlandu 1: PATH Variable
set njira = (install_dir/tools/bin/64bit $njira) yamakina a 64bit ndi
set path = (install_dir/tools/bin $path) pamakina a 32bit
Mlandu 2: Kugwiritsa ntchito -64bit Command-line Option
Mu mzere wolamula tchulani -64bit njira kuti muyimbire 64-bit yotheka.
Mlandu 3: Kukhazikitsa INCA_64BIT kapena CDS_AUTO_64BIT Zosintha Zachilengedwe
Kusiyana kwa INCA_64BIT kumatengedwa ngati boolean. Mutha kuyika kusinthaku kumtengo uliwonse kapena kukhala wopanda pake
chingwe.
setenv INCA_64BIT
Chofunika: The INCA_64BIT kusintha kwa chilengedwe sikukhudza zida zina za Cadence, monga zida za IC. Komabe, pa zida za Incisive, zosintha za INCA_64BIT zimaposa makonzedwe a CDS_AUTO_64BIT chilengedwe. Ngati INCA_64BIT kusintha kwa chilengedwe ndi et, zida zonse za Incisive zimayenda mu 64-bit mode.
setenv CDS_AUTO_64BIT KUPHATIKIRA:INCA
Chofunika: The chingwe INCA iyenera kukhala ya zilembo zazikulu. Zonse zomwe zikuyenera kuchitika ziyenera kuyendetsedwa munjira ya 2-bit kapena 64-bit mode, musakhazikitse zosinthika kuti ziphatikizepo chimodzi chotheka, monga izi:
setenv CDS_AUTO_64BIT KUPHATIKIRA:ncelab
Zida zina za Cadence, monga zida za IC, zimagwiritsanso ntchito CDS_AUTO_64BIT kusintha kwa chilengedwe kuwongolera kusankha kwa 32-bit kapena 64-bit executable. Gome lotsatirali likuwonetsa momwe mungakhazikitsire ma CDS_AUTO_64BIT kuti mugwiritse ntchito zida za Incisive ndi zida za IC m'njira zonse.
Gulu 4-1. Zithunzi za CDS_AUTO_64BIT
| CDS_AUTO_64BIT Zosintha | Incisive Zida | Zida za IC |
| setenv CDS_AUTO_64BIT ZONSE | 64-bit | 64-bit |
| setenv CDS_AUTO_64BIT NONE | 32-bit | 32-bit |
| setenv CDS_AUTO_64BIT KUPANDA:ic_binary |
64-bit | 32-bit |
| setenv CDS_AUTO_64BIT KUCHOKERA:INCA | 32-bit | 64-bit |
Zofunika: Zida zonse za Incisive ziyenera kuyendetsedwa munjira ya 32-bit kapena 64-bit mode, musagwiritse ntchito EXCLUDE kusiya zomwe zingatheke, monga izi:
setenv CDS_AUTO_64BIT EXCLUDE:ncelab
Ngati muyika CDS_AUTO_64BIT yosiyana kuti musaphatikize zida za Incisive (setnv)
CDS_AUTO_64BIT EXCLUDE:INCA), zida zonse za Incisive zimayendetsedwa munjira ya 32-bit. Komabe, a
-64bit mzere wotsatira mzere umaposa kusintha kwa chilengedwe.
Kukonzekera kotsatiraku files imakuthandizani kuyang'anira deta yanu ndikuwongolera magwiridwe antchito a zida zoyeserera ndi zofunikira:
- Mapu a library file (cds.lib) imatanthawuza dzina lomveka la malo omwe mwapanga.
- Ma library ndikuwagwirizanitsa ndi mayina a zolemba zenizeni.
- Zosintha file (hdl.var) imatanthauzira zosintha zomwe zimakhudza machitidwe a zida zofananira ndi zofunikira.
4.2 Tsitsani Library Yophatikizidwa (Funsani Funso)
Tsitsani malaibulale a Cadence Xcelium kuchokera ku Microsemi's webmalo.
4.3 Kupanga zolemba za Xcelium file (Funsani Funso)
Pambuyo popanga kopi ya run.do files, chitani zotsatirazi kuti mugwiritse ntchito kayeseleledwe kanu ka Xcelium script file.
- Pangani cds.lib file zomwe zimatanthawuza kuti ndi malaibulale ati omwe akupezeka komanso komwe ali.
The file ili ndi mawu omwe amalemba mayina omveka a library kumayendedwe awo enieni. Za example, ngati mukuyendetsa presynth simulation, cds.lib file ikhoza kulembedwa monga momwe iliri mu codeblock yotsatira.
TASINDIKIRANI presynth ./presynth
DEFINE COREAHBLITE_LIB ./COREAHBLITE_LIB
TULUKANSO smartfusion2 - Pangani hdl.var file chomwe chiri chosankha kasinthidwe file yomwe ili ndi masinthidwe osinthika, omwe amatsimikizira momwe chilengedwe chanu chimapangidwira. Izi zikuphatikizapo:
- Zosintha zomwe zimagwiritsidwa ntchito pofotokoza laibulale yantchito komwe wopanga amasunga zinthu zophatikizidwa ndi zina zotengedwa.
- Kwa Verilog, zosintha (LIB_MAP, VIEW_MAP, NTCHITO) zomwe zimagwiritsidwa ntchito kutchula malaibulale ndi views kufufuza pamene wofotokozerayo athetsa zochitika.
- Zosintha zomwe zimakupatsani mwayi wofotokozera zosankha ndi mikangano yamawu opangira, ofotokozera, ndi zoyeserera.
Pankhani ya presynth kayeseleledwe exampzomwe tawonetsedwa pamwambapa, tinene kuti tili ndi 3 RTL files a.v, b.v, ndi testbench.v, zomwe ziyenera kupangidwa kukhala presynth, COREAHBLITE_LIB, ndi malaibulale a presynth motsatana. hdl.var file ikhoza kulembedwa monga momwe iliri mu codeblock yotsatira.
TANTHAUZIRA NTCHITO presynth
DEFINE PROJECT_DIR <malo a files>
TANKHANI LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/a.v => presynth )
TAFOTANI LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/b.v => COREAHBLITE_LIB )
TANZANI LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/testbench.v => presynth )
TASINDIKIRANI LIB_MAP ( $LIB_MAP, + => presynth) - Lembani mapangidwe files pogwiritsa ntchito njira ya ncvlog.
xmvlog +incdir+ -cdslib ./cds.lib -hdlvar ./hdl.var -logfile
ncvlog.log -update -linedebug a.v b.v testbench.v - Konzani mapangidwe pogwiritsa ntchito ncelab. Wopangayo amapanga mawonekedwe owongolera potengera zomwe zachitika komanso kasinthidwe pamapangidwewo, amakhazikitsa kulumikizana kwazizindikiro, ndikuwerengera zoyambira zazinthu zonse zomwe zimapangidwira. Mapangidwe apamwamba amasungidwa mu chithunzi choyerekeza, chomwe ndi chithunzi cha mapangidwe anu omwe oyeserera amagwiritsa ntchito poyeserera.
Xcelium -Uthenga -cdslib ./cds.lib -hdlvar ./hdl.var -logfile ncelab.log -errormax 15 -
kupeza +rwc -status worklib.:module
Kufotokozera Pamafaniziro a Post-layout
Ngati mafanizidwe apangidwe pambuyo pake, choyamba SDF file ziyenera kuphatikizidwa musanafotokozere bwino pogwiritsa ntchito lamulo la ncsdfc.
Xceliumfilename>.sdf -output <filedzina>.sdf.X
Pakuwunikira gwiritsani ntchito zotulutsa za SDF zomwe zidapangidwa ndi -autosdf monga zikuwonetsedwa mu codeblock yotsatira.
xmelab -autosdf -Uthenga -cdslib ./cds.lib -hdlvar ./hdl.var -logfile ncelab.log -errormax
15 -access +rwc -status worklib. : module -sdf_cmd_file ./
sdf_cmd_file
sdf_cmd_file ziyenera kukhala monga momwe ziliri mu codeblock yotsatira.
COMPILED_SDF_FILE = "<malo a SDF yophatikizidwa file>” - Yesani kugwiritsa ntchito Xcelium. Pambuyo pofotokozera chithunzithunzi choyerekeza chimapangidwa chomwe chimayikidwa ndi Xcelium kuti chiyesedwe. Izi zitha kuyendetsedwa mu batch mode kapena GUI mode.
xmsim -Uthenga -batch/-gui -cdslib ./cds.lib -hdlvar ./hdl.var -logfile xmsim.log -
errormax 15 -status worklib. : module
Kukonzekera kwa Cadence Xcelium
Chofunika: Zonse masitepe atatu omwe ali pamwambawa akukonzekera, kulongosola ndi kuyerekezera akhoza kuikidwa mu chipolopolo file ndipo amachokera ku mzere wolamula. M'malo mogwiritsa ntchito masitepe atatuwa, mapangidwe amatha kutsatiridwa mu sitepe imodzi pogwiritsa ntchito njira ya ncverilog kapena xrun monga momwe zilili mu codeblock yotsatira.
xmverilog +incdir+ -cdslib ./cds.lib –hdlvar ./hdl.var <all RTL
files amagwiritsidwa ntchito pakupanga>
xrun +incdir+ -cdslib ./cds.lib –hdlvar ./hdl.var <all RTL files
amagwiritsidwa ntchito pakupanga>
4.3.1 Nkhani Zodziwika (Funsani Funso)
Testbench Workaround
Kugwiritsa ntchito mawu otsatirawa pofotokoza kuchuluka kwa wotchi mu testbench yopangidwa ndi wogwiritsa ntchito kapena testbench yosasinthika yopangidwa ndi Libero SoC sikugwira ntchito ndi Xcelium.
nthawi zonse @(SYSCLK)
#(SYSCLK_PERIOD / 2.0) SYSCLK <= !SYSCLK;
Sinthani motere kuti muyesere:
nthawi zonse #(SYSCLK_PERIOD / 2.0) SYSCLK = ~SYSCLK;
Zofunika: Malaibulale ophatikizidwa a Xcelium ndi a pulatifomu (ie 64 bit library sagwirizana ndi 32 bit platform and vice versa).
Postsynth ndi Post-layout Simulations pogwiritsa ntchito MSS ndi SERDES
Pamene mukuyendetsa mafanizidwe a postsynth a mapangidwe omwe ali ndi chipika cha MSS, kapena mafanizidwe opangidwa pambuyo pake pogwiritsa ntchito SERDES, zojambula za BFM sizigwira ntchito ngati -libmap njira siinatchulidwe panthawi yofotokozera. Izi zili choncho chifukwa panthawi yofotokozera, MSS imathetsedwa kuchokera ku laibulale ya ntchito (chifukwa chakumangirira kosasintha ndi worklib kukhala postsynth / post-layout) kumene ndi Ntchito Yokhazikika.
Lamulo la ncelab liyenera kulembedwa monga momwe zasonyezedwera mu code block kuti muthetse chipika cha MSS kuchokera ku laibulale yopangidwa ndi SmartFusion2.
xmelab -libmap lib.map -libverbose -Message -access +rwc cfg1
ndi lib.map file ziyenera kukhala motere:
sintha cfg1;
kupanga ;
kusakhulupirika liblist smartfusion2 ;
endconfig
Izi ziyenera kuthetsa selo iliyonse mulaibulale ya SmartFusion2 musanayang'ane mulaibulale ya ntchito i.e. postsynth/post-layout.
Njira ya -libmap ingagwiritsidwe ntchito mwachisawawa panthawi yofotokozera zonse (presynth, postsynth ndi post-layout). Izi zimapewa zovuta zongoyerekeza zomwe zimachitika chifukwa cha kuwongolera zochitika kuchokera kuma library.
xmelab: *F, INTERR: KUSINTHA KWAMKATI
Kupatula chida cha ncelab ichi ndi chenjezo la mapangidwe omwe ali ndi FDDR mu SmartFusion2 ndi IGLOO2
pazithunzi za postsynth ndi post-layout pogwiritsa ntchito -libmap njira.
Zofunika: Nkhaniyi idanenedwa ku gulu lothandizira la Cadence (SAR 52113).
4.4 Sample Tcl ndi shell script files (Funsani Funso)
Zotsatirazi files ndi kasinthidwe files zofunika kukhazikitsa mapangidwe ndi chipolopolo script file poyendetsa malamulo a Xcelium.
Cds.lib
KUTANTHULA smartfusion2 /scratch/krydor/tmpspace/users/me/nc-vlog64/SmartFusion2
DEFINE COREAHBLITE_LIB ./COREAHBLITE_LIB
TASINDIKIRANI presynth ./presynth
Hdl.var
TANTHAUZIRA NTCHITO presynth
TANTHAUZA PROJECT_DIR /scratch/krydor/tmpspace/sqausers/me/3rd_party_simulators/Cadence/IGLOO2/
ENVM/M2GL050/envm_fic1_ser1_v/eNVM_fab_master
TAFOTANI LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/core/coreahblite_addrdec.v => COREAHBLITE_LIB )
TAFOTANI LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/core/coreahblite_defaultslavesm.v => COREAHBLITE_LIB )
TAFOTANI LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/core/coreahblite_masterstagev => COREAHBLITE_LIB )
TAFOTANI LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/core/coreahblite_slavearbiter.v => COREAHBLITE_LIB )
TAFOTANI LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/core/coreahblite_slavestagev => COREAHBLITE_LIB )
TAFOTANI LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/core/coreahblite_matrix2x16.v => COREAHBLITE_LIB )
TAFOTANI LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/core/coreahblite.v => COREAHBLITE_LIB )
TAFOTANI LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB/CCC_0/SB_CCC_0_FCC.v =>
presynth)
TATULANI LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreConfigMaster/
2.0.101/rtl/vlog/core/coreconfigmaster.v => presynth )
TAFOTANI LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreConfigP/4.0.100/rtl/
vlog/core/coreconfigp.v => presynth)
TATULANI LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreResetP/5.0.103/rtl/
vlog/core/coresetp_pcie_hotreset.v => presynth)
TATULANI LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreResetP/5.0.103/rtl/
vlog/core/coresetp.v => presynth)
TAFOTANI LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB/FABOSC_0/SB_FABOSC_0_OSC.v =>
presynth)
TANZANI LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB_HPMS/SB_HPMS.v => presynth )
TAFOTANI LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB/SB.v => presynth )
TAFOTENGANI LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB_top/SERDES_IF_0/
SB_top_SERDES_IF_0_SERDES_IF.v => presynth )
TAFOTSANI LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB_top/SB_top.v => presynth )
TAFOTSANI LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB_top/testbench.v => presynth )
TASINDIKIRANI LIB_MAP ( $LIB_MAP, + => presynth)
Commands.csh
ncvlog +incdir+../../component/work/SB_top -cdslib ./cds.lib -hdlvar ./hdl.var -logfile
ncvlog.log -errormax 15 -update -linedebug
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite_addrdec.v
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/
coreahblite_defaultslavesm.v
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite_masterstagev
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite_slavearbiter.v
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite_slavestagev
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite_matrix2x16.v
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite.v
../../component/work/SB/CCC_0/SB_CCC_0_FCCC.v
../../component/Actel/DirectCore/CoreConfigMaster/2.0.101/rtl/vlog/core/coreconfigmaster.v
../../component/Actel/DirectCore/CoreConfigP/4.0.100/rtl/vlog/core/coreconfigp.v
../../component/Actel/DirectCore/CoreResetP/5.0.103/rtl/vlog/core/coreresetp_pcie_hotreset.v
../../component/Actel/DirectCore/CoreResetP/5.0.103/rtl/vlog/core/coreresetp.v
../../component/work/SB/FABOSC_0/SB_FABOSC_0_OSC.v ../../component/work/SB_HPMS/SB_HPMS.v
../../component/work/SB/SB.v ../../component/work/SB_top/SERDES_IF_0/
SB_top_SERDES_IF_0_SERDES_IF.v
../../component/work/SB_top/SB_top.v ../../component/work/SB_top/testbench.v
ncelab -Message -cdslib ./cds.lib -hdlvar ./hdl.var
-work presynth -logfile ncelab.log -errormax 15 -access +rwc -status presynth.testbench: module
ncsim -Message -batch -cdslib ./cds.lib -hdlvar ./
hdl.var -logfile ncsim.log -errormax 15 -status presynth.testbench: gawo
4.5 Zochita zokha (Kulowa kwa Microchip)
Zolemba zotsatirazi file amasintha ModelSim run.do files mu kasinthidwe files amafunikira kuyendetsa zoyeserera pogwiritsa ntchito Xcelium.
Zolemba File Kugwiritsa ntchito
perl cadence_parser.pl presynth_run.do postsynth_run.do
postlayout_run.do Microsemi_Family
Location_of_Cadence_Precompiled_libraries
Cadence_parser.pl
#!/usr/bin/perl -w
######################################################## ###############################################
####################
#Kagwiritsidwe: perl questa_parser.pl presynth_run.do postsynth_run.do postlayout_run.do
Microsemi_Family Precompiled_Libraries_location#
######################################################## ###############################################
####################
gwiritsani ntchito POSIX;
gwiritsani ntchito mwamphamvu;
wanga ($presynth, $postsynth, $postlayout, $family, $lib_location) = @ARGV;
&questa_parser($presynth, $family, $lib_location);
&questa_parser($postsynth, $family, $lib_location);
&questa_parser($postlayout, $family, $lib_location);
questa_parser {
wanga $ModelSim_run_do = $_[0];
my $actel_family = $_[1];
wanga $lib_location = $_[2];
dziko langa la $;
ngati (-e "$ModelSim_run_do")
{
open (INFILE,"$ModelSim_run_do");
wanga @ModelSim_run_do = <INFILE>;
mzere wanga $;
ngati ( $ModelSim_run_do =~ m/(presynth)/)
{
`mkdir QUESTA_PRESYNTH`;
open (OUTFILE,”>QUESTA_PRESYNTH/presynth_questa.do”);
$ dziko = $ 1;
} elsif ( $ModelSim_run_do =~ m/(postsynth)/)
{
`mkdir QUESTA_POSTSYNTH`;
open (OUTFILE,”>QUESTA_POSTSYNTH/postsynth_questa.do”);
$ dziko = $ 1;
} elsif ( $ModelSim_run_do =~ m/(postlayout)/ )
{
`mkdir QUESTA_POSTLAYOUT`;
open (OUTFILE,”>QUESTA_POSTLAYOUT/postlayout_questa.do”);
$ dziko = $ 1;
} wina
{
print “Zolemba Zolakwika Zoperekedwa kwa a file\n";
sindikizani "#Usage: perl questa_parser.pl presynth_run.do postsynth_run.do postlayout_run.do
\"Libraries_location\"\n";
}
foreach $line (@ModelSim_run_do)
{
# General Operations
$line =~ s/..\/designer.*kuyerekezera\///g;
$line =~ s/$state/$state\_questa/g;
#SINDIKIZANIFILE "$line \n";
ngati ($line =~ m/vmap\s+.*($actel_family)/)
{
SINDIKIZANIFILE "vmap $actel_family \"$lib_location\"\n";
} elsif ($line =~ m/vmap\s+(.*._LIB)/)
{
$line =~ s/..\/component/..\/..\/component/g;
SINDIKIZANIFILE "$line \n";
} elsif ($line =~ m/vsim/)
{
$ mzere =~ s/vsim/vsim -novopt/g;
SINDIKIZANIFILE "$line \n";
} wina
{
SINDIKIZANIFILE "$line \n";
}
}
pafupi (INFILE);
kutseka (OUTFILE);
} zina {
sindikizani "$ModelSim_run_do kulibe. Yambitsaninso kayeseleledwe katsopano \n";
}
}
Kukhazikitsa kwa Siemens QuestaSim/ModelSim (Funsani Funso)
The run.do files, yopangidwa ndi Libero SoC yofananira pogwiritsa ntchito ModelSim Microsemi Editions, ingagwiritsidwe ntchito pojambula pogwiritsa ntchito QuestaSim / ModelSim SE / DE / PE ndi kusintha kumodzi. Mu ModelSim ME/ModelSim Pro ME run.do file, malo a malaibulale omwe anasanjidwa kale akuyenera kusinthidwa.
Zofunika:
Mwachikhazikitso, chida chofananira kupatula ModelSim Pro ME imapanga kukhathamiritsa kwa mapangidwe panthawi yoyeserera yomwe ingakhudze kuwoneka muzinthu zofananira monga zinthu zopangidwa ndi zolimbikitsira.
Izi ndizothandiza kuchepetsa nthawi yoyeserera yoyeserera zovuta, pogwiritsa ntchito verbose, ma testbench odzifufuza okha. Komabe, kukhathamiritsa kosasinthika sikungakhale koyenera pazofananira zonse, makamaka nthawi zomwe mukuyembekeza kuyang'ana zotsatira zoyeserera pogwiritsa ntchito zenera la mafunde.
Kuti muthane ndi zovuta zomwe zimayambitsidwa ndi kukhathamiritsa uku, muyenera kuwonjezera malamulo oyenerera ndi mikangano yofananira pakuyerekeza kuti mubwezeretse mawonekedwe pamapangidwewo. Kuti mupeze malamulo okhudzana ndi zida, onani zolemba za simulator yomwe ikugwiritsidwa ntchito.
5.1 Zosintha Zachilengedwe (Funsani Funso)
M'munsimu ndi zofunika zosintha zachilengedwe.
- LM_LICENSE_FILE: iyenera kuphatikiza njira yopita ku chilolezo file.
- MODEL_TECH: ikuyenera kuzindikira njira yopita kumalo osungiramo malo a QuestaSim.
- PATH: ikuyenera kuloza komwe kukuyenera kuwonetsedwa ndi MODEL_TECH.
5.2 Kutembenuza run.do kwa Mentor QuestaSim (Funsani Funso)
The run.do files yopangidwa ndi Libero SoC yofananira pogwiritsa ntchito ModelSim Microsemi Editions ingagwiritsidwe ntchito poyerekezera pogwiritsa ntchito QuestaSim/ModelSim_SE ndi kusintha kumodzi.
Chofunika: Zonse mapangidwe omwe amapangidwa pogwiritsa ntchito QuestaSim ayenera kuphatikizapo -novopt
kusankha pamodzi ndi lamulo la vsim mu run.do script files.
5.3 Tsitsani Laibulale Yophatikizidwa (Funsani Funso)
Tsitsani malaibulale a Mentor Graphics QuestaSim kuchokera ku Microsemi's webmalo.
Kukhazikitsa kwa Synopsys VCS (Funsani Funso)
Kuyenda komwe kumalimbikitsidwa ndi Microsemi kumadalira Kuwongolera ndi Kuphatikiza Kuyenda mu VCS. Chikalatachi chili ndi script file yomwe imagwiritsa ntchito run.do script files yopangidwa ndi Libero SoC ndikupanga kukhazikitsidwa files zofunika kwa VCS kayeseleledwe. Zolemba file amagwiritsa ntchito run.do file kuchita zotsatirazi.
- Pangani mapu a library file, zomwe zimachitika pogwiritsa ntchito synopsys_sim.setup file ili mu bukhu lomwelo pomwe kuyerekezera kwa VCS kukuyenda.
- Pangani chipolopolo script file kuti mufotokoze bwino ndikuphatikiza kapangidwe kanu pogwiritsa ntchito VCS.
6.1 Zosintha Zachilengedwe (Funsani Funso)
Khazikitsani zosintha zoyenera za VCS kutengera kukhazikitsidwa kwanu. Zosintha zachilengedwe zomwe zimafunikira malinga ndi zolemba za VCS ndi:
- LM_LICENSE_FILE: iyenera kuphatikiza cholozera ku seva yalayisensi.
- VCS_HOME: ikuyenera kuloza komwe kuli chikwatu chakunyumba komwe kuyika VCS.
- PATH: iyenera kuphatikiza cholozera ku bukhu la bin pansi pa chikwatu cha VCS_HOME.
6.2 Tsitsani Library Yophatikizidwa (Funsani Funso)
Tsitsani malaibulale a Synopsys VCS kuchokera ku Microsemi's webmalo.
6.3 VCS Simulation Script File (Funsani Funso)
Pambuyo kukhazikitsa VCS ndi kupanga mapangidwe ndi zosiyana run.do filekuchokera ku Libero SoC, muyenera:
- Pangani mapu a library file synopsys_sim.setup; izi file ili ndi zolozera komwe kuli malaibulale onse oti agwiritse ntchito popanga.
Chofunika: The file dzina siliyenera kusintha ndipo liyenera kukhala m'ndandanda womwewo momwe kuyerekezera kukuchitika. Nayi example kwa izi file kwa presynthesis kayeseleledwe.
NTCHITO > ZOCHITIKA
SmartFusion2 :
presynth: ./presynth
ZOCHITA: ./work - Konzani mapangidwe osiyanasiyana files, kuphatikiza testbench, pogwiritsa ntchito vlogan command mu VCS. Malamulowa akhoza kuphatikizidwa muzolemba zachipolopolo file. Chotsatira ndi example la malamulo omwe amafunikira kuti afotokoze kamangidwe kamene kamafotokozedwa mu rtl.v ndi testbench yake yofotokozedwa mu
testbench.v.
vlogan +v2k -work presynth rtl.v
vlogan + v2k -work presynth testbench.v - Lembani mapangidwewo pogwiritsa ntchito VCS pogwiritsa ntchito lamulo ili.
vcs –sim_res=1fs presynth.testbench
Chidziwitso: The Kusintha kwanthawi koyerekeza kuyenera kukhazikitsidwa ku 1fs kuti muyesere moyenera. - Mapangidwewo akapangidwa, yambani kuyezetsa pogwiritsa ntchito lamulo ili.
./simv - Pakuyerekezera kobwerezabwereza, lamulo la VCS liyenera kukhala monga momwe likuwonetsedwa mu codeblock yotsatira.
vcs postlayout.testbench -sim_res=1fs -sdf max:.<DUT chitsanzo
dzina>: <sdf file njira> -gui -l postlayout.log
6.4 Zocheperako/Kupatulapo (Funsani Funso)
Zotsatirazi ndi zolephera/zopatula kukhazikitsidwa kwa Synopsys VCS.
- Zoyeserera za VCS zitha kuyendetsedwa pama projekiti a Verilog a Libero SoC okha. VCS simulator ili ndi zofunikira zolimba zachilankhulo cha VHDL zomwe sizikukwaniritsidwa ndi Libero SoC yodzipangira yokha VHDL. files.
- Muyenera kukhala ndi $ kumaliza mawu mu Verilog testbench kuti asiye kayeseleledwe nthawi iliyonse mukufuna.
Chofunika: Liti zoyeserera zimayendetsedwa mu GUI mode, nthawi yothamanga imatha kufotokozedwa mu GUI.
6.5 Sample Tcl ndi Shell Script Files (Funsani Funso)
Perl yotsatirayi imagwiritsa ntchito m'badwo wa synopsys_sim.setup file komanso script yogwirizana ndi chipolopolo files zofunika kufotokozera, kusonkhanitsa, ndi kuyerekezera mapangidwe.
Ngati mapangidwewo akugwiritsa ntchito MSS, koperani test.vec file yomwe ili mufoda yoyeserera ya pulojekiti ya Libero SoC mufoda yoyeserera ya VCS. Magawo otsatirawa ali ndi sampndi run.do files yopangidwa ndi Libero SoC, kuphatikiza mapu ofananirako laibulale ndi chipolopolo files zofunika kwa VCS kayeseleledwe.
6.5.1 Pre-synthesis (Funsani Funso)
Presynth_run.do
khalani mwakachetechete ACTELLIBNAME SmartFusion2
khalani mwakachetechete PROJECT_DIR "/sqa/users/me/VCS_Tests/Test_DFF"
ngati {[file zilipo presynth/_info]} {
echo "INFO: Silation library presynth ilipo kale"
} zina {
vlib presynth
}
vmap presynth presynth
vmap SmartFusion2 “/captures/lin/11_0_0_23_11prod/lib/ModelSim/precompiled/vlog/smartfusion2”
vlog -work presynth "${PROJECT_DIR}/component/work/SD1/SD1.v"
vlog "+ incdir+${PROJECT_DIR}/stimulus" -work presynth "${PROJECT_DIR}/stimulus/SD1_TB1.v"
vsim -L SmartFusion2 -L presynth -t 1fs presynth.SD1_TB1
onjezani mafunde /SD1_TB1/*
onjezani chipika -r /*
kuthamanga 1000ns
presynth_main.csh
#!/bin/csh -f
khalani PROJECT_DIR = "/sqa/users/Me/VCS_Tests/Test_DFF"
/cad_design/tools/vcs.dir/E-2011.03/bin/vlogan +v2k -work presynth “${PROJECT_DIR}/component/
ntchito/SD1/SD1.v”
/cad_design/tools/vcs.dir/E-2011.03/bin/vlogan +v2k “+incdir+${PROJECT_DIR}/stimulus” -ntchito
presynth “${PROJECT_DIR}/stimulus/SD1_TB1.v”
/cad_design/tools/vcs.dir/E-2011.03/bin/vcs -sim_res=1fs presynth.SD1_TB1 -l compile.log
./simv -l run.log
Synopsys_sim.setup
NTCHITO > ZOCHITA
SmartFusion2: /VCS/SmartFusion2
presynth: ./presynth
ZOCHITA: ./work
6.5.2 Kupanga pambuyo (Funsani Funso)
postsynth_run.do
khalani mwakachetechete ACTELLIBNAME SmartFusion2
khalani mwakachetechete PROJECT_DIR "/sqa/users/Me/VCS_Tests/Test_DFF"
ngati {[file zilipo postsynth/_info]} {
echo "INFO: Silation library postsynth ilipo kale"
} zina {
vlib postsynth
}
vmap postsynth postsynth
vmap SmartFusion2 “//idm/captures/pc/11_0_1_12_g4x/Designer/lib/ModelSim/precompiled/vlog/
SmartFusion2”
vlog -work postsynth "${PROJECT_DIR}/synthesis/SD1.v"
vlog "+ incdir+${PROJECT_DIR}/stimulus" -work postsynth "${PROJECT_DIR}/stimulus/SD1_TB1.v"
vsim -L SmartFusion2 -L postsynth -t 1fs postsynth.SD1_TB1
onjezani mafunde /SD1_TB1/*
onjezani chipika -r /*
kuthamanga 1000ns
chipika SD1_TB1/*
Potulukira
Postsynth_main.csh
#!/bin/csh -f
khalani PROJECT_DIR = "/sqa/users/Me/VCS_Tests/Test_DFF"
/cad_design/tools/vcs.dir/E-2011.03/bin/vlogan +v2k -work postsynth “${PROJECT_DIR}/synthesis/
SD1.v"
/cad_design/tools/vcs.dir/E-2011.03/bin/vlogan +v2k “+incdir+${PROJECT_DIR}/stimulus” -ntchito
postsynth "${PROJECT_DIR}/stimulus/SD1_TB1.v"
/cad_design/tools/vcs.dir/E-2011.03/bin/vcs -sim_res=1fs postsynth.SD1_TB1 -l compile.log
./simv -l run.log
Synopsys_sim.setup
NTCHITO > ZOCHITA
SmartFusion2: /VCS/SmartFusion2
postsynth: ./postsynth
ZOCHITA: ./work
6.5.3 Kupanga pambuyo (Funsani Funso)
postlayout_run.do
khalani mwakachetechete ACTELLIBNAME SmartFusion2
khazikitsa mwakachetechete PROJECT_DIR "E:/ModelSim_Work/Test_DFF"
ngati {[file ilipo ../designer/SD1/simulation/postlayout/_info]} {
tchulani "INFO: Library yoyeserera ../designer/SD1/simulation/postlayout ilipo kale"
} zina {
vlib ../designer/SD1/simulation/postlayout
}
vmap postlayout ../designer/SD1/simulation/postlayout
vmap SmartFusion2 “//idm/captures/pc/11_0_1_12_g4x/Designer/lib/ModelSim/precompiled/vlog/
SmartFusion2”
vlog -work postlayout "${PROJECT_DIR}/designer/SD1/SD1_ba.v"
vlog "+ incdir+${PROJECT_DIR}/stimulus" -chithunzi chantchito "${PROJECT_DIR}/stimulus/SD1_TB1.v"
vsim -L SmartFusion2 -L postlayout -t 1fs -sdfmax /SD1_0=${PROJECT_DIR}/designer/SD1/
SD1_ba.sdf postlayout.SD1_TB1
onjezani mafunde /SD1_TB1/*
onjezani chipika -r /*
kuthamanga 1000ns
Postlayout_main.csh
#!/bin/csh -f
khalani PROJECT_DIR = "/VCS_Test/Test_DFF"
/cad_design/tools/vcs.dir/E-2011.03/bin/vlogan +v2k -ndondomeko yantchito “${PROJECT_DIR}/
wopanga/SD1/SD1_ba.v”
/cad_design/tools/vcs.dir/E-2011.03/bin/vlogan +v2k “+incdir+${PROJECT_DIR}/stimulus” -ntchito
zolemba "${PROJECT_DIR}/stimulus/SD1_TB1.v"
/cad_design/tools/vcs.dir/E-2011.03/bin/vcs -sim_res=1fs postlayout.SD1_TB1 -sdf
max:SD1_TB1.SD1_0:${PROJECT_DIR}/designer/SD1/SD1_ba.sdf -l compile.log
./simv -l run.log
Synopsys_sim.setup
NTCHITO > ZOCHITA
SmartFusion2: /VCS/SmartFusion2
positi: ./postlayout
ZOCHITA: ./workVCS
6.6 Zochita zokha (Funsani Funso)
Kuthamanga kumatha kupangidwa pogwiritsa ntchito Perl script yotsatira file kutembenuza ModelSim run.do files kukhala script yogwirizana ndi VCS files, pangani zolembera zoyenera mkati mwa chikwatu cha Libero SoC, ndiyeno yambitsani zoyeserera.
Yendetsani script file pogwiritsa ntchito mawu otsatirawa.
perl vcs_parse.pl presynth_run.do postsynth_run.do postlayout_run.do
Vcs_parse_pl
#!/usr/bin/perl -w
######################################################## ###############################
#
#Kagwiritsidwe: perl vcs_parse.pl presynth_run.do postsynth_run.do postlayout_run.do
#
######################################################## ################################
wanga ($presynth, $postsynth, $postlayout) = @ARGV;
if(system(“mkdir VCS_Presynth”)) {sindikiza “mkdir yalephera:\n”;}
if(system(“mkdir VCS_Postsynth”)) {kusindikiza “mkdir analephera:\n”;}
if(system(“mkdir VCS_Postlayout”)) {print “mkdir yalephera:\n”;}
chdir(VCS_Presynth);
`cp ../$ARGV[0] .` ;
&parse_do($presynth,"presynth");
chdir (“../”);
chdir(VCS_Postsynth);
`cp ../$ARGV[1] .` ;
&parse_do($postsynth,"postsynth");
chdir (“../”);
chdir(VCS_Postlayout);
`cp ../$ARGV[2] .` ;
&parse_do($postlayout,"postlayout");
chdir (“../”);
phatikizani_chitani {
wanga $vlog = “/cad_design/tools/vcs.dir/E-2011.03/bin/vlogan +v2k” ;
wanga% LIB = ();
wanga $file = $_[0] ;
wanga $state = $_[1];
open(INFILE,”$file”) || kufa “Singatsegule File Chifukwa chingakhale:$!";
ngati ($state eq “presynth”)
{
open(OUT1,”>presynth_main.csh”) || kufa "Sindingathe kupanga Command File Chifukwa chingakhale:$!";
}
elsif ($state eq "postsynth")
{
open(OUT1,”>postsynth_main.csh”) || kufa "Sindingathe kupanga Command File Chifukwa chingakhale:$!";
}
elsif ($state eq "postlayout")
{
open(OUT1,”>postlayout_main.csh”) || kufa "Sindingathe kupanga Command File Chifukwa chingakhale:$!";
}
zina
{
sindikizani "Simulation State ikusowa \n" ;
}
open(OUT2,”>synopsys_sim.setup”) || kufa "Sindingathe kupanga Command File Chifukwa chingakhale:$!";
# .csh file
sindikizani OUT1 “#!/bin/csh -f\n\n\n” ;
#KHAZIKITSA FILE
sindikizani OUT2 “NTCHITO > ZOCHITIKA ZONSE\n” ;
sindikizani OUT2 “SmartFusion2 : /sqa/users/Aditya/VCS/SmartFusion2\n”;
pamene ($line = <INFILE>)
{
Kukonzekera kwa Synopsys VCS
ngati ($line =~ m/ika mwakachetechete PROJECT_DIR\s+\”(.*?)\”/)
{
sindikizani OUT1 "set PROJECT_DIR = \"$1\"\n\n\n" ;
}
elsif ( $line =~ m/vlog.*\.v\”/ )
{
ngati ($line =~ m/\s+(\w*?)\_LIB/)
{
#sindikizani “\$1 =$1 \n” ;
$ temp = “$1″.”_LIB”;
#print "Temp = $ temp \n" ;
$LIB{$temp}++;
}
chomp ($ mzere);
$mzere =~ s/^vlog/$vlog/ ;
$mzere =~ s/ //g;
sindikiza OUT1 “$line\n”;
}
elsif ( ($line =~ m/vsim.*presynth\.(.*)/) || ($line =~ m/vsim.*postsynth\.(.*)/) || ($line
=~ m/vsim.*postlayout\.(.*)/))
{
$TB = $1 ;
$TB =~ s///g;
chomp ($tb);
#print “TB Name : $tb \n”;
ngati ( $line =~ m/sdf(.*)\.sdf/)
{
chomp ($ mzere);
$ mzere = $ 1 ;
#print "LINE : $line \n" ;
ngati ($mzere =~ m/max/)
{
$ mzere =~ s/max \/// ;
$mzere =~ s/=/:/;
sindikizani OUT1 “\n\n/cad_design/tools/vcs.dir/E-2011.03/bin/vcs -sim_res=1fs postlayout.$tb -sdf
zazikulu:$tb.$line.sdf -l compile.log\n” ;
}
elsif ($line =~ m/min/)
{
$mzere =~ s/mphindi \/// ;
$mzere =~ s/=/:/;
sindikizani OUT1 “\n\n/cad_design/tools/vcs.dir/E-2011.03/bin/vcs -sim_res=1fs postlayout.$tb -sdf
min:$tb.$line.sdf -l compile.log\n” ;
}
elsif ($line =~ m/typ/)
{
$ mzere =~ s/typ \/// ;
$mzere =~ s/=/:/;
sindikizani OUT1 “\n\n/cad_design/tools/vcs.dir/E-2011.03/bin/vcs -sim_res=1fs postlayout.$tb -sdf
lembani:$tb.$line.sdf -l compile.log\n” ;
}
#-sdfmax /M3_FIC32_0=${PROJECT_DIR}/designer/M3_FIC32/M3_FIC32_ba.sdf — mtundu wa ModelSim SDF
#$sdf = “-sdf max:testbench.M3_FIC32_0:${PROJECT_DIR}/designer/M3_FIC32/M3_FIC32_ba.sdf”; - VCS
Mtundu wa SDF
}
}
}
sindikiza
OUT1 “\n\n”
;
if
($state eq “presynth”
)
{
sindikiza
OUT2 “presynth
: ./presynth\n”
;
sindikiza
OUT1 “/cad_design/tools/vcs.dir/E-2011.03/bin/vcs
-sim_res=1fs presynth.$tb -l
compile.log\n”
;
}
elsif
($state eq “postsynth”
)
{
sindikiza
OUT2 “postsynth
: ./postsynth\n”
;
sindikiza
OUT1 “/cad_design/tools/vcs.dir/E-2011.03/bin/vcs
-sim_res=1fs postsynth.$tb -l
compile.log\n”
;
}
elsif
($state eq "postlayout"
)
{
sindikiza OUT2 “postlayout : ./postlayout\n” ;
}
zina
{
sindikizani "Simulation State ikusowa \n" ;
}
foreach $i (makiyi %LIB)
{
#print "Kiyi : $i Mtengo : $LIB{$i} \n" ;
sindikiza OUT2 “$i : ./$i\n” ;
}
sindikizani OUT1 “\n\n” ;
sindikizani OUT1 “./simv -l run.log\n” ;
sindikizani OUT2 “KUSINTHA : ./work\n” ;
kutseka INFILE;
kutseka OUT1;
kutseka OUT2;
}
Mbiri Yowunikiranso (Kulowa kwa Microchip
Mbiri yokonzanso ikufotokoza zosintha zomwe zidakhazikitsidwa muzolemba. Zosintha
amandandalikidwa mwa kukonzedwanso, kuyambira ndi zofalitsidwa zamakono kwambiri.
| Kubwereza | Tsiku | Kufotokozera |
| A | 12/2023 | Zosintha zotsatirazi zasinthidwa mukusinthaku: • Zolemba zasinthidwa kukhala template ya Microchip. Kubwereza Koyamba. • Gawo losinthidwa 5. Siemens QuestaSim Setup/ModelSim Setup kuti aphatikizepo cholemba chatsopano chomwe chikufotokoza momwe zimakhudzira maonekedwe panthawi yoyerekezera ndi kukhathamiritsa. |
Thandizo la Microchip FPGA
Gulu lazinthu za Microchip FPGA limathandizira zogulitsa zake ndi ntchito zosiyanasiyana zothandizira, kuphatikiza Makasitomala, Customer Technical Support Center, a webmalo, ndi maofesi ogulitsa padziko lonse lapansi.
Makasitomala akulangizidwa kuti aziyendera zapaintaneti za Microchip asanakumane ndi chithandizo chifukwa ndizotheka kuti mafunso awo ayankhidwa kale.
Lumikizanani ndi Technical Support Center kudzera pa website pa www.microchip.com/support. Tchulani nambala ya Gawo la Chipangizo cha FPGA, sankhani gulu loyenera, ndikuyika mapangidwe files popanga chithandizo chaukadaulo.
Lumikizanani ndi Makasitomala kuti muthandizidwe ndi zinthu zomwe si zaukadaulo, monga mitengo yazinthu, kukweza kwazinthu, zambiri zosintha, mawonekedwe oyitanitsa, ndi chilolezo.
- Kuchokera ku North America, imbani 800.262.1060
- Kuchokera kudziko lonse lapansi, imbani 650.318.4460
- Fax, kuchokera kulikonse padziko lapansi, 650.318.8044
Zambiri za Microchip
The Microchip Webmalo
Microchip imapereka chithandizo cha intaneti kudzera pa athu website pa www.microchip.com/. Izi webtsamba limagwiritsidwa ntchito kupanga files ndi zambiri kupezeka mosavuta kwa makasitomala. Zina mwazinthu zomwe zilipo ndi izi:
- Thandizo lazinthu - Mapepala a deta ndi zolakwika, zolemba za ntchito ndi sampmapulogalamu, zida zamapangidwe, maupangiri a ogwiritsa ntchito ndi zikalata zothandizira pa Hardware, kutulutsa kwaposachedwa kwa mapulogalamu ndi mapulogalamu osungidwa zakale
- General Technical Support - Mafunso Ofunsidwa Kawirikawiri (FAQs), zopempha zothandizira luso, magulu okambirana pa intaneti, mndandanda wa mamembala a pulogalamu ya Microchip
- Business of Microchip - Zosankha katundu ndi maupangiri oyitanitsa, zofalitsa zaposachedwa za Microchip, mindandanda yamasemina ndi zochitika, mndandanda wamaofesi ogulitsa a Microchip, ogawa ndi oyimira mafakitale.
Ntchito Yodziwitsa Kusintha Kwazinthu
Ntchito yodziwitsa zakusintha kwazinthu za Microchip imathandizira makasitomala kuti azitha kudziwa zinthu za Microchip. Olembetsa adzalandira zidziwitso za imelo nthawi iliyonse pakakhala zosintha, zosintha, zosintha kapena zolakwika zokhudzana ndi banja linalake kapena chida chachitukuko.
Kuti mulembetse, pitani ku www.microchip.com/pcn ndikutsatira malangizo olembetsa.
Thandizo la Makasitomala
Ogwiritsa ntchito Microchip atha kulandira thandizo kudzera munjira zingapo:
- Wogawa kapena Woimira
- Local Sales Office
- Embedded Solutions Engineer (ESE)
- Othandizira ukadaulo
Makasitomala akuyenera kulumikizana ndi omwe amawagawa, oyimilira kapena ESE kuti awathandize. Maofesi ogulitsa am'deralo amapezekanso kuti athandize makasitomala. Mndandanda wamaofesi ogulitsa ndi malo uli m'chikalatachi.
Thandizo laukadaulo likupezeka kudzera mu webtsamba pa: www.microchip.com/support
Chitetezo cha Microchip Devices Code
Zindikirani tsatanetsatane wotsatira wa chitetezo cha code pazinthu za Microchip:
- Zogulitsa za Microchip zimakwaniritsa zomwe zili mu Microchip Data Sheet yawo.
- Microchip imakhulupirira kuti katundu wake ndi wotetezeka akagwiritsidwa ntchito m'njira yomwe akufuna, malinga ndi momwe amagwirira ntchito, komanso m'mikhalidwe yabwinobwino.
- Ma Microchip amawakonda ndikuteteza mwamphamvu ufulu wake wazinthu zamaluso. Kuyesa kuphwanya malamulo otetezedwa ndi zinthu za Microchip ndikoletsedwa ndipo zitha kuphwanya Digital Millennium Copyright Act.
- Ngakhale Microchip kapena wopanga semiconductor wina aliyense sangatsimikizire chitetezo cha code yake. Kutetezedwa kwa ma code sikutanthauza kuti tikutsimikizira kuti chinthucho ndi "chosasweka".
Chitetezo cha code chikusintha nthawi zonse. Microchip yadzipereka mosalekeza kuwongolera mawonekedwe achitetezo azinthu zathu.
Chidziwitso chazamalamulo
Bukuli ndi zambiri zomwe zili pano zitha kugwiritsidwa ntchito ndi zinthu za Microchip zokha, kuphatikiza kupanga, kuyesa, ndi kuphatikiza zinthu za Microchip ndi pulogalamu yanu. Kugwiritsa ntchito chidziwitsochi mwanjira ina iliyonse kumaphwanya mawuwa. Zambiri zokhudzana ndi kugwiritsa ntchito zida zimaperekedwa kuti zitheke ndipo zitha kulowedwa m'malo ndi zosintha. Ndi udindo wanu kuwonetsetsa kuti pulogalamu yanu ikugwirizana ndi zomwe mukufuna. Lumikizanani ndi ofesi yogulitsa za Microchip kwanuko kuti muthandizidwe zina kapena, pezani thandizo lina pa www.microchip.com/en-us/support/design-help/client-support-services.
ZIMENEZI AMAPEREKA NDI MICROCHIP "MONGA ILI". MICROCHIP SIIPEREKERA ZINTHU KAPENA ZIZINDIKIRO ZA MTIMA ULIWONSE KAYA KUTANTHAUZIRA KAPENA KUTANTHAWIRIKA, KULEMBEDWA KAPENA MWAMWAMBA, MALAMULO KAPENA ZINTHU ZINA, ZOKHUDZANA NDI CHIZINDIKIRO KUPHATIKIZAPO KOMA ZOSAKHALA PA CHENJEZO KILICHONSE, KUTENGA ZIPANGIZO, KUTENGA CHIZINDIKIRO, KUCHITIKA, NTCHITO, NTCHITO. PA CHOLINGA ENA, KAPENA ZINTHU ZOKHUDZA ZOKHUDZANA NDI MKHALIDWE WAKE, UKHALIDWE, KAPENA NTCHITO YAKE.
PAMENE MICROCHIP IDZAKHALA NDI NTCHITO PA CHIZINDIKIRO CHILICHONSE, CHAPADERA, CHILANGO, ZOCHITIKA, KAPENA ZOTSATIRA ZOTSATIRA, KUonongeka, mtengo, KAPENA NTCHITO ZONSE ZOMWE ZILI ZOKHUDZA CHIdziwitso KAPENA NTCHITO YAKE, KOMA CHIFUKWA CHIFUKWA CHOCHITIKA, ZOCHITIKA KAPENA ZOWONONGWA NDI ZOONERA. KUBWERA KWABWINO KWAMBIRI ZOLOLEZEDWA NDI MALAMULO, NDONDOMEKO YONSE YA MICROCHIP PA ZINSINSI ZONSE MU NJIRA ILIYONSE YOKHUDZANA NDI CHIdziwitso KAPENA KUKGWIRITSA NTCHITO CHOSAPYOTSA KUCHULUKA KWA ZOLIMBIKITSA, NGATI KULIPO, ZIMENE MULIPITSA CHIFUKWA CHIFUKWA CHIFUKWA CHIYANI.
Kugwiritsa ntchito zipangizo za Microchip pa chithandizo cha moyo ndi / kapena ntchito za chitetezo ndizoopsa kwa wogula, ndipo wogula akuvomera kuteteza, kubwezera ndi kusunga Microchip yopanda vuto lililonse ku zowonongeka, zodandaula, masuti, kapena ndalama zomwe zimachokera ku ntchito yotere. Palibe zilolezo zomwe zimaperekedwa, mobisa kapena mwanjira ina, pansi pa ufulu wazinthu zaukadaulo za Microchip pokhapokha zitanenedwa.
Zizindikiro
Dzina la Microchip ndi logo, logo ya Microchip, Adaptec, AVR, logo ya AVR, AVR Freaks, BesTime, BitCloud, CryptoMemory, CryptoRF, dsPIC, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXStylus MediaLB, megaAVR, Microsemi, Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, PolarFire, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SupercomFlash, , SyncServer, Tachyon, TimeSource, tinyAVR, UNI/O, Vectron, ndi XMEGA ndi zizindikiro zolembetsedwa za Microchip Technology Incorporated ku U.S.A. ndi mayiko ena.
AgileSwitch, APT, ClockWorks, The Embedded Control Solutions Company, EtherSynch, Flashtec, Hyper Speed Control, HyperLight Load, Libero, motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Waya, SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub, TimePictra, TimeProvider, TrueTime, ndi ZL ndi zizindikiro zolembetsedwa za Microchip Technology Incorporated ku USA.
Kuponderezedwa Kwachinsinsi, AKS, Analog-for-the-Digital Age, AnyCapacitor, AnyIn, AnyOut, Augmented Switching, BlueSky, BodyCom, Clockstudio, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEMAverage. , DAM, ECAN, Espresso T1S, EtherGREEN, GridTime, IdealBridge, In-Circuit Serial Programming, ICSP, INICnet, Intelligent Paralleling, IntelliMOS, Inter-Chip Connectivity, JitterBlocker, Knob-on-Display, KoD, maxCrypto, maxView, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net,
PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, RTAX, RTG4, SAMICE, Serial Quad I/O, simpleMAP, SimpliPHY, SmartBuffer, SmartHLS, SMART-IS, storClad, SQI, SuperSwitcher,
SuperSwitcher II, Switchtec, SynchroPHY, Kupirira Kwathunthu, Nthawi Yodalirika, TSHARC, USBCheck, VariSense, VectorBlox, VeriPHY, ViewSpan, WiperLock, XpressConnect, ndi ZENA ndi zizindikiro za Microchip Technology Incorporated
ku U.S.A. ndi mayiko ena.
SQTP ndi chizindikiro cha ntchito cha Microchip Technology Incorporated ku USA
Chizindikiro cha Adaptec, Frequency on Demand, Silicon Storage Technology, ndi Symmcom ndi zizindikilo zolembetsedwa za Microchip Technology Inc. m'maiko ena.
GestIC ndi chizindikiro cholembetsedwa cha Microchip Technology Germany II GmbH & Co. KG, kampani ya Microchip Technology Inc., m'maiko ena.
Zizindikiro zina zonse zomwe zatchulidwa pano ndi zamakampani awo.
© 2023, Microchip Technology Incorporated ndi mabungwe ake. Maumwini onse ndi otetezedwa.
ISBN: 978-1-6683-3694-6
Quality Management System
Kuti mudziwe zambiri za Microchip's Quality Management Systems, chonde pitani www.microchip.com/quality.
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| Ofesi Yakampani 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Othandizira ukadaulo: www.microchip.com/support Web Adilesi: www.microchip.com Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Austin, TX Tel: 512-257-3370 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Novi, MI Tel: 248-848-4000 Houston, TX Tel: 281-894-5983 Indianapolis Noblesville, PA Tel: 317-773-8323 Fax: 317-773-5453 Tel: 317-536-2380 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Tel: 951-273-7800 Raleigh, NC Tel: 919-844-7510 New York, NY Tel: 631-435-6000 San Jose, CA Tel: 408-735-9110 Tel: 408-436-4270 Canada - Toronto Tel: 905-695-1980 Fax: 905-695-2078 |
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© 2023 Microchip Technology Inc. ndi mabungwe ake
DS50003627A -
Zolemba / Zothandizira
 |
MICROCHIP Libero SoC Simulation Library Software [pdf] Buku Logwiritsa Ntchito DS50003627A, Libero SoC Simulation Library Software, SoC Simulation Library Software, Simulation Library Software, Library Software, mapulogalamu |
