MICROCHIP Libero SoC Simulation Library Software User Guide

Libero SoC Simulation
Raibhurari Setup Mirayiridzo

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1 Nhanganyaya

2 Libero SoC Kubatanidzwa

3 Aldec Setup yeActive-HDL uye Riviera-Pro (Bvunza Mubvunzo)

4 Cadence Incisive Setup (Bvunza Mubvunzo)

5 Cadence Xcelium Setup (Microchip Login)

6 Siemens QuestaSim Setup/ModelSim Setup (Bvunza Mubvunzo)

7 Synopsys VCS Setup (Bvunza Mubvunzo)

8 Yekudzokorora Nhoroondo (Microchip Login

9 Zvinyorwa / Zvishandiso

9.1 References

10 Related Posts

Nhanganyaya

(Bvunza Mubvunzo)

Chinangwa chegwaro iri kutsanangura maitiro ekumisikidza nharaunda yekunyepedzera uchishandisa Libero SoC purojekiti seyekuisa. Zvinyorwa izvi zvinoenderana nemaraibhurari akadhindwa akapihwa kuti ashandiswe neLibero SoC v11.9 uye nyowani software inoburitswa. Iwo maraibhurari akapihwa akagadzirirwa Verilog. Vashandisi veVHDL vanoda rezinesi rinobvumira musanganiswa-modhi simulation.
Iwo akaunganidzwa ekutevedzera raibhurari anowanikwa kune anotevera maturusi:

Aldec Active-HDL
Aldec Riviera-PRO
Cadence Incisive Enterprise uye Xcelium
Siemens QuestaSim
Synopsy VCS

Kukumbira raibhurari yeimwe simulator yakasiyana, bata Microchip Technical Support.

Libero SoC Kubatanidzwa

(Bvunza Mubvunzo)

Libero SoC inotsigira simulation uchishandisa ModelSim ME nekugadzira run.do file. Izvi file inoshandiswa neModelSim ME/ModelSim Pro ME kumisikidza uye kumhanyisa simulation. Kuti ushandise mamwe maturusi ekuenzanisa, unogona kugadzira iyo ModelSim ME/ModelSim Pro ME run.do uye gadzirisa Tcl script. file kushandisa mirairo inoenderana neyako simulator.
1.1 Libero SoC Tcl File Chizvarwa (Bvunza Mubvunzo)
Mushure mekugadzira uye kugadzira dhizaini muLibero SoC, tanga ModelSim ME/ModelSim Pro ME simulation pasi peese dhizaini zvikamu (presynth, postsynth, uye post-layout). Danho iri rinogadzira run.do file yeModelSim ME/ModelSim Pro ME yechikamu chimwe nechimwe chekugadzira.
Zvakakosha: Mushure mekutanga imwe neimwe simulation run, rename iyo auto-yakagadzirwa run.do file pasi peiyo simulation dhairekitori kudzivirira Libero SoC kubva pakunyora izvo file. For example, iyo files inogona kupihwa zita rekuti presynth_run.do, postsynth_run.do uye postlayout_run.do.

Aldec Setup yeActive-HDL uye Riviera-Pro (Bvunza Mubvunzo)

The run.do file inoshandiswa neModelSim ME/ModelSim Pro ME inogona kugadziridzwa uye kushandiswa kutevedzera uchishandisa Aldec simulators.
2.1 Environment Variable (Bvunza Mubvunzo)
Seta nharaunda yako inoshanduka kune rezinesi rako file nzvimbo:
LM_LICENSE_FILE: inofanira kusanganisira chinongedzo kune server rezinesi.
2.2 Dhaunirodha Raibhurari Yakaunganidzwa (Bvunza Mubvunzo)
Dhawunirodha maraibhurari eAldec Active-HDL uye iyo Aldec Riviera-PRO kubva kuMicrochip. website.
2.3 Kushandura run.do yeAldec simulation (Bvunza Mubvunzo)
The run.do files inogadzirwa neLibero SoC yekufananidza uchishandisa iyo Active-HDL uye Riviera-Pro chishandiso chinogona kushandiswa kufananidzira uchishandisa Active-HDL uye Riviera-Pro ine shanduko imwe chete. Tafura inotevera inoronga iyo Aldec-yakaenzana mirairo yekugadzirisa muModelSim run.do file.
Tafura 2-1. Aldec Equivalent Commands

ModelSim	Active-HDL
vlog	alog
vcom	acom
vlib	alib
vsim	asim
vmap	amap

Zvinotevera ndizvoample run.do inoenderana neAldec simulators.

Seta nzvimbo yedhairekitori rekushanda razvino.
set dsn

Seta zita reraibhurari rinoshanda, mepu nzvimbo yaro, uye wobva watora nzvimbo yeMicrochip FPGA mhuri
precompiled raibhurari (semuenzanisoample, SmartFusion2) pauri kumhanyisa dhizaini yako.
alib presynth
amap presynth presynth
amap SmartFusion2
Unganidza ese anodiwa HDL files inoshandiswa mukugadzira neraibhurari inodiwa.
alog -work presynth temp.v (yeVerilog)
alog -work presynth testbench.v
acom -work presynth temp.vhd (yeVhdl)
acom -work presynth testbench.vhd

Tevedzera magadzirirwo.
asim –L SmartFusion2 –L presynth –t 1ps presynth.testbench
kumhanya 10us

2.4 Nyaya Dzinozivikanwa (Bvunza Mubvunzo)
Ichi chikamu chinonyora nyaya dzinozivikanwa uye zvisingakwanisi.

Maraibhurari akaunganidzwa achishandisa Riviera-PRO ipuratifomu yakananga (kureva kuti 64-bit maraibhurari haagone kumhanyiswa papuratifomu makumi matatu neshanu uye zvichipesana).
Pamagadzirirwo ane SEDES/MDDR/FDDR, shandisa inotevera sarudzo mune yako run.do files pavanenge vachimhanyisa simulations mushure mekunyora magadzirirwo avo:
- Active-HDL: asim -o2
- Riviera-PRO: asim -O2 (ye presynth uye post-rongedzo simulations) uye asim -O5 (yemashure-magadzirirwo ekufungidzira)
Iyo Aldec setup yeActive-HDL uye Riviera-Pro ine anotevera akamirira maSAR. Kuti uwane rumwe ruzivo, bata Microchip Technical Support.

SAR 49908 - Active-HDL: VHDL Kanganiso yeMath block simulations
SAR 50627 - Riviera-PRO 2013.02: Kukanganisa kwekutevedzera kweSERDES magadzirirwo

SAR 50461 - Riviera-PRO: asim -O2/-O5 sarudzo mukuenzanisa

Cadence Incisive Setup (Bvunza Mubvunzo)

Iwe unofanirwa kugadzira script file yakafanana neModelSim ME/ModelSim Pro ME run.do kumhanyisa iyo
Cadence Incisive simulator. Tevedza aya matanho uye gadzira script file yeNCSim kana shandisa script file
yakapihwa kushandura iyo ModelSim ME/ModelSim Pro ME run.do files mukugadzirisa files
inodiwa kumhanyisa masimulation uchishandisa NCSim.
Zvakakosha: Cadence yamira kuburitsa zvinyorwa zvitsva zveIncisive Enterprise
simulator ndokutanga kutsigira Xcelium simulator.

3.1 Zvakasiyana-siyana (Bvunza Mubvunzo)
Kuti umhanye iyo Cadence Incisive simulator, gadzirisa zvinotevera nharaunda zvinosiyana:

LM_LICENSE_FILE: inofanira kusanganisira chinongedzo kune rezinesi file.
cds_root: inofanirwa kunongedza kune iyo imba dhairekitori nzvimbo yeCadence Incisive Installation.
PATH: inofanirwa kunongedza kunzvimbo yebhini pasi pematurusi dhairekitori akanongedza ne cds_root kureva kuti,
$cds_root/tools/bin/64bit (ye64-bit muchina uye $cds_root/tools/bin yemuchina we32-bit).
Pane nzira nhatu dzekumisikidza nharaunda yekufananidza kana paine chinja pakati pe64-bit uye 32-bit masisitimu anoshanda:

Nyaya 1: PATH Variable
Mhanya unotevera kuraira:
set nzira = (install_dir/zvishandiso/bin/64bit $nzira) ye64bit michina uye
set nzira = (install_dir/zvishandiso/bin $nzira) ye32bit michina
Nyaya yechipiri: Kushandisa iyo -2bit Command-line Option
Mune yekuraira-mutsara tsanangura -64bit sarudzo kuitira kuti invoke iyo 64bit inoitiswa.
Case 3: Kuseta iyo INCA_64BIT kana CDS_AUTO_64BIT Environment Variable
Iyo INCA_64BIT shanduko inotorwa se boolean. Iwe unogona kuseta iyi shanduko kune chero kukosha kana kune null tambo.
setenv INCA_64BIT

Mamwe maturusi eCadence, akadai seIC maturusi, anoshandisawo CDS_AUTO_64BIT nharaunda inoshanduka kudzora kusarudzwa kwe32-bit kana 64-bit zvinotemerwa. Tafura inotevera inoratidza kuti ungaseta sei CDS_AUTO_64BIT kusiyanisa kuti umhanye maIncisive maturusi uye maturusi eIC mumamodhi ese.
Tafura 3-1. CDS_AUTO_64BIT Variables

CDS_AUTO_64BIT Variable	Incisive Tools	IC Zvishandiso
setenv CDS_AUTO_64BIT ALL	64 zvishoma	64 zvishoma
setenv CDS_AUTO_64BIT HAPANA	32 zvishoma	32 zvishoma
setenv CDS_AUTO_64BIT EXCLUDE:ic_binary	64 zvishoma	32 zvishoma
setenv CDS_AUTO_64BIT EXCLUDE:INCA	32 zvishoma	64 zvishoma

Zvakakosha: Ese maturusi eIncisive anofanirwa kumhanyiswa mune angave 32-bit modhi kana 64-bit modhi, usashandise EXCLUDE kusasanganisa chimwe chinoitwa, sezvirikutevera: setenv CDS_AUTO_64BIT EXCLUDE:ncelab
Kana iwe ukaseta CDS_AUTO_64BIT chinja kuti usasanganise maIncisive maturusi (setenv CDS_AUTO_64BIT EXCLUDE:INCA), ese maIncisive maturusi anomhanya mu32-bit modhi. Nekudaro, iyo -64bit yekuraira-mutsara sarudzo inodarika iyo nharaunda shanduko.
Iyo inotevera configuration files inokubatsira kubata data rako uye kutonga mashandiro ezvishandiso zvekunyepedzera uye zvishandiso:

Mepu yeraibhurari file (cds.lib)—Inotsanangura zita rine musoro renzvimbo yedhizaini yako.
Maraibhurari uye anoabatanidza nemazita edhairekitori mazita.
Variables file (hdl.var)—Inotsanangura zvakasiyana-siyana zvinokanganisa maitiro ekufananidza maturusi uye zvinoshandiswa.

3.2 Dhaunirodha Raibhurari Yakaunganidzwa (Bvunza Mubvunzo)
Dhawunirodha maraibhurari eCadence Incisive kubva kuMicrosemi's website.
3.3 Kugadzira iyo NCSim Script File (Bvunza Mubvunzo)
Mushure mekugadzira kopi ye run.do files, ita matanho aya kumhanyisa simulation yako uchishandisa NCSim:

Gadzira a cds.lib file iyo inotsanangura maraibhurari anosvikika nenzvimbo yawo. The file ine zvirevo zvinomepu mazita eraibhurari ane musoro kune yavo chaiyo dhairekitori nzira. For example, kana uri kumhanyisa presynth simulation, iyo cds.lib file inonyorwa sezvinoratidzwa mucodeblock inotevera.
TSANANGURA presynth ./presynth
DEFINE COREAHBLITE_LIB ./COREAHBLITE_LIB
TSANANGURA smartfusion2

Gadzira a hdl.var file, imwe sarudzo inogadziriswa file iyo ine zvigadziriso zvinosiyana, izvo zvinotarisa kuti yako dhizaini nharaunda inogadziriswa sei. The rinotevera chinja files inosanganisirwa:
-Magetsi anoshandiswa kutsanangura raibhurari yebasa uko mugadziri anochengetera zvinhu zvakaunganidzwa uye imwe data inotorwa.
-KuVerilog, zvakasiyana (LIB_MAP, VIEW_MAP, BASA) ayo anoshandiswa kutsanangura maraibhurari uye views kutsvaga kana mutsananguri agadzirisa zviitiko.
-Magetsi anotendera iwe kutsanangura compiler, elaborator, uye simulator yekuraira-mutsara sarudzo uye nharo.
Kana iri presynth simulation exampinoratidzwa pamusoro, toti tine maRTL matatu files: av, bv, uye testbench.v, inoda kuunganidzwa kuita presynth, COREAHBLITE_LIB, uye presynth maraibhurari zvichiteerana. The HDl.var file inogona kunyorwa sezvinoratidzwa mucodeblock inotevera.
TSANANGURA BASA presynth
DEFINE PROJECT_DIR files>
TSANANGURA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/av => presynth )
TSANANGURA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/bv => COREAHBLITE_LIB)
TSANANGURA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/testbench.v => presynth )
TSANANGURA LIB_MAP ( $LIB_MAP, + => presynth)
Gadzira dhizaini files kushandisa ncvlog sarudzo.
ncvlog +incdir+ -cdslib ./cds.lib -hdlvar ./hdl.var -logfile
ncvlog.log -update -linedebug av bv testbench.v

Rongedza dhizaini uchishandisa ncelab. Iyo elaborator inovaka dhizaini yedhizaini yakavakirwa pane instantiation uye gadziriso ruzivo mudhizaini, inomisikidza chiratidzo chekubatanidza, uye inoverengera kukosha kwekutanga kwezvinhu zvese mudhizaini. Iyo yakakwenenzverwa dhizaini dhizaini inochengetwa mune yekufananidza snapshot, inova inomiririra yedhizaini yako iyo simulator inoshandisa kumhanyisa simulation.
ncelab -Mharidzo -cdslib ./cds.lib -hdlvar ./hdl.var -logfile ncelab.log -errormax 15 -
kuwana +rwc -status worklib. :module
Elaboration Panguva yePost-layout simulation
Kana iri post-layout simulations, kutanga SDF file inoda kuunganidzwa isati yatsanangurwa uchishandisa iyo ncsdfc command.
ncdfcfilezita>.sdf -outputfilezita>.sdf.X
Panguva yekutsanangudza shandisa yakaunganidzwa SDF inobuda ne -autosdf sarudzo sezvakaratidzwa mune inotevera codeblock.
ncelab -autosdf -Mharidzo -cdslib ./cds.lib -hdlvar ./hdl.var -logfile ncelab.log -errormax
15 -access +rwc -status worklib. :module -sdf_cmd_file ./
sdf_cmd_file
Iyo sdf_cmd_file inofanira kuva sezvinoratidzwa mucodeblock inotevera.
COMPILED_SDF_FILE =“ file>”
Tevedzera uchishandisa ncsim. Mushure mekutsanangura mufananidzo wekufananidza unogadzirwa, unotakurwa nencsim yekufananidza. Iwe unogona kumhanya mubatch mode kana GUI modhi.
ncsim -Mharidzo -batch/-gui -cdslib ./cds.lib -hdlvar ./hdl.var -logfile ncsim.log -
errormax 15 -status worklib. :module

Zvakakosha: Ese matanho matatu ari pamusoro ekunyora, kutsanangudza, uye kuenzanisa anogona kuiswa mugoko script file uye yakatorwa kubva kucommand-line. Panzvimbo pekushandisa matanho matatu aya, dhizaini inogona kutevedzerwa munhanho imwe uchishandisa ncverilog kana irun sarudzo sezvakaratidzwa mune inotevera codeblock.
ncverilog +incdir+ -cdslib ./cds.lib -hdlvar ./hdl.var
files inoshandiswa mukugadzira>
irun +incdir+ -cdslib ./cds.lib -hdlvar ./hdl.var files
inoshandiswa mukugadzira>

3.3.1 Nyaya Dzinozivikanwa (Bvunza Mubvunzo)
Testbench Workaround
Uchishandisa chirevo chinotevera kutsanangura frequency yewachi mu testbench inogadzirwa nemushandisi, kana iyo default testbench inogadzirwa neLibero SoC haishande neNCSim.
nguva dzose @(SYSCLK)
#(SYSCLK_PERIOD / 2.0) SYSCLK <= !SYSCLK;
Shandura sezvinotevera kuti uite simulation:
nguva dzose #(SYSCLK_PERIOD / 2.0) SYSCLK = ~SYSCLK;
Zvakakosha: Yakaunganidzwa maraibhurari eNCSim ipuratifomu chaiyo (kureva 64 bit maraibhurari haaenderane ne32 bit chikuva uye zvinopesana).
Postsynth nePost-layout Simulations Uchishandisa MSS neSERDES Paunenge uchimhanyisa postsynth simulations yezvigadziriso zvine MSS block kana iyo post-layout simulations yezvigadziriso uchishandisa SERDES, iyo BFM simulation haishande kana iyo -libmap sarudzo iri.
hazvina kutaurwa panguva yekuongorora. Izvi zvinodaro nekuti panguva yekutsanangudza, MSS inogadziriswa kubva kuraibhurari yebasa (nekuda kweiyo default kusunga uye worklib iri postsynth/post-layout) uko ingori Basa Rakagadziriswa.
Iyo ncelab command inofanirwa kunyorwa sezvakaratidzwa mune inotevera kodhi kodhi kugadzirisa iyo MSS
vhara kubva kuSmartFusion2 precompiled raibhurari.

ncelab -libmap lib.map -libverbose -Message -access +rwc cfg1
uye lib.map file inofanira kuva sezvinotevera:
config cfg1;
design ;
default liblist smartfusion2 ;
endconfig
Izvi zvinogadzirisa chero sero muraibhurari yeSmartFusion2 usati watarisa muraibhurari yebasa kureva postsynth/ post-layout.
Iyo -libmap sarudzo inogona kushandiswa nekusarudzika panguva yekutsanangudza kune yega simulation (presynth, postsynth, uye post-layout). Izvi zvinodzivirira nyaya dzekunyepedzera dzinokonzerwa nekuda kwekugadziriswa kwezviitiko kubva kumaraibhurari.
ncelab: *F, INTERR: KUSIYANA KWEMUKATI
Iyi ncelab chishandiso kunze ndeye caveat yezvigadziriso zvine FDDR muSmartFusion 2 uye IGLOO 2 panguva yepostsynth uye post-layout simulations uchishandisa -libmap sarudzo.
Zvakakosha: Nyaya iyi yakashumwa kuCadence support team (SAR 52113).

3.4 Sampuye Tcl uye Shell Script Files (Bvunza Mubvunzo)
Zvinotevera files ndiwo magadzirirwo files inodiwa kumisikidza dhizaini uye shell script file yekumhanyisa NCSim mirairo.
Cds.lib
NE smartfusion2 /scratch/krydor/tmpspace/users/me/nc-vlog64/SmartFusion2
DEFINE COREAHBLITE_LIB ./COREAHBLITE_LIB
TSANANGURA presynth ./presynth

Hdl.var
TSANANGURA BASA presynth
DEFINE PROJECT_DIR /scratch/krydor/tmpspace/sqausers/me/3rd_party_simulators/Cadence/IGLOO2/
ENVM/M2GL050/envm_fic1_ser1_v/eNVM_fab_master
TSANANGURA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/core/coreahblite_addrdec.v => COREAHBLITE_LIB )
TSANANGURA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/core/coreahblite_defaultslavesm.v => COREAHBLITE_LIB )
TSANANGURA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/core/coreahblite_masterstagev => COREAHBLITE_LIB )
TSANANGURA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/core/coreahblite_slavearbiter.v => COREAHBLITE_LIB )
TSANANGURA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/core/coreahblite_slavestagev => COREAHBLITE_LIB )
TSANANGURA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/core/coreahblite_matrix2x16.v => COREAHBLITE_LIB )
TSANANGURA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/core/coreahblite.v => COREAHBLITE_LIB )
TSANANGURA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB/CCC_0/SB_CCC_0_FCCC.v =>
presynth)
TSANANGURA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreConfigMaster/
2.0.101/rtl/vlog/core/coreconfigmaster.v => presynth )
TSANANGURA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreConfigP/4.0.100/rtl/
vlog/core/coreconfigp.v => presynth )
TSANANGURA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreResetP/5.0.103/rtl/
vlog/core/coresetp_pcie_hotreset.v => presynth )
TSANANGURA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreResetP/5.0.103/rtl/
vlog/core/coresetp.v => presynth )
TSANANGURA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB/FABOSC_0/SB_FABOSC_0_OSC.v =>
presynth)
TSANANGURA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB_HPMS/SB_HPMS.v => presynth )
TSANANGURA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB/SB.v => presynth )
TSANANGURA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB_top/SERDES_IF_0/
SB_top_SERDES_IF_0_SERDES_IF.v => presynth )
TSANANGURA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB_top/SB_top.v => presynth)
TSANANGURA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB_top/testbench.v => presynth)
TSANANGURA LIB_MAP ( $LIB_MAP, + => presynth)
Commands.csh
ncvlog +incdir+../../component/work/SB_top -cdslib ./cds.lib -hdlvar ./hdl.var -logfile
ncvlog.log -errormax 15 -update -linedebug
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite_addrdec.v
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/
coreahblite_defaultslavesm.v
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite_masterstagev
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite_slavearbiter.v
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite_slavestagev
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite_matrix2x16.v
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite.v
../../component/work/SB/CCC_0/SB_CCC_0_FCCC.v
../../component/Actel/DirectCore/CoreConfigMaster/2.0.101/rtl/vlog/core/coreconfigmaster.v
../../component/Actel/DirectCore/CoreConfigP/4.0.100/rtl/vlog/core/coreconfigp.v
../../component/Actel/DirectCore/CoreResetP/5.0.103/rtl/vlog/core/coreresetp_pcie_hotreset.v
../../component/Actel/DirectCore/CoreResetP/5.0.103/rtl/vlog/core/coreresetp.v
../../component/work/SB/FABOSC_0/SB_FABOSC_0_OSC.v ../../component/work/SB_HPMS/SB_HPMS.v
../../component/work/SB/SB.v ../../component/work/SB_top/SERDES_IF_0/
SB_top_SERDES_IF_0_SERDES_IF.v
../../component/work/SB_top/SB_top.v ../../component/work/SB_top/testbench.v
ncelab -Message -cdslib ./cds.lib -hdlvar ./hdl.var
-work presynth -logfile ncelab.log -errormax 15 -access +rwc -status presynth.testbench:module
ncsim -Message -batch -cdslib ./cds.lib -hdlvar ./
hdl.var -logfile ncsim.log -errormax 15 -status presynth.testbench:module

3.5 otomatiki (Bvunza Mubvunzo)
Chinyorwa chinotevera file inoshandura iyo ModelSim run.do files mune configuration files inodiwa kumhanyisa simulation uchishandisa NCSim.
Script File Usage
perl cadence_parser.pl presynth_run.do postsynth_run.do
postlayout_run.do Microsemi_Family
Nzvimbo_ye_Cadence_Precompiled_libraries

Cadence_parser.pl
#!/usr/bin/perl -w

###################################################### #############################################
###################
#Kushandiswa: perl questa_parser.pl presynth_run.do postsynth_run.do postlayout_run.do
Microsemi_Family Precompiled_Libraries_location#

###################################################### #############################################
###################
shandisa POSIX;
shandisa zvakasimba;
yangu ($presynth, $postsynth, $postlayout, $family, $lib_location) = @ARGV;
&questa_parser($presynth, $family, $lib_location);
&questa_parser($postsynth, $family, $lib_location);
&questa_parser($postlayout, $family, $lib_location);
sub questa_parser {
my $ModelSim_run_do = $_[0];
my $actel_family = $_[1];
my $lib_location = $_[2];
yangu $state;
kana (-e "$ModelSim_run_do")
{
vhura (INFILE,”$ModelSim_run_do”);
yangu @ModelSim_run_do =FILE>;
yangu $line;
kana ( $ModelSim_run_do =~ m/(presynth)/)
{
`mkdir QUESTA_PRESYNTH`;
vhura (OUTFILE,”>QUESTA_PRESYNTH/presynth_questa.do”);
$ state = $1;
} elsif ( $ModelSim_run_do =~ m/(postsynth)/)
{
`mkdir QUESTA_POSTSYNTH`;
vhura (OUTFILE,”>QUESTA_POSTSYNTH/postsynth_questa.do”);
$ state = $1;
} elsif ( $ModelSim_run_do =~ m/(postlayout)/ )
{
`mkdir QUESTA_POSTLAYOUT`;
vhura (OUTFILE,”>QUESTA_POSTLAYOUT/postlayout_questa.do”);
$ state = $1;
zvimwe
{
dhinda “Zvisina kururama zvinopihwa kune file\n";
dhinda “#Kushandiswa: perl questa_parser.pl presynth_run.do postsynth_run.do postlayout_run.do
\"Libraries_nzvimbo\"\n";
}
foreach $line (@ModelSim_run_do)
{
#General Operations
$line =~ s/..\/designer.*simulation\///g;
$line =~ s/$state/$state\_questa/g;
#print OUTFILE "$line \n";
kana ($line =~ m/vmap\s+.*($actel_family)/)
{
pirinda OUTFILE "vmap $actel_family \"$lib_location\"\n";
} elsif ($line =~ m/vmap\s+(.*._LIB)/)
{
$line =~ s/..\/component/..\/..\/component/g;
pirinda OUTFILE "$line \n";
} elsif ($line =~ m/vsim/)
{
$ mutsetse =~ s/vsim/vsim -novopt/g;
pirinda OUTFILE "$line \n";
zvimwe
{
pirinda OUTFILE "$line \n";
}
}
kuvhara (INFILE);
kuvhara (OUTFILE);
} zvimwe {
dhinda "$ModelSim_run_do haipo. Rerun simulation zvakare \n";
}
}

Cadence Xcelium Setup (Microchip Login)

Iwe unofanirwa kugadzira script file yakafanana neModelSim ME/ModelSim Pro ME run.do kumhanyisa Cadence Xcelium simulator. Tevedza aya matanho uye gadzira script file ye Xcelium kana shandisa script file yakapihwa kushandura iyo ModelSim ME/ModelSim Pro ME run.do files mukugadzirisa files inodiwa kumhanyisa simulation uchishandisa Xcelium.
4.1 Zvakasiyana-siyana (Bvunza Mubvunzo)
Kuti umhanye iyo Cadence Xcelium, gadzirisa zvinotevera nharaunda zvinosiyana:

LM_LICENSE_FILE: inofanira kusanganisira chinongedzo kune rezinesi file.
cds_root: inofanirwa kunongedza kune iyo imba dhairekitori nzvimbo yeCadence Incisive Installation.
PATH: inofanirwa kunongedza kunzvimbo yebhini pasi pematurusi dhairekitori akanongedza ne cds_root (kureva
$cds_root/tools/bin/64bit (ye64 bit machine uye $cds_root/tools/bin for a 32 bit
muchina).

Pane nzira nhatu dzekumisikidza nharaunda yekufananidza kana paine chinja pakati pe64-bit uye 32-bit masisitimu anoshanda:
Nyaya 1: PATH Variable
set nzira = (install_dir/zvishandiso/bin/64bit $nzira) ye64bit michina uye
set nzira = (install_dir/zvishandiso/bin $nzira) ye32bit michina
Nyaya yechipiri: Kushandisa iyo -2bit Command-line Option
Mune yekuraira-mutsara tsanangura -64bit sarudzo kuitira kuti invoke iyo 64-bit inoitiswa.
Case 3: Kuseta iyo INCA_64BIT kana CDS_AUTO_64BIT Environment Variable
Iyo INCA_64BIT shanduko inotorwa se boolean. Iwe unogona kuseta iyi shanduko kune chero kukosha kana kune isina chinhu
tambo.
setenv INCA_64BIT

Chinokosha: The INCA_64BIT nharaunda inosiyana haikanganisi mamwe maCadence maturusi, akadai seIC maturusi. Nekudaro, kune maIncisive maturusi, iyo INCA_64BIT shanduko inodarika marongero eCDS_AUTO_64BIT nharaunda inosiyana. Kana iyo INCA_64BIT nharaunda inoshanduka iri et, ese maIncisive maturusi anomhanya mu64-bit mode.
setenv CDS_AUTO_64BIT INCLUDE:INCA
Chinokosha: The tambo INCA inofanirwa kunge iri mumusoro. Zvese zvinoitiswa zvinofanirwa kumhanyiswa mune ingave 2-bit modhi kana mu 64-bit modhi, usaise shanduko kuti ibatanidze imwe inogoneka, sezvinotevera:
setenv CDS_AUTO_64BIT INCLUDE:ncelab
Mamwe maturusi eCadence, akadai seIC maturusi, anoshandisawo CDS_AUTO_64BIT nharaunda inoshanduka kudzora kusarudzwa kwe32-bit kana 64-bit zvinotemerwa. Tafura inotevera inoratidza kuti ungaseta sei CDS_AUTO_64BIT kusiyanisa kuti umhanye maIncisive maturusi uye maturusi eIC mumamodhi ese.

Tafura 4-1. CDS_AUTO_64BIT Variables

CDS_AUTO_64BIT Variable	Incisive Tools	IC Zvishandiso
setenv CDS_AUTO_64BIT ALL	64-bit	64-bit
setenv CDS_AUTO_64BIT HAPANA	32-bit	32-bit
setenv CDS_AUTO_64BIT KUSUNGAMIRIRA:ic_binary	64-bit	32-bit
setenv CDS_AUTO_64BIT EXCLUDE:INCA	32-bit	64-bit

Zvakakosha: Ese maturusi eIncisive anofanirwa kumhanyiswa mune angave 32-bit modhi kana mu64-bit modhi, usashandise EXCLUDE kusasanganisa chimwe chinoitwa, sezvinotevera:
setenv CDS_AUTO_64BIT EXCLUDE:ncelab
Kana iwe ukaseta iyo CDS_AUTO_64BIT shanduko yekusabvisa iyo Incisive maturusi (setenv
CDS_AUTO_64BIT EXCLUDE:INCA), ese maIncisive maturusi anomhanya mu32-bit mode. Zvisinei, the
-64bit yekuraira-mutsara sarudzo inodarika iyo nharaunda shanduko.
Iyo inotevera configuration files inokubatsira kubata data rako uye kutonga mashandiro ezvishandiso zvekunyepedzera uye zvishandiso:

Mepu yeraibhurari file (cds.lib) inotsanangura zita rine musoro renzvimbo yedhizaini yako.
Maraibhurari uye anoabatanidza nemazita edhairekitori mazita.
Variables file (hdl.var) inotsanangura zvakasiyana-siyana zvinokanganisa maitiro ekufananidza maturusi uye zvinoshandiswa.

4.2 Dhaunirodha Raibhurari Yakaunganidzwa (Bvunza Mubvunzo)
Dhawunirodha maraibhurari eCadence Xcelium kubva kuMicrosemi's website.
4.3 Kugadzira chinyorwa cheXcelium file (Bvunza Mubvunzo)
Mushure mekugadzira kopi ye run.do files, ita nhanho dzinotevera kumhanyisa simulation yako uchishandisa Xcelium script file.

Gadzira a cds.lib file iyo inotsanangura kuti mabhuku api anowanikwa uye kuti ari kupi.
The file ine zvirevo zvinomepu mazita eraibhurari ane musoro kune yavo chaiyo dhairekitori nzira. For example, kana uri kumhanyisa presynth simulation, iyo cds.lib file inogona kunyorwa sezvinoratidzwa mucodeblock inotevera.
TSANANGURA presynth ./presynth
DEFINE COREAHBLITE_LIB ./COREAHBLITE_LIB
TSANANGURA smartfusion2
Gadzira a hdl.var file inova sarudzo yesarudzo file iyo ine zvigadziriso zvinosiyana, izvo zvinotarisa kuti yako dhizaini nharaunda inogadziriswa sei. Izvi zvinosanganisira:
-Magetsi anoshandiswa kutsanangura raibhurari yebasa uko mugadziri anochengetera zvinhu zvakaunganidzwa uye imwe data inotorwa.
-KuVerilog, zvakasiyana (LIB_MAP, VIEW_MAP, BASA) ayo anoshandiswa kutsanangura maraibhurari uye views kutsvaga kana mutsananguri agadzirisa zviitiko.
-Magetsi anotendera iwe kutsanangura compiler, elaborator, uye simulator yekuraira-mutsara sarudzo uye nharo.
Kana iri presynth simulation exampyakaratidzwa pamusoro, toti tine 3 RTL files av, bv, uye testbench.v, inoda kuunganidzwa kuita presynth, COREAHBLITE_LIB, uye presynth maraibhurari zvichiteerana. The HDl.var file inogona kunyorwa sezvinoratidzwa mucodeblock inotevera.
TSANANGURA BASA presynth
DEFINE PROJECT_DIR files>
TSANANGURA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/av => presynth )
TSANANGURA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/bv => COREAHBLITE_LIB)
TSANANGURA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/testbench.v => presynth )
TSANANGURA LIB_MAP ( $LIB_MAP, + => presynth)

Gadzira dhizaini files kushandisa ncvlog sarudzo.
xmvlog +incdir+ -cdslib ./cds.lib -hdlvar ./hdl.var -logfile
ncvlog.log -update -linedebug av bv testbench.v
Rongedza dhizaini uchishandisa ncelab. Iyo elaborator inovaka dhizaini yedhizaini yakavakirwa pane instantiation uye gadziriso ruzivo mudhizaini, inomisikidza chiratidzo chekubatanidza, uye inoverengera kukosha kwekutanga kwezvinhu zvese mudhizaini. Iyo yakakwenenzverwa dhizaini dhizaini inochengetwa mune yekufananidza snapshot, inova inomiririra yedhizaini yako iyo simulator inoshandisa kumhanyisa simulation.
Xcelium -Mharidzo -cdslib ./cds.lib -hdlvar ./hdl.var -logfile ncelab.log -errormax 15 -
kuwana +rwc -status worklib. :module
Elaboration Panguva yePost-layout simulation
Kana iri post-layout simulations, kutanga SDF file inoda kuunganidzwa isati yatsanangurwa uchishandisa iyo ncsdfc command.
Xceliumfilezita>.sdf -outputfilezita>.sdf.X
Panguva yekutsanangudza shandisa yakaunganidzwa SDF inobuda ne -autosdf sarudzo sezvakaratidzwa mune inotevera codeblock.
xmelab -autosdf -Mharidzo -cdslib ./cds.lib -hdlvar ./hdl.var -logfile ncelab.log -errormax
15 -access +rwc -status worklib. :module -sdf_cmd_file ./
sdf_cmd_file
Iyo sdf_cmd_file inofanira kuva sezvinoratidzwa mucodeblock inotevera.
COMPILED_SDF_FILE =“ file>”
Tevedzera uchishandisa Xcelium. Mushure mekutsanangudza mufananidzo wekufananidza unogadzirwa uyo unotakurwa neXcelium yekufananidza. Izvi zvinogona kumhanya mubatch modhi kana GUI modhi.
xmsim -Mharidzo -batch/-gui -cdslib ./cds.lib -hdlvar ./hdl.var -logfile xmsim.log -
errormax 15 -status worklib. :module
Cadence Xcelium Setup
Zvakakosha: Zvose matanho matatu ari pamusoro ekunyora, kutsanangura uye kutevedzera anogona kuiswa mugoko script file uye yakatorwa kubva kucommand-line. Panzvimbo pekushandisa aya matanho matatu, dhizaini inogona kutevedzerwa munhanho imwe uchishandisa ncverilog kana xrun sarudzo sezvakaratidzwa mune inotevera codeblock.
xmverilog +incdir+ -cdslib ./cds.lib -hdlvar ./hdl.var
files inoshandiswa mukugadzira>
xrun +incdir+ -cdslib ./cds.lib -hdlvar ./hdl.var files
inoshandiswa mukugadzira>

4.3.1 Nyaya Dzinozivikanwa (Bvunza Mubvunzo)
Testbench Workaround
Kushandisa chirevo chinotevera kutsanangura frequency yewachi mu testbench inogadzirwa nemushandisi kana iyo default testbench inogadzirwa neLibero SoC haishande neXcelium.
nguva dzose @(SYSCLK)
#(SYSCLK_PERIOD / 2.0) SYSCLK <= !SYSCLK;
Shandura sezvinotevera kuti uite simulation:
nguva dzose #(SYSCLK_PERIOD / 2.0) SYSCLK = ~SYSCLK;

Zvakakosha: Maraibhurari akaunganidzwa eXcelium ane chikuva chaiwo (kureva 64 bit maraibhurari haaenderani ne32 bit chikuva uye zvichipesana).
Postsynth uye Post-layout Simulations uchishandisa MSS uye SERDES
Paunenge uchimhanyisa postsynth madhizaini ane MSS block, kana post-layout simulations yezvigadziriso uchishandisa SERDES, iyo BFM simulations haishande kana -libmap sarudzo isina kutaurwa panguva yekutsanangurwa. Izvi zvinodaro nekuti panguva yekutsanangudza, MSS inogadziriswa kubva kuraibhurari yebasa (nekuda kweiyo default kusunga uye worklib iri postsynth/post-layout) uko ingori Basa Rakagadziriswa.
Iyo ncelab command inofanirwa kunyorwa sezvakaratidzwa mune inotevera kodhi kodhi kugadzirisa iyo MSS block kubva kuSmartFusion2 precompiled raibhurari.
xmelab -libmap lib.map -libverbose -Message -access +rwc cfg1
uye lib.map file inofanira kuva sezvinotevera:
config cfg1;
design ;
default liblist smartfusion2 ;
endconfig
Izvi zvinofanirwa kugadzirisa chero sero muraibhurari yeSmartFusion2 usati watarisa muraibhurari yebasa kureva postsynth/post-layout.
Iyo -libmap sarudzo inogona kushandiswa nekusarudzika panguva yekutsanangudza kune yega simulation (presynth, postsynth uye post-layout). Izvi zvinodzivirira nyaya dzekunyepedzera dzinokonzerwa nekuda kwekugadziriswa kwezviitiko kubva kumaraibhurari.
xmelab: *F, INTERR: ZVIRI MUKATI
Iyi ncelab chishandiso kunze ndeye caveat yemagadzirirwo ane FDDR muSmartFusion2 uye IGLOO2.
panguva yepostsynth uye post-layout simulations uchishandisa -libmap sarudzo.
Zvakakosha: Nyaya iyi yakashumwa kuCadence support team (SAR 52113).

4.4 Sample Tcl uye shell script files (Bvunza Mubvunzo)
Zvinotevera files ndiwo magadzirirwo files inodiwa kumisikidza dhizaini uye shell script file yekumhanyisa Xcelium mirairo.
Cds.lib
TSANANGURA smartfusion2 /scratch/krydor/tmpspace/users/me/nc-vlog64/SmartFusion2
DEFINE COREAHBLITE_LIB ./COREAHBLITE_LIB
TSANANGURA presynth ./presynth
Hdl.var
TSANANGURA BASA presynth
DEFINE PROJECT_DIR /scratch/krydor/tmpspace/sqausers/me/3rd_party_simulators/Cadence/IGLOO2/
ENVM/M2GL050/envm_fic1_ser1_v/eNVM_fab_master
TSANANGURA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/core/coreahblite_addrdec.v => COREAHBLITE_LIB )
TSANANGURA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/core/coreahblite_defaultslavesm.v => COREAHBLITE_LIB )
TSANANGURA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/core/coreahblite_masterstagev => COREAHBLITE_LIB )
TSANANGURA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/core/coreahblite_slavearbiter.v => COREAHBLITE_LIB )
TSANANGURA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/core/coreahblite_slavestagev => COREAHBLITE_LIB )
TSANANGURA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/core/coreahblite_matrix2x16.v => COREAHBLITE_LIB )
TSANANGURA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/core/coreahblite.v => COREAHBLITE_LIB )
TSANANGURA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB/CCC_0/SB_CCC_0_FCCC.v =>
presynth)
TSANANGURA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreConfigMaster/
2.0.101/rtl/vlog/core/coreconfigmaster.v => presynth )
TSANANGURA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreConfigP/4.0.100/rtl/
vlog/core/coreconfigp.v => presynth )
TSANANGURA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreResetP/5.0.103/rtl/
vlog/core/coresetp_pcie_hotreset.v => presynth )
TSANANGURA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreResetP/5.0.103/rtl/
vlog/core/coresetp.v => presynth )
TSANANGURA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB/FABOSC_0/SB_FABOSC_0_OSC.v =>
presynth)
TSANANGURA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB_HPMS/SB_HPMS.v => presynth )
TSANANGURA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB/SB.v => presynth )
TSANANGURA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB_top/SERDES_IF_0/
SB_top_SERDES_IF_0_SERDES_IF.v => presynth )
TSANANGURA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB_top/SB_top.v => presynth)
TSANANGURA LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB_top/testbench.v => presynth)
TSANANGURA LIB_MAP ( $LIB_MAP, + => presynth)
Commands.csh
ncvlog +incdir+../../component/work/SB_top -cdslib ./cds.lib -hdlvar ./hdl.var -logfile
ncvlog.log -errormax 15 -update -linedebug
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite_addrdec.v
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/
coreahblite_defaultslavesm.v
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite_masterstagev
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite_slavearbiter.v
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite_slavestagev
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite_matrix2x16.v
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite.v
../../component/work/SB/CCC_0/SB_CCC_0_FCCC.v
../../component/Actel/DirectCore/CoreConfigMaster/2.0.101/rtl/vlog/core/coreconfigmaster.v
../../component/Actel/DirectCore/CoreConfigP/4.0.100/rtl/vlog/core/coreconfigp.v
../../component/Actel/DirectCore/CoreResetP/5.0.103/rtl/vlog/core/coreresetp_pcie_hotreset.v
../../component/Actel/DirectCore/CoreResetP/5.0.103/rtl/vlog/core/coreresetp.v
../../component/work/SB/FABOSC_0/SB_FABOSC_0_OSC.v ../../component/work/SB_HPMS/SB_HPMS.v
../../component/work/SB/SB.v ../../component/work/SB_top/SERDES_IF_0/
SB_top_SERDES_IF_0_SERDES_IF.v
../../component/work/SB_top/SB_top.v ../../component/work/SB_top/testbench.v
ncelab -Message -cdslib ./cds.lib -hdlvar ./hdl.var
-work presynth -logfile ncelab.log -errormax 15 -access +rwc -status presynth.testbench:module
ncsim -Message -batch -cdslib ./cds.lib -hdlvar ./
hdl.var -logfile ncsim.log -errormax 15 -status presynth.testbench:module

4.5 otomatiki (Microchip Login)
Chinyorwa chinotevera file inoshandura ModelSim run.do files mune configuration files inodiwa kumhanyisa simulation uchishandisa Xcelium.
Script File Usage
perl cadence_parser.pl presynth_run.do postsynth_run.do
postlayout_run.do Microsemi_Family
Nzvimbo_ye_Cadence_Precompiled_libraries
Cadence_parser.pl
#!/usr/bin/perl -w

&questa_parser($postlayout, $family, $lib_location);
sub questa_parser {
my $ModelSim_run_do = $_[0];
my $actel_family = $_[1];
my $lib_location = $_[2];
yangu $state;
kana (-e "$ModelSim_run_do")
{
vhura (INFILE,”$ModelSim_run_do”);
yangu @ModelSim_run_do =FILE>;
yangu $line;
kana ( $ModelSim_run_do =~ m/(presynth)/)
{
`mkdir QUESTA_PRESYNTH`;
vhura (OUTFILE,”>QUESTA_PRESYNTH/presynth_questa.do”);
$ state = $1;
} elsif ( $ModelSim_run_do =~ m/(postsynth)/)
{
`mkdir QUESTA_POSTSYNTH`;
vhura (OUTFILE,”>QUESTA_POSTSYNTH/postsynth_questa.do”);
$ state = $1;
} elsif ( $ModelSim_run_do =~ m/(postlayout)/ )
{
`mkdir QUESTA_POSTLAYOUT`;
vhura (OUTFILE,”>QUESTA_POSTLAYOUT/postlayout_questa.do”);
$ state = $1;
zvimwe
{
dhinda “Zvisina kururama zvinopihwa kune file\n";
dhinda “#Kushandiswa: perl questa_parser.pl presynth_run.do postsynth_run.do postlayout_run.do
\"Libraries_nzvimbo\"\n";
}
foreach $line (@ModelSim_run_do)
{
#General Operations
$line =~ s/..\/designer.*simulation\///g;
$line =~ s/$state/$state\_questa/g;
#print OUTFILE "$line \n";
kana ($line =~ m/vmap\s+.*($actel_family)/)
{
pirinda OUTFILE "vmap $actel_family \"$lib_location\"\n";
} elsif ($line =~ m/vmap\s+(.*._LIB)/)
{
$line =~ s/..\/component/..\/..\/component/g;
pirinda OUTFILE "$line \n";
} elsif ($line =~ m/vsim/)
{
$ mutsetse =~ s/vsim/vsim -novopt/g;
pirinda OUTFILE "$line \n";
zvimwe
{
pirinda OUTFILE "$line \n";
}
}
kuvhara (INFILE);
kuvhara (OUTFILE);
} zvimwe {
dhinda "$ModelSim_run_do haipo. Rerun simulation zvakare \n";
}
}

Siemens QuestaSim Setup/ModelSim Setup (Bvunza Mubvunzo)

The run.do files, yakagadzirwa neLibero SoC yekufananidza uchishandisa ModelSim Microsemi Editions, inogona kushandiswa pakuenzanisa uchishandisa QuestaSim/ModelSim SE/DE/PE neshanduko imwe chete. MuModelSim ME/ModelSim Pro ME run.do file, nzvimbo yeraibhurari yakarongwa inoda kuvandudzwa.
Zvakakosha:
Nekumisikidza, chishandiso chekufananidza kunze kweModelSim Pro ME inoita dhizaini yekugonesa panguva yekuenzanisa iyo inogona kukanganisa kuoneka muzvinhu zvekunyepedzera senge zvinhu zvekugadzira uye zvinosimudzira zvinosimudzira.
Izvi zvinowanzo batsira mukudzikisa simulation yekumhanyisa nguva yeakaomesesa simulations, uchishandisa verbose, wega-kutarisa testbenches. Nekudaro, iyo default optimizations inogona kunge isingakodzeri kune ese simulations, kunyanya mumamiriro ezvinhu apo iwe unotarisira kunyatsoongorora mhedzisiro yekufungidzira uchishandisa wave hwindo.
Kugadzirisa nyaya dzakakonzerwa nekugadzirisa uku, unofanirwa kuwedzera mirairo yakakodzera uye nharo dzine hukama panguva yekuenzanisa kudzoreredza kuoneka mudhizaini. Kuti uwane mirairo yakanangana nemidziyo, ona zvinyorwa zvesimulator mukushandisa.

5.1 Zvakasiyana-siyana (Bvunza Mubvunzo)
Zvinotevera ndizvo zvinodiwa zvakatipoteredza zvakasiyana.

LM_LICENSE_FILE: inofanira kusanganisira nzira yerezinesi file.
MODEL_TECH: inofanirwa kuona nzira inoenda kunzvimbo yekumba dhairekitori rekuisa QuestaSim.
PATH: inofanirwa kunongedza kunzvimbo inogoneka yakanongedzerwa neMODEL_TECH.

5.2 Kushandura run.do yeMentor QuestaSim (Bvunza Mubvunzo)
The run.do files inogadzirwa neLibero SoC yekufananidza uchishandisa ModelSim Microsemi Editions inogona kushandiswa pakuenzanisa uchishandisa QuestaSim/ModelSim_SE neshanduko imwe chete.
Zvakakosha: Zvose magadzirirwo ayo akateedzerwa uchishandisa QuestaSim anofanira kusanganisira -novopt
sarudzo pamwe ne vsim command mune run.do script files.
5.3 Dhaunirodha Raibhurari Yakaunganidzwa (Bvunza Mubvunzo)
Dhawunirodha maraibhurari eMentor Graphics QuestaSim kubva kuMicrosemi's website.

Synopsys VCS Setup (Bvunza Mubvunzo)

Kuyerera kunokurudzirwa neMicrosemi kunovimba neElaborate uye Compile kuyerera muVCS. Gwaro iri rinosanganisira script file iyo inoshandisa run.do script files inogadzirwa neLibero SoC uye inogadzira iyo setup files inodiwa paVCS simulation. The script file inoshandisa run.do file kuita zvinotevera.

Gadzira mepu yeraibhurari file, iyo inoitwa uchishandisa synopys_sim.setup file iri mune imwechete dhairekitori uko VCS simulation iri kushanda.
Gadzira shell script file kutsanangura uye kuunganidza dhizaini yako uchishandisa VCS.

6.1 Zvakasiyana-siyana (Bvunza Mubvunzo)
Seta iyo yakakodzera nharaunda inosiyana yeVCS zvichienderana nekuseta kwako. Mamiriro ekunze anodiwa sekuenderana nemagwaro eVCS ndeaya:

LM_LICENSE_FILE: inofanira kusanganisira chinongedzo kune server rezinesi.
VCS_HOME: inofanira kunongedza kunzvimbo yekumba dhairekitori rekuisa VCS.
PATH: inofanira kusanganisira chinongedzo kune bhini dhairekitori pazasi peVCS_HOME dhairekitori.

6.2 Dhaunirodha Raibhurari Yakaunganidzwa (Bvunza Mubvunzo)
Dhawunirodha maraibhurari eSynopsy VCS kubva kuMicrosemi's website.
6.3 VCS Simulation Script File (Bvunza Mubvunzo)
Mushure mekugadzirisa VCS uye kugadzira dhizaini uye zvakasiyana run.do files kubva kuLibero SoC, unofanirwa:

Gadzira mepu yeraibhurari file synopys_sim.setup; izvi file ine zvinongedzo kunzvimbo yemaraibhurari ese achashandiswa nedhizaini.
Chinokosha: The file zita harifanire kuchinja uye rinofanira kunge riri mune imwechete dhairekitori uko simulation iri kushanda. Heino example for such a file ye presynthesis simulation.
BASA > EFAULT
SmartFusion2 :
presynth : ./presynth
DEFAULT : ./work
Rongedza dhizaini yakasiyana files, kusanganisira testbench, uchishandisa vlogan command muVCS. Iyi mirairo inogona kuverengerwa mune shell script file. Kutevera kune example yemirairo inodiwa kutsanangura dhizaini inotsanangurwa murtl.v ine testbench yakatsanangurwa mu.
testbench.v.
vlogan +v2k -work presynth rtl.v
vlogan +v2k -work presynth testbench.v

Nyora dhizaini uchishandisa VCS uchishandisa murairo unotevera.
vcs –sim_res=1fs presynth.testbench
Cherechedza: The Kugadzirisa nguva yekufananidza kunofanirwa kusetwa kune 1fs yechokwadi inoshanda simulation.
Kana dhizaini yaunganidzwa, tanga simulation uchishandisa murairo unotevera.
./simv
Kune yekumashure-yakatsanangurwa simulation, iwo VCS murairo unofanirwa kunge unoratidzwa mune inotevera codeblock.
vcs postlayout.testbench -sim_res=1fs -sdf max: .
zita>: file nzira> -gui -l postlayout.log

6.4 Kuganhurirwa/Kunze (Bvunza Mubvunzo)
Zvinotevera zvinogumira/kusara kweSynopsys VCS setup.

VCS simulations inogona kumhanyirwa chete yeVerilog mapurojekiti eLibero SoC. Iyo VCS simulator ine yakasimba VHDL mutauro zvinodiwa izvo zvisingazadziswe neLibero SoC auto-yakagadzirwa VHDL. files.
Iwe unofanirwa kuva ne $ kupedza chirevo muVerilog testbench kuti umise simulation chero nguva yaunoda.
Zvinokosha: Rini simulations inomhanya muGUI modhi, nguva yekumhanya inogona kutsanangurwa muGUI.

6.5 Sampuye Tcl uye Shell Script Files (Bvunza Mubvunzo)
Iyo inotevera Perl inogadzirisa chizvarwa che synopsys_sim.setup file pamwe chete neyakaenderana shell script filezvinodikanwa kutsanangura, kuunganidza, uye kutevedzera dhizaini.
Kana dhizaini ichishandisa MSS, kopira test.vec file iri mufodhi yekufananidza yeLibero SoC purojekiti muVCS simulation folda. Zvikamu zvinotevera zvine sample run.do files inogadzirwa neLibero SoC, kusanganisira iyo inoenderana raibhurari mepu uye shell script files inodiwa paVCS simulation.
6.5.1 Pre-synthesis (Bvunza Mubvunzo)
Presynth_run.do
chinyararire seta ACTELLIBNAME SmartFusion2
gadzirisa chinyararire PROJECT_DIR "/sqa/users/me/VCS_Tests/Test_DFF"
kana {[file iripo presynth/_info]} {
echo "INFO: Simulation raibhurari presynth yatovapo"
} zvimwe {
vlib presynth
}
vmap presynth presynth
vmap SmartFusion2 “/captures/lin/11_0_0_23_11prod/lib/ModelSim/precompiled/vlog/smartfusion2”
vlog -work presynth "${PROJECT_DIR}/component/work/SD1/SD1.v"
vlog “+ incdir+${PROJECT_DIR}/stimulus” -work presynth “${PROJECT_DIR}/stimulus/SD1_TB1.v”
vsim -L SmartFusion2 -L presynth -t 1fs presynth.SD1_TB1
wedzera wave /SD1_TB1/*
wedzera log -r /*
kumhanya 1000ns
presynth_main.csh
#!/bin/csh -f
seta PROJECT_DIR = "/sqa/users/Me/VCS_Tests/Test_DFF"
/cad_design/tools/vcs.dir/E-2011.03/bin/vlogan +v2k -work presynth “${PROJECT_DIR}/component/
basa/SD1/SD1.v”
/cad_design/tools/vcs.dir/E-2011.03/bin/vlogan +v2k “+incdir+${PROJECT_DIR}/stimulus” -basa
presynth “${PROJECT_DIR}/stimulus/SD1_TB1.v”
/cad_design/tools/vcs.dir/E-2011.03/bin/vcs -sim_res=1fs presynth.SD1_TB1 -l compile.log
./simv -l run.log
Synopsys_sim.setup
BASA > DEFAULT
SmartFusion2: /VCS/SmartFusion2
presynth : ./presynth
DEFAULT : ./work

6.5.2 Post-synthesis (Bvunza Mubvunzo)
postsynth_run.do
chinyararire seta ACTELLIBNAME SmartFusion2
gadzirisa chinyararire PROJECT_DIR "/sqa/users/Me/VCS_Tests/Test_DFF"
kana {[file iripo postsynth/_info]} {
echo "INFO: Simulation raibhurari postsynth yatovapo"
} zvimwe {
vlib postsynth
}
vmap postsynth postsynth
vmap SmartFusion2 “//idm/captures/pc/11_0_1_12_g4x/Designer/lib/ModelSim/precompiled/vlog/
SmartFusion2”
vlog -work postsynth "${PROJECT_DIR}/synthesis/SD1.v"
vlog "+ incdir+${PROJECT_DIR}/stimulus" -work postsynth "${PROJECT_DIR}/stimulus/SD1_TB1.v"
vsim -L SmartFusion2 -L postsynth -t 1fs postsynth.SD1_TB1
wedzera wave /SD1_TB1/*
wedzera log -r /*
kumhanya 1000ns
log SD1_TB1/*
kubuda
Postsynth_main.csh
#!/bin/csh -f
seta PROJECT_DIR = "/sqa/users/Me/VCS_Tests/Test_DFF"
/cad_design/tools/vcs.dir/E-2011.03/bin/vlogan +v2k -work postsynth “${PROJECT_DIR}/synthesis/
SD1.v”
/cad_design/tools/vcs.dir/E-2011.03/bin/vlogan +v2k “+incdir+${PROJECT_DIR}/stimulus” -basa
postsynth “${PROJECT_DIR}/stimulus/SD1_TB1.v”
/cad_design/tools/vcs.dir/E-2011.03/bin/vcs -sim_res=1fs postsynth.SD1_TB1 -l compile.log
./simv -l run.log
Synopsys_sim.setup
BASA > DEFAULT
SmartFusion2: /VCS/SmartFusion2
postsynth : ./postsynth
DEFAULT : ./work
6.5.3 Post-rongedzo (Bvunza Mubvunzo)
postlayout_run.do
chinyararire seta ACTELLIBNAME SmartFusion2
gadzirisa chinyararire PROJECT_DIR "E:/ModelSim_Work/Test_DFF"
kana {[file iripo ../designer/SD1/simulation/postlayout/_info]} {
echo "INFO: Simulation raibhurari ../designer/SD1/simulation/postlayout yatovapo"
} zvimwe {
vlib ../designer/SD1/simulation/postlayout
}
vmap postlayout ../designer/SD1/simulation/postlayout
vmap SmartFusion2 “//idm/captures/pc/11_0_1_12_g4x/Designer/lib/ModelSim/precompiled/vlog/
SmartFusion2”
vlog -work postlayout "${PROJECT_DIR}/designer/SD1/SD1_ba.v"
vlog "+ incdir+${PROJECT_DIR}/stimulus" -basa rekugadzirisa "${PROJECT_DIR}/stimulus/SD1_TB1.v"
vsim -L SmartFusion2 -L postlayout -t 1fs -sdfmax /SD1_0=${PROJECT_DIR}/designer/SD1/
SD1_ba.sdf postlayout.SD1_TB1
wedzera wave /SD1_TB1/*
wedzera log -r /*
kumhanya 1000ns
Postlayout_main.csh
#!/bin/csh -f
seta PROJECT_DIR = "/VCS_Tests/Test_DFF"
/cad_design/tools/vcs.dir/E-2011.03/bin/vlogan +v2k -work postlayout “${PROJECT_DIR}/
mugadziri/SD1/SD1_ba.v”
/cad_design/tools/vcs.dir/E-2011.03/bin/vlogan +v2k “+incdir+${PROJECT_DIR}/stimulus” -basa
postrout "${PROJECT_DIR}/stimulus/SD1_TB1.v"
/cad_design/tools/vcs.dir/E-2011.03/bin/vcs -sim_res=1fs postlayout.SD1_TB1 -sdf

max:SD1_TB1.SD1_0:${PROJECT_DIR}/designer/SD1/SD1_ba.sdf -l compile.log
./simv -l run.log
Synopsys_sim.setup
BASA > DEFAULT
SmartFusion2: /VCS/SmartFusion2
postlayout : ./postlayout
DEFAULT : ./workVCS
6.6 otomatiki (Bvunza Mubvunzo)
Kuyerera kunogona kuve otomatiki uchishandisa inotevera Perl script file kushandura iyo ModelSim run.do files muVCS inoenderana shell script files, gadzira madhairekitori akakodzera mukati meLibero SoC simulation dhairekitori, uye wobva wamhanyisa simulations.
Mhanya script file uchishandisa syntax inotevera.
perl vcs_parse.pl presynth_run.do postynth_run.do postlayout_run.do
Vcs_parse_pl
#!/usr/bin/perl -w
###################################################### ##############################
#
#Kushandiswa: perl vcs_parse.pl presynth_run.do postsynth_run.do postlayout_run.do
#
###################################################### ###############################
yangu ($ presynth, $ postsynth, $ postlayout) = @ARGV;
kana(system(“mkdir VCS_Presynth”)) {print “mkdir yakundikana:\n”;}
kana(system(“mkdir VCS_Postsynth”)) {printa “mkdir yakundikana:\n”;}
kana(system(“mkdir VCS_Postlayout”)) {print “mkdir yakundikana:\n”;}
chdir(VCS_Presynth);
`cp ../$ARGV[0] .` ;
&parse_do($presynth,"presynth");
chdir (“../”);
chdir(VCS_Postsynth);
`cp ../$ARGV[1] .` ;
&parse_do($postsynth,"postsynth");
chdir (“../”);
chdir(VCS_Postlayout);
`cp ../$ARGV[2] .` ;
&parse_do($ postlayout,"postlayout");
chdir (“../”);
tsanangura_ita {
my $ vlog = “/cad_design/tools/vcs.dir/E-2011.03/bin/vlogan +v2k” ;
yangu %LIB = ();
$ yangufile = $_[0] ;
yangu $state = $_[1];
vhura (INFILE,”$file”) || kufa "Haigone kuvhura File Chikonzero chingava:$!”;
kana ($state eq “presynth”)
{
open(OUT1,”>presynth_main.csh”) || kufa "Haugone kugadzira Command File Chikonzero chingava:$!”;
}
elsif ($state eq “postsynth”)
{
open(OUT1,”>postsynth_main.csh”) || kufa "Haugone kugadzira Command File Chikonzero chingava:$!”;
}
elsif ($state eq "postlayout")
{
open(OUT1,”>postlayout_main.csh”) || kufa "Haugone kugadzira Command File Chikonzero chingava:$!”;
}
zvimwe
{
dhinda "Simulation State is missing \n" ;
}
open(OUT2,”>synopsys_sim.setup”) || kufa "Haugone kugadzira Command File Chikonzero chingava:$!”;
# .csh file
pirinda OUT1 “#!/bin/csh -f\n\n\n” ;
#GADZIRIRA FILE
pirinda OUT2 “BASA > DEFAULT\n” ;
pirinda OUT2 "SmartFusion2 : /sqa/users/Aditya/VCS/SmartFusion2\n" ;
apo ($ mutsara =FILE>)
{

Synopsys VCS Setup

kana ($line =~ m/zvinyararire isa PROJECT_DIR\s+\”(.*?)\”/)
{
pirinda OUT1 “set PROJECT_DIR = \”$1\”\n\n\n” ;
}
elsif ( $line =~ m/vlog.*\.v\”/ )
{
kana ($line =~ m/\s+(\w*?)\_LIB/)
{
#print “\$1 =$1 \n” ;
$temp = “$1″.”_LIB”;
#print "Temp = $ temp \n" ;
$LIB{$temp}++;
}
chomp ($ mutsara);
$mutsetse =~ s/^vlog/$vlog/ ;
$mutsetse =~ s/ //g;
pirinda OUT1 “$line\n”;
}
elsif ( ($line =~ m/vsim.*presynth\.(.*)/) || ($line =~ m/vsim.*postsynth\.(.*)/) || ($line
=~ m/vsim.*postlayout\.(.*)/) )
{
$tb = $1 ;
$tb =~ s/ //g;
chomp($tb);
#print "TB Zita : $tb \n";
kana ( $line =~ m/sdf(.*)\.sdf/)
{
chomp ($ mutsara);
$line = $1 ;
#print “LINE : $line \n” ;
kana ($mutsara =~ m/max/)
{
$line =~ s/max \/// ;
$line =~ s/=/:/;
dhinda OUT1 “\n\n/cad_design/tools/vcs.dir/E-2011.03/bin/vcs -sim_res=1fs postlayout.$tb -sdf
max:$tb.$line.sdf -l compile.log\n” ;
}
elsif ($mutsara =~ m/min/)
{
$line =~ s/min \/// ;
$line =~ s/=/:/;
dhinda OUT1 “\n\n/cad_design/tools/vcs.dir/E-2011.03/bin/vcs -sim_res=1fs postlayout.$tb -sdf
min:$tb.$line.sdf -l compile.log\n” ;
}
elsif ($line =~ m/typ/)
{
$line =~ s/typ \/// ;
$line =~ s/=/:/;
dhinda OUT1 “\n\n/cad_design/tools/vcs.dir/E-2011.03/bin/vcs -sim_res=1fs postlayout.$tb -sdf
typ:$tb.$line.sdf -l compile.log\n” ;
}
#-sdfmax /M3_FIC32_0=${PROJECT_DIR}/designer/M3_FIC32/M3_FIC32_ba.sdf — ModelSim SDF fomati
#$sdf = “-sdf max:testbench.M3_FIC32_0:${PROJECT_DIR}/designer/M3_FIC32/M3_FIC32_ba.sdf”; -VCS
SDF format
}
}
}
dhinda
OUT1 "\n\n"
;
if
($state eq “presynth”
)
{
dhinda
OUT2 “presynth
: ./presynth\n”
;
dhinda
OUT1 “/cad_design/tools/vcs.dir/E-2011.03/bin/vcs
-sim_res=1fs presynth.$tb -l
compile.log\n”
;
}
elsif
($state eq "postsynth"
)
{
dhinda
OUT2 “postsynth
: ./postsynth\n”
;
dhinda
OUT1 “/cad_design/tools/vcs.dir/E-2011.03/bin/vcs
-sim_res=1fs postsynth.$tb -l
compile.log\n”
;
}
elsif
($state eq "postlayout"
)
{
pirinda OUT2 “postlayout : ./postlayout\n” ;
}
zvimwe
{
dhinda "Simulation State is missing \n" ;
}
foreach $i ( makiyi %LIB)
{
#print "Kiyi : $i Kukosha : $LIB{$i} \n" ;
pirinda OUT2 “$i : ./$i\n” ;
}
pirinda OUT1 “\n\n” ;
pirinda OUT1 “./simv -l run.log\n” ;
pirinda OUT2 “DEFAULT : ./work\n” ;
kuvhara INFILE;
kuvhara OUT1;
kuvhara OUT2;
}

Revision History (Microchip Login

Nhoroondo yekudzokorora inotsanangura shanduko dzakaitwa mugwaro. Iko kushanduka
anorongwa nokudzokorora, kutanga nebhuku razvino uno.

Kudzokorora	Date	Tsanangudzo
A	12/2023	Shanduko dzinotevera dzinoitwa mudzokororo iyi: • Gwaro rakashandurwa kuita Microchip template. Ongororo Yokutanga. • Yakagadziridzwa chikamu 5. Siemens QuestaSim Setup/ModelSim Setup kuti iise chinyorwa chitsva chinotsanangura kukanganiswa kwekuonekwa panguva yekufananidza nekugadzirisa.

Microchip FPGA Tsigiro
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Vatengi vanokurudzirwa kushanyira Microchip online zviwanikwa vasati vabata rutsigiro sezvo paine mukana wekuti mibvunzo yavo yatopindurwa.
Bata Technical Support Center kuburikidza ne website pa www.microchip.com/support. Taura iyo FPGA Chidimbu Chikamu nhamba, sarudza yakakodzera nyaya chikamu, uye kurodha dhizaini files paunenge uchigadzira tekinoroji yekutsigira kesi.
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Iyo Microchip zita uye logo, iyo Microchip logo, Adaptec, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, CryptoMemory, CryptoRF, dsPIC, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXTouchlus MediaLB, megaAVR, Microsemi, Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, PolarFire, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetri , SyncServer, Tachyon, TimeSource, tinyAVR, UNI/O, Vectron, uye XMEGA zviratidzo zvakanyoreswa zveMicrochip Technology Incorporated muUSA nedzimwe nyika.
AgileSwitch, APT, ClockWorks, The Embedded Control Solutions Company, EtherSynch, Flashtec, Hyper Speed Control, HyperLight Load, Libero, motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet- Wire, SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub, TimePictra, TimeProvider, TrueTime, neZL zvikwangwani zvakanyoreswa zveMicrochip Technology Incorporated muU.SA.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Chero Capacitor, AnyIn, AnyOut, Augmented Switching, BlueSky, BodyCom, Clockstudio, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEMArage Average, dsPICDEMAverage.net , DAM, ECAN, Espresso T1S, EtherGREEN, GridTime, IdealBridge, In-Circuit Serial Programming, ICSP, INICnet, Intelligent Paralleling, IntelliMOS, Inter-Chip Connectivity, JitterBlocker, Knob-on-Display, KoD, maxCrypto, maxView, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net,
PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, RTAX, RTG4, SAMICE, Serial Quad I/O, simpleMAP, SimpliPHY, SmartBuffer, SmartHLS, SMART-IS, storClad, SQI, SuperSwitcher,
SuperSwitcher II, Switchtec, SynchroPHY, Total Endurance, Trusted Time, TSHARC, USBCheck, VariSense, VectorBlox, VeriPHY, ViewSpan, WiperLock, XpressConnect, uye ZENA zviratidzo zveMicrochip Technology Incorporated
muUSA nedzimwe nyika.
SQTP chiratidzo chesevhisi cheMicrochip Technology Incorporated muUSA
The Adaptec logo, Frequency on Demand, Silicon Storage Technology, neSymmcom zviratidzo zvekutengeserana zveMicrochip Technology Inc. kune dzimwe nyika.
GestIC ichiratidzo chekutengeserana chakanyoreswa cheMicrochip Technology Germany II GmbH & Co. KG, inotsigira Microchip Technology Inc., kune dzimwe nyika.
Mamwe matrademark ese ataurwa pano zvinhu zvemakambani avo.
© 2023, Microchip Technology Incorporated nemakambani ayo. All Rights Reserved.
ISBN: 978-1-6683-3694-6
Quality Management System
Kuti uwane ruzivo nezve Microchip's Quality Management Systems, ndapota shanya www.microchip.com/quality.

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Zvinyorwa / Zvishandiso

MICROCHIP Libero SoC Simulation Library Software [pdf] Bhuku reMushandisi
DS50003627A, Libero SoC Simulation Library Software, SoC Simulation Library Software, Simulation Library Software, Library Software, Software

References

User Manual