MICROCHIP Libero SoC Simulation Library Software Gid Itilizatè

Simulation Libero SoC
Enstriksyon Bibliyotèk Enstalasyon

Kontni kache

1 Entwodiksyon

2 Entegrasyon Libero SoC

3 Enstalasyon Aldec pou Active-HDL ak Riviera-Pro (Poze yon kesyon)

4 Kadans konfigirasyon ansèyman (Poze yon kesyon)

5 Cadence Xcelium Enstalasyon (Login Microchip)

6 Siemens QuestaSim Setup/ModelSim Setup (Poze yon kesyon)

7 Enstalasyon Synopsys VCS (Poze yon kesyon)

8 Istwa Revizyon (Konekte Microchip

9 Dokiman / Resous

9.1 Referans

10 Post ki gen rapò

Entwodiksyon

(Poze yon Kesyon)

Objektif dokiman sa a se pou dekri pwosedi pou etabli anviwònman simulation lè l sèvi avèk yon pwojè Libero SoC kòm opinyon. Dokiman sa a koresponn ak bibliyotèk yo pre-konpile yo bay pou itilize ak Libero SoC v11.9 ak nouvo degaje lojisyèl. Bibliyotèk yo bay yo konpile pou Verilog. Itilizatè VHDL bezwen yon lisans ki pèmèt simulation mòd melanje.
Bibliyotèk simulation konpile yo disponib pou zouti sa yo:

Aldec aktif-HDL
Aldec Riviera-PRO

Kadans Incisive Enterprise ak Xcelium
Siemens QuestaSim

Synopsys VCS

Pou mande yon bibliyotèk pou yon similatè diferan, kontakte Sipò teknik Microchip.

Entegrasyon Libero SoC

(Poze yon Kesyon)

Libero SoC sipòte simulation lè l sèvi avèk ModelSim ME pa jenere yon run.do file. Sa a file se ModelSim ME/ModelSim Pro ME itilize pou mete sou pye ak kouri simulation. Pou itilize lòt zouti simulation, ou ka jenere ModelSim ME/ModelSim Pro ME run.do epi modifye script Tcl la. file pou itilize kòmandman yo ki konpatib ak similatè ou a.
1.1 Libero SoC Tcl File jenerasyon (Poze yon Kesyon)
Apre kreye ak jenere konsepsyon nan Libero SoC, kòmanse yon simulation ModelSim ME/ModelSim Pro ME nan tout faz konsepsyon (presynth, postsynth, ak post-layout). Etap sa a jenere run.do la file pou ModelSim ME/ModelSim Pro ME pou chak faz konsepsyon.
Enpòtan: Apre kòmanse chak kouri simulation, chanje non run.do oto-pwodwi a file anba anyè simulation pou anpeche Libero SoC ranplase sa file. Pou egzanpample, la fileYo ka chanje non yo nan presesynth_run.do, postsynth_run.do ak postlayout_run.do.

Aldec Enstalasyon pou Active-HDL ak Riviera-Pro (Poze yon Kesyon)

Kouri a.fè file ModelSim ME/ModelSim Pro ME itilize yo ka modifye epi itilize pou simulation lè l sèvi avèk simulateur Aldec yo.
2.1 Varyab Anviwònman (Poze yon Kesyon)
Mete varyab anviwònman ou nan lisans ou file kote:
LM_LICENSE_FILE: dwe genyen yon pwent sou sèvè lisans lan.
2.2 Telechaje bibliyotèk konpile (Poze yon Kesyon)
Telechaje bibliyotèk yo pou Aldec Active-HDL ak Aldec Riviera-PRO nan Microchip la websit.
2.3 Konvèti run.do pou simulation Aldec (Poze yon Kesyon)
Kouri a.fè files ki te pwodwi pa Libero SoC pou simulation lè l sèvi avèk Active-HDL ak zouti Riviera-Pro ka itilize pou simulation lè l sèvi avèk Active-HDL ak Riviera-Pro ak yon sèl chanjman. Tablo sa a bay lis kòmandman ekivalan Aldec pou modifye nan ModelSim run.do file.
Tablo 2-1. Kòmandman ekivalan Aldec

ModelSim	Aktif-HDL
vlog	alològ
vcom	akon
vlib	alib
vsim	asim
vmap	amap

Swivan se kòmample run.do ki gen rapò ak simulateur Aldec.

Mete kote anyè k ap travay aktyèl la.
mete dsn
Mete yon non bibliyotèk k ap travay, kat kote li yo, epi answit kat kote fanmi Microchip FPGA yo
bibliyotèk prekonpile (pa egzanpample, SmartFusion2) kote w ap kouri konsepsyon ou a.
alib presinth
amap presinth presinth
amap SmartFusion2

Konpile tout HDL ki nesesè yo fileyo itilize nan konsepsyon an ak bibliyotèk ki nesesè yo.
alog –work presynth temp.v (pou Verilog)
alog –work presynth testbench.v
acom –work presynth temp.vhd (pou Vhdl)
acom –work presiynth testbench.vhd
Simile konsepsyon an.
asim –L SmartFusion2 –L presinth –t 1ps presynth.testbench
kouri 10us

2.4 Pwoblèm li te ye (Poze yon Kesyon)
Seksyon sa a bay lis pwoblèm ak limit yo konnen.

Bibliyotèk konpile lè l sèvi avèk Riviera-PRO yo se platfòm espesifik (sa vle di bibliyotèk 64-bit pa ka kouri sou platfòm 32-bit ak vis vèrsa).

Pou desen ki gen SERDES/MDDR/FDDR, sèvi ak opsyon sa a nan run.do ou files pandan y ap kouri simulation apre yo fin konpile desen yo:
– Aktif-HDL: asim –o2
– Riviera-PRO: asim –O2 (pou simulation presynth ak post-layout) ak asim –O5 (pou simulation apre layout)
Konfigirasyon Aldec pou Active-HDL ak Riviera-Pro gen SAR sa yo annatant. Pou plis enfòmasyon, kontakte Sipò teknik Microchip.
SAR 49908 – Active-HDL: Erè VHDL pou simulation blòk matematik

SAR 50627 - Riviera-PRO 2013.02: Erè simulation pou desen SERDES
SAR 50461 - Riviera-PRO: asim -O2/-O5 opsyon nan simulation

Kadans Enstalasyon Ensifizan (Poze yon Kesyon)

Ou bezwen kreye yon script file menm jan ak ModelSim ME/ModelSim Pro ME run.do pou kouri a
Kadans Incisive similatè. Swiv etap sa yo epi kreye script file pou NCSim oswa itilize script la file
bay pou konvèti ModelSim ME/ModelSim Pro ME run.do files nan konfigirasyon an files
bezwen kouri simulation yo lè l sèvi avèk NCSim.
Enpòtan: Kadans te sispann pibliye nouvo vèsyon Incisive Enterprise la
similatè ak te kòmanse sipòte Xcelium similatè.

3.1 Varyab anviwònman yo (Poze yon Kesyon)
Pou kouri similatè Cadence Incisive, konfigirasyon varyab anviwònman sa yo:

LM_LICENSE_FILE: dwe genyen yon pwent sou lisans lan file.
cds_root: dwe lonje dwèt sou anyè kay kote enstalasyon Cadence Incisive a.

PATH: dwe lonje dwèt sou kote bin la anba anyè zouti ki pwente pa cds_root sa vle di,
$cds_root/tools/bin/64bit (pou yon machin 64-bit ak $cds_root/tools/bin pou yon machin 32-bit).
Gen twa fason pou mete anviwònman simulation nan ka ta gen yon chanjman ant sistèm operasyon 64-bit ak 32-bit:

Ka 1: PATH Varyab
Kouri lòd sa a:
mete chemen = (install_dir/tools/bin/64bit $path) pou machin 64bit ak
mete chemen = (install_dir/tools/bin $path) pou machin 32bit
Ka 2: Sèvi ak Opsyon Liy Kòmandman -64bit la
Nan liy lòd la presize opsyon -64bit yo nan lòd yo envoke ègzèkutabl 64bit la.
Ka 3: Mete varyab anviwònman INCA_64BIT oswa CDS_AUTO_64BIT
Varyab INCA_64BIT la trete kòm booleyen. Ou ka mete varyab sa a nan nenpòt ki valè oswa nan yon fisèl nil.
setenv INCA_64BIT

Lòt zouti Cadence, tankou zouti IC, sèvi ak varyab anviwònman CDS_AUTO_64BIT tou pou kontwole seleksyon ègzèkutabl 32-bit oswa 64-bit. Tablo ki anba la a montre kouman ou ka mete varyab CDS_AUTO_64BIT pou kouri zouti Incisive ak zouti IC nan tout mòd.
Tablo 3-1. CDS_AUTO_64BIT Varyab

CDS_AUTO_64BIT Varyab	Zouti ansidan	Zouti IC
setenv CDS_AUTO_64BIT TOUT	64 bit	64 bit
setenv CDS_AUTO_64BIT NON	32 bit	32 bit
setenv CDS_AUTO_64BIT EXCLUDE:ic_binary	64 bit	32 bit
setenv CDS_AUTO_64BIT EXCLUDE:INCA	32 bit	64 bit

Enpòtan: Tout zouti Incisive dwe kouri swa nan mòd 32-bit oswa nan mòd 64-bit, pa sèvi ak EXCLUDE pou eskli yon ègzèkutabl espesifik, tankou nan sa ki annapre yo: setenv CDS_AUTO_64BIT EXCLUDE:ncelab
Si ou mete varyab CDS_AUTO_64BIT pou eskli zouti Incisive yo (setenv CDS_AUTO_64BIT EXCLUDE:INCA), tout zouti Incisive yo kouri nan mòd 32-bit. Sepandan, opsyon nan liy kòmand -64bit pase sou valè varyab anviwònman an.
Konfigirasyon sa a files ede w jere done ou yo ak kontwole operasyon an nan zouti simulation ak sèvis piblik yo:

Kat jeyografik bibliyotèk file (cds.lib)—Defini yon non ki lojik pou kote konsepsyon ou a.
Bibliyotèk ak asosye yo ak non anyè fizik.
Varyab file (hdl.var)—Defini varyab ki afekte konpòtman zouti simulation ak sèvis piblik yo.

3.2 Telechaje bibliyotèk konpile (Poze yon Kesyon)
Telechaje bibliyotèk yo pou Cadence Incisive nan Microsemi a websit.
3.3 Kreye Script NCSim la File (Poze yon Kesyon)
Apre kreye yon kopi run.do la files, fè etap sa yo pou kouri simulation ou a lè l sèvi avèk NCSim:

Kreye yon cds.lib file ki defini bibliyotèk ki aksesib ak kote yo ye. La file gen deklarasyon ki mete non bibliyotèk lojik nan chemen anyè fizik yo. Pou egzanpample, si w ap kouri simulation presynth, cds.lib la file ekri jan yo montre nan kòd kod sa a.
DEFINI presinth ./presynth
DEFINI COREAHBLITE_LIB ./COREAHBLITE_LIB
DEFINI smartfusion2
Kreye yon hdl.var file, yon konfigirasyon si ou vle file ki gen varyab konfigirasyon, ki detèmine ki jan anviwònman konsepsyon ou a se configuré. Varyab sa a fileyo enkli:
– Varyab ke yo itilize pou presize bibliyotèk travay la kote konpilatè a estoke objè konpile ak lòt done ki sòti.
– Pou Verilog, varyab (LIB_MAP, VIEW_MAP, WORK) ki itilize pou presize bibliyotèk yo ak views pou chèche lè elaborateur a rezoud ka.
– Varyab ki pèmèt ou defini opsyon ak agiman pou konpilatè, elaboratè, ak similatè.
Nan ka simulation presynth example montre pi wo a, di nou gen twa RTL files: av, bv, ak testbench.v, ki bezwen konpile nan presynth, COREAHBLITE_LIB, ak presenth bibliyotèk respektivman. hdl.var la file ka ekri jan yo montre nan kodblock sa a.
DEFINI TRAVAY presinth
DEFINI PROJECT_DIR files>
DEFINI LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/av => present)
DEFINI LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/bv => COREAHBLITE_LIB)
DEFINI LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/testbench.v => presynth)
DEFINE LIB_MAP ($LIB_MAP, + => present)
Konpile konsepsyon an files itilize opsyon ncvlog.
ncvlog +incdir+ –cdslib ./cds.lib –hdlvar ./hdl.var –logfile
ncvlog.log –update –linedebug av bv testbench.v
Elabore konsepsyon an lè l sèvi avèk ncelab. Elaboratè a konstwi yon yerachi konsepsyon ki baze sou enstansyasyon ak enfòmasyon konfigirasyon nan konsepsyon an, etabli koneksyon siyal, epi kalkile valè inisyal pou tout objè nan konsepsyon an. Yerachi konsepsyon elabore a estoke nan yon snapshot simulation, ki se reprezantasyon konsepsyon ou ke similatè a itilize pou kouri simulation la.
ncelab –Message –cdslib ./cds.lib –hdlvar ./hdl.var –logfile ncelab.log –errormax 15 –
aksè +rwc –status worklib. :modil
Elaborasyon pandan simulation Post-layout
Nan ka similasyon apre-layout, premye SDF la file bezwen konpile anvan élaboration lè l sèvi avèk lòd ncsdfc la.
ncsdfcfilenon> .sdf – pèsistans yap ogmante jiskafilenon>.sdf.X
Pandan elaborasyon, sèvi ak pwodiksyon SDF konpile a ak opsyon –autosdf jan yo montre nan kòd kod sa a.
ncelab -autosdf –Mesaj –cdslib ./cds.lib –hdlvar ./hdl.var –logfile ncelab.log –errormax
15 –access +rwc –status worklib. :module –sdf_cmd_file ./
sdf_cmd_file
sdf_cmd_ lafile dwe jan yo montre nan kodblock sa a.
COMPILED_SDF_FILE = " file>"
Simile lè l sèvi avèk ncsim. Apre elaborasyon yon snapshot simulation kreye, ki chaje pa ncsim pou simulation. Ou ka kouri nan mòd pakèt oswa mòd entèfas.
ncsim –Message –batch/-gui –cdslib ./cds.lib –hdlvar ./hdl.var –logfile ncsim.log –
errormax 15 -status worklib. :modil

Enpòtan: Tout twa etap ki anwo yo nan konpile, elabore, ak simulation ka mete nan yon script koki file ak soti nan liy lòd. Olye pou yo sèvi ak twa etap sa yo, konsepsyon ka simulation nan yon sèl etap lè l sèvi avèk ncverilog oswa opsyon irun jan yo montre nan codeblock sa a.
ncverilog +incdir+ -cdslib ./cds.lib –hdlvar ./hdl.var
fileyo itilize nan konsepsyon an>
irun +incdir+ -cdslib ./cds.lib –hdlvar ./hdl.var files
itilize nan konsepsyon an>

3.3.1 Pwoblèm li te ye (Poze yon Kesyon)
Testbench solisyon
Sèvi ak deklarasyon sa a pou espesifye frekans revèy la nan testbench ki te pwodwi pa itilizatè a, oswa defo testbench ki te pwodwi pa Libero SoC pa travay ak NCSim.
toujou @(SYSCLK)
#(SYSCLK_PERIOD / 2.0) SYSCLK <= !SYSCLK;
Modifye jan sa a pou kouri simulation:
toujou #(SYSCLK_PERIOD / 2.0) SYSCLK = ~SYSCLK;
Enpòtan: Konpile bibliyotèk pou NCSim yo se platfòm espesifik (sa vle di bibliyotèk 64 bit yo pa konpatib ak platfòm 32 bit ak vis vèrsa).
Similasyon post-synth ak post-layout lè l sèvi avèk MSS ak SERDES Pandan w ap fè simulation postsynth nan desen ki gen blòk MSS la oswa apre-layout simulation nan desen ki itilize SERDES, simulation BFM yo pa travay si opsyon –libmap la se.
pa espesifye pandan elaborasyon. Sa a se paske pandan elaborasyon, MSS rezoud nan bibliyotèk travay la (paske nan obligatwa nan default ak worklib la ap postsynth / post-layout) kote li se jis yon Fonksyon fiks.
Yo dwe ekri kòmandman ncelab la jan yo montre nan blòk kòd sa a pou rezoud MSS la
bloke nan bibliyotèk prekonpile SmartFusion2.

ncelab -libmap lib.map -libverbose -Message -access +rwc cfg1
ak lib.map la file dwe jan sa a:
konfigirasyon cfg1;
konsepsyon ;
default liblist smartfusion2 ;
endconfig
Sa a rezoud nenpòt selil nan bibliyotèk SmartFusion2 la anvan ou gade nan bibliyotèk travay la sa vle di postsynth/post-layout.
Opsyon –libmap a ka itilize pa default pandan elaborasyon pou chak simulation (presynth, postsynth, ak post-layout). Sa a evite pwoblèm simulation ki te koze akòz rezolisyon ka nan bibliyotèk yo.
ncelab: *F,INTERR: EXCEPTION INTERN
Eksepsyon zouti ncelab sa a se yon opozisyon pou desen ki gen FDDR nan SmartFusion 2 ak IGLOO 2 pandan simulation post-sentant ak apre-layout lè l sèvi avèk opsyon -libmap.
Enpòtan: Yo rapòte pwoblèm sa a bay ekip sipò Cadence (SAR 52113).

3.4 Sample Tcl ak Shell Script Files (Poze yon Kesyon)
Sa ki annapre yo files yo se konfigirasyon an files nesesè pou mete sou pye konsepsyon an ak script koki file pou kouri kòmandman NCSim.
Cds.lib
NE smartfusion2 /scratch/krydor/tmpspace/users/me/nc-vlog64/SmartFusion2
DEFINI COREAHBLITE_LIB ./COREAHBLITE_LIB
DEFINI presinth ./presynth

Hdl.var
DEFINI TRAVAY presinth
DEFINE PROJECT_DIR /scratch/krydor/tmpspace/sqausers/me/3rd_party_simulators/Cadence/IGLOO2/
ENVM/M2GL050/envm_fic1_ser1_v/eNVM_fab_master
DEFINI LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/core/coreahblite_addrdec.v => COREAHBLITE_LIB )
DEFINI LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/core/coreahblite_defaultslavesm.v => COREAHBLITE_LIB )
DEFINI LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/core/coreahblite_masterstagev => COREAHBLITE_LIB )
DEFINI LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/core/coreahblite_slavearbiter.v => COREAHBLITE_LIB )
DEFINI LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/core/coreahblite_slavestagev => COREAHBLITE_LIB )
DEFINI LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/core/coreahblite_matrix2x16.v => COREAHBLITE_LIB )
DEFINI LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/core/coreahblite.v => COREAHBLITE_LIB )
DEFINI LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB/CCC_0/SB_CCC_0_FCCC.v =>
presint)
DEFINI LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreConfigMaster/
2.0.101/rtl/vlog/core/coreconfigmaster.v => present)
DEFINI LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreConfigP/4.0.100/rtl/
vlog/core/coreconfigp.v => present )
DEFINI LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreResetP/5.0.103/rtl/
vlog/core/coreresetp_pcie_hotreset.v => present )
DEFINI LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreResetP/5.0.103/rtl/
vlog/core/coreresetp.v => present )
DEFINI LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB/FABOSC_0/SB_FABOSC_0_OSC.v =>
presint)
DEFINI LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/component/work/SB_HPMS/SB_HPMS.v => presynth)
DEFINI LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/component/work/SB/SB.v => presynth)
DEFINI LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/component/work/SB_top/SERDES_IF_0/
SB_top_SERDES_IF_0_SERDES_IF.v => present )
DEFINI LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/component/work/SB_top/SB_top.v => present)
DEFINI LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/component/work/SB_top/testbench.v => presynth)
DEFINE LIB_MAP ($LIB_MAP, + => present)
Commands.csh
ncvlog +incdir+../../component/work/SB_top -cdslib ./cds.lib -hdlvar ./hdl.var -logfile
ncvlog.log -errormax 15 -update -linedebug
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite_addrdec.v
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/
coreahblite_defaultslavesm.v
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite_masterstagev
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite_slavearbiter.v
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite_slavestagev
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite_matrix2x16.v
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite.v
../../component/work/SB/CCC_0/SB_CCC_0_FCCC.v
../../component/Actel/DirectCore/CoreConfigMaster/2.0.101/rtl/vlog/core/coreconfigmaster.v
../../component/Actel/DirectCore/CoreConfigP/4.0.100/rtl/vlog/core/coreconfigp.v
../../component/Actel/DirectCore/CoreResetP/5.0.103/rtl/vlog/core/coreresetp_pcie_hotreset.v
../../component/Actel/DirectCore/CoreResetP/5.0.103/rtl/vlog/core/coreresetp.v
../../component/work/SB/FABOSC_0/SB_FABOSC_0_OSC.v ../../component/work/SB_HPMS/SB_HPMS.v
../../component/work/SB/SB.v ../../component/work/SB_top/SERDES_IF_0/
SB_top_SERDES_IF_0_SERDES_IF.v
../../component/work/SB_top/SB_top.v ../../component/work/SB_top/testbench.v
ncelab -Message -cdslib ./cds.lib -hdlvar ./hdl.var
-travay presinth -logfile ncelab.log -errormax 15 -access +rwc -status presynth.testbench:module
ncsim -Message -batch -cdslib ./cds.lib -hdlvar ./
hdl.var -logfile ncsim.log -errormax 15 -status presynth.testbench:modil

3.5 Otomatik (Poze yon Kesyon)
Script sa a file konvèti ModelSim run.do la files nan konfigirasyon fileyo bezwen kouri simulation lè l sèvi avèk NCSim.
Script File Itilizasyon
perl cadence_parser.pl presynth_run.do postsynth_run.do
postlayout_run.do Microsemi_Family
Kote_Bibliyotèk_Kadans_Prekonpile

Cadence_parser.pl
#!/usr/bin/perl -w

###################################################### ############################################
#################
#Usage: perl questa_parser.pl presynth_run.do postsynth_run.do postlayout_run.do
Microsemi_Family Precompiled_Libraries_location#

###################################################### ############################################
#################
sèvi ak POSIX;
itilize strik;
mwen ($presynth, $postsynth, $postlayout, $family, $lib_location) = @ARGV;
&questa_parser($presynth, $fanmi, $lib_location);
&questa_parser($postsynth, $fanmi, $lib_location);
&questa_parser($postlayout, $family, $lib_location);
sub questa_parser {
mwen $ModelSim_run_do = $_[0];
my $actel_family = $_[1];
mwen $lib_location = $_[2];
$eta mwen;
si (-e "$ModelSim_run_do")
{
louvri (INFILE,”$ModelSim_run_do”);
mwen @ModelSim_run_do =FILE>;
$line mwen an;
si ($ModelSim_run_do =~ m/(presynth)/)
{
`mkdir QUESTA_PRESYNTH`;
louvri (SOTIFILE,”>QUESTA_PRESYNTH/presynth_questa.do”);
$eta = $1;
} elsif ($ModelSim_run_do =~ m/(postsynth)/)
{
`mkdir QUESTA_POSTSYNTH`;
louvri (SOTIFILE,”>QUESTA_POSTSYNTH/postsynth_questa.do”);
$eta = $1;
} elsif ($ModelSim_run_do =~ m/(postlayout)/)
{
`mkdir QUESTA_POSTLAYOUT`;
louvri (SOTIFILE,”>QUESTA_POSTLAYOUT/postlayout_questa.do”);
$eta = $1;
} Lòt bagay
{
enprime “Wrong inputs bay to the file\n”;
enprime "#Usage: perl questa_parser.pl presynth_run.do postsynth_run.do postlayout_run.do
\”Kote_Bibliyotèk\”\n”;
}
foreach $line (@ModelSim_run_do)
{
# Operasyon Jeneral
$line =~ s/..\/designer.*simulation\///g;
$liy =~ s/$eta/$eta\_questa/g;
#enprime SOTIFILE "$liy \n";
if ($line =~ m/vmap\s+.*($actel_family)/)
{
enprime SOTIFILE “vmap $actel_family \”$lib_location\”\n”;
} elsif ($line =~ m/vmap\s+(.*._LIB)/)
{
$line =~ s/..\/component/..\/..\/component/g;
enprime SOTIFILE "$liy \n";
} elsif ($line =~ m/vsim/)
{
$line =~ s/vsim/vsim -novopt/g;
enprime SOTIFILE "$liy \n";
} Lòt bagay
{
enprime SOTIFILE "$liy \n";
}
}
fèmen (nanFILE);
fèmen (SOTIFILE);
} lòt bagay {
enprime "$ModelSim_run_do pa egziste. Rerun simulation ankò \n”;
}
}

Cadence Xcelium Enstalasyon (Login Microchip)

Ou bezwen kreye yon script file menm jan ak ModelSim ME/ModelSim Pro ME run.do pou kouri similatè Cadence Xcelium la. Swiv etap sa yo epi kreye script file pou Xcelium oswa itilize script la file bay pou konvèti ModelSim ME/ModelSim Pro ME run.do files nan konfigirasyon an fileyo bezwen kouri simulation lè l sèvi avèk Xcelium.
4.1 Varyab anviwònman yo (Poze yon Kesyon)
Pou kouri Cadence Xcelium, konfigirasyon varyab anviwònman sa yo:

LM_LICENSE_FILE: dwe genyen yon pwent sou lisans lan file.
cds_root: dwe lonje dwèt sou kote anyè lakay Cadence Incisive Installation.
PATH: dwe lonje dwèt sou kote bin la anba anyè zouti ki pwente pa cds_root (sa vle di
$cds_root/tools/bin/64bit (pou yon machin 64 bit ak $cds_root/tools/bin pou yon 32 bit
machin).

Gen twa fason pou mete anviwònman simulation nan ka ta gen yon chanjman ant sistèm operasyon 64-bit ak 32-bit:
Ka 1: PATH Varyab
mete chemen = (install_dir/tools/bin/64bit $path) pou machin 64bit ak
mete chemen = (install_dir/tools/bin $path) pou machin 32bit
Ka 2: Sèvi ak Opsyon Liy Kòmandman -64bit la
Nan liy lòd la presize opsyon -64bit yo nan lòd yo envoke ègzèkutabl 64-bit la.
Ka 3: Mete varyab anviwònman INCA_64BIT oswa CDS_AUTO_64BIT
Varyab INCA_64BIT la trete kòm booleyen. Ou ka mete varyab sa a nan nenpòt ki valè oswa nan yon nil
fisèl.
setenv INCA_64BIT

Enpòtan: la Varyab anviwònman INCA_64BIT pa afekte lòt zouti Cadence, tankou zouti IC. Sepandan, pou zouti Incisive, varyab INCA_64BIT an ranvwaye paramèt pou varyab anviwònman CDS_AUTO_64BIT la. Si varyab anviwònman INCA_64BIT la se et, tout zouti Incisive kouri nan mòd 64-bit.
setenv CDS_AUTO_64BIT INCLUDE:INCA
Enpòtan: la fisèl INCA dwe an majiskil. Tout ègzèkutabl yo dwe kouri swa nan mòd 2-bit oswa nan mòd 64-bit, pa mete varyab la pou enkli yon sèl ègzèkutabl, tankou nan sa ki annapre yo:
setenv CDS_AUTO_64BIT INCLUDE:ncelab
Lòt zouti Cadence, tankou zouti IC, sèvi ak varyab anviwònman CDS_AUTO_64BIT tou pou kontwole seleksyon ègzèkutabl 32-bit oswa 64-bit. Tablo ki anba la a montre kouman ou ka mete varyab CDS_AUTO_64BIT pou kouri zouti Incisive ak zouti IC nan tout mòd.

Tablo 4-1. CDS_AUTO_64BIT Varyab

CDS_AUTO_64BIT Varyab	Zouti ansidan	Zouti IC
setenv CDS_AUTO_64BIT TOUT	64-bit	64-bit
setenv CDS_AUTO_64BIT NON	32-bit	32-bit
setenv CDS_AUTO_64BIT EXCLUDE:ic_binary	64-bit	32-bit
setenv CDS_AUTO_64BIT EXCLUDE:INCA	32-bit	64-bit

Enpòtan: Tout zouti Incisive dwe kouri swa nan mòd 32-bit oswa nan mòd 64-bit, pa sèvi ak EXCLUDE pou eskli yon ègzèkutabl espesifik, tankou sa ki annapre yo:
setenv CDS_AUTO_64BIT EXCLUDE:ncelab
Si ou mete varyab CDS_AUTO_64BIT pou eskli zouti Incisive (setenv
CDS_AUTO_64BIT EXCLUDE:INCA), tout zouti Incisive yo kouri nan mòd 32-bit. Sepandan, la
-Opsyon liy kòmand 64bit pase sou varyab anviwònman an.
Konfigirasyon sa a files ede w jere done ou yo ak kontwole operasyon an nan zouti simulation ak sèvis piblik yo:

Kat jeyografik bibliyotèk file (cds.lib) defini yon non ki lojik pou kote konsepsyon ou a.
Bibliyotèk ak asosye yo ak non anyè fizik.

Varyab file (hdl.var) defini varyab ki afekte konpòtman zouti simulation ak sèvis piblik yo.

4.2 Telechaje bibliyotèk konpile (Poze yon Kesyon)
Telechaje bibliyotèk yo pou Cadence Xcelium nan Microsemi a websit.
4.3 Kreye script Xcelium la file (Poze yon Kesyon)
Apre kreye yon kopi run.do la files, fè etap sa yo pou kouri simulation ou a lè l sèvi avèk script Xcelium file.

Kreye yon cds.lib file ki defini ki bibliyotèk ki aksesib ak ki kote yo ye.
La file gen deklarasyon ki mete non bibliyotèk lojik nan chemen anyè fizik yo. Pou egzanpample, si w ap kouri simulation presynth, cds.lib la file ka ekri jan yo montre nan kodblock sa a.
DEFINI presinth ./presynth
DEFINI COREAHBLITE_LIB ./COREAHBLITE_LIB
DEFINI smartfusion2

Kreye yon hdl.var file ki se yon konfigirasyon opsyonèl file ki gen varyab konfigirasyon, ki detèmine ki jan anviwònman konsepsyon ou a se configuré. Men sa yo enkli:
– Varyab ke yo itilize pou presize bibliyotèk travay la kote konpilatè a estoke objè konpile ak lòt done ki sòti.
– Pou Verilog, varyab (LIB_MAP, VIEW_MAP, WORK) ki itilize pou presize bibliyotèk yo ak views pou chèche lè elaborateur a rezoud ka.
– Varyab ki pèmèt ou defini opsyon ak agiman pou konpilatè, elaboratè, ak similatè.
Nan ka simulation presynth example montre pi wo a, di nou gen 3 RTL files av, bv, ak testbench.v, ki bezwen konpile nan presynth, COREAHBLITE_LIB, ak presenth bibliyotèk respektivman. hdl.var la file ka ekri jan yo montre nan kodblock sa a.
DEFINI TRAVAY presinth
DEFINI PROJECT_DIR files>
DEFINI LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/av => present)
DEFINI LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/bv => COREAHBLITE_LIB)
DEFINI LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/testbench.v => presynth)
DEFINE LIB_MAP ($LIB_MAP, + => present)
Konpile konsepsyon an files itilize opsyon ncvlog.
xmvlog +incdir+ –cdslib ./cds.lib –hdlvar ./hdl.var –logfile
ncvlog.log –update –linedebug av bv testbench.v
Elabore konsepsyon an lè l sèvi avèk ncelab. Elaboratè a konstwi yon yerachi konsepsyon ki baze sou enstansyasyon ak enfòmasyon konfigirasyon nan konsepsyon an, etabli koneksyon siyal, epi kalkile valè inisyal pou tout objè nan konsepsyon an. Yerachi konsepsyon elabore a estoke nan yon snapshot simulation, ki se reprezantasyon konsepsyon ou ke similatè a itilize pou kouri simulation la.
Xcelium –Message –cdslib ./cds.lib –hdlvar ./hdl.var –logfile ncelab.log –errormax 15 –
aksè +rwc –status worklib. :modil
Elaborasyon pandan simulation Post-layout
Nan ka similasyon apre-layout, premye SDF la file bezwen konpile anvan élaboration lè l sèvi avèk lòd ncsdfc la.
Xceliumfilenon> .sdf – pèsistans yap ogmante jiskafilenon>.sdf.X
Pandan elaborasyon, sèvi ak pwodiksyon SDF konpile a ak opsyon –autosdf jan yo montre nan kòd kod sa a.
xmelab -autosdf –Mesaj –cdslib ./cds.lib –hdlvar ./hdl.var –logfile ncelab.log –errormax
15 –access +rwc –status worklib. :module –sdf_cmd_file ./
sdf_cmd_file
sdf_cmd_ lafile dwe jan yo montre nan kodblock sa a.
COMPILED_SDF_FILE = " file>"

Simile lè l sèvi avèk Xcelium. Apre elaborasyon yon snapshot simulation kreye ki chaje pa Xcelium pou simulation. Sa a ka kouri nan mòd pakèt oswa mòd entèfas.
xmsim –Mesaj –pakèt/-gui –cdslib ./cds.lib –hdlvar ./hdl.var –logfile xmsim.log –
errormax 15 -status worklib. :modil
Kadans Xcelium Enstalasyon
Enpòtan: Tout twa etap ki anwo yo nan konpile, elabore ak simulation ka mete nan yon script koki file ak soti nan liy lòd. Olye pou yo sèvi ak twa etap sa yo, konsepsyon ka simulation nan yon sèl etap lè l sèvi avèk ncverilog oswa opsyon xrun jan yo montre nan codeblock sa a.
xmverilog +incdir+ -cdslib ./cds.lib –hdlvar ./hdl.var
fileyo itilize nan konsepsyon an>
xrun +incdir+ -cdslib ./cds.lib –hdlvar ./hdl.var files
itilize nan konsepsyon an>

4.3.1 Pwoblèm li te ye (Poze yon Kesyon)
Testbench solisyon
Sèvi ak deklarasyon sa a pou espesifye frekans revèy la nan testbench ki te pwodwi pa itilizatè a oswa testbench default ki te pwodwi pa Libero SoC pa travay ak Xcelium.
toujou @(SYSCLK)
#(SYSCLK_PERIOD / 2.0) SYSCLK <= !SYSCLK;
Modifye jan sa a pou kouri simulation:
toujou #(SYSCLK_PERIOD / 2.0) SYSCLK = ~SYSCLK;

Enpòtan: Bibliyotèk konpile pou Xcelium yo se platfòm espesifik (sa vle di bibliyotèk 64 bit yo pa konpatib ak platfòm 32 bit ak vis vèrsa).
Simulasyon Postsynth ak Post-layout lè l sèvi avèk MSS ak SERDES
Pandan y ap fè simulation postsynth nan desen ki gen blòk MSS, oswa apre-layout simulation nan desen lè l sèvi avèk SERDES, simulation BFM yo pa travay si opsyon -libmap pa espesifye pandan elaborasyon. Sa a se paske pandan elaborasyon, MSS rezoud nan bibliyotèk travay la (paske nan obligatwa nan default ak worklib la ap postsynth / post-layout) kote li se jis yon Fonksyon fiks.
Kòmandman ncelab la dwe ekri jan yo montre nan blòk kòd sa a pou rezoud blòk MSS ki soti nan bibliyotèk prekonpile SmartFusion2 la.
xmelab -libmap lib.map -libverbose -Message -access +rwc cfg1
ak lib.map la file dwe jan sa a:
konfigirasyon cfg1;
konsepsyon ;
default liblist smartfusion2 ;
endconfig
Sa a dwe rezoud nenpòt selil nan bibliyotèk SmartFusion2 la anvan ou gade nan bibliyotèk travay la sa vle di postsynth/post-layout.
Opsyon –libmap la ka itilize pa default pandan elaborasyon pou chak simulation (presynth, postsynth ak post-layout). Sa a evite pwoblèm simulation ki te koze akòz rezolisyon ka nan bibliyotèk yo.
xmelab: *F,INTERR: EKSEPSYON INTERN
Eksepsyon zouti ncelab sa a se yon opozisyon pou desen ki gen FDDR nan SmartFusion2 ak IGLOO2.
pandan simulation postsynth ak post-layout lè l sèvi avèk opsyon -libmap.
Enpòtan: Yo rapòte pwoblèm sa a bay ekip sipò Cadence (SAR 52113).

4.4 Sample Tcl ak script shell files (Poze yon Kesyon)
Sa ki annapre yo files yo se konfigirasyon an files nesesè pou mete sou pye konsepsyon an ak script koki file pou kouri kòmandman Xcelium.
Cds.lib
DEFINI smartfusion2 /scratch/krydor/tmpspace/users/me/nc-vlog64/SmartFusion2
DEFINI COREAHBLITE_LIB ./COREAHBLITE_LIB
DEFINI presinth ./presynth
Hdl.var
DEFINI TRAVAY presinth
DEFINE PROJECT_DIR /scratch/krydor/tmpspace/sqausers/me/3rd_party_simulators/Cadence/IGLOO2/
ENVM/M2GL050/envm_fic1_ser1_v/eNVM_fab_master
DEFINI LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/core/coreahblite_addrdec.v => COREAHBLITE_LIB )
DEFINI LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/core/coreahblite_defaultslavesm.v => COREAHBLITE_LIB )
DEFINI LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/core/coreahblite_masterstagev => COREAHBLITE_LIB )
DEFINI LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/core/coreahblite_slavearbiter.v => COREAHBLITE_LIB )
DEFINI LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/core/coreahblite_slavestagev => COREAHBLITE_LIB )
DEFINI LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/core/coreahblite_matrix2x16.v => COREAHBLITE_LIB )
DEFINI LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/
vlog/core/coreahblite.v => COREAHBLITE_LIB )
DEFINI LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB/CCC_0/SB_CCC_0_FCCC.v =>
presint)
DEFINI LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreConfigMaster/
2.0.101/rtl/vlog/core/coreconfigmaster.v => present)
DEFINI LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreConfigP/4.0.100/rtl/
vlog/core/coreconfigp.v => present )
DEFINI LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreResetP/5.0.103/rtl/
vlog/core/coreresetp_pcie_hotreset.v => present )
DEFINI LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreResetP/5.0.103/rtl/
vlog/core/coreresetp.v => present )
DEFINI LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB/FABOSC_0/SB_FABOSC_0_OSC.v =>
presint)
DEFINI LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/component/work/SB_HPMS/SB_HPMS.v => presynth)
DEFINI LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/component/work/SB/SB.v => presynth)
DEFINI LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/component/work/SB_top/SERDES_IF_0/
SB_top_SERDES_IF_0_SERDES_IF.v => present )
DEFINI LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/component/work/SB_top/SB_top.v => present)
DEFINI LIB_MAP ($LIB_MAP, ${PROJECT_DIR}/component/work/SB_top/testbench.v => presynth)
DEFINE LIB_MAP ($LIB_MAP, + => present)
Commands.csh
ncvlog +incdir+../../component/work/SB_top -cdslib ./cds.lib -hdlvar ./hdl.var -logfile
ncvlog.log -errormax 15 -update -linedebug
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite_addrdec.v
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/
coreahblite_defaultslavesm.v
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite_masterstagev
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite_slavearbiter.v
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite_slavestagev
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite_matrix2x16.v
../../component/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite.v
../../component/work/SB/CCC_0/SB_CCC_0_FCCC.v
../../component/Actel/DirectCore/CoreConfigMaster/2.0.101/rtl/vlog/core/coreconfigmaster.v
../../component/Actel/DirectCore/CoreConfigP/4.0.100/rtl/vlog/core/coreconfigp.v
../../component/Actel/DirectCore/CoreResetP/5.0.103/rtl/vlog/core/coreresetp_pcie_hotreset.v
../../component/Actel/DirectCore/CoreResetP/5.0.103/rtl/vlog/core/coreresetp.v
../../component/work/SB/FABOSC_0/SB_FABOSC_0_OSC.v ../../component/work/SB_HPMS/SB_HPMS.v
../../component/work/SB/SB.v ../../component/work/SB_top/SERDES_IF_0/
SB_top_SERDES_IF_0_SERDES_IF.v
../../component/work/SB_top/SB_top.v ../../component/work/SB_top/testbench.v
ncelab -Message -cdslib ./cds.lib -hdlvar ./hdl.var
-travay presinth -logfile ncelab.log -errormax 15 -access +rwc -status presynth.testbench:module
ncsim -Message -batch -cdslib ./cds.lib -hdlvar ./
hdl.var -logfile ncsim.log -errormax 15 -status presynth.testbench:modil

4.5 Otomatik (Login Microchip)
Script sa a file konvèti ModelSim run.do files nan konfigirasyon fileyo bezwen kouri simulation lè l sèvi avèk Xcelium.
Script File Itilizasyon
perl cadence_parser.pl presynth_run.do postsynth_run.do
postlayout_run.do Microsemi_Family
Kote_Bibliyotèk_Kadans_Prekonpile
Cadence_parser.pl
#!/usr/bin/perl -w

&questa_parser($postlayout, $family, $lib_location);
sub questa_parser {
mwen $ModelSim_run_do = $_[0];
my $actel_family = $_[1];
mwen $lib_location = $_[2];
$eta mwen;
si (-e "$ModelSim_run_do")
{
louvri (INFILE,”$ModelSim_run_do”);
mwen @ModelSim_run_do =FILE>;
$line mwen an;
si ($ModelSim_run_do =~ m/(presynth)/)
{
`mkdir QUESTA_PRESYNTH`;
louvri (SOTIFILE,”>QUESTA_PRESYNTH/presynth_questa.do”);
$eta = $1;
} elsif ($ModelSim_run_do =~ m/(postsynth)/)
{
`mkdir QUESTA_POSTSYNTH`;
louvri (SOTIFILE,”>QUESTA_POSTSYNTH/postsynth_questa.do”);
$eta = $1;
} elsif ($ModelSim_run_do =~ m/(postlayout)/)
{
`mkdir QUESTA_POSTLAYOUT`;
louvri (SOTIFILE,”>QUESTA_POSTLAYOUT/postlayout_questa.do”);
$eta = $1;
} Lòt bagay
{
enprime “Wrong inputs bay to the file\n”;
enprime "#Usage: perl questa_parser.pl presynth_run.do postsynth_run.do postlayout_run.do
\”Kote_Bibliyotèk\”\n”;
}
foreach $line (@ModelSim_run_do)
{
# Operasyon Jeneral
$line =~ s/..\/designer.*simulation\///g;
$liy =~ s/$eta/$eta\_questa/g;
#enprime SOTIFILE "$liy \n";
if ($line =~ m/vmap\s+.*($actel_family)/)
{
enprime SOTIFILE “vmap $actel_family \”$lib_location\”\n”;
} elsif ($line =~ m/vmap\s+(.*._LIB)/)
{
$line =~ s/..\/component/..\/..\/component/g;
enprime SOTIFILE "$liy \n";
} elsif ($line =~ m/vsim/)
{
$line =~ s/vsim/vsim -novopt/g;
enprime SOTIFILE "$liy \n";
} Lòt bagay
{
enprime SOTIFILE "$liy \n";
}
}
fèmen (nanFILE);
fèmen (SOTIFILE);
} lòt bagay {
enprime "$ModelSim_run_do pa egziste. Rerun simulation ankò \n”;
}
}

Siemens QuestaSim Setup/ModelSim Setup (Poze yon Kesyon)

Kouri a.fè files, ki te pwodwi pa Libero SoC pou simulation lè l sèvi avèk ModelSim Microsemi Editions, ka itilize pou simulation lè l sèvi avèk QuestaSim/ModelSim SE/DE/PE ak yon chanjman sèl. Nan ModelSim ME/ModelSim Pro ME run.do file, kote bibliyotèk yo prekonpile yo bezwen modifye.
Enpòtan:
Pa default, zouti simulation ki pa ModelSim Pro ME fè optimize konsepsyon pandan simulation ki ka afekte vizibilite nan zafè simulation tankou objè konsepsyon ak estimilis opinyon.
Sa a se tipikman itil nan diminye ègzekutabl simulation pou simulation konplèks yo, lè l sèvi avèk pwolib, oto-tcheke tèsbanch. Sepandan, optimize default yo ta ka pa apwopriye pou tout simulation, espesyalman nan ka kote ou espere grafikman enspekte rezilta simulation yo lè l sèvi avèk fenèt la vag.
Pou rezoud pwoblèm ki te koze pa optimize sa a, ou dwe ajoute kòmandman apwopriye ak agiman ki gen rapò pandan simulation pou retabli vizibilite nan konsepsyon an. Pou kòmandman zouti espesifik yo, gade dokiman ki nan similatè a nan itilize.

5.1 Varyab anviwònman yo (Poze yon Kesyon)
Sa yo se varyab anviwònman ki nesesè yo.

LM_LICENSE_FILE: dwe gen ladann chemen pou lisans lan file.
MODEL_TECH: dwe idantifye chemen an nan kote anyè lakay enstalasyon QuestaSim.

PATH: dwe lonje dwèt sou kote ègzekutabl la montre pa MODEL_TECH.

5.2 Konvèti run.do pou Mentor QuestaSim (Poze yon Kesyon)
Kouri a.fè files ki te pwodwi pa Libero SoC pou simulation lè l sèvi avèk ModelSim Microsemi Editions ka itilize pou simulation lè l sèvi avèk QuestaSim/ModelSim_SE ak yon sèl chanjman.
Enpòtan: Tout desen yo ki similye lè l sèvi avèk QuestaSim dwe gen ladan -novopt
opsyon ansanm ak kòmand vsim nan run.do script la files.
5.3 Telechaje Bibliyotèk Konpile a (Poze yon Kesyon)
Telechaje bibliyotèk yo pou Mentor Graphics QuestaSim soti nan Microsemi a websit.

Synopsys VCS Enstalasyon (Poze yon Kesyon)

Koule a rekòmande pa Microsemi depann sou koule nan Elaborate ak Konpile nan VCS. Dokiman sa a gen ladan l yon script file ki itilize script run.do la files ki te pwodwi pa Libero SoC ak jenere konfigirasyon an files nesesè pou VCS simulation. Script la file itilize kouri a.do file fè sa ki annapre yo.

Kreye yon kat bibliyotèk file, ki fè lè l sèvi avèk synopsys_sim.setup la file sitiye nan menm anyè kote VCS simulation ap kouri.
Kreye yon script shell file pou elabore ak konpile konsepsyon ou lè l sèvi avèk VCS.

6.1 Varyab anviwònman yo (Poze yon Kesyon)
Mete varyab anviwònman ki apwopriye pou VCS ki baze sou konfigirasyon w la. Varyab anviwònman ki nesesè dapre dokiman VCS yo se:

LM_LICENSE_FILE: dwe genyen yon pwent sou sèvè lisans lan.
VCS_HOME: dwe lonje dwèt sou kote anyè lakay enstalasyon VCS la.
PATH: dwe gen ladann yon konsèy sou anyè bin ki anba a anyè VCS_HOME.

6.2 Telechaje bibliyotèk konpile (Poze yon Kesyon)
Telechaje bibliyotèk yo pou Synopsys VCS soti nan Microsemi a websit.
6.3 Script simulation VCS File (Poze yon Kesyon)
Apre mete kanpe VCS ak jenere konsepsyon an ak diferan run.do la files soti nan Libero SoC, ou dwe:

Kreye kat bibliyotèk la file synopsys_sim.setup; sa a file gen endikasyon sou kote tout bibliyotèk yo dwe itilize pa konsepsyon an.
Enpòtan: la file non pa dwe chanje epi li dwe lokalize nan menm anyè kote simulation ap kouri. Isit la se yon ansyenample pou tankou yon file pou simulation presintèz.
TRAVAY > EFAULT
SmartFusion2:
presinth : ./presynth
DEFAULT: ./travay
Elabore diferan konsepsyon an files, ki gen ladan testbench la, lè l sèvi avèk lòd la vlogan nan VCS. Kòmandman sa yo ka enkli nan yon script shell file. Swivan se yon ansyenampkòmandman ki nesesè pou elabore yon konsepsyon ki defini nan rtl.v ak testbench li yo defini nan
tèsbanch.v.
vlogan +v2k -work presinth rtl.v
vlogan +v2k -work presynth testbench.v

Konpile konsepsyon an lè l sèvi avèk VCS lè l sèvi avèk kòmandman sa a.
vcs –sim_res=1fs presynth.testbench
Nòt: la rezolisyon distribisyon simulation dwe mete sou 1fs pou simulation fonksyonèl kòrèk.
Yon fwa ke konsepsyon an konpile, kòmanse simulation lè l sèvi avèk lòd sa a.
./simv
Pou simulation back-anote, lòd VCS la dwe jan yo montre nan kodblock sa a.
vcs postlayout.testbench –sim_res=1fs –sdf max: .
non>: file chemen> –gui –l postlayout.log

6.4 Limit/Esepsyon (Poze yon Kesyon)
Sa ki anba yo se limit/eksepsyon nan konfigirasyon Synopsys VCS.

Similyasyon VCS yo ka kouri sèlman pou pwojè Verilog nan Libero SoC. Similatè VCS a gen egzijans strik langaj VHDL ki pa satisfè pa Libero SoC oto-jenere VHDL la. files.
Ou dwe gen yon deklarasyon $finish nan Verilog testbench la pou sispann simulation chak fwa ou vle.
Enpòtan: Lè simulation yo kouri nan mòd entèfas, tan kouri ka espesifye nan entèfas la.

6.5 Sample Tcl ak Shell Script Files (Poze yon Kesyon)
Perl sa a otomatize jenerasyon synopsys_sim.setup la file osi byen ke script koki ki koresponn lan files bezwen elabore, konpile, ak simulation konsepsyon an.
Si konsepsyon an sèvi ak yon MSS, kopye test.vec la file ki sitiye nan katab la simulation nan pwojè Libero SoC nan katab la simulation VCS. Seksyon sa yo genyen sample run.do files ki te pwodwi pa Libero SoC, ki gen ladan kat bibliyotèk korespondan ak script shell files nesesè pou VCS simulation.
6.5.1 Pre-sentèz (Poze yon Kesyon)
Presynth_run.do
tou dousman mete ACTELLIBNAME SmartFusion2
tou dousman mete PROJECT_DIR "/sqa/users/me/VCS_Tests/Test_DFF"
si {[file egziste presynth/_info]} {
eko "INFO: Presynth bibliyotèk simulation deja egziste"
} lòt bagay {
vlib presinth
}
vmap presynth presynth
vmap SmartFusion2 “/captures/lin/11_0_0_23_11prod/lib/ModelSim/precompiled/vlog/smartfusion2”
vlog -work presynth "${PROJECT_DIR}/component/work/SD1/SD1.v"
vlog "+incdir+${PROJECT_DIR}/stimulus" -travay presynth "${PROJECT_DIR}/stimulus/SD1_TB1.v"
vsim -L SmartFusion2 -L presynth -t 1fs presynth.SD1_TB1
ajoute vag /SD1_TB1/*
ajoute log -r /*
kouri 1000ns
presinth_main.csh
#!/bin/csh -f
mete PROJECT_DIR = "/sqa/users/Me/VCS_Tests/Test_DFF"
/cad_design/tools/vcs.dir/E-2011.03/bin/vlogan +v2k -work presynth "${PROJECT_DIR}/component/
travay/SD1/SD1.v”
/cad_design/tools/vcs.dir/E-2011.03/bin/vlogan +v2k "+incdir+${PROJECT_DIR}/stimulus" -travay
present "${PROJECT_DIR}/stimulus/SD1_TB1.v"
/cad_design/tools/vcs.dir/E-2011.03/bin/vcs -sim_res=1fs presynth.SD1_TB1 -l compile.log
./simv -l run.log
Synopsys_sim.setup
TRAVAY > DEFAULT
SmartFusion2 : /VCS/SmartFusion2
presinth : ./presynth
DEFAULT: ./travay

6.5.2 Post-sentèz (Poze yon Kesyon)
postsynth_run.do
tou dousman mete ACTELLIBNAME SmartFusion2
tou dousman mete PROJECT_DIR "/sqa/users/Me/VCS_Tests/Test_DFF"
si {[file egziste postsynth/_info]} {
eko "INFO: Postsynth bibliyotèk simulation deja egziste"
} lòt bagay {
vlib postsynth
}
vmap postsynth postsynth
vmap SmartFusion2 “//idm/captures/pc/11_0_1_12_g4x/Designer/lib/ModelSim/precompiled/vlog/
SmartFusion2"
vlog -work postsynth "${PROJECT_DIR}/synthesis/SD1.v"
vlog "+incdir+${PROJECT_DIR}/stimulus" -travay postsynth "${PROJECT_DIR}/stimulus/SD1_TB1.v"
vsim -L SmartFusion2 -L postsynth -t 1fs postsynth.SD1_TB1
ajoute vag /SD1_TB1/*
ajoute log -r /*
kouri 1000ns
journal SD1_TB1/*
sòti
Postsynth_main.csh
#!/bin/csh -f
mete PROJECT_DIR = "/sqa/users/Me/VCS_Tests/Test_DFF"
/cad_design/tools/vcs.dir/E-2011.03/bin/vlogan +v2k -work postsynth “${PROJECT_DIR}/synthesis/
SD1.v"
/cad_design/tools/vcs.dir/E-2011.03/bin/vlogan +v2k "+incdir+${PROJECT_DIR}/stimulus" -travay
postsynth "${PROJECT_DIR}/stimulus/SD1_TB1.v"
/cad_design/tools/vcs.dir/E-2011.03/bin/vcs -sim_res=1fs postsynth.SD1_TB1 -l compile.log
./simv -l run.log
Synopsys_sim.setup
TRAVAY > DEFAULT
SmartFusion2 : /VCS/SmartFusion2
postsynth : ./postsynth
DEFAULT: ./travay
6.5.3 Post-layout (Poze yon Kesyon)
postlayout_run.do
tou dousman mete ACTELLIBNAME SmartFusion2
tou dousman mete PROJECT_DIR "E:/ModelSim_Work/Test_DFF"
si {[file egziste ../designer/SD1/simulation/postlayout/_info]} {
eko "INFO: Bibliyotèk simulation ../designer/SD1/simulation/postlayout deja egziste"
} lòt bagay {
vlib ../designer/SD1/simulation/postlayout
}
vmap postlayout ../designer/SD1/simulation/postlayout
vmap SmartFusion2 “//idm/captures/pc/11_0_1_12_g4x/Designer/lib/ModelSim/precompiled/vlog/
SmartFusion2"
vlog -work postlayout "${PROJECT_DIR}/designer/SD1/SD1_ba.v"
vlog "+incdir+${PROJECT_DIR}/stimulus" -work postlayout "${PROJECT_DIR}/stimulus/SD1_TB1.v"
vsim -L SmartFusion2 -L postlayout -t 1fs -sdfmax /SD1_0=${PROJECT_DIR}/designer/SD1/
SD1_ba.sdf postlayout.SD1_TB1
ajoute vag /SD1_TB1/*
ajoute log -r /*
kouri 1000ns
Postlayout_main.csh
#!/bin/csh -f
mete PROJECT_DIR = "/VCS_Tests/Test_DFF"
/cad_design/tools/vcs.dir/E-2011.03/bin/vlogan +v2k -work postlayout “${PROJECT_DIR}/
designer/SD1/SD1_ba.v”
/cad_design/tools/vcs.dir/E-2011.03/bin/vlogan +v2k "+incdir+${PROJECT_DIR}/stimulus" -travay
postlayout "${PROJECT_DIR}/stimulus/SD1_TB1.v"
/cad_design/tools/vcs.dir/E-2011.03/bin/vcs -sim_res=1fs postlayout.SD1_TB1 -sdf

max:SD1_TB1.SD1_0:${PROJECT_DIR}/designer/SD1/SD1_ba.sdf -l compile.log
./simv -l run.log
Synopsys_sim.setup
TRAVAY > DEFAULT
SmartFusion2 : /VCS/SmartFusion2
postlayout : ./postlayout
DEFAULT : ./workVCS
6.6 Otomatik (Poze yon Kesyon)
Koule a ka otomatize lè l sèvi avèk script Perl sa a file pou konvèti ModelSim run.do files nan script shell konpatib VCS files, kreye repèrtwar apwopriye andedan anyè simulation Libero SoC, epi answit kouri simulation.
Kouri script la file lè l sèvi avèk sentaks sa a.
perl vcs_parse.pl presynth_run.do postsynth_run.do postlayout_run.do
Vcs_parse_pl
#!/usr/bin/perl -w
###################################################### ############################
#
#Usage: perl vcs_parse.pl presynth_run.do postsynth_run.do postlayout_run.do
#
###################################################### #############################
mwen ($presynth, $postsynth, $postlayout) = @ARGV;
si(sistèm ("mkdir VCS_Presynth")) {enprime "mkdir echwe:\n";}
si(sistèm ("mkdir VCS_Postsynth")) {enprime "mkdir echwe:\n";}
si(sistèm ("mkdir VCS_Postlayout")) {enprime "mkdir echwe:\n";}
chdir(VCS_Presynth);
`cp ../$ARGV[0] .` ;
&parse_do($presynth,”presynth”);
chdir ("../");
chdir(VCS_Postsynth);
`cp ../$ARGV[1] .` ;
&parse_do($postsynth,”postsynth”);
chdir ("../");
chdir(VCS_Postlayout);
`cp ../$ARGV[2] .` ;
&parse_do($postlayout,”postlayout”);
chdir ("../");
sub parse_do {
mwen $vlog = "/cad_design/tools/vcs.dir/E-2011.03/bin/vlogan +v2k" ;
%LIB mwen = ();
$ mwenfile = $_[0] ;
mwen $eta = $_[1];
louvri (INFILE,”$file» || mouri "Pa ka louvri File Rezon ki fè yo ta ka: $!”;
if ($state eq "presynth")
{
louvri(OUT1,”>presynth_main.csh”) || mouri "Pa ka kreye kòmandman File Rezon ki fè yo ta ka: $!”;
}
elsif ($state eq “postsynth”)
{
louvri(OUT1,”>postsynth_main.csh”) || mouri "Pa ka kreye kòmandman File Rezon ki fè yo ta ka: $!”;
}
elsif ($state eq “postlayout”)
{
louvri(OUT1,”>postlayout_main.csh”) || mouri "Pa ka kreye kòmandman File Rezon ki fè yo ta ka: $!”;
}
lòt bagay
{
enprime "Eta simulation manke \n" ;
}
louvri(OUT2,”>synopsys_sim.setup”) || mouri "Pa ka kreye kòmandman File Rezon ki fè yo ta ka: $!”;
# .csh file
enprime OUT1 "#!/bin/csh -f\n\n\n" ;
#SET UP FILE
enprime OUT2 "TRAVAY > DEFAULT\n" ;
enprime OUT2 "SmartFusion2: /sqa/users/Aditya/VCS/SmartFusion2\n";
pandan ($liy =FILE>)
{

Enstalasyon Synopsys VCS

if ($liy =~ m/touman mete PROJECT_DIR\s+\”(.*?)\”/)
{
enprime OUT1 "set PROJECT_DIR = \"$1\"\n\n\n" ;
}
elsif ($liy =~ m/vlog.*\.v\”/ )
{
si ($liy =~ m/\s+(\w*?)\_LIB/)
{
#print “\$1 =$1 \n” ;
$temp = “$1″.”_LIB”;
#print "Temp = $temp \n" ;
$LIB{$temp}++;
}
chomp($line);
$liy =~ s/^vlog/$vlog/ ;
$liy =~ s/ //g;
enprime OUT1 "$line\n";
}
elsif (($line =~ m/vsim.*presynth\.(.*)/) || ($line =~ m/vsim.*postsynth\.(.*)/) || ($line
=~ m/vsim.*postlayout\.(.*)/) )
{
$tb = $1 ;
$tb =~ s/ //g;
chomp($tb);
#print "Non TB: $tb \n";
si ($liy =~ m/sdf(.*)\.sdf/)
{
chomp($line);
$liy = $1 ;
#print “LINE : $line \n” ;
si ($liy =~ m/max/)
{
$line =~ s/max \/// ;
$liy =~ s/=/:/;
enprime OUT1 "\n\n/cad_design/tools/vcs.dir/E-2011.03/bin/vcs -sim_res=1fs postlayout.$tb -sdf
max:$tb.$line.sdf -l compile.log\n” ;
}
elsif ($line =~ m/min/)
{
$liy =~ s/min \/// ;
$liy =~ s/=/:/;
enprime OUT1 "\n\n/cad_design/tools/vcs.dir/E-2011.03/bin/vcs -sim_res=1fs postlayout.$tb -sdf
min:$tb.$line.sdf -l compile.log\n” ;
}
elsif ($liy =~ m/tip/)
{
$liy =~ s/tip \/// ;
$liy =~ s/=/:/;
enprime OUT1 "\n\n/cad_design/tools/vcs.dir/E-2011.03/bin/vcs -sim_res=1fs postlayout.$tb -sdf
typ:$tb.$line.sdf -l compile.log\n” ;
}
#-sdfmax /M3_FIC32_0=${PROJECT_DIR}/designer/M3_FIC32/M3_FIC32_ba.sdf — Fòma ModelSim SDF
#$sdf = "-sdf max:testbench.M3_FIC32_0:${PROJECT_DIR}/designer/M3_FIC32/M3_FIC32_ba.sdf"; -VCS
Fòma SDF
}
}
}
enprime
OUT1 "\n\n"
;
if
( $state eq "presynth"
)
{
enprime
OUT2 “presynth
: ./presynth\n”
;
enprime
OUT1 "/cad_design/tools/vcs.dir/E-2011.03/bin/vcs
-sim_res=1fs presinth.$tb -l
compile.log\n”
;
}
elsif
( $state eq "postsynth"
)
{
enprime
OUT2 “postsynth
: ./postsynth\n”
;
enprime
OUT1 "/cad_design/tools/vcs.dir/E-2011.03/bin/vcs
-sim_res=1fs postsynth.$tb -l
compile.log\n”
;
}
elsif
( $state eq "postlayout"
)
{
enprime OUT2 "postlayout: ./postlayout\n" ;
}
lòt bagay
{
enprime "Eta simulation manke \n" ;
}
foreach $i ( kle %LIB)
{
#print “Kle : $i Valè : $LIB{$i} \n” ;
enprime OUT2 "$i : ./$i\n" ;
}
enprime OUT1 "\n\n" ;
enprime OUT1 "./simv -l run.log\n" ;
enprime OUT2 "DEFAULT: ./travay\n" ;
fèmen NANFILE;
fèmen OUT1;
fèmen OUT2;
}

Istwa revizyon (Login Microchip

Istwa revizyon an dekri chanjman ki te aplike nan dokiman an. Chanjman yo
yo make pa revizyon, kòmanse ak piblikasyon ki pi aktyèl la.

Revizyon	Dat	Deskripsyon
A	12/2023	Chanjman sa yo fèt nan revizyon sa a: • Dokiman konvèti nan modèl Microchip. Premye revizyon. • Mete ajou seksyon 5. Siemens QuestaSim Setup/ModelSim Setup pou mete yon nouvo nòt ki eksplike enpak sou vizibilite pandan simulation ak optimize.

Sipò pou Microchip FPGA
Gwoup pwodwi Microchip FPGA apiye pwodwi li yo ak plizyè sèvis sipò, tankou Sèvis Kliyan, Sant Sipò Teknik Kliyan, yon websit, ak biwo lavant atravè lemond.
Yo sijere kliyan yo vizite resous sou entènèt Microchip yo anvan yo kontakte sipò paske li gen anpil chans pou kesyon yo te deja reponn.
Kontakte Sant Sipò Teknik atravè websit nan www.microchip.com/support. Mansyone nimewo Pati Aparèy FPGA la, chwazi kategori ka ki apwopriye a, epi telechaje konsepsyon an files pandan y ap kreye yon ka sipò teknik.
Kontakte Sèvis Kliyan pou sipò pwodwi ki pa teknik, tankou pri pwodwi, amelyorasyon pwodwi, enfòmasyon aktyalizasyon, estati lòd, ak otorizasyon.

Soti nan Amerik di Nò, rele 800.262.1060
Soti nan rès mond lan, rele 650.318.4460

Fakse, nenpòt kote nan mond lan, 650.318.8044

Enfòmasyon sou Microchip
Microchip la Websit
Microchip bay sipò sou entènèt atravè nou an websit nan www.microchip.com/. Sa a websit ki itilize pou fè files ak enfòmasyon fasil disponib pou kliyan. Gen kèk nan kontni ki disponib yo enkli:

Sipò pou pwodwi - Done fèy ak errata, nòt aplikasyon ak sample pwogram, resous konsepsyon, gid itilizatè a ak dokiman sipò pyès ki nan konpitè, dènye degaje lojisyèl ak lojisyèl achiv

Sipò teknik jeneral - Kesyon yo poze souvan (FAQs), demann sipò teknik, gwoup diskisyon sou entènèt, lis manm pwogram patnè konsepsyon Microchip.
Biznis Microchip - Seleksyon pwodwi ak gid kòmande, dènye communiqués pou laprès Microchip, lis seminè ak evènman, lis biwo lavant Microchip, distribitè ak reprezantan faktori.

Sèvis Notifikasyon Chanjman pwodwi
Sèvis notifikasyon chanjman pwodwi Microchip la ede kenbe kliyan yo kouran sou pwodwi Microchip yo. Abònen yo pral resevwa yon notifikasyon imel chak fwa gen chanjman, mizajou, revizyon oswa erè ki gen rapò ak yon fanmi pwodwi espesifik oswa zouti devlopman ki enterese yo.
Pou anrejistre, ale nan www.microchip.com/pcn epi swiv enstriksyon enskripsyon yo.
Sipò pou Kliyan
Itilizatè pwodwi Microchip ka resevwa asistans atravè plizyè chanèl:

Distribitè oswa Reprezantan
Biwo Komèsyal Lokal
Enjenyè solisyon entegre (ESE)

Sipò teknik

Kliyan yo ta dwe kontakte distribitè yo, reprezantan yo oswa ESE pou jwenn sipò. Biwo lavant lokal yo disponib tou pou ede kliyan yo. Yon lis biwo lavant ak lokal yo enkli nan dokiman sa a.
Gen sipò teknik ki disponib atravè la websit nan: www.microchip.com/support
Aparèy Microchip Kòd Pwoteksyon Karakteristik
Remake detay sa yo sou karakteristik pwoteksyon kòd sou pwodwi Microchip:

Pwodwi Microchip satisfè espesifikasyon yo nan Fich Done Microchip yo.

Microchip kwè ke fanmi li nan pwodwi yo an sekirite lè yo itilize nan fason ki gen entansyon an, nan espesifikasyon opere, ak nan kondisyon nòmal.
Microchip valè ak agresif pwoteje dwa pwopriyete entelektyèl li yo. Tantativ pou vyole karakteristik pwoteksyon kòd nan pwodwi Microchip se entèdi entèdi epi yo ka vyole Digital Millennium Copyright Act.
Ni Microchip ni okenn lòt manifakti semi-conducteurs ka garanti sekirite kòd li a. Pwoteksyon Kòd pa vle di ke nou garanti pwodwi a se "ki pa ka kase".
Pwoteksyon Kòd toujou ap evolye. Microchip pran angajman pou li kontinye amelyore karakteristik pwoteksyon kòd pwodwi nou yo.

Avi Legal
Piblikasyon sa a ak enfòmasyon ki ladan l yo ka itilize sèlman ak pwodwi Microchip, tankou pou konsepsyon, teste, ak entegre pwodwi Microchip ak aplikasyon w lan. Sèvi ak enfòmasyon sa yo nan nenpòt lòt fason vyole kondisyon sa yo. Enfòmasyon konsènan aplikasyon pou aparèy yo bay sèlman pou konvenyans ou epi yo ka ranplase pa mizajou. Se responsablite w pou asire ke aplikasyon w lan satisfè espesifikasyon w yo. Kontakte biwo lavant Microchip lokal ou a pou plis sipò oswa, jwenn plis sipò nan www.microchip.com/en-us/support/design-help/client-support-services.
ENFÒMASYON SA A SE MICROCHIP "KÒM YO". MICROCHIP PA FÈ OKENN REPREZANTASYON OUBYEN GARANTI KI KIT EXPRESSO BYEN ENPLIKITE, EKRI OUBYEN ORAL, LEGAL OSWA ONYÈ, KI GENYEN AK ENFÒMASYON YO KI GENYEN MEN PA LIMITE A NENPÒT GARANTI ENPLIKITE SOU KI PA Vyolasyon, Komèsyal ak PATISIBILITE, AK PATISIBILITE. GARANTI KI GENYEN AK KONDISYON, KALITE, OSWA PERFORMANS LI.
MICROCHIP PAP RESPONSABLE POU NENPÒT PÈT ENDRÈK, ESPESYAL, PINITIF, AK ENSEDAN, OSWA KONSEKANS, DOGAJ, PRI, OSWA DEPANS KI GENYEN KELÈ AK ENFÒMASYON AN OSWA ITILIZ YO, KELANSAN SA KOZE, MENM SI PWOFÈ SA A. POSIBILITE OSWA DOmaj YO PREVIVWA. NAN PWOFÈ LA LWA OBLÈ, RESPONSABILITE TOTAL MICROCHIP A SOU TOUT REKLAMASYON KI GENYEN KI GENYEN AK ENFÒMASYON AN OSWA ITILIZ YO PAP DEPASSE KANTITE FRÈ A, SI GEN GENYEN, OU TE PEYE DIRECTÈTMAN POU MICROCHIP POU ENFÒMASYON AN.
Itilizasyon aparèy Microchip nan aplikasyon pou sipò lavi ak/oswa sekirite se antyèman nan risk achtè a, epi achtè a dakò pou defann, dedomaje epi kenbe Microchip inonsan kont nenpòt ak tout domaj, reklamasyon, kostim, oswa depans ki soti nan itilizasyon sa a. Pa gen okenn lisans yo transmèt, implicitement oswa otreman, anba okenn dwa pwopriyete entelektyèl Microchip sof si sa di otreman.
Mak komèsyal yo
Non ak logo Microchip, logo Microchip, Adaptec, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, CryptoMemory, CryptoRF, dsPIC, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXStyluuchs, MediaLB, megaAVR, Microsemi, Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, PolarFire, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetricom , SyncServer, Tachyon, TimeSource, tinyAVR, UNI/O, Vectron, ak XMEGA se mak anrejistre Microchip Technology Incorporated nan Etazini ak lòt peyi yo.
AgileSwitch, APT, ClockWorks, The Embedded Control Solutions Company, EtherSynch, Flashtec, Hyper Speed Control, HyperLight Load, Libero, motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet- Wire, SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub, TimePictra, TimeProvider, TrueTime, ak ZL se mak anrejistre Microchip Technology Incorporated nan Etazini.
Sipresyon kle adjasan, AKS, Analog-pou-laj-dijital, Nenpòt kondansateur, AnyIn, AnyOut, Ogmante Chanjman, BlueSky, BodyCom, Clockstudio, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM Matching, Dynamic Matching. , DAM, ECAN, Espresso T1S, EtherGREEN, GridTime, IdealBridge, Programmation seri nan sikwi, ICSP, INICnet, Paralèl Entelijan, IntelliMOS, Koneksyon Inter-Chip, JitterBlocker, Knob-on-Display, KoD, maxCrypto, maxView, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net,
PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, RTAX, RTG4, SAMICE, Serial Quad I/O, simpleMAP, SimpliPHY, SmartBuffer, SmartHLS, SMART-IS, storClad, SQI, SuperSwitcher,
SuperSwitcher II, Switchtec, SynchroPHY, Total Endurance, Trusted Time, TSHARC, USBCheck, VariSense, VectorBlox, VeriPHY, ViewSpan, WiperLock, XpressConnect, ak ZENA se mak komèsyal Microchip Technology Incorporated.
nan USA ak lòt peyi yo.
SQTP se yon mak sèvis nan Microchip Technology Incorporated nan Etazini
Logo Adaptec, Frequency on Demand, Silicon Storage Technology, ak Symmcom se mak ki anrejistre Microchip Technology Inc. nan lòt peyi yo.
GestIC se yon mak ki anrejistre Microchip Technology Germany II GmbH & Co. KG, yon sipòtè Microchip Technology Inc., nan lòt peyi yo.
Tout lòt mak ki mansyone isit la se pwopriyete konpayi respektif yo.
© 2023, Microchip Technology Incorporated ak filiales li yo. Tout dwa rezève.
ISBN: 978-1-6683-3694-6
Sistèm Jesyon Kalite
Pou enfòmasyon konsènan Sistèm Jesyon Kalite Microchip, tanpri vizite www.microchip.com/quality.

AMERIK	AZI / PASIFIK	AZI / PASIFIK	EWÒP
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Dokiman / Resous

MICROCHIP Libero SoC Simulation Library Software [pdfGid Itilizatè
DS50003627A, Libero SoC Simulation Library Software, SoC Simulation Library Software, Simulation Library Software, Library Software, Software

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