Tambarin MICROCHIP Libero SoC Simulation
Umarnin Saita Laburare

Abubuwan da ke ciki boye
1 Gabatarwa
2 Haɗin gwiwar Libero SoC
3 Saitin Aldec don Active-HDL da Riviera-Pro (Tambaya Tambaya)
4 Saitin Inciive na Cadence (Tambaya Tambaya)
5 Saitin Cadence Xcelium (Microchip Login)
6 Siemens QuestaSim Saita/SaitinSim (Tambaya Tambayoyi)
7 Saitin VCS Synopsys (Tambaya Tambaya)
8 Tarihin Bita (Microchip Login
9 Takardu / Albarkatu
9.1 Magana
10 Labarai masu alaka

Gabatarwa

(Yi Tambaya)

Manufar wannan takarda ita ce bayyana hanyar da za a kafa yanayin kwaikwayo ta amfani da aikin Libero SoC a matsayin shigarwa. Wannan takaddun ya yi daidai da ɗakunan karatu da aka riga aka haɗa waɗanda aka tanadar don amfani tare da Libero SoC v11.9 da sabbin sabbin software. An haɗa ɗakunan karatu da aka bayar don Verilog. Masu amfani da VHDL suna buƙatar lasisi da ke ba da izinin simintin yanayin gauraye.
Haɗaɗɗen ɗakunan karatu na kwaikwayo suna samuwa don kayan aiki masu zuwa:

  • Aldec Active-HDL
  • Aldec Riviera-PRO
  • Cadence Incisive Enterprise da Xcelium
  • Siemens QuestaSim
  • Rahoton da aka ƙayyade na VCS

Don neman ɗakin karatu don na'urar kwaikwayo ta daban, tuntuɓi Taimakon Fasaha na Microchip.

Haɗin gwiwar Libero SoC

(Yi Tambaya)

Libero SoC yana goyan bayan kwaikwayo ta amfani da ModelSim ME ta hanyar samar da run.do file. Wannan file ModelSim ME/ModelSim Pro ME ke amfani dashi don saitawa da gudanar da simintin. Don amfani da wasu kayan aikin kwaikwayo, zaku iya ƙirƙirar ModelSim ME/ModelSim Pro ME run.do kuma canza rubutun Tcl. file don amfani da umarnin da suka dace da na'urar kwaikwayo.
1.1 Libero SoC Tcl File Zamani (Yi Tambaya)
Bayan ƙirƙira da samar da ƙira a cikin Libero SoC, fara ModelSim ME/ModelSim Pro ME simulation a ƙarƙashin duk matakan ƙira (presynth, postsynth, da post-layout). Wannan matakin yana haifar da run.do file don ModelSim ME/ModelSim Pro ME don kowane lokaci ƙira.
MICROCHIP Libero SoC Simulation Library Software - icon Muhimmi: Bayan fara kowane aikin simulation, sake suna run.do da aka yi ta atomatik file ƙarƙashin littafin simulation don hana Libero SoC sake rubuta wancan file. Don misaliample, da files za a iya sake masa suna zuwa presynth_run.do, postsynth_run.do da postlayout_run.do.

Saitin Aldec don Active-HDL da Riviera-Pro (Yi Tambaya)

Gudun.do file ModelSim ME/ModelSim Pro ME ke amfani da shi za'a iya gyaggyarawa da amfani dashi don yin kwaikwaiyo ta amfani da na'urar kwaikwayo ta Aldec.
2.1 Canjin Muhalli (Yi Tambaya)
Saita canjin yanayin ku zuwa lasisinku file wuri:
LM_LICENSE_FILE: dole ne ya haɗa da mai nuni zuwa uwar garken lasisi.
2.2 Zazzage Laburaren da aka Haɗa (Yi Tambaya)
Zazzage dakunan karatu don Aldec Active-HDL da Aldec Riviera-PRO daga Microchip website.
2.3 Maida run.do don simintin Aldec (Yi Tambaya)
Gudun.do files wanda Libero SoC ya samar don simulations ta amfani da Active-HDL da Riviera-Pro kayan aiki za a iya amfani da su don yin amfani da Active-HDL da Riviera-Pro tare da sauyi ɗaya. Tebu mai zuwa yana lissafin umarnin Aldec-daidai don gyara a cikin ModelSim run.do file.
Tebur 2-1. Aldec Kwatankwacin Dokokin

ModelSim Active-HDL
vlog alog
vcom acom
vlib alib
vsim asim
vmap amap

Mai bi shine kamarample run.do masu alaƙa da Aldec simulators.

  1. Saita wurin daftarin aiki na yanzu.
    saita dsn
  2. Saita sunan ɗakin karatu mai aiki, taswirar wurinsa, sannan taswirar wurin dangin Microchip FPGA
    dakunan karatu da aka riga aka tattara (misaliample, SmartFusion2) wanda kuke gudanar da ƙirar ku.
    alib presynth
    presynth presynth
    SmartFusion 2
  3. Haɗa duk abin da ake buƙata HDL files amfani a cikin zane tare da ɗakin karatu da ake buƙata.
    alog -work presynth temp.v (na Verilog)
    alog - aikin presynth testbench.v
    acom –work presynth temp.vhd (na Vhdl)
    acom - aikin presynth testbench.vhd
  4. Yi kwaikwayon ƙira.
    asim –L SmartFusion2 –L presynth –t 1ps presynth.testbench
    gudu 10us

2.4 Abubuwan da aka sani (Yi Tambaya)
Wannan sashe yana lissafa abubuwan da aka sani da iyakoki.

  • Laburaren da aka haɗa ta amfani da Riviera-PRO ƙayyadaddun dandamali ne (watau ɗakunan karatu 64-bit ba za a iya gudanar da su akan dandamali 32-bit ba kuma akasin haka).
  • Don ƙira da ke ɗauke da SERDES/MDDR/FDDR, yi amfani da zaɓi mai zuwa a cikin run.do files yayin da suke gudanar da simulations bayan sun haɗa ƙirar su:
    – Active-HDL: asim –o2
    - Riviera-PRO: asim –O2 (na presynth da simulations post-layout) da kuma asim – O5 (don simintin shimfidar wuri)
    Saitin Aldec don Active-HDL da Riviera-Pro yana da SARs masu zuwa. Don ƙarin bayani, tuntuɓi Taimakon Fasaha na Microchip.
  • SAR 49908 - HDL mai aiki: Kuskuren VHDL don simintin toshe lissafi
  • SAR 50627 - Riviera-PRO 2013.02: Kurakurai na kwaikwayo don ƙirar SErdES
  • SAR 50461 - Riviera-PRO: asim -O2/-O5 zaɓi a cikin simulations

Saitin Incisive Cadence (Yi Tambaya)

Kuna buƙatar ƙirƙirar rubutun file kama da ModelSim ME/ModelSim Pro ME run.do don gudanar da
Cadence Incisive na'urar kwaikwayo. Bi waɗannan matakan kuma ƙirƙirar rubutun file don NCSim ko amfani da rubutun file
An bayar don canza ModelSim ME/ModelSim Pro ME run.do files a cikin sanyi files
da ake buƙata don gudanar da simulations ta amfani da NCsim.
MICROCHIP Libero SoC Simulation Library Software - icon Muhimmi: Cadence ya daina fitar da sabbin nau'ikan Kasuwancin Inciive
na'urar kwaikwayo kuma ya fara tallafawa na'urar kwaikwayo ta Xcelium.

3.1 Canje-canjen Muhalli (Yi Tambaya)
Don gudanar da na'urar kwaikwayo ta Cadence Incisive, saita masu canjin yanayi masu zuwa:

  1. LM_LICENSE_FILE: dole ne ya haɗa da mai nuni ga lasisi file.
  2. cds_root: dole ne ya nuna wurin adireshin gida na Shigar da Inciive na Cadence.
  3. HANYA: dole ne a nuna wurin da aka ajiye a ƙarƙashin kundin kayan aikin da cds_root ke nunawa wato,
    $cds_root/kayan aiki/bin/64bit (na na'ura mai 64-bit da $cds_root/kayan aiki/bin na injin 32-bit).
    Akwai hanyoyi guda uku na kafa yanayin siminti idan akwai sauyawa tsakanin tsarin aiki na 64-bit da 32-bit:

Hali na 1: Canjin PATH
Gudanar da umarni mai zuwa:
saita hanya = (install_dir / kayan aiki / bin / 64bit $ hanya) don injunan 64bit da
saita hanya = (install_dir / kayan aiki / bin $ hanya) don injunan 32bit
Case 2: Yin amfani da -64bit Zaɓin layin umarni
A cikin layin umarni saka -64bit zaɓi don kiran 64bit mai aiwatarwa.
Hali na 3: Saita INCA_64BIT ko CDS_AUTO_64BIT Canjin Muhalli
Ana ɗaukar madaidaicin INCA_64BIT azaman boolean. Kuna iya saita wannan canjin zuwa kowace ƙima ko zuwa igiyar banza.
saitin INCA_64BIT

MICROCHIP Libero SoC Simulation Library Software - icon Muhimmi: The INCA_64BIT canjin yanayi baya shafar sauran kayan aikin Cadence, kamar kayan aikin IC. Koyaya, don kayan aikin Inciive, madaidaicin INCA_64BIT ya ƙetare saitin madaidaicin yanayin CDS_AUTO_64BIT. Idan aka saita canjin yanayi INCA_64BIT, duk kayan aikin Insiive suna aiki a yanayin 64-bit. setenv CDS_AUTO_64BIT HADA:INCA
MICROCHIP Libero SoC Simulation Library Software - icon Muhimmi: The kirtani INCA dole ne ya kasance cikin babban harafi. Dole ne a gudanar da duk abubuwan da za a iya aiwatarwa a cikin yanayin 32-bit ko a cikin yanayin 64-bit, kar a saita canjin don haɗa da aiwatarwa ɗaya, kamar a cikin masu zuwa:
setenv CDS_AUTO_64BIT HADA: celab

Sauran kayan aikin Cadence, kamar kayan aikin IC, suma suna amfani da madaidaicin yanayi na CDS_AUTO_64BIT don sarrafa zaɓin masu aiwatarwa na 32-bit ko 64-bit. Tebur mai zuwa yana nuna yadda zaku iya saita canjin CDS_AUTO_64BIT don gudanar da kayan aikin Inciive da kayan aikin IC a kowane yanayi.
Table 3-1. CDS_AUTO_64BIT masu Sauyawa

CDS_AUTO_64BIT Mai Sauyawa Kayayyakin Ƙarfafawa Kayan aikin IC
setenv CDS_AUTO_64BIT DUK 64 bit 64 bit
setenv CDS_AUTO_64BIT BA KOWA 32 bit 32 bit
setenv CDS_AUTO_64BIT EXCLUDE:ic_binary 64 bit 32 bit
setenv CDS_AUTO_64BIT EXCLUDE:INCA 32 bit 64 bit

MICROCHIP Libero SoC Simulation Library Software - icon Muhimmi: Dole ne a gudanar da duk kayan aikin Inciive a cikin yanayin 32-bit ko a cikin yanayin 64-bit, kar a yi amfani da EXCLUDE don ware takamaiman aiwatarwa, kamar a cikin mai zuwa: setenv CDS_AUTO_64BIT EXCLUDE:ncelab
Idan kun saita canjin CDS_AUTO_64BIT don keɓance kayan aikin Insiive (setenv CDS_AUTO_64BIT EXCLUDE:INCA), ana gudanar da duk kayan aikin Incisive a yanayin 32-bit. Koyaya, zaɓin layin umarni -64bit ya mamaye canjin yanayi.
Tsari mai zuwa fileyana taimaka muku sarrafa bayanan ku da sarrafa ayyukan kayan aikin kwaikwayo da abubuwan amfani:

  • Taswirar ɗakin karatu file (cds.lib) — Yana bayyana suna mai ma'ana don wurin ƙirar ku.
  • Laburare kuma yana haɗa su da sunaye na zahiri.
  • Masu canji file (hdl.var) — Yana bayyana sauye-sauye waɗanda ke shafar halayen kayan aikin kwaikwayo da abubuwan amfani.

3.2 Zazzage Laburaren da aka Haɗa (Yi Tambaya)
Zazzage dakunan karatu don Cadence Incisive daga Microsemi's website.
3.3 Ƙirƙirar Rubutun NCsim File (Yi Tambaya)
Bayan ƙirƙirar kwafin run.do files, yi waɗannan matakan don gudanar da simintin ku ta amfani da NCsim:

  1. Ƙirƙiri cds.lib file wanda ke bayyana dakunan karatu da ake iya shiga da kuma wurin da suke. The file yana ƙunshe da kalamai waɗanda ke taswirar sunaye masu ma'ana a ɗakin karatu zuwa hanyoyin tarihinsu na zahiri. Domin misaliample, idan kuna gudana presynth simulation, cds.lib file an rubuta kamar yadda aka nuna a cikin codeblock mai zuwa.
    BAYANIN presynth ./presynth
    BAYANI COREAHBLITE_LIB ./COREAHBLITE_LIB
    SANARWA smartfusion2
  2. Ƙirƙiri hdl.var file, tsari na zaɓi file wanda ke ƙunshe da ma'aunin daidaitawa, wanda ke ƙayyade yadda aka tsara yanayin ƙirar ku. Mai canzawa mai zuwa files sun hada da:
    - Bambance-bambancen da ake amfani da su don tantance ɗakin karatu na aiki inda mai tarawa ke adana abubuwan da aka haɗa da sauran bayanan da aka samo.
    - Don Verilog, masu canji (LIB_MAP, VIEW_MAP, AIKI) waɗanda ake amfani da su don tantance ɗakunan karatu da views don bincika lokacin da mai bayani ya warware al'amura.
    - Maɓalli waɗanda ke ba ku damar ayyana mai tarawa, mai fayyace, da zaɓuɓɓukan layin umarni da muhawara.
    Idan akwai simintin presynth exampa sama, ka ce muna da RTL guda uku files: av, bv, da testbench.v, waɗanda ke buƙatar haɗa su zuwa presynth, COREAHBLITE_LIB, da presynth dakunan karatu bi da bi. hdl.var file za a iya rubuta kamar yadda aka nuna a cikin codeblock na gaba.
    Ƙayyadadden aikin presynth
    BAYANIN PROJECT_DIR files>
    BAYANIN LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/av => presynth)
    BAYANIN LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/bv => COREAHBLITE_LIB)
    BAYANIN LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/testbench.v => presynth)
    BAYANIN LIB_MAP ($ LIB_MAP, + => presynth)
  3. Haɗa zane files ta amfani da zaɓin ncvlog.
    ncvlog + incdir+ –cdslib ./cds.lib –hdlvar ./hdl.var –logfile
    ncvlog.log - sabuntawa -linedebug av bv testbench.v
  4. Ƙirƙiri ƙira ta amfani da celab. Mai faɗakarwa yana gina tsarin ƙira bisa ga bayanan nan take da daidaitawa a cikin ƙira, yana kafa haɗin sigina, kuma yana ƙididdige ƙimar farko ga duk abubuwan da ke cikin ƙira. An adana ƙayyadaddun tsarin ƙira a cikin hoton simintin, wanda shine wakilcin ƙirar ku wanda na'urar kwaikwayo ke amfani da ita don gudanar da simulation.
    ncelab –Saƙo –cdslib ./cds.lib –hdlvar ./hdl.var –logfile celab.log –errormax 15 –
    samun damar +rwc-status worklib. :module
    Ƙaddamarwa Yayin Kwaikwayon Bayan-tsayi
    Idan akwai abubuwan kwaikwayo na bayan-tsayi, da farko SDF file yana buƙatar haɗawa kafin ƙarin bayani ta amfani da umarnin ncsdfc.
    ncsdfcfilesuna> sdf - fitarwafilesuna> sdf.X
    A yayin haɓakawa yi amfani da kayan aikin SDF da aka haɗa tare da zaɓin –autosdf kamar yadda aka nuna a cikin katangar lambar.
    ncelab -autosdf –Saƙo –cdslib ./cds.lib –hdlvar ./hdl.var –logfile celab.log -errormax
    15-access + rwc -matsayin aiki lib. :module -sdf_cmd_file ./
    sdf_cmd_file
    sdf_cmd_file dole ne a kasance kamar yadda aka nuna a cikin codeblock mai zuwa.
    COMPILED_SDF_FILE =" file>>
  5. Yi kwaikwayon ta amfani da ncsim. Bayan ƙarin bayani an ƙirƙiri hoto na simulation, wanda ncsim ke lodawa don simulation. Kuna iya aiki a yanayin tsari ko yanayin GUI.
    ncsim –Saƙo –batch/-gui –cdslib ./cds.lib –hdlvar ./hdl.var –logfile ncsim.log -
    errormax 15 - matsayin aiki lib. :module

MICROCHIP Libero SoC Simulation Library Software - icon Muhimmi: Duk matakai uku na sama na haɗawa, haɓakawa, da kwaikwaya ana iya sanya su cikin rubutun harsashi file kuma an samo shi daga layin umarni. Maimakon amfani da waɗannan matakai guda uku, za a iya kwatanta ƙira a mataki ɗaya ta amfani da ncverilog ko zaɓin irun kamar yadda aka nuna a cikin codeblock mai zuwa.
ncverilog + incdir+ -cdslib ./cds.lib -hdlvar ./hdl.var
files amfani a cikin zane>
irin + incdir+ -cdslib ./cds.lib -hdlvar ./hdl.var files
amfani a cikin zane>

3.3.1 Abubuwan da aka sani (Yi Tambaya)
Testbench Workaround
Yin amfani da bayanin da ke biyowa don ƙididdige mitar agogo a cikin testbench ɗin da mai amfani ya ƙirƙira, ko kuma tsohuwar gwajin da Libero SoC ta samar baya aiki tare da NCsim.
kullum @(SYSCLK)
#(SYSCLK_PERIOD / 2.0) SYSCLK <= !SYSCLK;
Gyara kamar haka don gudanar da simulation:
ko da yaushe #(SYSCLK_PERIOD / 2.0) SYSCLK = ~SYSCLK;
MICROCHIP Libero SoC Simulation Library Software - icon Muhimmi: Haɗa dakunan karatu na NCSim ƙayyadaddun dandamali ne (watau ɗakunan karatu na 64 ba su dace da dandamali na 32 ba kuma akasin haka).
Postsynth da Post-layout Simulations Amfani da MSS da SERDES Yayin da ake gudanar da simintin POSynth na ƙira da ke ɗauke da toshe MSS ko simintin ƙirar ƙira ta amfani da SERDES, simintin BFM ba sa aiki idan zaɓi -libmap ya kasance.
ba a kayyade lokacin bayani ba. Wannan saboda a lokacin haɓakawa, ana warware MSS daga ɗakin karatu na aiki (saboda tsoho da ɗaurin aiki da kuma worklib kasancewa postsynth/post-layout) inda kawai Kafaffen Aiki ne.
Dole ne a rubuta umarnin ncelab kamar yadda aka nuna a cikin toshe lambar don warware MSS
toshe daga ɗakin karatu na SmartFusion2 da aka riga aka haɗa.

ncelab -libmap lib.map -libverbose -Message -access +rwc cfg1
da lib.map file dole ne ya kasance kamar haka:
tsarin cfg1;
zane ;
tsoho liblist smartfusion2 ;
endconfig
Wannan yana warware kowane tantanin halitta a cikin ɗakin karatu na SmartFusion2 kafin duba cikin ɗakin karatu na aiki watau postsynth/ post-layout.
Za a iya amfani da zaɓin –libmap ta tsohuwa yayin haɓakawa ga kowane simintin (presynth, postsynth, da post-layout). Wannan yana nisantar al'amurran da suka shafi simintin gyare-gyare waɗanda ke faruwa saboda ƙudurin lokuta daga ɗakunan karatu.
celab: *F,INTERR: INTERNAL EXECEPTION
Wannan keɓanta kayan aikin ncelab shine faɗakarwa don ƙira mai ƙunshe da FDDR a cikin SmartFusion 2 da IGLOO 2 yayin wasan kwaikwayo na postsynth da post-layout ta amfani da zaɓin -libmap.
MICROCHIP Libero SoC Simulation Library Software - icon Muhimmi: An bayar da rahoton wannan fitowar ga ƙungiyar tallafin Cadence (SAR 52113).

3.4 SampLe Tcl da Shell Script Files (Yi Tambaya)
Masu biyowa files su ne sanyi files da ake buƙata don saita ƙira da rubutun harsashi file don gudanar da umarnin NCSim.
Cds.lib
NE smartfusion2 /scratch/krydor/tmpspace/users/me/nc-vlog64/SmartFusion2
BAYANI COREAHBLITE_LIB ./COREAHBLITE_LIB
BAYANIN presynth ./presynth

HDl.var
Ƙayyadadden aikin presynth
Ƙayyade PROJECT_DIR / Scratch / krydor / tmpspace / sqausers / ni / 3rd_party_simulators / Cadence / IGLOO2 /
ENVM/M2GL050/envm_fic1_ser1_v/eNVM_fab_master
Ƙayyade LIB_MAP ($ LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBlite/4.0.100/rtl/
vlog/core/coreahblite_addrdec.v => COREAHBLITE_LIB)
Ƙayyade LIB_MAP ($ LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBlite/4.0.100/rtl/
vlog/core/coreahblite_defaultslavesm.v => COREAHBLITE_LIB)
Ƙayyade LIB_MAP ($ LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBlite/4.0.100/rtl/
vlog/core/coreahblite_masterstagev => COREAHBLITE_LIB )
Ƙayyade LIB_MAP ($ LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBlite/4.0.100/rtl/
vlog/core/coreahblite_slavearbiter.v => COREAHBLITE_LIB)
Ƙayyade LIB_MAP ($ LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBlite/4.0.100/rtl/
vlog/core/coreahblite_slavestagev => COREAHBLITE_LIB )
Ƙayyade LIB_MAP ($ LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBlite/4.0.100/rtl/
vlog/core/coreahblite_matrix2x16.v => COREAHBLITE_LIB)
Ƙayyade LIB_MAP ($ LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBlite/4.0.100/rtl/
vlog/core/coreahblite.v => COREAHBLITE_LIB )
BAYANIN LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB/CCC_0/SB_CCC_0_FCCC.v =>
presynth)
BAYANIN LIB_MAP ($ LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreConfigMaster/
2.0.101/rtl/vlog/core/coreconfigmaster.v => presynth)
Ƙayyade LIB_MAP ($ LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreConfigP/4.0.100/rtl/
vlog/core/coreconfigp.v => presynth)
Ƙayyade LIB_MAP ($ LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreResetP/5.0.103/rtl/
vlog/core/coreresetp_pcie_hotreset.v => presynth)
Ƙayyade LIB_MAP ($ LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreResetP/5.0.103/rtl/
vlog/core/coreresetp.v => presynth)
BAYANIN LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB/FABOSC_0/SB_FABOSC_0_OSC.v =>
presynth)
BAYANIN LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB_HPMS/SB_HPMS.v => presynth)
BAYANIN LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB/SB.v => presynth)
Ƙayyade LIB_MAP ($ LIB_MAP, ${PROJECT_DIR}/component/work/SB_top/SERDES_IF_0/
SB_top_SERDES_IF_0_SERDES_IF.v => presynth)
BAYANIN LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB_top/SB_top.v => presynth)
BAYANIN LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB_top/testbench.v => presynth)
BAYANIN LIB_MAP ($ LIB_MAP, + => presynth)
Umurni.csh
ncvlog +incdir+.../../component/work/SB_top -cdslib ./cds.lib -hdlvar ./hdl.var -logfile
ncvlog.log -errormax 15 -update -linedebug
../../component/actel/Coccore/coreahbblite/4.0.100/RTL/Voreahblite_addretec.v
../../bangaren/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/
coreahblite_defaultslavesm.v
../../bangaren/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite_masterstagev
../../component/actel/directcore/coreahbblite/4.0.100/RTL/Voreahblite_slaivearber.v
../../bangaren/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite_slavestagev
../../bangaren/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite_matrix2x16.v
../../bangaren/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite.v
../../bangaren/aiki/SB/CCC_0/SB_CCC_0_FCCC.v
../../component/Actel/DirectCore/CoreConfigMaster/2.0.101/rtl/vlog/core/coreconfigmaster.v
../../bangaren/Actel/DirectCore/CoreConfigP/4.0.100/rtl/vlog/core/coreconfigp.v
../../componononenuan/corettcore/coreretetp/5.0.103/RORETP_PCOE_HotTreset.v
../../bangaren/Actel/DirectCore/CoreResetP/5.0.103/rtl/vlog/core/coreresetp.v
../../bangaren/aiki/SB/FABOSC_0/SB_FABOSC_0_OSC.v
../../bangaren/aiki/SB/SB.v
SB_top_SERDES_IF_0_SERDES_IF.v
../../bangaren/aiki/SB_top/SB_top.v ../../component/aiki/SB_top/testbench.v
ncelab -Message -cdslib ./cds.lib -hdlvar ./hdl.var
- aikin presynth -logfile ncelab.log -errormax 15 -access +rwc -status presynth.testbench:module
ncsim -Message -batch -cdslib ./cds.lib -hdlvar ./
hdl.var -logfile ncsim.log -errormax 15 -status presynth.testbench:module

3.5 Ta atomatikYi Tambaya)
Rubutun mai zuwa file yana canza ModelSim run.do files cikin sanyi fileAna buƙatar gudanar da simulations ta amfani da NCsim.
Rubutun File Amfani
perl cadence_parser.pl presynth_run.do postsynth_run.do
postlayout_run.do Microsemi_Family
Wuri_na_Cadence_Dakunan karatu

Cadence_parser.pl
#!/usr/bin/perl -w

##################################### ###############################
############
#Amfani: perl questa_parser.pl presynth_run.do postsynth_run.do postlayout_run.do
Microsemi_Family Precompiled_Libraries_location#

##################################### ###############################
############
amfani da POSIX;
amfani da tsauri;
my ($presynth, $postsynth, $postlayout, $ iyali, $lib_location) = @ARGV;
&questa_parser($presynth, $iyali, $lib_location);
&questa_parser($postsynth, $iyali, $lib_location);
&questa_parser ($ postlayout, $ iyali, $ lib_location);
sub questa_parser {
na $ModelSim_run_do = $_[0];
my $actel_family = $_[1];
na $lib_location = $_[2];
jihara ta;
idan (-e “$ModelSim_run_do”)
{
bude (INFILE,"$ModelSim_run_do");
na @ModelSim_run_do =FILE>;
layin $ na;
idan ( $ModelSim_run_do = ~ m / (presynth) /)
{
'mkdir QUESTA_PRESYNTH';
bude (OUTFILE,”>QUESTA_PRESYNTH/presynth_questa.do”);
$state = $1;
} elsif ( $ModelSim_run_do =~ m/(postsynth)/)
{
'mkdir QUESTA_POSTSYNTH';
bude (OUTFILE,”>QUESTA_POSTSYNTH/postsynth_questa.do”);
$state = $1;
} elsif ( $ModelSim_run_do =~ m/(postlayout)/)
{
`mkdir QUESTA_POSTLAYOUT';
bude (OUTFILE,”>QUESTA_POSTLAYOUT/postlayout_questa.do”);
$state = $1;
} sauran
{
buga “Ba daidai ba abubuwan da aka ba wa file\n";
buga "#Usage: perl questa_parser.pl presynth_run.do postsynth_run.do postlayout_run.do
\"Wurin_Libraries\"\n";
}
layin $ (@ModelSim_run_do)
{
#Ayyukan Gabaɗaya
$line = ~ s / .. \/ mai tsarawa. * kwaikwayo /// g;
$layi =~ s/$state/$state\_questa/g;
#kwafiFILE "$layi \n";
idan ($layi =~ m/vmap\s+.*($actel_family)/)
{
kwafiFILE "vmap $actel_family \"$lib_location\"\n";
} elsif ($layi =~ m/vmap\s+(.*._LIB)/)
{
$line = ~ s / .. \/ bangaren / .. \/ .. \/component/g;
kwafiFILE "$layi \n";
} elsif ($ layi = ~ m/vsim/)
{
$line = ~ s/vsim/vsim -novopt/g;
kwafiFILE "$layi \n";
} sauran
{
kwafiFILE "$layi \n";
}
}
kusa (INFILE);
rufe (OUTFILE);
} kuma {
buga “$ModelSim_run_do babu shi. Sake kunna simulation \n";
}
}

Saitin Cadence Xcelium (Microchip Login)

Kuna buƙatar ƙirƙirar rubutun file kama da ModelSim ME/ModelSim Pro ME run.do don gudanar da na'urar kwaikwayo ta Cadence Xcelium. Bi waɗannan matakan kuma ƙirƙirar rubutun file don Xcelium ko amfani da rubutun file An bayar don canza ModelSim ME/ModelSim Pro ME run.do files a cikin sanyi files da ake buƙata don gudanar da simulations ta amfani da Xcelium.
4.1 Canje-canjen Muhalli (Yi Tambaya)
Don gudanar da Cadence Xcelium, saita masu canjin yanayi masu zuwa:

  1. LM_LICENSE_FILE: dole ne ya haɗa da mai nuni ga lasisi file.
  2. cds_root: dole ne ya nuna wurin adireshin gida na shigarwar Incisive na Cadence.
  3. PATH: dole ne ya nuna wurin bin ƙarƙashin kundin adireshin kayan aikin da cds_root ke nunawa (watau
    $cds_root/kayan aiki/bin/64bit (don injin 64-bit da $cds_root/kayan aiki/bin don 32 bit)
    mashin).

Akwai hanyoyi guda uku na kafa yanayin siminti idan akwai sauyawa tsakanin tsarin aiki na 64-bit da 32-bit:
Hali na 1: Canjin PATH
saita hanya = (install_dir / kayan aiki / bin / 64bit $ hanya) don injunan 64bit da
saita hanya = (install_dir / kayan aiki / bin $ hanya) don injunan 32bit
Case 2: Yin amfani da -64bit Zaɓin layin umarni
A cikin layin umarni saka -64bit zaɓi don kiran 64-bit mai aiwatarwa.
Hali na 3: Saita INCA_64BIT ko CDS_AUTO_64BIT Canjin Muhalli
Ana ɗaukar madaidaicin INCA_64BIT azaman boolean. Kuna iya saita wannan canjin zuwa kowace ƙima ko zuwa maras kyau
kirtani.
saitin INCA_64BIT

MICROCHIP Libero SoC Simulation Library Software - icon Muhimmi: The INCA_64BIT canjin yanayi baya shafar sauran kayan aikin Cadence, kamar kayan aikin IC. Koyaya, don kayan aikin Inciive, madaidaicin INCA_64BIT ya ƙetare saitin madaidaicin yanayin CDS_AUTO_64BIT. Idan INCA_64BIT m yanayi ne et, duk Insiive kayan aikin aiki a 64-bit yanayin.
setenv CDS_AUTO_64BIT HADA:INCA
MICROCHIP Libero SoC Simulation Library Software - icon Muhimmi: The kirtani INCA dole ne ya kasance cikin babban harafi. Dole ne a gudanar da duk abubuwan da za a iya aiwatarwa a cikin yanayin 2-bit ko a cikin yanayin 64-bit, kar a saita canjin don haɗa da aiwatarwa ɗaya, kamar a cikin masu zuwa:
setenv CDS_AUTO_64BIT HADA: celab
Sauran kayan aikin Cadence, kamar kayan aikin IC, suma suna amfani da madaidaicin yanayi na CDS_AUTO_64BIT don sarrafa zaɓin masu aiwatarwa na 32-bit ko 64-bit. Tebur mai zuwa yana nuna yadda zaku iya saita canjin CDS_AUTO_64BIT don gudanar da kayan aikin Inciive da kayan aikin IC a kowane yanayi.

Table 4-1. CDS_AUTO_64BIT masu Sauyawa

CDS_AUTO_64BIT Mai Sauyawa Kayayyakin Ƙarfafawa Kayan aikin IC
setenv CDS_AUTO_64BIT DUK 64-bit 64-bit
setenv CDS_AUTO_64BIT BA KOWA 32-bit 32-bit
saitin CDS_AUTO_64BIT
EXCLUDE: ic_binary		 64-bit 32-bit
setenv CDS_AUTO_64BIT EXCLUDE:INCA 32-bit 64-bit

MICROCHIP Libero SoC Simulation Library Software - icon Muhimmi: Dole ne a gudanar da duk kayan aikin Inciive a cikin yanayin 32-bit ko a cikin yanayin 64-bit, kar a yi amfani da EXCLUDE don ware takamaiman aiwatarwa, kamar a cikin masu zuwa:
setenv CDS_AUTO_64BIT EXCLUDE: celab
Idan kun saita canjin CDS_AUTO_64BIT don keɓance kayan aikin Insiive (setenv)
CDS_AUTO_64BIT EXCLUDE:INCA), duk kayan aikin Ƙarfafa ana gudanar da su a cikin yanayin 32-bit. Duk da haka, da
Zaɓin layin umarni -64bit ya ƙetare canjin yanayi.
Tsari mai zuwa fileyana taimaka muku sarrafa bayanan ku da sarrafa ayyukan kayan aikin kwaikwayo da abubuwan amfani:

  • Taswirar ɗakin karatu file (cds.lib) yana bayyana suna mai ma'ana don wurin ƙirar ku.
  • Laburare kuma yana haɗa su da sunaye na zahiri.
  • Masu canji file (hdl.var) yana bayyana masu canji waɗanda ke shafar halayen kayan aikin kwaikwayo da abubuwan amfani.

4.2 Zazzage Laburaren da aka Haɗa (Yi Tambaya)
Zazzage dakunan karatu na Cadence Xcelium daga Microsemi's website.
4.3 Ƙirƙirar rubutun Xcelium file (Yi Tambaya)
Bayan ƙirƙirar kwafin run.do files, aiwatar da matakai masu zuwa don gudanar da simintin ku ta amfani da rubutun Xcelium file.

  1. Ƙirƙiri cds.lib file wanda ke fayyace waɗanne dakunan karatu ne da kuma inda suke.
    The file yana ƙunshe da kalamai waɗanda ke taswirar sunaye masu ma'ana a ɗakin karatu zuwa hanyoyin tarihinsu na zahiri. Domin misaliample, idan kuna gudana presynth simulation, cds.lib file za a iya rubuta kamar yadda aka nuna a cikin codeblock na gaba.
    BAYANIN presynth ./presynth
    BAYANI COREAHBLITE_LIB ./COREAHBLITE_LIB
    SANARWA smartfusion2
  2. Ƙirƙiri hdl.var file wanda shine tsari na zaɓi file wanda ke ƙunshe da ma'aunin daidaitawa, wanda ke ƙayyade yadda aka tsara yanayin ƙirar ku. Waɗannan sun haɗa da:
    - Bambance-bambancen da ake amfani da su don tantance ɗakin karatu na aiki inda mai tarawa ke adana abubuwan da aka haɗa da sauran bayanan da aka samo.
    - Don Verilog, masu canji (LIB_MAP, VIEW_MAP, AIKI) waɗanda ake amfani da su don tantance ɗakunan karatu da views don bincika lokacin da mai bayani ya warware al'amura.
    - Maɓalli waɗanda ke ba ku damar ayyana mai tarawa, mai fayyace, da zaɓuɓɓukan layin umarni da muhawara.
    Idan akwai simintin presynth example da aka nuna a sama, ka ce muna da 3 RTL files av, bv, da testbench.v, waɗanda ke buƙatar haɗa su zuwa presynth, COREAHBLITE_LIB, da presynth dakunan karatu bi da bi. hdl.var file za a iya rubuta kamar yadda aka nuna a cikin codeblock na gaba.
    Ƙayyadadden aikin presynth
    BAYANIN PROJECT_DIR files>
    BAYANIN LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/av => presynth)
    BAYANIN LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/bv => COREAHBLITE_LIB)
    BAYANIN LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/testbench.v => presynth)
    BAYANIN LIB_MAP ($ LIB_MAP, + => presynth)
  3. Haɗa zane files ta amfani da zaɓin ncvlog.
    xmvlog + incdir+ –cdslib ./cds.lib –hdlvar ./hdl.var –logfile
    ncvlog.log - sabuntawa -linedebug av bv testbench.v
  4. Ƙirƙiri ƙira ta amfani da celab. Mai faɗakarwa yana gina tsarin ƙira bisa ga bayanan nan take da daidaitawa a cikin ƙira, yana kafa haɗin sigina, kuma yana ƙididdige ƙimar farko ga duk abubuwan da ke cikin ƙira. An adana ƙayyadaddun tsarin ƙira a cikin hoton simintin, wanda shine wakilcin ƙirar ku wanda na'urar kwaikwayo ke amfani da ita don gudanar da simulation.
    Xcelium –Saƙo –cdslib ./cds.lib –hdlvar ./hdl.var –logfile celab.log –errormax 15 –
    samun damar +rwc-status worklib. :module
    Ƙaddamarwa Yayin Kwaikwayon Bayan-tsayi
    Idan akwai abubuwan kwaikwayo na bayan-tsayi, da farko SDF file yana buƙatar haɗawa kafin ƙarin bayani ta amfani da umarnin ncsdfc.
    Xceliumfilesuna> sdf - fitarwafilesuna> sdf.X
    A yayin haɓakawa yi amfani da kayan aikin SDF da aka haɗa tare da zaɓin –autosdf kamar yadda aka nuna a cikin katangar lambar.
    xmelab -autosdf –Saƙo –cdslib ./cds.lib –hdlvar ./hdl.var –logfile celab.log -errormax
    15-access + rwc -matsayin aiki lib. :module -sdf_cmd_file ./
    sdf_cmd_file
    sdf_cmd_file dole ne a kasance kamar yadda aka nuna a cikin codeblock mai zuwa.
    COMPILED_SDF_FILE =" file>>
  5. Yi amfani da Xcelium. Bayan ƙarin bayani an ƙirƙiri hoton simulation wanda Xcelium ke lodawa don simulation. Ana iya gudanar da wannan a yanayin tsari ko yanayin GUI.
    xmsim –Saƙo –batch/-gui –cdslib ./cds.lib –hdlvar ./hdl.var –logfile xmsim.log -
    errormax 15 - matsayin aiki lib. :module
    Cadence Xcelium Saita
    MICROCHIP Libero SoC Simulation Library Software - icon Muhimmi: Duk matakai uku na sama na haɗawa, haɓakawa da kwaikwaya ana iya sanya su cikin rubutun harsashi file kuma an samo shi daga layin umarni. Maimakon amfani da waɗannan matakai guda uku, za a iya kwatanta ƙira a mataki ɗaya ta amfani da ncverilog ko xrun zaɓi kamar yadda aka nuna a cikin codeblock na gaba.
    xmverilog + incdir+ -cdslib ./cds.lib -hdlvar ./hdl.var
    files amfani a cikin zane>
    xrun + incdir+ -cdslib ./cds.lib -hdlvar ./hdl.var files
    amfani a cikin zane>

4.3.1 Abubuwan da aka sani (Yi Tambaya)
Testbench Workaround
Yin amfani da bayanin da ke biyowa don ƙididdige mitar agogo a cikin testbench ɗin da mai amfani ya ƙirƙira ko tsohuwar gwajin da Libero SoC ya samar baya aiki tare da Xcelium.
kullum @(SYSCLK)
#(SYSCLK_PERIOD / 2.0) SYSCLK <= !SYSCLK;
Gyara kamar haka don gudanar da simulation:
ko da yaushe #(SYSCLK_PERIOD / 2.0) SYSCLK = ~SYSCLK;

MICROCHIP Libero SoC Simulation Library Software - icon Muhimmi: Haɗaɗɗen ɗakunan karatu don Xcelium takamaiman dandamali ne (watau ɗakunan karatu na 64 ba su dace da dandamalin 32 bit ba kuma akasin haka).
Postsynth da Post-layout Simulations ta amfani da MSS da SERDES
Yayin gudanar da simintin POSynth na ƙira mai ɗauke da toshe MSS, ko simintin ƙirar ƙira ta amfani da SERDES, simintin BFM ba sa aiki idan -libmap zaɓin ba a ƙayyade ba yayin haɓakawa. Wannan saboda a lokacin haɓakawa, ana warware MSS daga ɗakin karatu na aiki (saboda tsoho da ɗaurin aiki da kuma worklib kasancewa postsynth/post-layout) inda kawai Kafaffen Aiki ne.
Dole ne a rubuta umarnin ncelab kamar yadda aka nuna a cikin toshe lambar don warware toshewar MSS daga ɗakin karatu da aka riga aka haɗa SmartFusion2.
xmelab -libmap lib.map -libverbose -Message -access +rwc cfg1
da lib.map file dole ne ya kasance kamar haka:
tsarin cfg1;
zane ;
tsoho liblist smartfusion2 ;
endconfig
Wannan dole ne ya warware kowane tantanin halitta a cikin ɗakin karatu na SmartFusion2 kafin duba cikin ɗakin karatu na aiki watau postsynth/post-layout.
Za a iya amfani da zaɓin –libmap ta tsohuwa yayin haɓakawa ga kowane simintin (presynth, postsynth da post-layout). Wannan yana nisantar al'amurran da suka shafi simintin gyare-gyare waɗanda ke faruwa saboda ƙudurin lokuta daga ɗakunan karatu.
xmelab: *F,INTERR: INTERNAL EXEPTION
Wannan keɓanta kayan aikin ncelab shine faɗakarwa don ƙira da ke ɗauke da FDDR a cikin SmartFusion2 da IGLOO2
yayin wasan kwaikwayo na postsynth da post-layout ta amfani da zaɓin -libmap.
MICROCHIP Libero SoC Simulation Library Software - icon Muhimmi: An bayar da rahoton wannan fitowar ga ƙungiyar tallafin Cadence (SAR 52113).

4.4 Sample Tcl da rubutun harsashi files (Yi Tambaya)
Masu biyowa files su ne sanyi files da ake buƙata don saita ƙira da rubutun harsashi file don gudanar da umarnin Xcelium.
Cds.lib
SANARWA smartfusion2 /scratch/krydor/tmpspace/users/ni/nc-vlog64/SmartFusion2
BAYANI COREAHBLITE_LIB ./COREAHBLITE_LIB
BAYANIN presynth ./presynth
HDl.var
Ƙayyadadden aikin presynth
Ƙayyade PROJECT_DIR / Scratch / krydor / tmpspace / sqausers / ni / 3rd_party_simulators / Cadence / IGLOO2 /
ENVM/M2GL050/envm_fic1_ser1_v/eNVM_fab_master
Ƙayyade LIB_MAP ($ LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBlite/4.0.100/rtl/
vlog/core/coreahblite_addrdec.v => COREAHBLITE_LIB)
Ƙayyade LIB_MAP ($ LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBlite/4.0.100/rtl/
vlog/core/coreahblite_defaultslavesm.v => COREAHBLITE_LIB)
Ƙayyade LIB_MAP ($ LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBlite/4.0.100/rtl/
vlog/core/coreahblite_masterstagev => COREAHBLITE_LIB )
Ƙayyade LIB_MAP ($ LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBlite/4.0.100/rtl/
vlog/core/coreahblite_slavearbiter.v => COREAHBLITE_LIB)
Ƙayyade LIB_MAP ($ LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBlite/4.0.100/rtl/
vlog/core/coreahblite_slavestagev => COREAHBLITE_LIB )
Ƙayyade LIB_MAP ($ LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBlite/4.0.100/rtl/
vlog/core/coreahblite_matrix2x16.v => COREAHBLITE_LIB)
Ƙayyade LIB_MAP ($ LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreAHBlite/4.0.100/rtl/
vlog/core/coreahblite.v => COREAHBLITE_LIB )
BAYANIN LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB/CCC_0/SB_CCC_0_FCCC.v =>
presynth)
BAYANIN LIB_MAP ($ LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreConfigMaster/
2.0.101/rtl/vlog/core/coreconfigmaster.v => presynth)
Ƙayyade LIB_MAP ($ LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreConfigP/4.0.100/rtl/
vlog/core/coreconfigp.v => presynth)
Ƙayyade LIB_MAP ($ LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreResetP/5.0.103/rtl/
vlog/core/coreresetp_pcie_hotreset.v => presynth)
Ƙayyade LIB_MAP ($ LIB_MAP, ${PROJECT_DIR}/component/Actel/DirectCore/CoreResetP/5.0.103/rtl/
vlog/core/coreresetp.v => presynth)
BAYANIN LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB/FABOSC_0/SB_FABOSC_0_OSC.v =>
presynth)
BAYANIN LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB_HPMS/SB_HPMS.v => presynth)
BAYANIN LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB/SB.v => presynth)
Ƙayyade LIB_MAP ($ LIB_MAP, ${PROJECT_DIR}/component/work/SB_top/SERDES_IF_0/
SB_top_SERDES_IF_0_SERDES_IF.v => presynth)
BAYANIN LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB_top/SB_top.v => presynth)
BAYANIN LIB_MAP ( $LIB_MAP, ${PROJECT_DIR}/component/work/SB_top/testbench.v => presynth)
BAYANIN LIB_MAP ($ LIB_MAP, + => presynth)
Umurni.csh
ncvlog +incdir+.../../component/work/SB_top -cdslib ./cds.lib -hdlvar ./hdl.var -logfile
ncvlog.log -errormax 15 -update -linedebug
../../component/actel/Coccore/coreahbblite/4.0.100/RTL/Voreahblite_addretec.v
../../bangaren/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/
coreahblite_defaultslavesm.v
../../bangaren/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite_masterstagev
../../component/actel/directcore/coreahbblite/4.0.100/RTL/Voreahblite_slaivearber.v
../../bangaren/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite_slavestagev
../../bangaren/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite_matrix2x16.v
../../bangaren/Actel/DirectCore/CoreAHBLite/4.0.100/rtl/vlog/core/coreahblite.v
../../bangaren/aiki/SB/CCC_0/SB_CCC_0_FCCC.v
../../component/Actel/DirectCore/CoreConfigMaster/2.0.101/rtl/vlog/core/coreconfigmaster.v
../../bangaren/Actel/DirectCore/CoreConfigP/4.0.100/rtl/vlog/core/coreconfigp.v
../../componononenuan/corettcore/coreretetp/5.0.103/RORETP_PCOE_HotTreset.v
../../bangaren/Actel/DirectCore/CoreResetP/5.0.103/rtl/vlog/core/coreresetp.v
../../bangaren/aiki/SB/FABOSC_0/SB_FABOSC_0_OSC.v
../../bangaren/aiki/SB/SB.v
SB_top_SERDES_IF_0_SERDES_IF.v
../../bangaren/aiki/SB_top/SB_top.v ../../component/aiki/SB_top/testbench.v
ncelab -Message -cdslib ./cds.lib -hdlvar ./hdl.var
- aikin presynth -logfile ncelab.log -errormax 15 -access +rwc -status presynth.testbench:module
ncsim -Message -batch -cdslib ./cds.lib -hdlvar ./
hdl.var -logfile ncsim.log -errormax 15 -status presynth.testbench:module

4.5 Ta atomatikMicrochip Login)
Rubutun mai zuwa file yana canza ModelSim run.do files cikin sanyi files da ake buƙata don gudanar da simulations ta amfani da Xcelium.
Rubutun File Amfani
perl cadence_parser.pl presynth_run.do postsynth_run.do
postlayout_run.do Microsemi_Family
Wuri_na_Cadence_Dakunan karatu
Cadence_parser.pl
#!/usr/bin/perl -w

##################################### ###############################
############
#Amfani: perl questa_parser.pl presynth_run.do postsynth_run.do postlayout_run.do
Microsemi_Family Precompiled_Libraries_location#

##################################### ###############################
############
amfani da POSIX;
amfani da tsauri;
my ($presynth, $postsynth, $postlayout, $ iyali, $lib_location) = @ARGV;
&questa_parser($presynth, $iyali, $lib_location);
&questa_parser($postsynth, $iyali, $lib_location);

&questa_parser ($ postlayout, $ iyali, $ lib_location);
sub questa_parser {
na $ModelSim_run_do = $_[0];
my $actel_family = $_[1];
na $lib_location = $_[2];
jihara ta;
idan (-e “$ModelSim_run_do”)
{
bude (INFILE,"$ModelSim_run_do");
na @ModelSim_run_do =FILE>;
layin $ na;
idan ( $ModelSim_run_do = ~ m / (presynth) /)
{
'mkdir QUESTA_PRESYNTH';
bude (OUTFILE,”>QUESTA_PRESYNTH/presynth_questa.do”);
$state = $1;
} elsif ( $ModelSim_run_do =~ m/(postsynth)/)
{
'mkdir QUESTA_POSTSYNTH';
bude (OUTFILE,”>QUESTA_POSTSYNTH/postsynth_questa.do”);
$state = $1;
} elsif ( $ModelSim_run_do =~ m/(postlayout)/)
{
`mkdir QUESTA_POSTLAYOUT';
bude (OUTFILE,”>QUESTA_POSTLAYOUT/postlayout_questa.do”);
$state = $1;
} sauran
{
buga “Ba daidai ba abubuwan da aka ba wa file\n";
buga "#Usage: perl questa_parser.pl presynth_run.do postsynth_run.do postlayout_run.do
\"Wurin_Libraries\"\n";
}
layin $ (@ModelSim_run_do)
{
#Ayyukan Gabaɗaya
$line = ~ s / .. \/ mai tsarawa. * kwaikwayo /// g;
$layi =~ s/$state/$state\_questa/g;
#kwafiFILE "$layi \n";
idan ($layi =~ m/vmap\s+.*($actel_family)/)
{
kwafiFILE "vmap $actel_family \"$lib_location\"\n";
} elsif ($layi =~ m/vmap\s+(.*._LIB)/)
{
$line = ~ s / .. \/ bangaren / .. \/ .. \/component/g;
kwafiFILE "$layi \n";
} elsif ($ layi = ~ m/vsim/)
{
$line = ~ s/vsim/vsim -novopt/g;
kwafiFILE "$layi \n";
} sauran
{
kwafiFILE "$layi \n";
}
}
kusa (INFILE);
rufe (OUTFILE);
} kuma {
buga “$ModelSim_run_do babu shi. Sake kunna simulation \n";
}
}

Siemens QuestaSim Saita/SaitinSim (ModelSim Setup)Yi Tambaya)

Gudun.do files, wanda Libero SoC ya samar don simulations ta amfani da ModelSim Microsemi Editions, za a iya amfani da su don yin simintin ta amfani da QuestaSim/ModelSim SE/DE/PE tare da sauyi ɗaya. A cikin ModelSim ME/ModelSim Pro ME run.do file, wurin da aka riga aka haɗa ɗakunan karatu yana buƙatar gyara.
MICROCHIP Libero SoC Simulation Library Software - icon Muhimmi: 
Ta hanyar tsoho, kayan aikin simintin ban da ModelSim Pro ME yana aiwatar da haɓaka ƙira yayin simintin da zai iya tasiri ga gani a cikin kayan aikin kwaikwayo kamar kayan ƙira da abubuwan ƙara kuzari.
Wannan yawanci yana taimakawa wajen rage lokacin aiki na simulation don hadadden siminti, ta amfani da verbose, benches na tantance kai. Koyaya, haɓakawa na asali bazai dace da duk siminti ba, musamman a lokuta da kuke tsammanin bincika sakamakon simintin ta amfani da taga kalaman.
Don magance matsalolin da wannan haɓakawa ya haifar, dole ne ku ƙara umarni masu dacewa da kuma muhawara masu alaƙa yayin kwaikwayo don dawo da gani a cikin ƙira. Don takamaiman umarni na kayan aiki, duba takaddun na'urar da ake amfani da ita.

5.1 Canje-canjen Muhalli (Yi Tambaya)
Masu biyo baya sune masu canjin yanayi da ake buƙata.

  • LM_LICENSE_FILE: dole ne ya haɗa da hanyar zuwa lasisi file.
  • MODEL_TECH: dole ne a gano hanyar zuwa wurin adireshin gida na shigarwa na QuestaSim.
  • PATH: dole ne ya nuna wurin da ake iya aiwatarwa ta MODEL_TECH.

5.2 Canza run.do don Mentor QuestaSimYi Tambaya)
Gudun.do fileZa a iya amfani da s da Libero SoC ya samar don simulators ta amfani da ModelSim Microsemi Editions don yin amfani da siminti ta amfani da QuestaSim/ModelSim_SE tare da sauyi ɗaya.
MICROCHIP Libero SoC Simulation Library Software - icon Muhimmi: Duk ƙirar da aka kwaikwaya ta amfani da QuestaSim dole ne su haɗa da -novopt
zaɓi tare da umarnin vsim a cikin rubutun run.do files.
5.3 Zazzage Laburaren da aka Haɗa (Yi Tambaya)
Zazzage dakunan karatu don Mentor Graphics QuestaSim daga Microsemi's website.

Saita VCS Synopsys (Yi Tambaya)

Gudun da Microsemi ya ba da shawarar ya dogara da Ƙaddamarwa da Tattaunawa a cikin VCS. Wannan takaddar ta ƙunshi rubutun file wanda ke amfani da rubutun run.do files wanda Libero SoC ya samar kuma yana haifar da saitin files da ake buƙata don kwaikwayo na VCS. Rubutun file yana amfani da gudu.do file yin haka.

  • Ƙirƙiri taswirar ɗakin karatu file, wanda aka yi ta amfani da synopsys_sim.setup file wanda ke cikin directory guda ɗaya inda simulation VCS ke gudana.
  • Ƙirƙiri rubutun harsashi file don fayyace da haɗa ƙirar ku ta amfani da VCS.

6.1 Canje-canjen Muhalli (Yi Tambaya)
Saita sauye-sauyen yanayi masu dacewa don VCS dangane da saitin ku. Matsalolin mahalli da ake buƙata kamar yadda takaddun VCS suke:

  • LM_LICENSE_FILE: dole ne ya haɗa da mai nuni zuwa uwar garken lasisi.
  • VCS_HOME: dole ne ya nuna wurin da ake shigar da VCS directory na gida.
  • PATH: dole ne ya haɗa da mai nuni zuwa ga kundin adireshi da ke ƙasa da adireshin VCS_HOME.

6.2 Zazzage Laburaren da aka Haɗa (Yi Tambaya)
Zazzage dakunan karatu don Synopsys VCS daga Microsemi's website.
6.3 VCS Rubutun kwaikwaiyo File (Yi Tambaya)
Bayan kafa VCS da samar da zane da daban-daban run.do files daga Libero SoC, dole ne ku:

  1. Ƙirƙiri taswirar ɗakin karatu file synopsys_sim.saitin; wannan file yana ƙunshe da masu nuni zuwa wurin duk ɗakunan karatu da za a yi amfani da su ta hanyar ƙira.
    MICROCHIP Libero SoC Simulation Library Software - icon  Muhimmi: The file sunan ba dole ba ne ya canza kuma dole ne a kasance a cikin wannan kundin adireshi inda simulation ke gudana. Ga wani tsohonample don irin wannan file don presynthesis simulation.
    AIKI > GAGARI
    SmartFusion2 :
    presynth: ./presynth
    KYAUTA: ./aiki
  2. Bayyana zane daban-daban files, gami da testbench, ta amfani da umarnin vlogan a cikin VCS. Ana iya haɗa waɗannan umarni a cikin rubutun harsashi file. Mai biyo baya shine tsohonample daga cikin umarnin da ake buƙata don ƙayyadaddun ƙira da aka ayyana a cikin rtl.v tare da siffanta testbench ɗin sa a ciki
    testbench.v.
    vlogan + v2k - aikin presynth rtl.v
    vlogan + v2k - aikin presynth testbench.v
  3. Haɗa ƙira ta amfani da VCS ta amfani da umarni mai zuwa.
    vcs –sim_res=1fs presynth.testbench
    Note: The Dole ne a saita ƙudurin lokaci na simintin zuwa 1fs don daidaitaccen simintin aiki.
  4. Da zarar an haɗa ƙirar, fara simulation ta amfani da umarni mai zuwa.
    ./simv
  5. Don kwaikwaiyon bayanan baya, dole ne umarnin VCS ya kasance kamar yadda aka nuna a cikin makullin lambar.
    vcs postlayout.testbench –sim_res=1fs –sdf max: .
    suna >: file hanya > –gui –l postlayout.log

6.4 Iyakoki/Bambanta (Yi Tambaya)
Masu biyowa sune iyakoki/bangare na saitin Synopsys VCS.

  • Za a iya gudanar da simintin VCS don ayyukan Verilog na Libero SoC kawai. Na'urar kwaikwayo ta VCS tana da tsauraran buƙatun yaren VHDL waɗanda ba su cika ta VHDL mai sarrafa kansa ta Libero SoC ba. files.
  • Dole ne ku sami bayanin ƙare $ a cikin Verilog testbench don dakatar da simintin a duk lokacin da kuke so.
    MICROCHIP Libero SoC Simulation Library Software - icon Muhimmi: Lokacin ana gudanar da simulations a yanayin GUI, ana iya ƙayyade lokacin gudu a cikin GUI.

6.5 SampLe Tcl da Shell Script Files (Yi Tambaya)
Perl mai zuwa yana sarrafa tsarar synopsys_sim.setup file da kuma rubutun harsashi mai dacewa files da ake buƙata don haɓakawa, tarawa, da kwaikwaya ƙira.
Idan ƙirar tana amfani da MSS, kwafi test.vec file wanda ke cikin babban fayil ɗin kwaikwayo na aikin Libero SoC a cikin babban fayil ɗin kwaikwayo na VCS. Sashe masu zuwa sun ƙunshi sampda run.do files wanda Libero SoC ya ƙirƙira, gami da daidaitaccen taswirar ɗakin karatu da rubutun harsashi files da ake buƙata don kwaikwayo na VCS.
6.5.1 Gabatarwa (Yi Tambaya)
Presynth_run.do
a hankali saita ACTELLIBNAME SmartFusion2
a hankali saita PROJECT_DIR "/sqa/users/ni/VCS_Tests/Test_DFF"
idan {[file akwai presynth/_info]} {
echo "INFO: Simulators presynth ya riga ya wanzu"
} kuma {
vlib presynth
}
vmap presynth presynth
vmap SmartFusion2 “/captures/lin/11_0_0_23_11prod/lib/ModelSim/precompiled/vlog/smartfusion2”
vlog -work presynth "${PROJECT_DIR}/component/work/SD1/SD1.v"
vlog "+incdir+${PROJECT_DIR}/mai kara kuzari" -aiki presynth "${PROJECT_DIR}/stimulus/SD1_TB1.v"
vsim -L SmartFusion2 -L presynth -t 1fs presynth.SD1_TB1
ƙara kalaman /SD1_TB1/*
ƙara log -r /*
gudu 1000ns
presynth_main.csh
#!/bin/csh -f
saita PROJECT_DIR = "/sqa/users/Ni/VCS_Tests/Test_DFF"
/cad_design/tools/vcs.dir/E-2011.03/bin/vlogan +v2k -aiki presynth “${PROJECT_DIR}/component/
aiki/SD1/SD1.v”
/cad_design/tools/vcs.dir/E-2011.03/bin/vlogan +v2k "+incdir+${PROJECT_DIR}/stimulus" -aiki
presynth "${PROJECT_DIR}/stimulus/SD1_TB1.v"
/cad_design/tools/vcs.dir/E-2011.03/bin/vcs -sim_res=1fs presynth.SD1_TB1 -l compile.log
./simv -l run.log
Synopsys_sim.saitin
AIKI > TSOKACI
SmartFusion2: /VCS/SmartFusion2
presynth: ./presynth
KYAUTA: ./aiki

6.5.2 Bayan-Kira (Yi Tambaya)
postsynth_run.do
a hankali saita ACTELLIBNAME SmartFusion2
a hankali saita PROJECT_DIR "/sqa/users/Ni/VCS_Tests/Test_DFF"
idan {[file akwai postsynth/_info]} {
sake maimaita "INFO: Littattafan simulators sun riga sun wanzu"
} kuma {
vlib postsynth
}
vmap postsynth postsynth
vmap SmartFusion2 “//idm/captures/pc/11_0_1_12_g4x/Designer/lib/ModelSim/precompiled/vlog/
SmartFusion2"
vlog -work postsynth "${PROJECT_DIR}/synthesis/SD1.v"
vlog "+incdir+${PROJECT_DIR}/mai kara kuzari" -aiki postsynth "${PROJECT_DIR}/stimulus/SD1_TB1.v"
vsim -L SmartFusion2 -L postsynth -t 1fs postsynth.SD1_TB1
ƙara kalaman /SD1_TB1/*
ƙara log -r /*
gudu 1000ns
log SD1_TB1/*
fita
Postsynth_main.csh
#!/bin/csh -f
saita PROJECT_DIR = "/sqa/users/Ni/VCS_Tests/Test_DFF"
/cad_design/tools/vcs.dir/E-2011.03/bin/vlogan +v2k -work postsynth “${PROJECT_DIR}/synthesis/
SD1.v"
/cad_design/tools/vcs.dir/E-2011.03/bin/vlogan +v2k "+incdir+${PROJECT_DIR}/stimulus" -aiki
postsynth "${PROJECT_DIR}/stimulus/SD1_TB1.v"
/cad_design/tools/vcs.dir/E-2011.03/bin/vcs -sim_res=1fs postsynth.SD1_TB1 -l compile.log
./simv -l run.log
Synopsys_sim.saitin
AIKI > TSOKACI
SmartFusion2: /VCS/SmartFusion2
postsynth: ./postsynth
KYAUTA: ./aiki
6.5.3 Bayan tsariYi Tambaya)
postlayout_run.do
a hankali saita ACTELLIBNAME SmartFusion2
a hankali saita PROJECT_DIR "E:/ModelSim_Work/Test_DFF"
idan {[file akwai ../designer/SD1/simulation/postlayout/_info]} {
sake maimaita "INFO: Laburare na kwaikwayo ../designer/SD1/simulation/postlayout already wanzu"
} kuma {
vlib ../designer/SD1/simulation/postlayout
}
vmap postlayout ../designer/SD1/simulation/postlayout
vmap SmartFusion2 “//idm/captures/pc/11_0_1_12_g4x/Designer/lib/ModelSim/precompiled/vlog/
SmartFusion2"
vlog -aiki postlayout "${PROJECT_DIR}/designer/SD1/SD1_ba.v"
vlog "+incdir+${PROJECT_DIR}/mai kara kuzari" -aiki postlayout "${PROJECT_DIR}/stimulus/SD1_TB1.v"
vsim -L SmartFusion2 -L postlayout -t 1fs -sdfmax /SD1_0=${PROJECT_DIR}/designer/SD1/
SD1_ba.sdf postlayout.SD1_TB1
ƙara kalaman /SD1_TB1/*
ƙara log -r /*
gudu 1000ns
Postlayout_main.csh
#!/bin/csh -f
saita PROJECT_DIR = "/ VCS_Tests/Test_DFF"
/cad_design/tools/vcs.dir/E-2011.03/bin/vlogan +v2k -aiki postlayout "${PROJECT_DIR}/
mai tsarawa/SD1/SD1_ba.v”
/cad_design/tools/vcs.dir/E-2011.03/bin/vlogan +v2k "+incdir+${PROJECT_DIR}/stimulus" -aiki
postlayout "${PROJECT_DIR}/stimulus/SD1_TB1.v"
/cad_design/tools/vcs.dir/E-2011.03/bin/vcs -sim_res=1fs postlayout.SD1_TB1 -sdf

max:SD1_TB1.SD1_0:${PROJECT_DIR}/designer/SD1/SD1_ba.sdf -l compile.log
./simv -l run.log
Synopsys_sim.saitin
AIKI > TSOKACI
SmartFusion2: /VCS/SmartFusion2
postlayout: ./postlayout
KYAUTA: ./workVCS
6.6 Ta atomatikYi Tambaya)
Ana iya sarrafa kwararar ta atomatik ta amfani da rubutun Perl mai zuwa file don canza ModelSim run.do files cikin VCS rubutun harsashi masu jituwa files, ƙirƙiri kundayen adireshi masu dacewa a cikin kundin kundin kwaikwaiyo na Libero SoC, sannan gudanar da simulations.
Gudanar da rubutun file ta amfani da ma'auni mai zuwa.
perl vcs_parse.pl presynth_run.do postsynth_run.do postlayout_run.do
Vcs_parse_pl
#!/usr/bin/perl -w
##################################### ####################
#
#Amfani: perl vcs_parse.pl presynth_run.do postsynth_run.do postlayout_run.do
#
##################################### #####################
na ($presynth, $postsynth, $postlayout) = @ARGV;
idan (tsarin ("mkdir VCS_Presynth")) {buga "mkdir ya kasa:\n";}
idan (tsarin ("mkdir VCS_Postsynth")) {buga "mkdir ya kasa:\n";}
idan (tsarin ("mkdir VCS_Postlayout")) {buga "mkdir ya kasa:\n";}
chdir(VCS_Presynth);
`cp ../$ARGV[0] .`;
&parse_do($presynth,”presynth”);
chdir ("../");
chdir(VCS_Postsynth);
`cp ../$ARGV[1] .`;
&parse_do($postsynth,”postsynth”);
chdir ("../");
chdir(VCS_Postlayout);
`cp ../$ARGV[2] .`;
&parse_do ($ postlayout, "postlayout");
chdir ("../");
sub parse_do {
my $vlog = "/cad_design/tools/vcs.dir/E-2011.03/bin/vlogan +v2k" ;
na%LIB = ();
zan $file = $__[0];
jihar na = $_[1];
bude (INFILE"$file”) || mutu “Ba za a iya bude File Dalili na iya zama:$!";
idan ($state eq "presynth")
{
bude(OUT1,”>presynth_main.csh”) || mutu “Ba za a iya ƙirƙirar Umurni ba File Dalili na iya zama:$!";
}
elsif ($state eq “postsynth”)
{
bude(OUT1,”>postsynth_main.csh”) || mutu “Ba za a iya ƙirƙirar Umurni ba File Dalili na iya zama:$!";
}
elsif ($state eq “postlayout”)
{
bude(OUT1,”>postlayout_main.csh”) || mutu “Ba za a iya ƙirƙirar Umurni ba File Dalili na iya zama:$!";
}
wani
{
buga "Jihar Simulation ya ɓace \n";
}
bude(OUT2,”>synopsys_sim.setup”) || mutu “Ba za a iya ƙirƙirar Umurni ba File Dalili na iya zama:$!";
# .csh file
buga OUT1 "#!/bin/csh -f\n\n\n" ;
# SATA FILE
buga OUT2 "AIKI > TSOKACI\n";
buga OUT2 “SmartFusion2: /sqa/users/Aditya/VCS/SmartFusion2\n”;
yayin ($line =FILE>)
{

Synopsys VCS Saita

idan ($layi =~ m/saitin shiru PROJECT_DIR\s+\”(.*?)\”/)
{
buga OUT1 "saitin PROJECT_DIR = \"$1"\n\n\n";
}
elsif ( $line = ~ m/vlog.*\.v \”/ )
{
idan ($layi =~ m/\s+(\w*?)\_LIB/)
{
# buga "\$1 =$1 \n";
$temp = "$1″."_LIB";
#print "Temp = $temp \n";
$LIB{$ temp}++;
}
chomp ($ layi);
$layi =~ s/^vlog/$vlog/ ;
$layi =~ s///g;
buga OUT1 "$ line\n";
}
elsif ( ($ layi = ~ m/vsim. * presynth \. (.*)/) || ($ layi = ~ m/vsim.*postsynth \. (.*)/) || ($ layi).
=~ m/vsim.*postlayout\.(.*)/) )
{
$tb = $1;
$tb = ~ s/ // g;
kumfa($tb);
# buga "Sunan TB: $tb \n";
idan ( $line = ~ m/sdf(.*)\.sdf/)
{
chomp ($ layi);
$layi = $1;
# buga "LINE : $line \n" ;
idan ($ layi = ~ m / max /)
{
$line = ~ s/max \/// ;
$layi =~ s/=/:/;
buga OUT1 "\n\n/cad_design/tools/vcs.dir/E-2011.03/bin/vcs -sim_res=1fs postlayout.$tb -sdf
max:$tb.$line.sdf -l compile.log\n" ;
}
elsif ($layi =~ m/min/)
{
$layi =~ s/min \/// ;
$layi =~ s/=/:/;
buga OUT1 "\n\n/cad_design/tools/vcs.dir/E-2011.03/bin/vcs -sim_res=1fs postlayout.$tb -sdf
min:$tb.$line.sdf -l compile.log\n” ;
}
elsif ($layi =~ m/typ/)
{
$line = ~ s/typ \/// ;
$layi =~ s/=/:/;
buga OUT1 "\n\n/cad_design/tools/vcs.dir/E-2011.03/bin/vcs -sim_res=1fs postlayout.$tb -sdf
buga:$tb.$line.sdf -l compile.log\n” ;
}
#-sdfmax /M3_FIC32_0=${PROJECT_DIR}/mai tsarawa/M3_FIC32/M3_FIC32_ba.sdf — Tsarin Sim SDF
#$sdf = "-sdf max:testbench.M3_FIC32_0:${PROJECT_DIR}/designer/M3_FIC32/M3_FIC32_ba.sdf"; -VCS
Tsarin SDF
}
}
}
buga
OUT1 "\n\n"
;
if
($state eq "presynth"
)
{
buga
OUT2 “presynth
: ./presynth\n"
;
buga
OUT1 "/cad_design/tools/vcs.dir/E-2011.03/bin/vcs
-sim_res=1fs presynth.$tb -l
tara.log\n"
;
}
elsif
($state eq "postsynth"
)
{
buga
OUT2 “postsynth
: ./postsynth\n"
;
buga
OUT1 "/cad_design/tools/vcs.dir/E-2011.03/bin/vcs
-sim_res=1fs postsynth.$tb -l
tara.log\n"
;
}
elsif
($state eq "postlayout"
)
{
buga OUT2 "postlayout: ./postlayout\n";
}
wani
{
buga "Jihar Simulation ya ɓace \n";
}
foreach $i (maɓallai%LIB)
{
#print "Maɓalli: $i Darajar: $LIB{$i} \n" ;
buga OUT2 "$i : ./$i\n" ;
}
buga OUT1 "\n\n" ;
buga OUT1 "./simv -l run.log\n" ;
buga OUT2 "DEFAULT: ./work\n";
kusa INFILE;
rufe OUT1;
rufe OUT2;
}

Tarihin Bita (Microchip Login

Tarihin bita ya bayyana canje-canjen da aka aiwatar a cikin takaddar. Canje-canje
an jera su ta hanyar bita, farawa da mafi kyawun bugawa.

Bita Kwanan wata Bayani
A 12/2023 Ana yin canje-canje masu zuwa a cikin wannan bita:
• An canza daftarin aiki zuwa samfurin Microchip. Bita na farko.
• Sashe na 5 da aka sabunta. Siemens QuestaSim Setup/ModelSim Setup don haɗa sabon bayanin kula wanda ke bayyana tasirin ganuwa yayin kwaikwayo da haɓakawa.

Tallafin FPGA Microchip
Ƙungiyar samfuran Microchip FPGA tana goyan bayan samfuran ta tare da sabis na tallafi daban-daban, gami da Sabis na Abokin Ciniki, Cibiyar Tallafin Fasaha ta Abokin Ciniki, a website, da ofisoshin tallace-tallace na duniya.
Ana ba abokan ciniki shawarar ziyartar albarkatun kan layi na Microchip kafin tuntuɓar tallafi saboda da yuwuwar an riga an amsa tambayoyinsu.
Tuntuɓi Cibiyar Tallafawa Fasaha ta hanyar websaiti a www.microchip.com/support. Ambaci lambar Sashe na Na'urar FPGA, zaɓi nau'in shari'ar da ta dace, da ƙaddamar da ƙira files yayin ƙirƙirar shari'ar tallafin fasaha.
Tuntuɓi Sabis na Abokin Ciniki don tallafin samfur mara fasaha, kamar farashin samfur, haɓaka samfur, sabunta bayanai, matsayin tsari, da izini.

  • Daga Arewacin Amirka, kira 800.262.1060
  • Daga sauran duniya, kira 650.318.4460
  • Fax, daga ko'ina cikin duniya, 650.318.8044

Bayanin Microchip
Microchip Website
Microchip yana ba da tallafin kan layi ta hanyar mu websaiti a www.microchip.com/. Wannan webana amfani da site don yin files da bayanai cikin sauƙin samuwa ga abokan ciniki. Wasu daga cikin abubuwan da ake samu sun haɗa da:

  • Tallafin samfur - Taswirar bayanai da errata, bayanin kula da aikace-aikace da sampshirye-shirye, albarkatun ƙira, jagororin mai amfani da takaddun tallafi na hardware, sabbin fitattun software da software da aka adana
  • Gabaɗaya Taimakon Fasaha - Tambayoyin da ake Yi akai-akai (FAQs), buƙatun tallafin fasaha, ƙungiyoyin tattaunawa kan layi, jerin membobin shirin abokan hulɗa na Microchip
  • Kasuwancin Microchip - Mai zaɓin samfur da jagororin ba da oda, sabbin fitowar manema labarai na Microchip, jerin tarukan karawa juna sani da abubuwan da suka faru, jerin ofisoshin tallace-tallace na Microchip, masu rarrabawa da wakilan masana'anta

Sabis ɗin Sanarwa Canjin samfur
Sabis ɗin sanarwar canjin samfur na Microchip yana taimakawa abokan ciniki su kasance a halin yanzu akan samfuran Microchip. Masu biyan kuɗi za su karɓi sanarwar imel a duk lokacin da aka sami canje-canje, sabuntawa, bita ko ƙirƙira masu alaƙa da ƙayyadadden dangin samfur ko kayan aikin haɓaka na ban sha'awa.
Don yin rajista, je zuwa www.microchip.com/pcn kuma bi umarnin rajista.
Tallafin Abokin Ciniki
Masu amfani da samfuran Microchip na iya samun taimako ta hanyoyi da yawa:

  • Mai Rarraba ko Wakili
  • Ofishin Talla na Gida
  • Injiniyan Magance Ciki (ESE)
  • Goyon bayan sana'a

Abokan ciniki yakamata su tuntuɓi mai rarraba su, wakilin ko ESE don tallafi. Hakanan akwai ofisoshin tallace-tallace na gida don taimakawa abokan ciniki. An haɗa lissafin ofisoshin tallace-tallace da wurare a cikin wannan takarda.
Ana samun tallafin fasaha ta hanyar websaiti a: www.microchip.com/support
Siffar Kariyar Lambar Na'urorin Microchip
Kula da cikakkun bayanai masu zuwa na fasalin kariyar lambar akan samfuran Microchip:

  • Samfuran Microchip sun haɗu da ƙayyadaddun bayanai da ke ƙunshe a cikin takamaiman takaddar bayanan Microchip ɗin su.
  • Microchip ya yi imanin cewa dangin samfuran sa suna da tsaro lokacin da aka yi amfani da su ta hanyar da aka yi niyya, cikin ƙayyadaddun aiki, da kuma ƙarƙashin yanayi na yau da kullun.
  • Ƙimar Microchip kuma tana kare haƙƙin mallaka na fasaha da ƙarfi. Ƙoƙarin keta fasalulluka na kariyar lambar samfurin Microchip an haramta shi sosai kuma yana iya keta dokar haƙƙin mallaka na Millennium Digital.
  • Babu Microchip ko kowane masana'anta na semiconductor ba zai iya tabbatar da amincin lambar sa ba. Kariyar lambar ba ta nufin cewa muna ba da garantin samfurin "ba zai karye ba".
    Kariyar lambar tana ci gaba da haɓakawa. Microchip ya himmatu don ci gaba da haɓaka fasalin kariyar lambar samfuranmu.

Sanarwa na Shari'a
Ana iya amfani da wannan ɗaba'ar da bayanin nan tare da samfuran Microchip kawai, gami da ƙira, gwadawa, da haɗa samfuran Microchip tare da aikace-aikacenku. Amfani da wannan bayanin ta kowace hanya ya saba wa waɗannan sharuɗɗan. Bayani game da aikace-aikacen na'ura an bayar da shi ne kawai don jin daɗin ku kuma ana iya maye gurbinsu da sabuntawa. Alhakin ku ne don tabbatar da cewa aikace-aikacenku ya dace da ƙayyadaddun bayananku. Tuntuɓi ofishin tallace-tallace na Microchip na gida don ƙarin tallafi ko, sami ƙarin tallafi a www.microchip.com/en-us/support/design-help/client-support-services.
WANNAN BAYANI AN BAYAR DA MICROCHIP "KAMAR YADDA". MICROCHIP BA YA YI WAKILI KO GARANTIN KOWANE IRIN BAYANI KO BAYANI, RUBUTU KO BAKI, DOKA KO SAURAN BA, GAME DA BAYANIN GAME DA BAYANI AMMA BAI IYA IYAKA GA WANI GARGADI BA, DA KYAUTATA DON MUSAMMAN MANUFAR, KO GARANTIN DA KE DANGANTA DA SHARADINSA, INGANCI, KO AIKINSA.
BABU WANI FARKO MICROCHIP BA ZAI IYA HANNU GA DUK WATA BAYANI NA MUSAMMAN, HUKUNCI, MASU FARU, KO SAKAMAKON RASHI, LALATA, KUDI, KO KUDI NA KOWANE IRIN ABINDA YA DANGANE BAYANI KO SAMUN HANYAR AMFANINSA, ANA SHAWARAR DA YIWU KO LALACEWAR DA AKE SANYA. ZUWA CIKAKKIYAR DOKA, JAMA'AR DOKAR MICROCHIP A KAN DUK DA'AWA A KOWANE HANYA DAKE DANGANTA BAYANI KO AMFANINSA BA ZAI WUCE YAWAN KUDADE BA, IDAN WATA, CEWA KA BIYA GASKIYA GA GADON.
Amfani da na'urorin Microchip a cikin tallafin rayuwa da/ko aikace-aikacen aminci gabaɗaya yana cikin haɗarin mai siye, kuma mai siye ya yarda ya kare, ramuwa da riƙe Microchip mara lahani daga kowane lalacewa, iƙirari, dacewa, ko kashe kuɗi sakamakon irin wannan amfani. Ba a isar da lasisi, a fakaice ko akasin haka, ƙarƙashin kowane haƙƙin mallaka na Microchip sai dai in an faɗi haka.
Alamomin kasuwanci
Sunan Microchip da tambari, tambarin Microchip, Adaptec, AVR, tambarin AVR, AVR Freaks, BestTime, BitCloud, CryptoMemory, CryptoRF, dsPIC, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXStylus MediaLB, megaAVR, Microsemi, tambarin Microsemi, MAFI YAWAN tambari, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, tambarin PIC32, PolarFire, Prochip Designer, QTouch, SAM-BA, Sengenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetric , SyncServer, Tachyon, TimeSource, tinyAVR, UNI/O, Vectron, da XMEGA alamun kasuwanci ne masu rijista na Microchip Technology Incorporated a cikin Amurka da sauran ƙasashe.
AgileSwitch, APT, ClockWorks, Kamfanin Haɓaka Sarrafa Sarrafa, EtherSynch, Flashtec, Sarrafa Saurin Saurin, HyperLight Load, Libero, motorBench, mTouch, Powermite 3, Daidaitaccen Edge, ProASIC, ProASIC Plus, Tambarin ProASIC Plus, Shuru- Waya, SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub, TimePictra, TimeProvider, TrueTime, da ZL alamun kasuwanci ne masu rijista na Microchip Technology Incorporated a cikin Amurka
Maɓallin Maɓalli na kusa, AKS, Analog-for-da-Digital Age, Duk wani Capacitor, AnyIn, AnyOut, Ƙarfafa Canjawa, BlueSky, BodyCom, Clockstudio, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPImicnatching Average, Matsakaicin Aiki. , DAM, ECAN, Espresso T1S, EtherGREEN, GridTime, IdealBridge, In-Circuit Serial Programming, ICSP, INICnet, Intelligent Paralleling, IntelliMOS, Inter-Chip Connectivity, JitterBlocker, Knob-on-Display, KoD, maxCrypto, maxView, memBrain, Mindi, MiWi, MPASM, MPF, Tambarin Tambarin MPLAB, MPLIB, MPLINK, MultiTRAK, NetDetach, Ƙwararren Code Generation, PICDEM, PICDEM.net,
PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, RTAX, RTG4, SAMICE, Serial Quad I/O, simpleMAP, SimpliPHY, SmartBuffer, SmartHLS, SMART-IS, storClad, SQI, SuperSwitcher,
SuperSwitcher II, Switchtec, SynchroPHY, Jimlar Jimiri, Amintaccen Lokaci, TSHARC, USBCheck, VariSense, VectorBlox, VeriPHY, ViewSpan, WiperLock, XpressConnect, da ZENA alamun kasuwanci ne na Microchip Technology Incorporated
a Amurka da sauran kasashe.
SQTP alamar sabis ce ta Microchip Technology Incorporated a cikin Amurka
Alamar Adaptec, Mitar Buƙatu, Fasahar Adana Silicon, da Symmcom alamun kasuwanci ne masu rijista na Microchip Technology Inc. a wasu ƙasashe.
GestIC alamar kasuwanci ce mai rijista ta Microchip Technology Germany II GmbH & Co. KG, reshen Microchip Technology Inc., a wasu ƙasashe.
Duk sauran alamun kasuwanci da aka ambata a nan mallakin kamfanoninsu ne.
© 2023, Microchip Technology Incorporated da rassanta. Duka Hakkoki.
ISBN: 978-1-6683-3694-6
Tsarin Gudanar da inganci
Don bayani game da Tsarin Gudanar da Ingancin Microchip, da fatan za a ziyarci www.microchip.com/quality.

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