intel Native Loopback Accelerator Functional Unit (AFU) Phau Ntawv Qhia

Cov ntsiab lus zais

1 Intel Native Loopback Accelerator Functional Unit (AFU)

2 Hais txog Cov Ntaub Ntawv no

3 Lub Native Loopback Accelerator Functional Unit (AFU)

4 Cov ntaub ntawv kho dua tshiab rau Native Loopback Accelerator Functional Unit (AFU) Phau Ntawv Qhia

5 Cov ntaub ntawv / Cov ntaub ntawv

5.1 Cov ntaub ntawv

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Intel Native Loopback Accelerator Functional Unit (AFU)

Hais txog Cov Ntaub Ntawv no

Cov rooj sib txoos
Table 1. Document Conventions

Convention	Kev piav qhia
#	Precedes ib lo lus txib uas qhia tias cov lus txib yuav tsum tau nkag mus rau hauv paus.
$	Qhia tau hais tias yuav tsum tau nkag mus ua tus neeg siv.
Qhov no font	Filecov npe, cov lus txib, thiab cov lus tseem ceeb tau luam tawm hauv daim ntawv no. Cov kab hais kom ntev tau luam tawm hauv daim ntawv no. Txawm hais tias cov kab hais kom ntev yuav qhwv mus rau kab tom ntej, qhov rov qab tsis yog ib feem ntawm cov lus txib; tsis txhob nias nkag.
	Qhia qhov chaw cov ntawv nyeem uas tshwm ntawm lub kaum sab xis yuav tsum tau hloov nrog tus nqi tsim nyog. Tsis txhob nkag mus rau lub kaum sab xis.

Cov ntsiab lus
Table 2. Cov ntsiab lus

Cov ntsiab lus	Kev nthuav dav	Kev piav qhia
AF	Accelerator muaj nuj nqi	Compiled Hardware Accelerator duab siv nyob rau hauv FPGA logic uas accelerates ib daim ntawv thov.
AFU	Accelerator Functional Unit	Kho vajtse Accelerator siv nyob rau hauv FPGA logic uas offloads ib tug xam ua hauj lwm rau ib daim ntawv thov los ntawm CPU los txhim kho kev ua tau zoo.
API	Daim ntawv thov Programming Interface	Cov txheej txheem subroutine txhais, raws tu qauv, thiab cov cuab yeej rau kev tsim software siv.
ASE	AFU Simulation Ib puag ncig	Co-simulation ib puag ncig uas tso cai rau koj siv tib lub tswv yim thov thiab AF hauv ib puag ncig simulation. ASE yog ib feem ntawm Intel® Acceleration Stack rau FPGAs.
CCI-P	Core Cache Interface	CCI-P yog tus qauv interface AFUs siv los sib txuas lus nrog tus tswv tsev.
CL	Cache Kab	64-byte cache kab
DFH	Ntaus Feature Header	Tsim ib daim ntawv txuas ntawm cov ntawv headers los muab txoj hauv kev txuas ntxiv ntawm kev ntxiv cov yam ntxwv.
FIM	FPGA Interface Manager	FPGA kho vajtse uas muaj FPGA Interface Unit (FIU) thiab sab nraud interfaces rau kev nco, kev sib txuas, thiab lwm yam. Lub Accelerator Function (AF) cuam tshuam nrog FIM thaum lub sijhawm ua haujlwm.
FIU	FPGA Interface Unit	FIU yog txheej txheej txheej txheej txheej txheej platform uas ua tus choj ntawm lub platform interfaces xws li PCIe *, UPI thiab AFU-sab interfaces xws li CCI-P.
*txuas ntxiv…*

Intel Corporation. Txhua txoj cai. Intel, Intel logo, thiab lwm yam Intel cov cim yog cov cim lag luam ntawm Intel Corporation lossis nws cov koom haum. Intel lav kev ua tau zoo ntawm nws cov FPGA thiab cov khoom lag luam semiconductor rau cov kev qhia tshwj xeeb tam sim no raws li Intel tus qauv kev lees paub, tab sis muaj txoj cai los hloov cov khoom thiab cov kev pabcuam txhua lub sijhawm yam tsis muaj ntawv ceeb toom. Intel xav tias tsis muaj lub luag haujlwm lossis kev lav phib xaub uas tshwm sim los ntawm daim ntawv thov lossis siv cov ntaub ntawv, cov khoom lag luam, lossis cov kev pabcuam uas tau piav qhia hauv no tshwj tsis yog raws li tau pom zoo hauv kev sau ntawv los ntawm Intel. Intel cov neeg siv khoom tau qhia kom tau txais qhov tseeb version ntawm cov cuab yeej tshwj xeeb ua ntej tso siab rau cov ntaub ntawv tshaj tawm thiab ua ntej muab xaj rau cov khoom lossis cov kev pabcuam. * Lwm lub npe thiab hom yuav raug lees paub raws li cov cuab yeej ntawm lwm tus.

Cov ntsiab lus	Kev nthuav dav	Kev piav qhia
MPF	Memory Properties Factory	MPF yog ib qho Kev Txhim Kho Hauv Tsev (BBB) uas AFUs tuaj yeem siv los muab CCI-P kev tsim kho tsheb khiav lag luam rau kev lag luam nrog FIU.
Msg	Xov xwm	Message – kev ceeb toom tswj
NLB	Native Loopback	NLB ua haujlwm nyeem thiab sau ntawv mus rau CCI-P txuas mus kuaj kev sib txuas thiab kev xa tawm.
RdLine_I	Nyeem Kab Invalid	Nco Nyeem Thov, nrog FPGA cache hint teeb rau qhov tsis raug. Cov kab tsis yog cached hauv FPGA, tab sis yuav ua rau FPGA cache muaj kuab paug. Nco tseg: Lub cache tag taug qab cov xwm txheej thov rau txhua qhov kev thov tseem ceeb ntawm Intel Ultra Path Interconnect (Intel UPI). Yog li ntawd, txawm tias RdLine_I raug cim tsis raug thaum ua tiav, nws siv lub cache tag ib ntus txhawm rau taug qab cov xwm txheej thov ntawm UPI. Qhov kev txiav txim no tuaj yeem ua rau raug tshem tawm ntawm kab cache, ua rau cache muaj kuab paug. Lub advantage ntawm kev siv RdLine_I yog tias nws tsis tau taug qab los ntawm CPU directory; yog li nws tiv thaiv snooping ntawm CPU.
RdLine-S	Nyeem Kab Qhia	Nco nyeem thov nrog FPGA cache hint teem rau sib koom. Ib qho kev sim ua kom nws nyob hauv FPGA cache hauv ib lub xeev sib koom.
WrLine_I	Sau kab Invalid	Nco Sau Thov, nrog FPGA cache hint teeb rau Invalid. FIU sau cov ntaub ntawv tsis muaj lub siab xav khaws cov ntaub ntawv hauv FPGA cache.
WrLine_M	Sau Kab Hloov Kho	Nco Sau Thov, nrog rau FPGA cache hint teem rau Hloov. FIU sau cov ntaub ntawv thiab tawm hauv FPGA cache hauv lub xeev hloov.

Acceleration Glossary
Table 3. Acceleration Stack rau Intel Xeon® CPU nrog FPGAs Glossary

Lub sij hawm	Cov ntawv luv	Kev piav qhia
Intel Acceleration Stack rau Intel Xeon® CPU nrog FPGAs	Acceleration Stack	Ib qho kev sau ntawm software, firmware, thiab cov cuab yeej uas muab kev ua tau zoo- optimized txuas ntawm Intel FPGA thiab Intel Xeon processor.
Intel FPGA Programmable Acceleration Card (Intel FPGA PAC)	Intel FPGA PAC Cov	PCIe FPGA accelerator daim npav. Muaj FPGA Interface Manager (FIM) uas ua ke nrog Intel Xeon processor hla lub npav PCIe.

Lub Native Loopback Accelerator Functional Unit (AFU)

Native Loopback (NLB) AFU Tshajview

NLB sample AFUs suav nrog ib txheej ntawm Verilog thiab System Verilog files los ntsuas kev nco nyeem thiab sau ntawv, bandwidth, thiab latency.

Cov pob no suav nrog peb AFUs uas koj tuaj yeem tsim los ntawm tib RTL qhov chaw. Koj qhov kev teeb tsa ntawm RTL qhov chaws tsim cov AFUs no.

NLB Sample Accelerator Function (AF)
The $OPAE_PLATFORM_ROOT/hw/samples directory stores source code rau NLB sample AFUs:

nlb_mode_0
nlb_mode_0_stp
nlb_mode_3

Nco tseg: The $DCP_LOC/hw/samples directory stores NLB sample AFUs qhov chaws rau 1.0 tso tawm pob.

To taub NLB sample AFU cov qauv code thiab yuav ua li cas los tsim nws, xa mus rau ib qho ntawm cov nram qab no Quick Start Guides (nyob ntawm seb Intel FPGA PAC koj siv):

Yog tias koj siv Intel PAC nrog Intel Arria® 10 GX FPGA, xa mus rau IntelProgrammable Acceleration Card nrog Intel Arria 10 GX FPGA.
Yog tias koj siv Intel FPGA PAC D5005, xa mus rau Intel Acceleration Stack Quick Start Guide rau Intel FPGA Programmable Acceleration Card D5005.

Lub pob tso tawm muab cov nram qab no peb sample AFs:

NLB hom 0 AF: xav tau hello_fpga lossis fpgadiag utility los ua qhov kev xeem lpbk1.
NLB hom 3 AF: yuav tsum tau siv fpgadiag los ua qhov kev xeem, nyeem, thiab sau ntawv.

NLB hom 0 stp AF: xav tau hello_fpga lossis fpgadiag qhov hluav taws xob los ua qhov kev xeem lpbak1.
Nco tseg: Lub nlb_mode_0_stp yog tib yam AFU li nlb_mode_0 tab sis nrog teeb liab Tap debug feature enabled.
Cov khoom siv fpgadiag thiab hello_fpga pab qhov tsim nyog AF los kuaj xyuas, kuaj thiab tshaj tawm ntawm FPGA kho vajtse.

Daim duab 1. Native Loopback (nlb_lpbk.sv) Sab saum toj Level Wrapper

Table 4. NLB Files

File Lub npe	Kev piav qhia
nlb_lpbk.sv	Sab saum toj-theem wrapper rau NLB uas instantiates tus thov thiab arbiter.
ib arbiter.sv	Instantiates qhov kev xeem AF.
thov.sv	Txais kev thov los ntawm tus kws txiav txim plaub thiab tsim cov ntawv thov raws li CCI-P specification. Kuj tseem siv tswj kev ntws.
nlb_csr.sv	Ua raws li 64-ntsis nyeem / sau Kev Tswj thiab Txheej Txheem (CSR) sau npe. Cov ntawv sau npe txhawb nqa 32- thiab 64-ntsis nyeem thiab sau ntawv.
nlb_gram_sdp.sv	Siv lub generic dual-port RAM nrog ib qho chaw sau ntawv thiab ib qho chaw nyeem ntawv.

NLB yog qhov kev siv ntawm AFU sib xws nrog Intel Acceleration Stack rau Intel Xeon CPU nrog FPGAs Core Cache Interface (CCI-P) Phau Ntawv Qhia. NLB lub luag haujlwm tseem ceeb yog ua kom muaj kev sib txuas nrog tus tswv tsev siv cov qauv kev nco sib txawv. NLB kuj ntsuas bandwidth thiab nyeem / sau latency. Kev xeem bandwidth muaj cov kev xaiv hauv qab no:

100% nyeem
100% sau
50% nyeem thiab 50% sau

Cov ntaub ntawv ntsig txog

Intel Acceleration Stack Quick Start Guide rau Intel Programmable Acceleration Card nrog Arria 10 GX FPGA

Acceleration Stack rau Intel Xeon CPU nrog FPGAs Core Cache Interface (CCI-P) Phau Ntawv Qhia
Intel Acceleration Stack Quick Start Guide rau Intel FPGA Programmable Acceleration Card D5005

Native Loopback Control thiab Status Register Descriptions
Table 5. CSR npe, chaw nyob thiab piav qhia

Byte Chaw nyob (OPAE)	Lo lus Chaw nyob (CCI-P)	Nkag mus	Lub npe	Dav	Kev piav qhia
0 x 0000	0 x 0000	RO	DFH	64	AF Device Feature Header.
0 x 0008	0 x 0002	RO	AFU_ID_L	64	AF ID qis.
0 x 0010	0 x 0004	RO	AFU_ID_H	64	AF ID siab.
0 x 0018	0 x 0006	Rsvd	CSR_DFH_RSVD0	64	Yuav Tsum Reserved 0.
0 x 0020	0 x 0008	RO	CSR_DFH_RSVD1	64	Yuav Tsum Reserved 1.
0 x 0100	0 x 0040	RW	CSR_SCRATCHPAD0	64	Scratchpad sau npe 0.
0 x 0108	0 x 0042	RW	CSR_SCRATCHPAD1	64	Scratchpad sau npe 2.
0 x 0110	0 x 0044	RW	CSR_AFU_DSM_BASE L	32	Tsawg 32-ntsis ntawm AF DSM qhov chaw nyob. Qhov qis 6 ntsis yog 4 × 00 vim qhov chaw nyob yog ua raws li 64-byte cache kab loj.
0 x 0114	0 x 0045	RW	CSR_AFU_DSM_BASE H	32	Sab saum toj 32-ntsis ntawm AF DSM qhov chaw nyob.
0 x 0120	0 x 0048	RW	CSR_SRC_ADDR	64	Pib qhov chaw nyob ntawm lub cev rau qhov chaw tsis nyob. Txhua qhov kev thov nyeem tau tsom rau cheeb tsam no.
0 x 0128	0 x004a	RW	CSR_DST_ADDR	64	Pib qhov chaw nyob ntawm lub cev rau qhov chaw tsis nyob. Txhua daim ntawv thov tsom rau cheeb tsam no
0 x 0130	0x004 wb	RW	CSR_NUM_LINES	32	Tus naj npawb ntawm cov kab cache.
0 x 0138	0 x004e	RW	CSR_CTL	32	Tswj kev xeem khiav, pib, nres, quab yuam ua tiav.
0 x 0140	0 x 0050	RW	CSR_CFG	32	Configures test parameters.
0 x 0148	0 x 0052	RW	CSR_INACT_THRESH	32	Inactivity pib txwv.
0 x 0150	0 x 0054	RW	CSR_INTERRUPT0	32	SW faib cuam tshuam APIC ID thiab Vector rau ntaus ntawv.
DSM Offset Map
0 x 0040	0 x 0010	RO	DSM_STATUS	32	Test raws li txoj cai thiab yuam kev register.

Table 6. CSR Bit Fields nrog Examples
Cov lus no teev cov CSR me me teb uas nyob ntawm tus nqi ntawm CSR_NUM_LINES, . Hauv example nram = 14.

Lub npe	Bit Field	Nkag mus	Kev piav qhia
CSR_SRC_ADDR	[63:]	RW	2^(N+6)MB raws li qhov chaw nyob taw qhia rau qhov pib ntawm kev nyeem tsis tau.
CSR_SRC_ADDR	[-1:0]	RW	0 x0.
CSR_DST_ADDR	[63:]	RW	2^(N+6)MB dlhos qhov chaw nyob taw tes rau qhov pib ntawm kev sau tsis.
CSR_DST_ADDR	[-1:0]	RW	0 x0.
CSR_NUM_LINES	[31:]	RW	0 x0.
*txuas ntxiv…*

Lub npe	Bit Field	Nkag mus	Kev piav qhia
	[-1:0]	RW	Tus lej ntawm cov kab cache nyeem lossis sau. Qhov chaw pib no yuav txawv rau txhua qhov kev xeem AF. Nco tseg: Xyuas kom meej tias qhov chaw thiab qhov chaw buffers loj txaus kom haum rau kab cache. CSR_NUM_LINES yuav tsum tsawg dua lossis sib npaug .
Rau cov txiaj ntsig hauv qab no, xav tias = 14. Tom qab ntawd, CSR_SRC_ADDR thiab CSR_DST_ADDR lees txais 2^20 (0x100000).
CSR_SRC_ADDR	[31:14]	RW	1MB aligned chaw nyob.
CSR_SRC_ADDR	[13:0]	RW	0 x0.
CSR_DST_ADDR	[31:14]	RW	1MB aligned chaw nyob.
CSR_DST_ADDR	[13:0]	RW	0 x0.
CSR_NUM_LINES	[31:14]	RW	0 x0.
CSR_NUM_LINES	[13:0]	RW	Tus lej ntawm cov kab cache nyeem lossis sau. Qhov chaw pib no yuav txawv rau txhua qhov kev xeem AF. Nco tseg: Xyuas kom meej tias qhov chaw thiab qhov chaw buffers loj txaus kom haum rau kab cache.

Table 7. Ntxiv CSR Bit Fields

Lub npe	Bit Field	Nkag mus	Kev piav qhia
CSR_CTL	[31:3]	RW	Khaws tseg.
	[2]	RW	Kev sim ua kom tiav. Sau ntawv xeem tiav tus chij thiab lwm yam kev ua tau zoo suav rau csr_stat. Tom qab yuam kev ua tiav, lub xeev kho vajtse zoo ib yam rau qhov tsis raug yuam kom ua tiav.
	[1]	RW	Pib qhov kev xeem ua tiav.
	[0]	RW	Active low test pib dua. Thaum qis, tag nrho cov configuration parameters hloov mus rau lawv cov nqi qub.
CSR_CFG	[29]	RW	cr_interrupt_testmode kuaj cuam tshuam. Tsim ib qho kev cuam tshuam thaum kawg ntawm txhua qhov kev xeem.
	[28]	RW	cr_interrupt_on_error xa kev cuam tshuam thaum ua yuam kev
			kuaj pom.
	[27:20]	RW	cr_test_cfg teeb tsa tus cwj pwm ntawm txhua hom kev sim.
	[13:12]	RW	cr_chsel xaiv cov channel virtual.
	[10:9]	RW	cr_rdsel teeb tsa hom kev thov nyeem. Cov encodings muaj
			cov nram qab no siv tau:
			• 1'b00: RdLine_S
			• 2'b01: RdLine_I
			• 2'b11: Hom sib xyaw
	[8]	RW	cr_delay_en enables random ncua kev nkag ntawm kev thov.
	[6:5]	RW	Configures test mode, cr_multiCL-len. Cov nqi siv tau yog 0,1, thiab 3.
	[4:2]	RW	cr_mode, configures xeem hom. Cov nqi hauv qab no siv tau:
			• 3'b000: LPBK1
			• 3'b001: Nyeem
			• 3'b010: Sau
			• 3'b011: TRPUT
*txuas ntxiv…*

Lub npe	Bit Field	Nkag mus	Kev piav qhia
			Yog xav paub ntxiv txog hom kev xeem, saib mus rau Test hom lub ntsiab lus hauv qab no.
	[1]	RW	c_cont xaiv qhov kev xeem rollover lossis kev xeem txiav. • Thaum 1'b0, qhov kev xeem xaus. Hloov kho cov xwm txheej CSR thaum CSR_NUM_LINES suav tau mus txog. • Thaum 1'b1, qhov kev xeem dov mus rau qhov chaw pib tom qab nws nce mus txog CSR_NUM_LINES suav. Nyob rau hauv rollover hom, qhov kev xeem terminates tsuas yog thaum yuam kev.
	[0]	RW	cr_wrthru_en hloov ntawm WrLine_I thiab Wrline_M thov hom. • 1'b0: WrLine_M • 1'b1: WrLine_I
CSR_INACT_THRESHOLD	[31:0]	RW	Inactivity pib txwv. Txheeb xyuas lub sijhawm ntawm cov khw muag khoom thaum lub sijhawm sim khiav. Suav tus naj npawb ntawm qhov sib law liag tsis ua haujlwm. Yog qhov tsis ua haujlwm suav > CSR_INACT_THRESHOLD, tsis muaj kev thov raug xa, tsis muaj lus teb tau txais, thiab lub teeb liab inact_timeout tau teeb tsa. Sau 1 rau CSR_CTL[1] qhib lub txee no.
CSR_INTERRUPT0	[23:16]	RW	Interrupt Vector Number rau lub cuab yeej.
CSR_INTERRUPT0	[15:0]	RW	apic_id yog APIC OD rau lub cuab yeej.
DSM_STATUS	[511:256]	RO	yuam kev dump form Test Mode.
	[255:224]	RO	End Overhead.
	[223:192]	RO	Pib Lub Taub Hau.
	[191:160]	RO	Tus lej Sau.
	[159:128]	RO	Tus naj npawb nyeem.
	[127:64]	RO	Lub moos.
	[63:32]	RO	Test yuam kev register.
	[31:16]	RO	Sib piv thiab sib pauv kev vam meej txee.
	[15:1]	RO	Cim ID rau txhua tus txheej xwm DSM sau.
	[0]	RO	Test tiav chij.

Test hom
CSR_CFG[4:2] configures hom kev xeem. Plaub qhov kev xeem hauv qab no muaj:

LPBK 1: Qhov no yog ib qho kev ntsuam xyuas kev nco. AF luam CSR_NUM_LINES los ntawm qhov chaw tsis mus rau qhov chaw tsis nyob. Tom qab kev xeem tiav, lub software sib piv qhov chaw thiab qhov chaw tsis muaj chaw nyob.

Nyeem: Qhov kev ntsuam xyuas no txhawb txoj kev nyeem ntawv thiab ntsuas kev nyeem bandwidth lossis latency. AF nyeem CSR_NUM_LINES pib los ntawm CSR_SRC_ADDR. Qhov no tsuas yog bandwidth lossis latency test. Nws tsis txheeb xyuas cov ntaub ntawv nyeem.
Sau: Qhov kev sim no txhawb txoj kev sau ntawv thiab ntsuas kev sau bandwidth lossis latency. AF nyeem CSR_NUM_LINES pib los ntawm CSR_SRC_ADDR. Qhov no tsuas yog bandwidth lossis latency test. Nws tsis txheeb xyuas cov ntaub ntawv sau.

TRPUT: Qhov kev xeem no muab cov ntawv nyeem thiab sau. Nws nyeem CSR_NUM_LINES pib los ntawm CSR_SRC_ADDR qhov chaw thiab sau CSR_NUM_LINES rau CSR_SRC_ADDR. Nws kuj ntsuas kev nyeem thiab sau bandwidth. Qhov kev sim no tsis kuaj cov ntaub ntawv. Cov ntawv nyeem thiab sau ntawv tsis muaj kev cuam tshuam

Cov lus hauv qab no qhia txog CSR_CFG encodings rau plaub qhov kev xeem. Cov lus no teev thiab CSR_NUM_LINES, = 14. Koj tuaj yeem hloov tus lej ntawm cov kab cache los ntawm kev hloov kho CSR_NUM_LINES rau npe.

Table 8. Cov qauv kuaj

FPGA Diagnostics: fpgadiag
Cov khoom siv fpgadiag suav nrog ntau qhov kev sim tshuaj ntsuam xyuas, kuaj, thiab tshaj tawm ntawm FPGA kho vajtse. Siv cov khoom siv fpgadiag los khiav txhua hom kev sim. Yog xav paub ntxiv txog kev siv fpgadiag utility, xa mus rau fpgadiag seem hauv Open Programmable Acceleration Engine (OPAE) Tools Guide.

NLB Mode0 Hello_FPGA Test Flow

Software pib ua lub cim xeeb ntaus ntawv (DSM) rau xoom.
Software sau DSM BASE chaw nyob rau AFU. CSR Write(DSM_BASE_H), CSRWrite(DSM_BASE_L)

Software npaj qhov chaw thiab qhov chaw nco tsis tau. Qhov kev npaj no yog kuaj tshwj xeeb.
Software sau CSR_CTL[2:0] = 0x1. Qhov kev sau no coj qhov kev sim tawm ntawm kev pib dua thiab mus rau hauv hom kev teeb tsa. Kev teeb tsa tuaj yeem ua tau tsuas yog thaum CSR_CTL[0]=1 & CSR_CTL[1]=1.

Software teeb tsa qhov ntsuas ntsuas, xws li src, destaddress, csr_cfg, lej kab, thiab lwm yam.
Software CSR sau CSR_CTL[2:0] = 0x3. AF pib sim ua tiav.

Kev xeem tiav:
- Kho vajtse ua tiav thaum qhov kev xeem ua tiav lossis kuaj pom qhov yuam kev. Thaum ua tiav, kho vajtse AF hloov kho DSM_STATUS. Software polls DSM_STATUS[31:0]==1 txhawm rau kuaj qhov ua tiav.
- Software tuaj yeem yuam kev ua tiav los ntawm kev sau CSR sau CSR_CTL[2:0] = 0x7. Kho vajtse AF hloov tshiab DSM_STATUS.

Cov ntaub ntawv kho dua tshiab rau Native Loopback Accelerator Functional Unit (AFU) Phau Ntawv Qhia

Cov ntaub ntawv Version	Intel Acceleration Stack Version	Hloov
2019.08.05	2.0 (txhawb nrog Intel Quartus Prime Pro tsab 18.1.2) thiab 1.2 (txhawb nrog Intel Quartus Prime Pro Tsab Ntawv 17.1.1)	Ntxiv kev txhawb nqa rau Intel FPGA PAC D5005 platform hauv kev tso tawm tam sim no.
2018.12.04	1.2 (txhawb nrog Intel Quartus® Prime Pro tsab 17.1.1)	Txhim kho kev tso tawm.
2018.08.06	1.1 (txhawb nrog Intel Quartus Prime Pro tsab 17.1.1) thiab 1.0 (txhawb nrog Intel Quartus Prime Pro Tsab Ntawv 17.0.0)	Hloov kho qhov chaw ntawm qhov chaws rau NLB sample AFU NLB Sample Accelerator Function (AF) ntu.
2018.04.11	1.0 (txhawb nrog Intel Quartus Prime Pro tsab 17.0.0)	Kev tso tawm thawj zaug.

Cov ntaub ntawv / Cov ntaub ntawv

Intel Native Loopback Accelerator Functional Unit (AFU) [ua pdf] Cov neeg siv phau ntawv qhia
Native Loopback Accelerator Functional Unit AFU, Native Loopback, Accelerator Functional Unit AFU, Functional Unit AFU

Cov ntaub ntawv

Cov neeg siv phau ntawv