SmartFusion2
DDR Controller uye Serial High Speed ​​​​Mutongi
Initialization Methodology
User Guide

Nhanganyaya

Paunenge uchigadzira dhizaini uchishandisa SmartFusion2 mudziyo, kana ukashandisa imwe yeaviri maDDR controller (FDDR kana MDDR) kana chero yeSerial High speed controller (SERDESIF) mabhuroko, unofanira kutanga maregisheni ezvivharo izvi panguva yekumhanya isati yasvika. vanogona kushandiswa. For example, yeDDR controller, unofanira kuseta iyo DDR modhi (DDR3/DDR2/LPDDR), PHY upamhi, burst mode uye ECC.
Saizvozvo, kune SERDESIF block inoshandiswa sePCIe endpoint, unofanirwa kuseta iyo PCIE BAR kuAXI (kana AHB) hwindo.
Gwaro iri rinotsanangura matanho anodiwa kugadzira Libero dhizaini iyo inongotanga iyo DDR controller uye SERDESIF inovhara pamagetsi kumusoro. Inotsanangurawo maitiro ekugadzira iyo firmware kodhi kubva kuLibero SOC iyo inoshandiswa mune yakamisikidzwa dhizaini kuyerera.
Tsanangudzo yakadzama yedzidziso yekushanda inopiwa kutanga.
Chikamu chinotevera chinotsanangura nzira yekugadzira dhizaini yakadai uchishandisa Libero SoC System Builder, chishandiso chine simba chekugadzira icho, pakati pezvimwe zvinhu, chinogadzira iyo 'initialization' mhinduro kwauri kana uri kushandisa DDR kana SERDESIF zvidhinha mukugadzira kwako.
Chikamu chinotevera chinotsanangura nzira yekuisa yakakwana 'yekutanga' mhinduro pamwechete pasina kushandisa iyo SmartFusion2 System Builder. Izvi zvinobatsira kutsanangura zvinofanirwa kuitwa kana iwe usingade kushandisa iyo System Builder, uye zvakare inotsanangura izvo chaizvo izvo System Builder chishandiso chinokugadzirisira. Chikamu ichi chinotarisa:

• Kugadzirwa kweiyo data yekumisikidza yeDDR controller uye SERDESIF yekumisikidza marejista
• Kugadzirwa kweiyo FPGA logic inodiwa kuendesa iyo data yekumisikidza kune akasiyana ASIC marejista ekugadzirisa.

Pakupedzisira tinotsanangura zvakagadzirwa filezvinoenderana ne:

• Iko kusikwa kweiyo firmware 'initialization' mhinduro.
• Iyo simulation yedhizaini yeDDR 'initialization' mhinduro.

Kuti uwane ruzivo nezve DDR controller uye SERDESIF yekumisikidza marejista, tarisa kune Microsemi SmartFusion2 Yakakwira Kumhanya seri uye DDR Interfaces Mushandisi's Guide.

Dzidziso yeKushanda

Iyo Peripheral yekutanga mhinduro inoshandisa zvinotevera zvikamu zvikuru:

• Iyo CMSIS SystemInit () basa, inomhanya paCortex-M3 uye inoronga maitiro ekutanga.
• Iyo CoreConfigP yakapfava IP musimboti, iyo inotanga maperipherals ekugadzirisa marejista.
• Iyo CoreResetP yakapfava IP musimboti, iyo inokwenenzvera kutevedzana kweMSS, DDR controllers, uye SERDESIF zvidhinha.

Iyo peripheral yekutanga maitiro inoshanda seinotevera:

1. Pakugadziridzwa patsva, iyo Cortex-M3 inomhanyisa CMSIS SystemInit () basa. Iri basa rinoitwa otomatiki risati raitwa main () basa rekushandisa.
   Iyo CoreResetP inobuda chiratidzo MSS_HPMS_READY inosimbiswa pakutanga kwekutanga maitiro, zvichiratidza kuti MSS uye ese maperipherals (kunze kweMDDR) akagadzirira kutaurirana.
2. Iyo SystemInit () basa rinonyora dhizaini yedhizaini kune DDR controller uye SERDESIF marejista ekugadzirisa kuburikidza neMSS FIC_2 APB3 bhazi. Iyi interface yakabatana kune yakapfava CoreConfigP musimboti wakamisikidzwa mumucheka weFPGA.
3. Mushure mekunge marejista ese agadziriswa, iyo SystemInit () basa inonyorera kuCoreConfigP control register kuratidza kupera kwechikamu chekugadzirisa rejista; iyo CoreConfigP inobuda masiginecha CONFIG1_DONE uye CONIG2_DONE anobva asimbiswa.
   Pane zvikamu zviviri zvekugadzirisa kunyoresa (CONFIG1 uye CONFIG2) zvichienderana nemaperipherals anoshandiswa mukugadzira.
4. Kana imwe kana ese maviri eMDDR/FDDR akashandiswa, uye hapana yeSERDESIF mabhuroko anoshandiswa mukugadzira, pane chikamu chimwe chete chekugadzirisa rejista. Ose ari maviri CoreConfigP anobuda masaini CONFIG1_DONE uye CONIG2_DONE anosimbiswa mumwe mushure memumwe pasina kumirira/kunonoka.
   Kana imwe kana yakawanda SERDESIF ichivharira mune isiri-PCIe modhi inoshandiswa mukugadzira, pane chikamu chimwe chete chekugadzirisa kunyoresa. CONFIG1_DONE uye CONIG2_DONE zvinotemerwa imwe mushure meimwe pasina kumirira/kunonoka.
   Kana imwe kana anopfuura SERDESIF inovharira muPCIe modhi yakashandiswa mukugadzira, kune zvikamu zviviri zvekugadziriswa kwerejista. CONFIG1_DONE inosimbiswa mushure mekunge chikamu chekutanga chekugadzirisa kunyoresa chapera. SERDESIF system uye marejista enzira akagadziridzwa muchikamu ichi. Kana SERDESIF ikagadziridzwa mune isiri-PCIE modhi, CONFIG2_DONE siginecha inosimbiswawo nekukasika.
5. Chikamu chechipiri chekugadzirisa kunyoresa chinozotevera (kana SERDESIF yakagadziridzwa muPCIE mode). Izvi zvinotevera zviitiko zvakasiyana zvinoitika muchikamu chechipiri:
   -CoreResetP de-asserts PHY_RESET_N uye CORE_RESET_N masiginecha anoenderana neimwe yeSERDESIF blocks anoshandiswa. Inotiwo chiratidzo chinobuda SDIF_RELEASED mushure mekunge mabhuroko ese eSERDESIF abviswa patsva. Iyi SDIF_RELEASED siginecha inoshandiswa kuratidza kuCoreConfigP kuti iyo SERDESIF musimboti yabuda patsva uye yakagadzirira chikamu chechipiri chekugadzirisa kunyoresa.
   - Kana iyo SDIF_RELEASED chiratidzo ichinge yasimbiswa, iyo SystemInit () basa rinotanga kuvhota kuti isimbiswe ye PMA_READY panzira yakakodzera yeSERDESIF. Kana iyo PMA_READY ichinge yasimbiswa, iyo yechipiri seti yeSERDESIF marejista (PCIE rejista) inogadziriswa/inonyorwa neSystemInit() basa.
6. Mushure mekunge marejista ese ePCIE agadziriswa, SystemInit () basa rinonyora kuCoreConfigP control register kuratidza kupera kwechikamu chechipiri chekugadzirisa kunyoresa; iyo CoreConfigP inobuda chiratidzo CONIG2_DONE inobva yasimbiswa.
7. Kunze kwezviratidziro zviri pamusoro apa/de-assertions, CoreResetP inobatawo kutanga kwemabhuroko akasiyana nekuita zvinotevera mabasa:
   -De-kusimbisa iyo FDDR musimboti reset
   -Kubvisa-kusimbisa iyo SERDESIF inovhara PHY uye CORE kuseta zvakare
   -Kuongorora kweiyo FDDR PLL (FPLL) yekukiya chiratidzo. Iyo FPLL inofanirwa kunge yakakiyiwa kuti ive nechokwadi chekuti FDDR AXI/AHBLite data interface uye jira reFPGA rinogona kutaurirana nemazvo.
   -Kutarisisa kweSERDESIF block PLL (SPLL) masiginecha ekukiya. Iyo SPLL inofanirwa kunge yakakiyiwa kuvimbisa kuti iyo SERDESIF inovhara AXI/AHBLite interface (PCIe modhi) kana XAUI interface inogona kutaurirana nemazvo nejira reFPGA.
   -Kumirira iyo yekunze DDR ndangariro kuti dzigadzikane uye gadzirira kuwanikwa nevanodzora DDR.
8. Kana ese maperipheral apedza kutanga, CoreResetP inosimbisa INIT_DONE chiratidzo; iyo CoreConfigP yemukati regisheni INIT_DONE inobva yasimbiswa.
   Kana imwe kana ese maviri eMDDR/FDDR akashandiswa, uye nguva yekutanga yeDDR yasvika, CoreResetP inobuda chiratidzo DDR_READY inosimbiswa. Kutaura kwechiratidzo ichi DDR_READY kunogona kutariswa sechiratidzo chekuti DDR (MDDR/FDDR) yakagadzirira kutaurirana.
   Kana imwe kana akawanda eSERDESIF mabhuraki akashandiswa, uye chikamu chechipiri chekugadzirisa rejista chikapedzwa zvinobudirira, CoreResetP inobuda chiratidzo SDIF_READY inosimbiswa. Kusimbisa kwechiratidzo ichi SDIF_READY kunogona kutariswa sechiratidzo chekuti ese ma SERDESIF mabhuroko akagadzirira kutaurirana.
9. Iyo SystemInit () basa, yanga yakamirira kuti INIT_DONE isimbiswe, ipedze, uye basa rekushandisa guru () rinoitwa. Panguva iyoyo, ese anoshandiswa DDR controllers uye SERDESIF zvidhinha zvakatangwa, uye iyo firmware application uye iyo FPGA machira logic inogona kutaurirana navo zvakavimbika.

Iyo nzira inotsanangurwa mugwaro iri inotsamira pane iyo Cortex-M3 ichiita yekutanga maitiro sechikamu cheiyo system yekutanga kodhi yakaitwa pamberi pechikumbiro chikuru()basa.
Ona Flow Charts muFigure 1-1, Figure 1-2 uye Figure 1-3 yeInitialization nhanho dzeFDDR/MDDR, SEREDES(non-PCIe mode) uye SERDES (PCIe mode).
Mufananidzo 1-4 inoratidza Peripheral Initialization yenguva dhiyagiramu.

Mufananidzo 1-3 • SEDESIF (PCIe) Kutanga Kuyerera Kwematanho
Maitiro ekutanga anotsanangurwa mugwaro rino anoda kuti iwe umhanye Cortex-M3 panguva yekutanga maitiro, kunyangwe usiri kuronga kumhanyisa chero kodhi paCortex-M3. Iwe unofanirwa kugadzira yekutanga firmware application isingaite chinhu (yakareruka loop, yeexample) uye kurodha izvo zvinogoneka muyakamisikidzwa Non Volatile Memory (eNVM) kuitira kuti maDDR controllers uye SERDESIF zvidhinha zvinotangwa kana Cortex-M3 bhutsu.

Kushandisa System Builder Kugadzira Dhizaini Uchishandisa DDR neSERDESIF Zvivharo

Iyo SmartFusion2 System Builder chishandiso chine simba chekugadzira chinokubatsira kutora yako system-level zvinodiwa uye inogadzira dhizaini inoita izvo zvinodiwa. Basa rakakosha kwazvo reSystem Builder ndiko kugadzira otomatiki kwePeripheral Initialization sub-system. "Kushandisa SmartDesign Kugadzira Dhizaini Uchishandisa DDR neSERDESIF Zvivharo" papeji 17 inotsanangura zvakadzama magadzirirwo ekugadzirisa akadaro pasina System Builder.
Kana iwe uri kushandisa System Builder, iwe unofanirwa kuita anotevera mabasa kugadzira dhizaini inotanga yako DDR controller uye SERDESIF inovharira pakusimba kumusoro:

1. Muchikamu cheDevice Features peji (Mufananidzo 2-1), tsanangura kuti ndeapi maDDR controllers anoshandiswa uye mabhuroko mangani eSERDESIF anoshandiswa mukugadzira kwako.
2. MuMemory peji, tsanangura rudzi rweDDR (DDR2/DDR3/LPDDR) uye data yekumisikidza yendangariro dzako dzekunze dzeDDR. Ona chikamu cheMemory Page kuti uwane ruzivo.
3. Mune Peripherals peji, wedzera machira masters akagadziridzwa seAHBLite/AXI kuFabric DDR Subsystem uye/kana MSS DDR FIC Subsystem (inosarudza).
4. Mupeji yeClock Settings, tsanangura mafambisirwo ewachi eDDR sub-systems.
5. Pedzisa dhizaini yako uye tinya Finish. Izvi zvinogadzira iyo System Builder yakagadzirwa dhizaini, kusanganisira iyo logic inodiwa kune 'kutanga' mhinduro.
6. Kana uri kushandisa mabhuroko eSERDESIF, unofanira kumisa zvibhuroko zveSERDESIF mudhizaini yako uye wobatanidza zviteshi zvekutanga kune izvo zveSystem Builder yakagadzirwa musimboti.

System Builder Device Features Peji
Muchikamu cheDevice Features peji, tsanangura kuti ndeapi maDDR controller (MDDR uye/kana FDDR) anoshandiswa uye mabhuroko mangani eSERDESIF anoshandiswa pakugadzira kwako (Mufananidzo 2-1).

Mufananidzo 2-1 • System Builder Device Features Peji

System Builder Memory Peji
Kuti ushandise MSS DDR (MDDR) kana Fabric DDR (FDDR), sarudza Rudzi rweMemory kubva pakudonhedza pasi (Mufananidzo 2-2).

Mufananidzo 2-2 • MSS External Memory

Unofanira:

1. Sarudza rudzi rweDDR (DDR2, DDR3 kana LPDDR).
2. Tsanangura iyo DDR memory kugadzirisa nguva. Bvunza yako yekunze DDR Memory Specification kuti uise iyo chaiyo yekumisikidza ndangariro nguva. Iyo DDR ndangariro inogona kutadza kutanga nemazvo kana nguva yekumisikidza ndangariro isina kunyatsoiswa.
3. Pamwe pinza iyo DDR rejista yekumisikidza data kana kuseta yako DDR Memory Parameter. Kuti uwane ruzivo, tarisa kune Microsemi SmartFusion2 Yakakwira Kumhanya seri uye DDR Interfaces Mushandisi's Guide.

Iyi data inoshandiswa kugadzira iyo DDR rejista BFM uye firmware kumisikidza files sekutsanangurwa kwazvinoitwa mu "Kugadzira uye Kugadzira iyo Firmware Chikumbiro" papeji 26 uye "BFM Files Inoshandiswa Kutevedzera Dhizaini” papeji 27. Kuti uwane rumwe ruzivo nezveDDR controller configuration register, tarisa Microsemi SmartFusion2 Yakakwira Kumhanya seri uye DDR Interfaces Mushandisi's Guide.
Anove example ye configuration file Syntax inoratidzwa mumufananidzo 2-3. Mazita erejista anoshandiswa mune izvi file zvakafanana nezvinotsanangurwa mu Microsemi SmartFusion2 Yakakwira Kumhanya seri uye DDR Interfaces Mushandisi's Guide

Mufananidzo 2-3 • Kugadzirisa File Syntax Example
System Builder Peripherals Peji
MuPeripherals peji, kune yega yega DDR controller imwe yakaparadzana subsystem inogadzirwa (Fabric DDR Subsystem yeFDDR uye MSS DDR FIC Subsystem yeMDDR). Iwe unogona kuwedzera Fabric AMBA Master (yakagadzirirwa seAXI / AHBLite) musimboti kune imwe neimwe yeaya masisitimu kuitira kuti machira akwanise kuwana kune maDDR controllers. Pamusoro pechizvarwa, System Builder inomisikidza otomatiki ma cores (zvichienderana nerudzi rweAMBA Master yakawedzerwa) uye inofumura tenzi BIF yepakati yebhazi newachi uye nekugadzirisa mapini eiyo inoenderana subsystems (FDDR/MDDR) pasi pemapoka epini akakodzera, kune pamusoro. Zvese iwe zvunofanirwa kuita kubatanidza maBIF kune akakodzera Fabric Master cores aungasimbisa mukugadzira. Panyaya yeMDDR, isarudzo yekuwedzera Fabric AMBA Master core kune MSS DDR FIC Subsystem; Cortex-M3 ishe yakasarudzika pane iyi subsystem. Mufananidzo 2-4 inoratidza System Builder Peripherals Peji.

Mufananidzo 2-4 • System Builder Peripherals Peji

System Builder Clock Settings Peji
Mupeji yeClock Settings, kune yega yega DDR controller, iwe unofanirwa kutsanangura mafambisirwo ewachi ane chekuita neDDR (MDDR uye/kana FDDR) sub-system.
Kune MDDR, unofanira kutsanangura:

• MDDR_CLK - Iyi wachi inosarudza mafambisirwo ekushanda kweDDR Controller uye inofanirwa kuenderana newachi frequency yaunoshuvira yako yekunze DDR memory kuti imhanye pairi. Iyi wachi inotsanangurwa seyakawanda yeM3_CLK (Cortex-M3 uye MSS Main Clock, Mufananidzo 2-5). Iyo MDDR_CLK inofanira kunge iri pasi pe333 MHz.
• DDR_FIC_CLK - Kana ukasarudza kuwanawo MDDR kubva kuFPGA jira, unofanira kutsanangura DDR_FIC_CLK. Iyi wachi frequency inotsanangurwa sereshiyo yeMDDR_CLK uye inofanirwa kuenzanisa frequency iyo iyo FPGA jira sub-system inowana iyo MDDR iri kushanda.

Mufananidzo 2-5 • Cortex-M3 uye MSS Main Clock; MDDR Wachi

Kune FDDR, unofanira kutsanangura:

• FDDR_CLK - Inogadza mafambisirwo ekushanda kweDDR Controller uye inofanirwa kuenderana newachi frequency kwaunoshuvira yako yekunze DDR memory kuti imhanye. Ziva kuti wachi iyi inotsanangurwa seyakawanda yeM3_CLK (MSS uye Cortex-M3 wachi, Mufananidzo 2-5). Iyo FDDR_CLK inofanirwa kunge iri mukati me20 MHz uye 333 MHz.
• FDDR_SUBSYSTEM_CLK - Iyi nguva yewachi inotsanangurwa seyero yeFDDR_CLK uye inofanirwa kuenzanisa frequency iyo iyo FPGA jira sub-system inowana iyo FDDR iri kushanda.

Mufananidzo 2-6 • Mucheka DDR Wachi
SEDESIF Configuration
Iyo SERDESIF mabhuroki haana kuisirwa muSystem Builder yakagadzirwa dhizaini. Nekudaro, kune ese mavharoti eSERDESIF, masaini ekutanga anowanikwa pane iyo interface yeSystem Builder core uye inogona kubatanidzwa neSERDESIF cores pane inotevera nhanho yehutungamiriri, sezvakaratidzwa muFigure 2-7.Mufananidzo 2-7 • SEDESIF Peripheral Initialization Connectivity
Zvakafanana neDDR kumisikidzwa marejista, yega yega SERDES block inewo marejista ekugadzirisa anofanirwa kutakurwa panguva yekumhanya. Unogona kuendesa kunze aya marejista emhando kana kushandisa iyo Yepamusoro Speed ​​Serial Interface Configurator (Mufananidzo 2-8) kuisa PCIe yako kana EPCS maparamita uye hunhu hwerejista hunoverengerwa iwe pachako. Kuti uwane ruzivo, tarisa kune SERDES Configurator User's Guide.Mufananidzo 2-8 • High Speed ​​Serial Interface Configurator
Kana uchinge wabatanidza yako mushandisi logic neSystem Builder block uye SEDES block, unogona kugadzira yako yepamusoro nhanho SmartDesign. Izvi zvinogadzira zvese HDL uye BFM files izvo zvinodikanwa kuita uye kutevedzera dhizaini yako. Iwe unogona ipapo kuenderera nekumwe Kuyerera Kwekugadzira.

Kushandisa SmartDesign Kugadzira Dhizaini Uchishandisa DDR uye SEDESIF Zvivharo

Ichi chikamu chinotsanangura nzira yekuisa yakakwana 'initialization' mhinduro pamwechete pasina kushandisa iyo SmartFusion2 System Builder. Chinangwa ndechekukubatsira kuti unzwisise zvaunofanira kuita kana usingade kushandisa iyo System Builder. Ichi chikamu chinotsanangurawo izvo zvinogadzirwa neSystem Builder kwauri. Ichi chikamu chinotsanangura nzira yeku:

• Isa iyo data yekumisikidza yeDDR controller uye SERDESIF yekumisikidza marejista.
• Simbisa uye ubatanidze iyo Fabric Cores inodiwa kuendesa iyo data yekumisikidza kune DDR controllers uye SERDESIF marejista ekugadzirisa.

DDR Controller Configuration
Iyo MSS DDR (MDDR) uye Fabric DDR (FDDR) ma controller anofanirwa kugadzirwa zvine simba (panguva yekumhanya) kuti aenderane nekunze DDR memory configuration zvinodiwa (DDR modhi, PHY upamhi, burst mode, ECC, nezvimwewo). Dhata yakapinda muMDDR/FDDR configurator inonyorerwa kuDDR controller kumisikidza marejista neCMSIS SystemInit() basa. Iyo Configurator ine matatu akasiyana ma tabo ekupinda akasiyana marudzi e data yekumisikidza:

• Yese data (DDR modhi, Hupamhi hwedhata, Clock Frequency, ECC, Fabric Interface, Dhivha Simba)
• Memory Initialization data (Burst Length, Burst Order, Timing Mode, Latency, nezvimwewo)
• Memory Nguva yedata

Tarisa kune zvakatemwa zvekunze DDR ndangariro uye gadzirisa iyo DDR Controller kuti ienderane nezvinodiwa zvekunze DDR memory.
Kuti uwane ruzivo nezveDDR kumisikidzwa, tarisa kune SmartFusion2 MSS DDR Configuration User Guide.
SEDESIF Configuration
Dzvanya kaviri chivharo cheSERDES muSmartDesign canvas kuti uvhure Configurator kugadzirisa SEDES (Mufananidzo 3-1). Unogona kuendesa kunze aya marejitari maitiro kana kushandisa iyo SEDES configurator kuisa PCIe yako kana EPCS paramita uye marejista emhando anoverengerwa iwe pachako. Kuti uwane ruzivo, tarisa kune SERDES Configurator User's Guide.Mufananidzo 3-1 • High Speed ​​Serial Interface Configurator
Kugadzira iyo FPGA Dhizaini Initialization Sub-System
Kuti utange DDR neSERDESIF zvidhinha, unofanirwa kugadzira iyo yekutanga subsystem mumucheka weFPGA. Iyo FPGA jira rekutanga subsystem inofambisa data kubva kuCortex-M3 kuenda kuDDR uye SERDESIF yekumisikidza marejista, inokwenenzvera kutevedzana kunodiwa kuti aya mabhuraki ashande uye masaini kana aya mabhuraki agadzirira kutaurirana neasara dhizaini yako. Kuti ugadzire iyo yekutanga subsystem, unofanirwa:

• Gadzirisa FIC_2 mukati meMSS
• Isa uye gadzirisa CoreConfigP uye CoreResetP cores
• Isa iyo pa-chip 25/50MHz RC oscillator
• Isa iyo System Reset (SYSRESET) macro
• Batanidza izvi zvikamu kune yega yega yekumisikidzwa yekumisikidzwa, wachi, reset uye PLL kukiya ports.

MSS FIC_2 APB Configuration
Kugadzirisa iyo MSS FIC_2:

1. Vhura iyo FIC_2 configurator dialog box kubva kuMSS configurator (Mufananidzo 3-2).
2. Sarudza Tanga peripherals uchishandisa Cortex-M3.
3. Zvichienderana nehurongwa hwako, tarisa imwe kana ese ari maviri einotevera mabhokisi ekutarisa:
   - MSS DDR
   -Mucheka DDR uye/kana SEDES Zvivharo
4. Dzvanya OK uye enderera mberi kugadzira iyo MSS (unogona kuverengera chiitiko ichi kusvika wanyatso gadzirisa iyo MSS kune yako dhizaini zvaunoda). FIC_2 ports (FIC_2_APB_MASTER, FIC_2_APB_M_PCLK neFIC_2_APB_M_RESET_N) dzava pachena paMSS interface uye dzinogona kubatana neCoreConfigP neCoreResetP cores.

Mufananidzo 3-2 • MSS FIC_2 Configurator

CoreConfigP
Kugadzirisa CoreConfigP:

1. Isa CoreConfigP mune yako SmartDesign (kazhinji iyo iyo MSS inomisikidzwa).
   Iyi musimboti inogona kuwanikwa muLibero Catalog (pasi Peripherals).
2. Dzvanya kaviri pakati kuti uvhure configurator.
3. Rongedza musimboti kuti utsanangure kuti ndeapi maperipheral anoda kutanga (Mufananidzo 3-3)

Mufananidzo 3-3 • CoreConfigP Dialog Bhokisi

CoreResetP
Kugadzirisa CoreResetP:

1. Isa CoreResetP mune yako SmartDesign (kazhinji iyo iyo MSS inosimbiswa).
   Iyi musimboti inogona kuwanikwa muLibero Catalog, pasi pePeripherals.
2. Dzvanya kaviri musimboti mukati meSmartDesign Canvas kuti uvhure Configurator (Mufananidzo 3-4).
3. Gadzirisa iyo core ku:
   - Rondedzera maitiro ekunze ekugadzirisa zvakare (EXT_RESET_OUT yakasimbiswa). Sarudza chimwe chezvasarudzo zvina:
   o EXT_RESET_OUT haina kumbotaurwa
   o EXT_RESET_OUT inotemerwa kana simba rekudzimisa patsva (POWER_ON_RESET_N) richinzi
   o EXT_RESET_OUT inotemerwa kana FAB_RESET_N ichinzi
   o EXT_RESET_OUT inosimbiswa kana simba rekudzimisa patsva (POWER_ON_RESET_N) kana FAB_RESET_N richinzi
   – Taura mudziyo Voltage. Iko kukosha kwakasarudzwa kunofanirwa kuenderana nevoltage iwe wakasarudza muLibero Project Settings dialog box.
   - Tarisa mabhokisi ekutarisa akakodzera kuratidza kuti ndeapi maperipheral auri kushandisa mukugadzira kwako.
   - Rondedzera yekunze DDR memory yekumisikidza nguva. Uku ndiko kukosha kwakanyanya kune ese maDDR ndangariro anoshandiswa mukushandisa kwako (MDDR neFDDR). Tarisa kune yekunze DDR memory mutengesi dheteti kuti ugadzirise iyi parameter. 200us yakanaka default kukosha kweDDR2 uye DDR3 ndangariro dzinomhanya pa200MHz. Iyi ndiyo parameter yakakosha yekuvimbisa kushanda kufananidzira uye hurongwa hwekushanda pasilicon. Kukosha kusina kururama kwenguva yekugadzirisa kunogona kukonzera kukanganisa kwekufananidza. Tarisa kune DDR memory mutengesi dhata kuti ugadzirise iyi parameter.
   -Kune yega yega SEDES block mudhizaini yako, tarisa mabhokisi akakodzera kuratidza kana:
   o PCIe inoshandiswa
   o Tsigiro yePCIe Hot Reset inodiwa
   o Tsigiro yePCIe L2/P2 inodiwa

Cherechedza: Kana iwe uri kushandisa iyo 090 die(M2S090) uye dhizaini yako inoshandisa SEDESIF, haufanirwe kutarisa chero anotevera mabhokisi ekutarisa: 'Inoshandiswa kuPCIe', 'Batanidza PCIe HotReset rutsigiro' uye 'Batanidza PCIe L2/P2 rutsigiro'. Kana uri kushandisa chero mudziyo usiri we090 uye uchishandisa chimwe kana anopfuura mabhuroko eSERDESIF, unofanira kutarisa mabhokisi mana echeki pasi pechikamu chakakodzera cheSERDESIF.
Cherechedza: Kuti uwane rumwe ruzivo nezve sarudzo dziripo kwauri mune ino configurator, tarisa CoreResetP Handbook.

Mufananidzo 3-4 • CoreResetPCConfigurator

25/50MHz Oscillator Instantiation
CoreConfigP uye CoreResetP inovharwa neiyo on-chip 25/50MHz RC oscillator. Iwe unofanirwa kusimbisa 25/50MHz Oscillator uye kuibatanidza kune aya macores.

1. Isa iyo Chip Oscillators musimboti mune yako SmartDesign (kazhinji iyo iyo MSS inosimbiswa). Iyi musimboti inogona kuwanikwa muLibero Catalog pasi peClock & Management.
2. Rongedza musimboti uyu zvekuti RC oscillator inotyaira jira reFPGA, sezvakaratidzwa mumufananidzo 3-5.

Mufananidzo 3-5 • Chip Oscillators Configurator

Sisitimu Reset (SYSRESET) Instantiation
Iyo SYSRESET macro inopa dhizaini reset mashandiro kune dhizaini yako. Iyo POWER_ON_RESET_N inobuda siginecha inotemerwa/de-kusimbirwa pese panobatidzwa chip kana pini yekunze DEVRST_N ichinzi/de-asserted (Mufananidzo 3-6).
Isa iyo SYSRESET macro mune yako SmartDesign (kazhinji iyo iyo MSS inosimbiswa). Iyi macro inogona kuwanikwa muLibero Catalog pasi peMacro Library.Hapana kurongeka kweiyi macro kunodiwa.

Mufananidzo 3-6 • SYSRESET Macro

Kwose Kubatana
Mushure mekunge wasimbisa nekugadzirisa iyo MSS, FDDR, SERDESIF, OSC, SYSRESET, CoreConfigP uye CoreResetP cores mudhizaini yako, unofanirwa kuzvibatanidza kuti dzigadzire iyo Peripheral Initialization subsystem. Kurerutsa tsananguro yekubatanidza mugwaro iri, rakatyorwa mu APB3 inoenderana negadziriro yedata nzira yekubatanidza ine chekuita neCoreConfigP uye CoreResetP ine hukama.
Configuration Data Path Kubatana
Mufananidzo 3-7 unoratidza nzira yekubatanidza CoreConfigP kune MSS FIC_2 masiginecha uye maperipherals' APB3 anowirirana nemagadzirirwo enzvimbo.
Tafura 3-1 • Kugadzirisa Dhata Nzira Port/BIF Mabatanidza

KUBVA Port/Bus Interface (BIF)/ Chikamu	TO Port/Bus Interface (BIF)/Component
APB S PRESET N/ CoreConfigP	APB S PRESET N/ SDIF <0/1/2/3>	APB S PRESET N/ FDDR	MDDR APB S PRESE TN/MSS
APB S PCLK/ CoreConfigP	APB S PCLK/SDIF	APB S PCLK/FDDR	MDDR APB S POLK/ MSS
MDDR APBmslave/ CoreConfig			MDDR APB SLAVE (BIF)/MSS
SDIF<0/1/2/ 3> APBmslave/Config	APB SLAVE (BIF)/ SDIF <0/1/2/3>
FDDR APB muranda		APB SLAVE (BIF)/ FDDR
FIC 2 APBmmaster/ CoreConfigP			FIC 2 APB MASTER/ MSS

Mufananidzo 3-7 • FIC_2 APB3 Sub-System Connectivity

Mawachi uye Reset Kubatana
Mufananidzo 3-8 inoratidza nzira yekubatanidza iyo CoreResetP kune ekunze reset masosi uye maperipherals epakati reset masaini. Iyo inoratidzawo nzira yekubatanidza iyo CoreResetP kune peripherals 'wachi synchronization mamiriro masiginecha (PLL kukiya masaini). Pamusoro pezvo, inoratidza kuti CoreConfigP uye CoreResetP zvakabatana sei.

Mufananidzo 3-8 • Core SF2Reset Sub-System Connectivity

Kugadzira uye Kugadzira iyo Firmware application

Paunotumira kunze iyo firmware kubva kuLiberoSoC (Design Flow Window> Export Firmware> Export Firmware), Libero inogadzira zvinotevera. files muri /firmware/drivers_config/ sys_config folda:

• sys_config.c -Ine zvimiro zvedata zvinobata kukosha kweiyo peripheral register.
• sys_config.h -Ine #define zvirevo zvinotsanangura kuti ndeapi maperipheral anoshandiswa mukugadzira uye anoda kutanga.
• sys_config_mddr_define.h -Ine iyo MDDR dhizaini yekumisikidza data yakaiswa muRejista Configuration dialog box.
• sys_config_fddr_define.h -Ine iyo FDDR controller yekumisikidza data yakapinda muRejista Configuration dialog box.
• sys_config_mss_clocks.h – Izvi file ine MSS wachi frequency sekutsanangurwa kwazvinoitwa muMSS CCC configurator. Aya mafambiro anoshandiswa neiyo CMSIS kodhi yekupa ruzivo rwewachi kune vakawanda veMSS vatyairi vanofanirwa kuwana yavo Peripheral Clock (PCLK) frequency (semuenzaniso, MSS UART baud rate divisor ibasa reiyo baud rate uye PCLK frequency. )
• sys_config_SERDESIF_ .c – Ine SEARDESIF_ regisa data yekumisikidza yakapihwa panguva yeSERDESIF_ block configuration mukugadzira dhizaini.
• sys_config_SERDESIF_ .h -Ine iyo #define zvirevo zvinotsanangura huwandu hwerejista yekumisikidza pairi uye nhamba yenzira inoda kuvhoterwa yePMA_READY (chete muPCIe modhi).

Izvi files inodiwa kuti CMSIS kodhi iunganidzwe zvakanaka uye iine ruzivo maererano nedhizaini yako yazvino, kusanganisira peripheral configuration data uye wachi yekumisikidza ruzivo rweMSS.
Usagadzirise izvi files manually; iwo anogadzirwa kune inoenderana chikamu / peripheral madhairekitori pese pese iyo SmartDesign zvikamu zvine iwo anoenderana peripherals anogadzirwa. Kana chero shanduko ikaitwa kune yekumisikidza dhata yechero peripherals, iwe unofanirwa kuendesa kunze kunze kweiyo firmware mapurojekiti kuitira kuti yakagadziridzwa firmware. files (ona rondedzero iri pamusoro) inotumirwa kune iyo / firmware/drivers_config/sys_config folda.
Paunotumira kunze iyo firmware, Libero SoC inogadzira iyo firmware mapurojekiti: raibhurari uko yako dhizaini dhizaini files uye vatyairi vanounganidzwa.
Kana iwe ukatarisa Gadzira purojekiti bhokisi rekutarisa paunotumira kunze firmware, software yeSoftConsole/IAR/Keil inogadzirwa kuti ibate chirongwa chekunyorera kwaunogona kugadzirisa main.c uye mushandisi C/H. files. Vhura iyo SoftConSole/IAR/Keil purojekiti kuunganidza iyo CMSIS kodhi nenzira kwayo uye ita kuti firmware application yako igadziriswe zvakanaka kuti ienderane nedhizaini yako yehardware.

BFM Files Inoshandiswa Kutevedzera Dhizaini

Paunogadzira zvinhu zveSmartDesign zvine maperipheral ane hukama nedhizaini yako, simulation files inoenderana neyakasiyana peripherals inogadzirwa mu / simulation directory:

• test.bfm – Yepamusoro-nhanho BFM file iyo inotanga kuurayiwa panguva chero yekufungidzira inoshandisa SmartFusion2 MSS Cortex-M3 processor. Inoita peripheral_init.bfm uye user.bfm, nenzira iyoyo.
• MDDR_init.bfm - Kana dhizaini yako ichishandisa iyo MDDR, Libero inogadzira izvi file; ine BFM yekunyora mirairo inoteedzera zvinyorwa zveMSS DDR yekumisikidza rejista data yawakaisa (uchishandisa Rongedza Rejista dialogbox kana muMSS_MDDR GUI) muMSS DDR Controller marejista.
• FDDR_init.bfm - Kana dhizaini yako ichishandisa iyo FDDR, Libero inogadzira izvi file; iyo ine BFM yekunyora mirairo inoteedzera inonyora yeFabric DDR kumisikidza rejista data yawakaisa (uchishandisa Rongedza Rejista dialogbox kana muFDDR GUI) muFabric DDR Controller marejista.
• SEDESIF_ _init.bfm - Kana dhizaini yako ichishandisa imwe kana anopfuura mabhuroka eSERDESIF, Libero inogadzira izvi file kune yega yega yeSERDESIF_ zvidhinha zvakashandiswa; ine BFM yekunyora mirairo inoteedzera zvinyorwa zveSERDESIF yekumisikidza rejista data yawakaisa (uchishandisa Bhokisi reRejista rebhokisi rebhokisi kana muSERDESIF_ GUI) muSERDESIF_ mabhuku. Kana iyo SERDESIF block yakagadziriswa sePCIe, izvi file zvakare ine zvimwe #define zvirevo zvinodzora kuitiswa kweiyo 2 rejista yekumisikidza zvikamu muhurongwa hwakakwana.
• user.bfm -Ine mirairo yemushandisi. Mirairo iyi inozoitwa mushure mekunge peripheral_init.bfm yapera. Edit izvi file kuisa yako BFM mirairo.
• SEDESIF_ _mushandisi.bfm -Ine mushandisi mirairo. Edit izvi file kuisa yako BFM mirairo. Shandisa izvi kana wakagadzira SEDDESIF_ vhara muBFM PCIe simulation modhi uye seAXI/AHBLite tenzi. Kana wakagadzirisa SEDDESIF_ vhara muRTL simulation mode, hauzodi izvi file.

Paunodaidza simulation nguva dzese, maviri anotevera simulation files dzakasikwa patsva kune / simulation dhairekitori ine zvakagadziridzwa zvirimo:

• subsystem.bfm -Ine #define zvirevo zvechero peripheral inoshandiswa mukugadzira kwako, iyo inotsanangura icho chikamu cheperipheral_init.bfm ichaitwa inoenderana nechero peripheral.
• operipheral_init.bfm -Ine maitiro eBFM anotevedzera CMSIS :: SystemInit () basa rinomhanya paCortex-M3 usati wapinda main() maitiro. Inokopa iyo data yekumisikidza yechero peripheral inoshandiswa mudhizaini kune iyo chaiyo peripheral configuration register uye yobva yamirira kuti maperipherals ese agadzirire asati ataura kuti unogona kushandisa aya maperipheral. Inoita MDDR_init.bfm uye FDDR_init.bfm.

Kushandisa izvi zvakagadzirwa files, maDDR anodzora mudhizaini yako anogadziriswa otomatiki, achitevedzera zvaizoitika pane SmartFusion2 mudziyo. Unogona kugadzirisa mushandisi.bfm file kuwedzera chero mirairo inodiwa kutevedzera dhizaini yako (Cortex-M3 ndiye tenzi). Iyi mirairo inoitwa mushure mekunge ma peripherals atanga. Usagadzirise test.bfm, subsystem.bfm, peripheral_init.bfm, MDDR_init.bfm, FDDR_init.bfm files uye SEDESIF_ _init.bfm files.

Product Support

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Zvinyorwa / Zvishandiso

Microsemi SmartFusion2 DDR Controller uye Serial High Speed ​​​​Control [pdf] Bhuku reMushandisi SmartFusion2 DDR Controller uye Serial High Speed ​​​​Controller, SmartFusion2 DDR, Controller uye Serial High Speed ​​​​Controller, High Speed ​​​​Controller.

References

• User Manual