SmartFusion 2
DDR Controller thiab Serial High Speed ​​Controller
Initialization Methodology
Cov neeg siv phau ntawv qhia

Taw qhia

Thaum tsim ib qho kev tsim siv SmartFusion2 ntaus ntawv, yog tias koj siv ib qho ntawm ob lub DDR controllers (FDDR lossis MDDR) lossis ib qho ntawm Serial High Speed ​​Controller (SERDESIF) blocks, koj yuav tsum pib tsim cov ntawv teev npe ntawm cov blocks ntawm lub sijhawm ua ntej. lawv tuaj yeem siv tau. Rau example, rau DDR maub los, koj yuav tsum teeb tsa hom DDR (DDR3 / DDR2 / LPDDR), PHY dav, tawg hom thiab ECC.
Ib yam li ntawd, rau SERDESIF thaiv siv los ua PCIe kawg, koj yuav tsum teeb lub PCIE BAR rau AXI (lossis AHB) qhov rais.
Cov ntaub ntawv no piav qhia txog cov kauj ruam tsim nyog los tsim Libero tsim uas tau pib pib lub DDR maub los thiab SERDESIF blocks ntawm lub zog. Nws kuj piav qhia yuav ua li cas los tsim cov firmware code los ntawm Libero SOC uas yog siv nyob rau hauv lub embedded tsim txaus.
Cov lus piav qhia ntxaws txog qhov kev xav ntawm kev ua haujlwm yog muab ua ntej.
Ntu tom ntej no piav qhia txog yuav ua li cas tsim cov qauv tsim siv Libero SoC System Builder, lub cuab yeej tsim muaj zog uas, ntawm lwm cov nta, tsim cov 'initialization' daws rau koj yog tias koj siv DDR lossis SERDESIF blocks hauv koj tus qauv tsim.
Tshooj tom ntej piav qhia yuav ua li cas muab qhov ua tiav 'initialization' kev daws teeb meem ua ke yam tsis siv SmartFusion2 System Builder. Qhov no pab piav qhia qhov yuav tsum tau ua yog tias koj tsis xav siv System Builder, thiab tseem piav qhia txog qhov System Builder lub cuab yeej tsim rau koj. Ntu no hais txog:

• Tsim cov ntaub ntawv configuration rau DDR maub los thiab SERDESIF configuration registers
• Kev tsim ntawm FPGA logic yuav tsum tau hloov cov ntaub ntawv teeb tsa mus rau qhov sib txawv ASIC configuration registers

Thaum kawg peb piav txog cov generated files related to:

• Lub creation ntawm firmware 'initialization' daws.
• Lub simulation ntawm tus tsim rau DDR 'initialization' daws.

Yog xav paub meej txog DDR maub los thiab SERDESIF configuration registers, xa mus rau Microsemi SmartFusion2 High Speed ​​Serial thiab DDR Interfaces Tus Neeg Siv Phau Ntawv Qhia.

Txoj Kev Ua Haujlwm

Cov tshuaj Peripheral pib siv cov khoom tseem ceeb hauv qab no:

• Lub CMSIS SystemInit() muaj nuj nqi, uas khiav ntawm Cortex-M3 thiab orchestrates cov txheej txheem pib.
• CoreConfigP soft IP core, uas pib lub peripherals 'configuration registers.
• CoreResetP soft IP core, uas tswj xyuas qhov rov pib ua ntu zus ntawm MSS, DDR controllers, thiab SERDESIF blocks..

Cov txheej txheem peripheral pib ua haujlwm raws li hauv qab no:

1. Thaum rov pib dua, Cortex-M3 khiav CMSIS SystemInit() muaj nuj nqi. Qhov kev ua haujlwm no tau ua tiav ua ntej daim ntawv thov lub ntsiab () ua haujlwm raug tua.
   CoreResetP tso zis teeb liab MSS_HPMS_READY tau lees paub thaum pib ntawm cov txheej txheem pib, qhia tias MSS thiab tag nrho cov khoom siv peripherals (tshwj tsis yog MDDR) tau npaj rau kev sib txuas lus.
2. Qhov SystemInit() muaj nuj nqi sau cov ntaub ntawv teeb tsa rau DDR cov tswj hwm thiab SERDESIF teeb tsa kev sau npe ntawm MSS FIC_2 APB3 tsheb npav. Qhov kev sib txuas no txuas nrog cov tub ntxhais mos CoreConfigP instantiated hauv FPGA ntaub.
3. Tom qab tag nrho cov ntawv teev npe raug teeb tsa, SystemInit() muaj nuj nqi sau rau CoreConfigP tswj cov ntawv sau npe los qhia txog kev ua tiav ntawm theem kev sau npe; cov CoreConfigP tso tawm cov cim CONFIG1_DONE thiab CONIG2_DONE tau lees paub.
   Muaj ob theem ntawm kev sau npe configuration (CONFIG1 thiab CONFIG2) nyob ntawm seb lub peripherals siv hauv kev tsim.
4. Yog tias ib lossis ob qho ntawm MDDR / FDDR tau siv, thiab tsis muaj SERDESIF blocks siv rau hauv kev tsim, tsuas muaj ib theem kev teeb tsa. Ob qhov CoreConfigP tso tawm cov cim CONFIG1_DONE thiab CONIG2_DONE tau lees paub ib qho tom qab lwm yam yam tsis muaj kev tos / ncua.
   Yog hais tias ib los yog ntau tshaj SERDESIF blocks nyob rau hauv uas tsis yog-PCIe hom siv nyob rau hauv tus tsim, tsuas muaj ib theem ntawm kev sau npe configuration. CONFIG1_DONE thiab CONIG2_DONE tau lees paub ib qho tom qab lwm yam yam tsis muaj kev tos / ncua.
   Yog hais tias ib los yog ntau tshaj SERDESIF blocks nyob rau hauv PCIe hom siv nyob rau hauv tus tsim, muaj ob theem ntawm kev sau npe configuration. CONFIG1_DONE tau lees paub tom qab thawj theem ntawm kev sau npe teeb tsa tiav. SERDESIF system thiab txoj kab sau npe tau teeb tsa hauv theem no. Yog tias SERDESIF tau teeb tsa hauv hom tsis yog PCIE, CONFIG2_DONE teeb liab kuj tau lees paub tam sim ntawd.
5. Qhov thib ob theem ntawm kev sau npe configuration tom qab ntawd ua raws (yog tias SERDESIF tau teeb tsa hauv PCIE hom). Cov hauv qab no yog cov xwm txheej sib txawv uas tshwm sim nyob rau theem ob:
   - CoreResetP de-asserts PHY_RESET_N thiab CORE_RESET_N cov cim qhia sib raug rau txhua qhov SERDESIF blocks siv. Nws kuj tseem lees paub cov teeb liab tso zis SDIF_RELEASED tom qab tag nrho cov SERDESIF blocks tsis rov pib dua. Qhov teeb liab SDIF_RELEASED no yog siv los qhia rau CoreConfigP tias SERDESIF core yog tawm ntawm kev pib dua thiab npaj txhij rau theem thib ob ntawm kev sau npe teeb tsa.
   - Thaum SDIF_RELEASED teeb liab tau lees paub, SystemInit() muaj nuj nqi pib xaiv tsa rau qhov kev lees paub ntawm PMA_READY ntawm txoj kab SERDESIF uas tsim nyog. Thaum PMA_READY tau lees paub, qhov thib ob ntawm SERDESIF cov npe (PCIE cov npe) tau teeb tsa / sau los ntawm SystemInit() muaj nuj nqi.
6. Tom qab tag nrho cov PCIE cov ntawv teev npe raug teeb tsa, SystemInit() muaj nuj nqi sau rau CoreConfigP tswj kev sau npe los qhia txog kev ua tiav ntawm theem thib ob ntawm kev sau npe teeb tsa; CoreConfigP tso zis teeb liab CONIG2_DONE yog tom qab ntawd lees paub.
7. Sib nrug los ntawm cov teeb liab hais saum toj no / de-assertions, CoreResetP tseem tswj kev pib ntawm ntau yam blocks los ntawm kev ua cov haujlwm hauv qab no:
   - Tsis lees paub FDDR core reset
   - Tsis lees paub SERDESIF thaiv PHY thiab CORE rov pib dua
   - Kev soj ntsuam ntawm FDDR PLL (FPLL) lub teeb liab xauv. FPLL yuav tsum tau kaw kom lav tias FDDR AXI / AHBLite cov ntaub ntawv interface thiab FPGA ntaub tuaj yeem sib txuas lus kom raug.
   - Kev soj ntsuam ntawm SERDESIF thaiv PLL (SPLL) cov cim ntsuas phoo. SPLL yuav tsum tau kaw kom lav tias SERDESIF thaiv AXI / AHBLite interface (PCIe hom) lossis XAUI interface tuaj yeem sib txuas lus nrog FPGA ntaub.
   - Tos rau sab nraud DDR nco kom daws tau thiab npaj kom nkag tau los ntawm DDR cov tswj hwm.
8. Thaum txhua qhov peripherals tau ua tiav lawv qhov pib, CoreResetP lees paub INIT_DONE teeb liab; lub CoreConfigP sab hauv sau npe INIT_DONE yog tom qab ntawd lees paub.
   Yog hais tias ib los yog ob qho tib si ntawm MDDR / FDDR tau siv, thiab lub sijhawm pib DDR tau mus txog, CoreResetP tso zis teeb liab DDR_READY tau lees paub. Kev lees paub ntawm lub teeb liab DDR_READY tuaj yeem saib xyuas raws li qhov qhia tau tias DDR (MDDR / FDDR) tau npaj rau kev sib txuas lus.
   Yog tias siv ib lossis ntau qhov SERDESIF blocks, thiab theem ob ntawm kev sau npe teeb tsa tau ua tiav, CoreResetP tso zis teeb liab SDIF_READY tau lees paub. Kev lees paub ntawm lub teeb liab SDIF_READY tuaj yeem saib xyuas raws li qhov qhia tau tias txhua qhov SERDESIF blocks tau npaj rau kev sib txuas lus.
9. Lub SystemInit() muaj nuj nqi, uas tau tos rau INIT_DONE kom lees paub, ua tiav, thiab daim ntawv thov lub ntsiab () ua haujlwm raug tua. Lub sijhawm ntawd, txhua tus siv DDR tswj thiab SERDESIF blocks tau pib, thiab daim ntawv thov firmware thiab FPGA ntaub logic tuaj yeem sib txuas lus nrog lawv.

Cov txheej txheem tau piav qhia hauv daim ntawv no tso siab rau Cortex-M3 ua tiav cov txheej txheem pib ua ib feem ntawm qhov system pib code ua ntej daim ntawv thov lub ntsiab () ua haujlwm.
Saib cov Flow Charts hauv daim duab 1-1, Daim duab 1-2 thiab daim duab 1-3 rau cov kauj ruam pib ntawm FDDR/MDDR, SEREDES (tsis yog PCIe hom) thiab SERDES (PCIe hom).
Daim duab 1-4 qhia txog Peripheral Initialization timing daim duab.

Daim duab 1-3 • SERDESIF (PCIe) Initialization Flow Chart
Cov txheej txheem pib pib piav qhia hauv daim ntawv no xav kom koj khiav Cortex-M3 thaum lub sijhawm pib txheej txheem, txawm tias koj tsis npaj yuav khiav ib qho chaws ntawm Cortex-M3. Koj yuav tsum tsim ib daim ntawv thov firmware yooj yim uas tsis muaj dab tsi (lub voj voog yooj yim, piv txwv liample) thiab thauj khoom uas tuaj yeem ua tiav hauv cov cim tsis muaj qhov tsis haum xeeb (eNVM) yog li DDR cov tswj hwm thiab SERDESIF blocks tau pib thaum Cortex-M3 khau raj.

Siv System Builder los tsim kev tsim siv DDR thiab SERDESIF Blocks

SmartFusion2 System Builder yog lub cuab yeej tsim muaj zog uas pab koj ntes koj cov kev xav tau ntawm cov txheej txheem thiab tsim cov qauv tsim ua raws li cov kev xav tau. Lub luag haujlwm tseem ceeb ntawm System Builder yog qhov tsis siv neeg tsim ntawm Peripheral Initialization sub-system. "Siv SmartDesign los tsim Tsim Tsim Siv DDR thiab SERDESIF Blocks" nyob rau nplooj 17 piav qhia meej yuav ua li cas los tsim cov kev daws teeb meem no yam tsis muaj System Builder.
Yog tias koj tab tom siv System Builder, koj yuav tsum ua cov haujlwm hauv qab no los tsim cov qauv tsim uas pib koj cov DDR controllers thiab SERDESIF blocks ntawm lub zog:

1. Hauv nplooj ntawv Cov Ntaus Ntaus (Daim duab 2-1), qhia meej tias DDR cov tswj tau siv thiab pes tsawg SERDESIF blocks siv hauv koj tus qauv tsim.
2. Hauv nplooj ntawv Nco, qhia hom DDR (DDR2 / DDR3 / LPDDR) thiab cov ntaub ntawv teeb tsa rau koj qhov kev nco sab nraud DDR. Mus saib nplooj ntawv Memory kom paub meej.
3. Hauv nplooj ntawv Peripherals, ntxiv cov ntaub masters teeb tsa raws li AHBLite / AXI rau Fabric DDR Subsystem thiab / lossis MSS DDR FIC Subsystem (yeem).
4. Hauv nplooj ntawv teev moos, qhia lub moos zaus rau DDR sub-systems.
5. Ua kom tiav koj tus qauv tsim thiab nyem Finish. Qhov no ua rau System Builder tsim tsim, suav nrog cov logic tsim nyog rau 'initialization' daws.
6. Yog tias koj siv SERDESIF blocks, koj yuav tsum instantiate SERDESIF blocks hauv koj tus qauv tsim thiab txuas lawv cov chaw nres nkoj pib rau cov System Builder generated core.

Qhov System Builder Device Features Page
Hauv nplooj ntawv Ntaus Ntaus Ntaus, qhia meej uas DDR controllers (MDDR thiab/lossis FDDR) tau siv thiab siv ntau npaum li cas SERDESIF blocks hauv koj tus tsim (Daim duab 2-1).

Daim duab 2-1 • System Builder Device Features Page

Qhov System Builder Memory Page
Txhawm rau siv MSS DDR (MDDR) lossis Fabric DDR (FDDR), xaiv Hom Nco los ntawm cov npe poob (Daim duab 2-2).

Daim duab 2-2 • MSS Sab Nraud Memory

Koj yuav tsum:

1. Xaiv hom DDR (DDR2, DDR3 lossis LPDDR).
2. Txhais lub sijhawm DDR nco daws teeb meem. Nrog koj tus DDR Memory Specifications sab nraud los teeb tsa lub cim xeeb kom raug. Lub cim xeeb DDR tuaj yeem ua tsis tiav yog tias lub sijhawm teeb tsa lub cim xeeb tsis raug teeb tsa.
3. Los yog import DDR cov ntaub ntawv teev npe teeb tsa lossis teeb tsa koj qhov DDR Memory Parameters. Yog xav paub ntxiv, xa mus rau lub Microsemi SmartFusion2 High Speed ​​Serial thiab DDR Interfaces Tus Neeg Siv Phau Ntawv Qhia.

Cov ntaub ntawv no yog siv los tsim DDR sau npe BFM thiab firmware configuration files raws li tau piav nyob rau hauv "Tsim thiab Compiling lub Firmware Application" nyob rau nplooj 26 thiab "BFM Files Siv rau Simulating tus Tsim" nyob rau nplooj 27. Yog xav paub meej txog DDR maub los configuration registers, xa mus rau lub Microsemi SmartFusion2 High Speed ​​Serial thiab DDR Interfaces Tus Neeg Siv Phau Ntawv Qhia.
Ib example ntawm configuration file syntax muaj nyob rau hauv daim duab 2-3. Cov npe sau npe siv hauv qhov no file zoo ib yam li cov uas tau piav nyob rau hauv Microsemi SmartFusion2 High Speed ​​Serial thiab DDR Interfaces Tus Neeg Siv Phau Ntawv Qhia

Daim duab 2-3 • Configuration File Syntax Example
Qhov System Builder Peripherals Page
Hauv nplooj ntawv Peripherals, rau txhua tus tswj DDR ib qho kev sib cais subsystem yog tsim (Ntaub DDR Subsystem rau FDDR thiab MSS DDR FIC Subsystem rau MDDR). Koj tuaj yeem ntxiv Fabric AMBA Master (configured as AXI/AHBLite) core rau txhua qhov subsystems los pab cov ntaub ntawv nkag mus rau DDR controllers. Thaum tiam, System Builder cia li instantiates lub tsheb npav cores (nyob ntawm seb hom AMBA Master ntxiv) thiab nthuav tawm tus tswv BIF ntawm lub tsheb npav core thiab moos thiab rov pib dua pins ntawm cov sib txuas subsystems (FDDR / MDDR) nyob rau hauv cov pab pawg pin tsim nyog, mus rau saum. Txhua yam koj yuav tsum tau ua yog txuas BIFs rau qhov tsim nyog Fabric Master cores uas koj yuav instantiate hauv tus tsim. Nyob rau hauv rooj plaub ntawm MDDR, nws yog xaiv tau los ntxiv ib tug Fabric AMBA Master core rau MSS DDR FIC Subsystem; Cortex-M3 yog tus thawj coj ntawm lub subsystem no. Daim duab 2-4 qhia qhov System Builder Peripherals Page.

Daim duab 2-4 • Page Builder Peripherals

Qhov System Builder Clock Settings Page
Hauv nplooj ntawv teev moos, rau txhua tus tswj hwm DDR, koj yuav tsum qhia lub moos zaus cuam tshuam rau txhua qhov DDR (MDDR thiab / lossis FDDR) sub-system.
Rau MDDR, koj yuav tsum qhia meej:

• MDDR_CLK - Lub moos no txiav txim siab qhov ua haujlwm zaus ntawm DDR Controller thiab yuav tsum phim lub moos zaus koj xav kom koj lub cim xeeb sab nraud DDR khiav ntawm. Lub moos no txhais tau tias yog ntau yam ntawm M3_CLK (Cortex-M3 thiab MSS Main Clock, Daim duab 2-5). MDDR_CLK yuav tsum tsawg dua 333 MHz.
• DDR_FIC_CLK - Yog tias koj tau xaiv los kuj nkag mus rau MDDR los ntawm FPGA ntaub, koj yuav tsum tau qhia DDR_FIC_CLK. Lub moos zaus no tau txhais raws li qhov piv ntawm MDDR_CLK thiab yuav tsum phim qhov zaus ntawm FPGA npuag sub-system uas nkag mus rau MDDR tab tom khiav.

Daim duab 2-5 • Cortex-M3 thiab MSS Main Clock; MDDR Clocks

Rau FDDR, koj yuav tsum qhia:

• FDDR_CLK - Txiav txim siab qhov kev khiav hauj lwm zaus ntawm DDR Controller thiab yuav tsum phim lub moos zaus uas koj xav kom koj lub cim xeeb sab nraud DDR khiav. Nco ntsoov tias lub moos no txhais tau tias yog ntau yam ntawm M3_CLK (MSS thiab Cortex-M3 moos, Daim duab 2-5). FDDR_CLK yuav tsum nyob hauv 20 MHz thiab 333 MHz.
• FDDR_SUBSYSTEM_CLK - Lub moos zaus no txhais tau tias yog qhov piv ntawm FDDR_CLK thiab yuav tsum phim qhov zaus ntawm FPGA ntaub sub-system uas nkag mus rau FDDR tab tom khiav.

Daim duab 2-6 • Npuag DDR Clocks
SERDESIF Configuration
Cov SERDESIF blocks tsis instantiated hauv System Builder generated tsim. Txawm li cas los xij, rau tag nrho cov SERDESIF blocks, cov cim pib pib muaj nyob rau ntawm qhov sib cuam tshuam ntawm System Builder cores thiab tuaj yeem txuas nrog SERDESIF cores ntawm qib tom ntej ntawm hierarchy, raws li qhia hauv daim duab 2-7.Daim duab 2-7 • SERDESIF Peripheral Initialization Connectivity
Zoo ib yam li DDR configuration registers, txhua qhov SERDES block kuj muaj cov ntawv teev npe uas yuav tsum tau thauj khoom thaum lub sijhawm ua haujlwm. Koj tuaj yeem xa cov nqi sau npe no lossis siv High Speed ​​Serial Interface Configurator (Daim duab 2-8) kom nkag mus rau koj qhov PCIe lossis EPCS tsis tau thiab cov nqi sau npe yuav raug suav rau koj. Yog xav paub ntxiv, xa mus rau lub SERDES Configurator Tus neeg siv phau ntawv qhia.Daim duab 2-8 • High Speed ​​Serial Interface Configurator
Thaum koj tau koom ua ke koj cov neeg siv logic nrog System Builder thaiv thiab SERDES thaiv, koj tuaj yeem tsim koj qib siab SmartDesign. Qhov no tsim tag nrho HDL thiab BFM files uas tsim nyog los siv thiab simulate koj tus qauv tsim. Tom qab ntawd koj tuaj yeem txuas ntxiv mus rau qhov seem ntawm Kev Tsim Nyog.

Siv SmartDesign los tsim kev tsim siv DDR thiab SERDESIF Blocks

Tshooj lus no piav qhia txog yuav ua li cas tso ib qho kev daws teeb meem 'initialization' ua ke yam tsis siv SmartFusion2 System Builder. Lub hom phiaj yog los pab koj nkag siab qhov koj yuav tsum ua yog tias koj tsis xav siv System Builder. Tshooj lus no kuj piav qhia txog qhov System Builder lub cuab yeej ua tau tiag tiag rau koj. Nqe lus no piav qhia yuav ua li cas:

• Muab cov ntaub ntawv teeb tsa rau DDR maub los thiab SERDESIF configuration registers.
• Instantiate thiab txuas cov Fabric Cores xav tau los hloov cov ntaub ntawv teeb tsa mus rau DDR controllers thiab SERDESIF configuration registers.

DDR Controller Configuration
MSS DDR (MDDR) thiab Fabric DDR (FDDR) maub los yuav tsum tau teeb tsa dynamically (thaum runtime) kom phim cov kev cai sab nraud DDR nco configuration (DDR hom, PHY dav, tawg hom, ECC, thiab lwm yam). Cov ntaub ntawv nkag rau hauv MDDR / FDDR configurator yog sau rau DDR tswj kev teeb tsa kev sau npe los ntawm CMSIS SystemInit() muaj nuj nqi. Lub Configurator muaj peb qhov sib txawv tab rau nkag mus rau ntau hom kev teeb tsa cov ntaub ntawv:

• Cov ntaub ntawv dav dav (DDR hom, Cov ntaub ntawv dav, moos zaus, ECC, Fabric Interface, Tsav Zog)
• Cov ntaub ntawv nco Initialization (Tshaj Tawm Length, Kev Txiav Txim Siab, Lub Sijhawm Hom, Latency, thiab lwm yam)
• Memory Timing data

Xa mus rau cov lus qhia tshwj xeeb ntawm koj lub cim xeeb DDR sab nraud thiab teeb tsa DDR Controller kom phim cov kev xav tau ntawm koj lub cim xeeb sab nraud DDR.
Yog xav paub ntxiv txog DDR teeb tsa, saib mus rau SmartFusion2 MSS DDR Configuration User Guide.
SERDESIF Configuration
Ob-nias lub SERDES thaiv hauv SmartDesign canvas qhib Configurator los teeb tsa SERDES (Daim duab 3-1). Koj tuaj yeem xa cov nqi sau npe no lossis siv SERDES configurator kom nkag mus rau koj qhov PCIe lossis EPCS tsis tau thiab cov nqi sau npe yuav raug suav rau koj. Yog xav paub ntxiv, xa mus rau lub SERDES Configurator Tus neeg siv phau ntawv qhia.Daim duab 3-1 • High Speed ​​Serial Interface Configurator
Tsim cov FPGA Tsim Kev Tsim Nyog Pib Ua Haujlwm Sub-System
Txhawm rau pib qhov DDR thiab SERDESIF blocks, koj yuav tsum tsim qhov pib ua haujlwm subsystem hauv FPGA ntaub. FPGA fabric initialization subsystem txav cov ntaub ntawv los ntawm Cortex-M3 mus rau DDR thiab SERDESIF configuration registers, tswj cov reset sequences uas yuav tsum tau rau cov blocks yuav ua hauj lwm thiab teeb liab thaum cov blocks yog npaj txhij mus sib txuas lus nrog tus so ntawm koj tsim. Txhawm rau tsim qhov pib subsystem, koj yuav tsum:

• Configure FIC_2 hauv MSS
• Instantiate thiab teeb tsa CoreConfigP thiab CoreResetP cores
• Instantiate on-chip 25/50MHz RC oscillator
• Instantiate qhov System Reset (SYSRESET) macro
• Txuas cov khoom no mus rau txhua qhov peripheral lub teeb tsa interfaces, moos, rov pib dua thiab PLL cov chaw nres nkoj xauv

MSS FIC_2 APB Configuration
Txhawm rau teeb tsa MSS FIC_2:

1. Qhib FIC_2 configurator dialog box los ntawm MSS configurator (Daim duab 3-2).
2. Xaiv qhov pib ua haujlwm peripheral siv Cortex-M3.
3. Nyob ntawm koj qhov system, kos ib lossis ob qho tib si hauv qab no:
   - MSS DDR
   - Npuag DDR thiab / lossis SERDES Blocks
4. Nyem OK thiab txuas ntxiv mus tsim MSS (koj tuaj yeem ncua qhov kev txiav txim no kom txog thaum koj tau teeb tsa MSS tag nrho rau koj qhov kev tsim qauv). FIC_2 chaw nres nkoj (FIC_2_APB_MASTER, FIC_2_APB_M_PCLK thiab FIC_2_APB_M_RESET_N) tam sim no nthuav tawm ntawm MSS interface thiab tuaj yeem txuas nrog CoreConfigP thiab CoreResetP cores.

Daim duab 3-2 • MSS FIC_2 Configurator

CoreConfigP
Txhawm rau teeb tsa CoreConfigP:

1. Instantiate CoreConfigP rau hauv koj lub SmartDesign (feem ntau yog qhov uas MSS yog instantiated).
   Cov tub ntxhais no tuaj yeem pom hauv Libero Catalog (hauv qab Peripherals).
2. Muab ob npaug rau-nias lub core qhib lub configurator.
3. Configure cov tub ntxhais kom qhia meej tias qhov twg peripherals yuav tsum tau pib (Daim duab 3-3)

Daim duab 3-3 • CoreConfigP Dialog Box

CoreResetP
Txhawm rau teeb tsa CoreResetP:

1. Instantiate CoreResetP rau hauv koj lub SmartDesign (feem ntau yog qhov uas MSS yog instantiated).
   Cov tub ntxhais no tuaj yeem pom hauv Libero Catalog, hauv qab Peripherals.
2. Muab ob npaug rau-nias lub hauv paus hauv SmartDesign Canvas qhib lub Configurator (Daim duab 3-4).
3. Configure lub core rau:
   - Qhia tawm tus cwj pwm rov pib dua sab nraud (EXT_RESET_OUT lees paub). Xaiv ib qho ntawm plaub txoj kev xaiv:
   o EXT_RESET_OUT yeej tsis lees paub
   o EXT_RESET_OUT tau lees paub yog tias lub zog rov pib dua (POWER_ON_RESET_N) tau lees paub
   o EXT_RESET_OUT tau lees paub yog FAB_RESET_N tau lees paub
   o EXT_RESET_OUT tau lees paub yog tias lub zog rov pib dua (POWER_ON_RESET_N) lossis FAB_RESET_N tau lees paub
   - Qhia meej lub Ntaus Voltage. Tus nqi xaiv yuav tsum phim lub voltage koj xaiv hauv Libero Project Settings dialog box.
   - Txheeb xyuas lub checkboxes uas tsim nyog los qhia seb qhov khoom siv twg koj siv hauv koj tus qauv tsim.
   - Qhia tawm lub sijhawm teeb tsa lub cim xeeb sab nraud DDR. Qhov no yog tus nqi siab tshaj plaws rau tag nrho DDR nco siv hauv koj daim ntawv thov (MDDR thiab FDDR). Xa mus rau sab nraud DDR lub cim xeeb tus neeg muag khoom datasheet kom teeb tsa qhov ntsuas no. 200us yog tus nqi zoo rau DDR2 thiab DDR3 nco khiav ntawm 200MHz. Qhov no yog qhov tseem ceeb heev los lav qhov kev sim ua haujlwm thiab kev ua haujlwm ntawm silicon. Tus nqi tsis raug rau lub sijhawm daws teeb meem tuaj yeem ua rau simulation yuam kev. Xa mus rau DDR nco tus neeg muag khoom datasheet kom teeb tsa qhov ntsuas no.
   - Rau txhua qhov SERDES thaiv hauv koj qhov tsim, kos cov thawv tsim nyog los qhia seb:
   o PCIe yog siv
   o Kev them nyiaj yug rau PCIe Kub Reset yog xav tau
   o Kev them nyiaj yug rau PCIe L2 / P2 yog xav tau

Nco tseg: Yog tias koj siv 090 tuag (M2S090) thiab koj tus qauv tsim siv SERDESIF, koj tsis tas yuav kuaj ib qho ntawm cov checkboxes hauv qab no: 'Siv rau PCIe', 'Include PCIe HotReset support' thiab 'Include PCIe L2/P2 support'. Yog tias koj siv cov khoom siv uas tsis yog-090 thiab siv ib lossis ntau dua SERDESIF blocks, koj yuav tsum xyuas tag nrho plaub lub thawv nyob rau hauv seem SERDESIF uas tsim nyog.
Nco tseg: Yog xav paub meej txog cov kev xaiv muaj rau koj nyob rau hauv no configurator, xa mus rau CoreResetP Phau Ntawv.

Daim duab 3-4 • CoreResetPConfigurator

25/50MHz Oscillator Instantiation
CoreConfigP thiab CoreResetP yog clocked los ntawm on-chip 25/50MHz RC oscillator. Koj yuav tsum instantiate 25/50MHz Oscillator thiab txuas rau cov cores no.

1. Instantiate Chip Oscillators core rau hauv koj lub SmartDesign (feem ntau yog qhov uas MSS yog instantiated). Cov tub ntxhais no tuaj yeem pom hauv Libero Catalog hauv Clock & Management.
2. Kho cov tub ntxhais no xws li RC oscillator tsav FPGA ntaub, raws li qhia hauv daim duab 3-5.

Daim duab 3-5 • Chip Oscillators Configurator

Qhov System Reset (SYSRESET) Instantiation
SYSRESET macro muab cov cuab yeej qib pib ua haujlwm rau koj tus qauv tsim. POWER_ON_RESET_N tso zis teeb liab yog asserted/de-asserted thaum twg lub nti yog powered los yog lwm tus pin DEVRST_N yog asserted/de-asserted (Daim duab 3-6).
Instantiate SYSRESET macro rau hauv koj lub SmartDesign (feem ntau yog ib qho uas MSS instantiated). Cov macro no tuaj yeem pom hauv Libero Catalog hauv qab Macro Library.No configuration ntawm no macro yog tsim nyog.

Daim duab 3-6 • SYSRESET Macro

Kev sib txuas tag nrho
Tom qab koj tau instantiated thiab teeb tsa MSS, FDDR, SERDESIF, OSC, SYSRESET, CoreConfigP thiab CoreResetP cores hauv koj tus qauv tsim, koj yuav tsum txuas lawv los tsim Peripheral Initialization subsystem. Txhawm rau ua kom yooj yim cov lus piav qhia txog kev sib txuas hauv cov ntaub ntawv no, nws tau tawg rau hauv APB3 raws li kev teeb tsa cov ntaub ntawv kev sib txuas nrog rau CoreConfigP thiab CoreResetP ntsig txog kev sib txuas.
Configuration Data Path Connectivity
Daim duab 3-7 qhia tau hais tias yuav ua li cas txuas CoreConfigP rau MSS FIC_2 cov teeb liab thiab cov khoom siv hluav taws xob 'APB3 raws li kev teeb tsa interfaces.
Table 3-1 • Configuration Data Path Port/BIF Connections

Los ntawm Chaw nres nkoj/Bus Interface (BIF)/Cov	TO Chaw nres nkoj/Bus Interface (BIF)/Component
APB S PreSET N / CoreConfigP	APB S PreSET N/ SDIF<0/1/2/3>	APB S PreSET N/ FDDR	MDDR APB S PRESE TN/MSS
APB S PCLK/ CoreConfigP	APB S PCLK/SDIF	APB S PCLK/FDDR	MDDR APB S POLK/MSS
MDDR APBmslave/CoreConfig			MDDR APB SLAVE (BIF)/MSS
SDIF<0/1/2/3> APBmslave/Config	APB SLAVE (BIF)/ SDIF<0/1/2/3>
FDDR APBmslave		APB SLAVE (BIF) / FDDR
FIC 2 APBmmaster / CoreConfigP			FIC 2 APB MASTER/MSS

Daim duab 3-7 • FIC_2 APB3 Sub-System Connectivity

Clocks thiab Resets Connectivity
Daim duab 3-8 qhia tau hais tias yuav ua li cas txuas CoreResetP mus rau qhov chaw rov pib dua sab nraud thiab cov khoom siv hluav taws xob rov pib dua. Nws kuj qhia tau hais tias yuav ua li cas txuas CoreResetP rau cov khoom siv hluav taws xob 'clock synchronization raws li txoj cai (PLL lock signals). Tsis tas li ntawd, nws qhia tau hais tias yuav ua li cas CoreConfigP thiab CoreResetP txuas nrog.

Daim duab 3-8 • Core SF2Reset Sub-System Connectivity

Tsim thiab sau daim ntawv thov Firmware

Thaum koj xa cov firmware los ntawm LiberoSoC (Design Flow Window> Export Firmware> Export Firmware), Libero tsim cov hauv qab no files hauv /firmware/drivers_config/ sys_config folder:

• sys_config.c - Muaj cov qauv ntaub ntawv uas tuav cov txiaj ntsig rau cov ntawv sau npe peripheral.
• sys_config.h - Muaj cov lus #define uas qhia meej tias cov khoom siv twg yog siv rau hauv kev tsim thiab yuav tsum tau pib.
• sys_config_mddr_define.h - Muaj MDDR cov ntaub ntawv teeb tsa kev teeb tsa nkag mus rau hauv Cov Ntawv Teev Npe Kev teeb tsa dialog box.
• sys_config_fddr_define.h - Muaj FDDR cov ntaub ntawv teeb tsa kev teeb tsa tau nkag mus rau hauv Cov Ntawv Sau Npe Configuration dialog box.
• sys_config_mss_clocks.h - Qhov no file muaj MSS moos zaus raws li tau teev tseg hauv MSS CCC configurator. Cov zaus no yog siv los ntawm CMSIS code los muab cov ntaub ntawv moos kom raug rau ntau tus neeg tsav tsheb MSS uas yuav tsum muaj kev nkag mus rau lawv cov Peripheral Clock (PCLK) zaus (piv txwv li, MSS UART baud rate divisors yog qhov ua haujlwm ntawm baud tus nqi thiab PCLK zaus. ).
• sys_config_SERDESIF_ .c - Muaj SERDESIF_ sau npe configuration cov ntaub ntawv muab thaum lub sij hawm SERDESIF_ thaiv kev teeb tsa hauv kev tsim tsim.
• sys_config_SERDESIF_ .h - Muaj cov nqe lus #define uas qhia cov naj npawb ntawm cov npe kev teeb tsa ua khub thiab tus lej kab uas yuav tsum tau xaiv rau PMA_READY (tsuas yog hauv PCIe hom).

Cov no files yuav tsum tau rau CMSIS code los sau ua ke kom raug thiab muaj cov ntaub ntawv hais txog koj tus qauv tam sim no, suav nrog cov ntaub ntawv teeb tsa peripheral thiab cov ntaub ntawv teev teev rau MSS.
Tsis txhob hloov cov no files manually; lawv raug tsim los rau cov khoom sib txuas / cov npe khoom siv peripheral txhua zaus cov khoom siv SmartDesign uas muaj cov khoom siv sib txuas tau tsim. Yog tias muaj kev hloov pauv rau cov ntaub ntawv teeb tsa ntawm ib qho ntawm cov khoom siv, koj yuav tsum rov xa tawm cov haujlwm firmware kom cov firmware tshiab. files (saib cov npe saum toj no) raug xa tawm mus rau / firmware/drivers_config/sys_config folder.
Thaum koj xa tawm cov firmware, Libero SoC tsim cov firmware tej yaam num: lub tsev qiv ntawv uas koj tsim configuration files thiab cov tsav tsheb tau muab tso ua ke.
Yog tias koj kos rau Tsim qhov project checkbox thaum koj export lub firmware, software SoftConsole / IAR / Keil project yog tsim los tuav daim ntawv thov qhov project uas koj tuaj yeem hloov kho lub main.c thiab cov neeg siv C / H. files. Qhib SoftConSole/IAR/Keil qhov project los sau cov CMSIS code kom raug thiab muaj koj daim ntawv thov firmware teeb tsa kom haum rau koj tus qauv tsim kho vajtse.

BFM Files Siv rau Simulating tus tsim

Thaum koj tsim cov khoom siv SmartDesign uas muaj cov khoom siv txuas nrog koj tus qauv tsim, simulation files sib raug rau cov peripherals uas yog generated nyob rau hauv lub / simulation directory:

• tes bfm - Sab saum toj BFM file uas yog thawj zaug tua thaum lub sijhawm simulation uas ua haujlwm ntawm SmartFusion2 MSS Cortex-M3 processor. Nws ua haujlwm peripheral_init.bfm thiab user.bfm, hauv qhov kev txiav txim ntawd.
• MDDR_init.bfm - Yog tias koj tus qauv tsim siv MDDR, Libero tsim qhov no file; nws muaj BFM sau cov lus txib uas simulate sau ntawm MSS DDR teeb tsa kev sau npe cov ntaub ntawv koj tau nkag mus (siv cov Hloov Kho Cov Npe dialogbox lossis hauv MSS_MDDR GUI) rau hauv MSS DDR Controller sau npe.
• FDDR_init.bfm - Yog tias koj tus qauv tsim siv FDDR, Libero tsim qhov no file; nws muaj BFM sau cov lus txib uas simulate sau ntawm Fabric DDR teeb tsa cov ntaub ntawv sau npe koj tau nkag mus (siv cov Kho Kho Cov Ntawv Sau Npe dialogbox lossis hauv FDDR GUI) rau hauv Fabric DDR Controller sau npe.
• SERDESIF_ _init.bfm ib - Yog tias koj tus qauv tsim siv ib lossis ntau dua SERDESIF thaiv, Libero tsim qhov no file rau txhua tus SERDESIF_ blocks siv; nws muaj BFM sau cov lus txib uas simulate sau ntawm SERDESIF teeb tsa cov ntaub ntawv sau npe koj tau nkag mus (siv lub Edit Registers dialog box lossis hauv SERDESIF_ GUI) rau hauv SERDESIF_ sau npe. Yog tias SERDESIF thaiv tau teeb tsa raws li PCIe, qhov no file kuj tseem muaj qee qhov #define nqe lus uas tswj kev ua tiav ntawm 2 teev cov txheej txheem teeb tsa hauv kev txiav txim zoo.
• siv bfm - Muaj cov neeg siv cov lus txib. Cov lus txib no raug tua tom qab peripheral_init.bfm ua tiav. Kho qhov no file nkag mus rau koj cov lus txib BFM.
• SERDESIF_ _user.bfm ib - Muaj cov neeg siv cov lus txib. Kho qhov no file nkag mus rau koj cov lus txib BFM. Siv qhov no yog tias koj tau teeb tsa SERDESIF_ thaiv hauv BFM PCIe simulation hom thiab ua tus tswv AXI/AHBLite. Yog tias koj tau teeb tsa SERDESIF_ thaiv hauv RTL simulation hom, koj yuav tsis xav tau qhov no file.

Thaum koj hu simulation txhua lub sijhawm, ob qhov simulation hauv qab no files yog re-created rau lub / simulation directory nrog cov ntsiab lus tshiab:

• subsystem.bfm - Muaj cov lus qhia #define rau txhua qhov khoom siv peripheral siv hauv koj tus qauv tsim, uas qhia txog ntu tshwj xeeb ntawm peripheral_init.bfm yuav tsum tau ua raws li txhua qhov peripheral.
• operipheral_init.bfm ib - Muaj cov txheej txheem BFM uas emulates CMSIS:: SystemInit() muaj nuj nqi khiav ntawm Cortex-M3 ua ntej koj nkag mus rau lub ntsiab() txheej txheem. Nws luam tawm cov ntaub ntawv teeb tsa rau ib qho khoom siv peripheral siv hauv kev tsim rau cov ntawv teev npe peripheral kom raug thiab tom qab ntawd tos kom tag nrho cov khoom siv peripherals npaj ua ntej lees paub tias koj tuaj yeem siv cov khoom siv no. Nws ua haujlwm MDDR_init.bfm thiab FDDR_init.bfm.

Siv cov generated files, DDR controllers nyob rau hauv koj tus tsim yog configured txiav, simulating dab tsi yuav tshwm sim ntawm ib tug SmartFusion2 ntaus ntawv. Koj tuaj yeem hloov kho user.bfm file ntxiv cov lus txib uas yuav tsum tau simulate koj tus tsim (Cortex-M3 yog tus tswv). Cov lus txib no raug tua tom qab lub peripherals tau pib. Tsis txhob hloov qhov test.bfm, subsystem.bfm, peripheral_init.bfm, MDDR_init.bfm, FDDR_init.bfm files thiab SERDESIF_ _init.bfm ib files.

Khoom txhawb

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Webqhov chaw
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Cov ntaub ntawv / Cov ntaub ntawv

Microsemi SmartFusion2 DDR Controller thiab Serial High Speed ​​Controller [ua pdf] Cov neeg siv phau ntawv qhia SmartFusion2 DDR Controller thiab Serial High Speed ​​Controller, SmartFusion2 DDR, Controller thiab Serial High Speed ​​Controller, High Speed ​​Controller

Cov ntaub ntawv

• Cov neeg siv phau ntawv