SmartFusion2
DDR Controller le Serial High Speed ​​Controller
Mokhoa oa ho Qala
Bukana ea Mosebelisi

Selelekela

Ha u theha moralo o sebelisa sesebelisoa sa SmartFusion2, haeba u sebelisa e 'ngoe ea li-control tse peli tsa DDR (FDDR kapa MDDR) kapa leha e le efe ea li-block tsa Serial High speed controller (SERDESIF), u tlameha ho qala li-registering tsa tlhophiso ea li-blocks ka nako ea pele. li ka sebelisoa. Bakeng sa mohlalaample, bakeng sa molaoli oa DDR, o tlameha ho seta mokhoa oa DDR (DDR3/DDR2/LPDDR), bophara ba PHY, mokhoa oa ho phatloha le ECC.
Ka mokhoa o ts'oanang, bakeng sa boloko ba SERDESIF e sebelisoang joalo ka PCIe qetellong, o tlameha ho seta PCIE BAR ho fensetere ea AXI (kapa AHB).
Tokomane ena e hlalosa mehato e hlokahalang bakeng sa ho theha moralo oa Libero o qalang ka bohona molaoli oa DDR le li-block tsa SERDESIF ha li ntse li phahama. E boetse e hlalosa mokhoa oa ho hlahisa khoutu ea firmware ho tloha Libero SOC e sebelisoang ho phalla ha moralo o kentsoeng.
Tlhaloso e qaqileng ea khopolo ea ts'ebetso e fanoa pele.
Karolo e latelang e hlalosa mokhoa oa ho etsa moralo o joalo o sebelisa Libero SoC System Builder, sesebelisoa se matla sa moralo seo, har'a likarolo tse ling, se u etsetsang tharollo ea 'ho qala' haeba u sebelisa li-block tsa DDR kapa SERDESIF moqapi oa hau.
Karolo e latelang e hlalosa mokhoa oa ho kopanya tharollo e felletseng ea 'ho qala' ntle le ho sebelisa SmartFusion2 System Builder. Sena se thusa ho hlalosa se lokelang ho etsoa haeba o sa batle ho sebelisa System Builder, hape e hlalosa hore na sesebelisoa sa System Builder se u hlahisetsa eng. Karolo ena e bua ka:

• Theho ea lintlha tsa tlhophiso bakeng sa molaoli oa DDR le lirejistara tsa tlhophiso ea SERDESIF
• Ho theoa ha mohopolo oa FPGA o hlokahalang ho fetisetsa data ea tlhophiso ho lirekoto tse fapaneng tsa tlhophiso tsa ASIC.

Qetellong re hlalosa tse hlahisitsoeng filee amana le:

• Ho theha tharollo ea firmware 'initialization'.
• Ketsiso ea moralo bakeng sa tharollo ea DDR 'ho qala'.

Bakeng sa lintlha tse mabapi le molaoli oa DDR le lirejistara tsa tlhophiso ea SERDESIF, sheba ho Microsemi SmartFusion2 High Speed ​​Serial le DDR Interfaces Tataiso ea Basebelisi.

Khopolo ea Ts'ebetso

Tharollo ea Peripheral initialization e sebelisa likarolo tse latelang tse kholo:

• Mosebetsi oa CMSIS SystemInit(), o sebetsang ho Cortex-M3 mme o hlophisa ts'ebetso ea ho qala.
• CoreConfigP e bonolo ea IP ea mantlha, e qalang lirejistara tsa tlhophiso ea peripherals.
• CoreResetP e bonolo ea IP ea mantlha, e laolang tatellano ea reset ea MSS, balaoli ba DDR, le li-block tsa SERDESIF.

Ts'ebetso ea peripheral initialization e sebetsa ka tsela e latelang:

1. Ha e seta bocha, Cortex-M3 e tsamaisa mosebetsi oa CMSIS SystemInit(). Ts'ebetso ena e etsoa ka bo eona pele ts'ebetso e kholo () ea ts'ebeliso e etsoa.
   Letšoao la CoreResetP la MSS_HPMS_READY le tiisitsoe qalong ea ts'ebetso ea ho qala, e bontšang hore MSS le lisebelisoa tsohle (ntle le MDDR) li se li loketse puisano.
2. Ts'ebetso ea SystemInit() e ngola lintlha tsa tlhophiso ho balaoli ba DDR le lirejistara tsa tlhophiso tsa SERDESIF ka bese ea MSS FIC_2 APB3. Khokahano ena e hokahane le motheo o bonolo oa CoreConfigP o kentsoeng leselang la FPGA.
3. Ka mor'a hore li-registas tsohle li hlophisoe, mosebetsi oa SystemInit () o ngolla li-registas tsa taolo ea CoreConfigP ho bontša ho phethoa ha karolo ea tlhophiso ea ngoliso; matshwao a tlhahiso ya CoreConfigP CONFIG1_DONE le CONIG2_DONE di a hlahiswa.
   Ho na le mekhahlelo e 'meli ea tlhophiso ea ngoliso (CONFIG1 le CONFIG2) ho latela likarolo tse sebelisitsoeng moralong.
4. Haeba ho sebelisoa e le 'ngoe kapa tse peli tsa MDDR/FDDR, 'me ha ho le e 'ngoe ea li-blocks tsa SERDESIF e sebelisoang moahong, ho na le mohato o le mong feela oa tlhophiso ea ngoliso. Ka bobeli matshwao a tlhahiso ya CoreConfigP CONFIG1_DONE le CONIG2_DONE a tiisetswa ka ho latellana ntle le ho ema/tieho.
   Haeba ho sebelisoa li-block tsa SERDESIF ka mokhoa oo eseng oa PCIe ho sebelisoa moralo, ho na le karolo e le 'ngoe feela ea tlhophiso ea ngoliso. CONFIG1_DONE le CONIG2_DONE li tiisetsoa ka ho latellana ntle le ho ema/tieho.
   Haeba ho sebelisoa li-block tsa SERDESIF ka mokhoa oa PCIe ka moralo, ho na le mekhahlelo e 'meli ea tlhophiso ea ngoliso. CONFIG1_DONE e tiisitsoe ka mor'a hore karolo ea pele ea tokiso ea ngoliso e phetheloe. Sistimi ea SERDESIF le lirejisete tsa litselana li entsoe mokhahlelong ona. Haeba SERDESIF e hlophisitsoe ka mokhoa oo e seng oa PCIE, lets'oao la CONFIG2_DONE le tla tiisoa hang hang.
5. Mokhahlelo oa bobeli oa tokiso ea ngoliso e tla latela (haeba SERDESIF e lokiselitsoe ka mokhoa oa PCIE). Tse latelang ke liketsahalo tse fapaneng tse etsahalang mokhahlelong oa bobeli:
   - CoreResetP de-asserts PHY_RESET_N le CORE_RESET_N matšoao a tsamaellanang le e 'ngoe le e 'ngoe ea li-block tsa SERDESIF tse sebelisitsoeng. E boetse e fana ka lets'oao la tlhahiso SDIF_RELEASED kamora hore li-block tsa SERDESIF li felisoe. Letšoao lena la SDIF_RELEASED le sebelisetsoa ho bontša CoreConfigP hore SERDESIF core ha e sa sebetsa 'me e se e loketse mokhahlelo oa bobeli oa tokiso ea ngoliso.
   - Hang ha lets'oao la SDIF_RELEASED le netefalitsoe, ts'ebetso ea SystemInit() e qala ho khetha bakeng sa polelo ea PMA_READY tseleng e nepahetseng ea SERDESIF. Hang ha PMA_READY e tiisitsoe, sehlopha sa bobeli sa lirejisetara tsa SERDESIF (PCIE registara) lia hlophisoa/li ngoloa ke tšebetso ea SystemInit().
6. Ka mor'a hore litlaleho tsohle tsa PCIE li hlophisoe, mosebetsi oa SystemInit () o ngolla lirejisete tsa taolo tsa CoreConfigP ho bontša ho phethoa ha karolo ea bobeli ea tlhophiso ea ngoliso; lets'oao la CoreConfigP la CONIG2_DONE lea tiisoa.
7. Ntle le lipolelo / de-assertions tse ka holimo, CoreResetP e boetse e laola ho qalisoa ha li-blocks tse fapa-fapaneng ka ho etsa mesebetsi e latelang:
   - Ho hlakisa ts'ebetso ea mantlha ea FDDR
   - Ho hana SERDESIF ho thibela PHY le CORE reset
   - Ho beha leihlo lets'oao la senotlolo la FDDR PLL (FPLL). FPLL e tlameha ebe e notletsoe ho netefatsa hore sebopeho sa data sa FDDR AXI/AHBLite le lesela la FPGA li ka buisana ka nepo.
   - Ho beha leihlo matšoao a senotlolo sa SERDESIF block PLL (SPLL). SPLL e tlameha ebe e notletsoe ho tiisa hore SERDESIF e thibela AXI/AHBLite interface (PCIe mode) kapa XAUI interface e ka buisana hantle le lesela la FPGA.
   - E emetse mehopolo ea kantle ea DDR ho tsitsa le ho itokisetsa ho fihleloa ke balaoli ba DDR.
8. Ha lisebelisoa tsohle li qetile ho qala, CoreResetP e fana ka letšoao la INIT_DONE; rejisetara ea ka hare ea CoreConfigP INIT_DONE e tla tiisoa.
   Haeba ho sebelisoa e le 'ngoe kapa tse peli tsa MDDR/FDDR, 'me nako ea ho qala DDR e fihletsoe, lets'oao la CoreResetP la DDR_READY le tiisitsoe. Polelo ea lets'oao lena DDR_READY e ka shejoa joalo ka sesupo sa hore DDR (MDDR/FDDR) e se e loketse puisano.
   Haeba ho sebelisoa li-block tsa SERDESIF tse le 'ngoe kapa tse ngata, 'me karolo ea bobeli ea tokiso ea ngoliso e phethetsoe ka katleho, ho netefatsoa lets'oao la CoreResetP SDIF_READY. Netefatso ea lets'oao lena SDIF_READY e ka shejoa joalo ka sesupo sa hore li-block tsa SERDESIF li se li loketse puisano.
9. Ts'ebetso ea SystemInit() esale e emetse hore INIT_DONE e phatlalatsoe, e phethehe, 'me mosebetsi oa mantlha () oa ts'ebeliso o kenngoe. Ka nako eo, balaoli bohle ba DDR ba sebelisitsoeng le li-block tsa SERDESIF li se li qalile, 'me sesebelisoa sa firmware le logic ea lesela la FPGA li ka buisana le bona ka botšepehi.

Mokhoa o hlalositsoeng tokomaneng ena o ipapisitse le Cortex-M3 e phethahatsang ts'ebetso ea ho qala e le karolo ea khoutu ea ho qala ea sistimi e phethiloeng pele ho ts'ebetso ea mantlha () ea kopo.
Sheba Phallo Charts ho Setšoantšo sa 1-1, Setšoantšo sa 1-2 le Setšoantšo sa 1-3 bakeng sa mehato ea Qalo ea FDDR/MDDR, SEREDES(mokhoa o seng oa PCIe) le SERDES (mokhoa oa PCIe).
Setšoantšo sa 1-4 se bontša setšoantšo sa nako ea Peripheral Initialization.

Setšoantšo sa 1-3 • SERDESIF (PCIe) Chate ea Phallo ea ho Qala
Mokhoa oa ho qala o hlalositsoeng tokomaneng ena o hloka hore o tsamaise Cortex-M3 nakong ea ts'ebetso ea ho qala, leha o sa rera ho sebelisa khoutu efe kapa efe ho Cortex-M3. U tlameha ho theha sesebelisoa sa firmware se sa etse letho (loop e bonolo, mohlalaample) le ho kenya tse ka phethisoang ho Non Volatile Memory (eNVM) e kentsoeng e le hore balaoli ba DDR le li-block tsa SERDESIF li qalisoa ha lirifi tsa Cortex-M3.

Ho Sebelisa Sehahi sa Tsamaiso ho Etsa Moralo ka ho Sebelisa Li-DDR le SERDESIF Blocks

SmartFusion2 System Builder ke sesebelisoa se matla sa meralo se u thusang ho hapa litlhoko tsa boemo ba sistimi mme se hlahisa moralo o phethahatsang litlhoko tseo. Mosebetsi oa bohlokoa haholo oa System Builder ke ho iketsetsa ka mokhoa o ikemetseng oa tsamaiso e nyenyane ea Peripheral Initialization. "Ho Sebelisa SmartDesign ho Etsa Moqapi o Sebelisang DDR le SERDESIF Blocks" leqepheng la 17 e hlalosa ka botlalo mokhoa oa ho etsa tharollo e joalo ntle le Sehahi sa Tsamaiso.
Haeba u sebelisa System Builder, u tlameha ho etsa mesebetsi e latelang ho etsa moralo o qalang lilaoli tsa DDR tsa hau le li-block tsa SERDESIF ha li ntse li phahama:

1. Leqepheng la Likarolo tsa Sesebelisoa (setšoantšo sa 2-1), hlakisa hore na ho sebelisoa lilaoli life tsa DDR le hore na ke li-block tsa SERDESIF tse kae tse sebelisoang moralong oa hau.
2. Leqepheng la Memori, bolela mofuta oa DDR (DDR2/DDR3/LPDDR) le lintlha tsa tlhophiso bakeng sa mehopolo ea hau ea kantle ea DDR. Sheba karolo ea Leqephe la Memori ho fumana lintlha.
3. Leqepheng la Peripherals, eketsa li-master masters tse hlophisitsoeng joalo ka AHBLite/AXI ho Fabric DDR Subsystem le/kapa MSS DDR FIC Subsystem (ka boikhethelo).
4. Leqepheng la Litlhophiso tsa Oache, hlakisa maqhubu a oache bakeng sa li-sub-system tsa DDR.
5. Tlatsa litlhaloso tsa moralo oa hau ebe o tobetsa Finish. Sena se hlahisa moralo o entsoeng ke Sehahi sa Sistimi, ho kenyeletsoa le logic e hlokahalang bakeng sa tharollo ea 'ho qala'.
6. Haeba u sebelisa li-block tsa SERDESIF, u tlameha ho tiisa li-block tsa SERDESIF moralong oa hau le ho hokela likou tsa tsona tsa ho qala ho tsa mantlha tse hlahisitsoeng ke System Builder.

Leqephe la Lisebelisoa tsa Sehahi sa Sistimi
Leqepheng la Likarolo tsa Sesebelisoa, hlakisa hore na ke li-controller life tsa DDR (MDDR le/kapa FDDR) tse sebelisoang le hore na ke li-block tsa SERDESIF tse kae tse sebelisitsoeng moralong oa hau (Setšoantšo sa 2-1).

Setšoantšo sa 2-1 • Leqephe la Likarolo tsa Lisebelisoa tsa Sehahi sa Tsamaiso

Leqephe la Memori ea Sehahi sa Sistimi
Ho sebelisa MSS DDR (MDDR) kapa Lesela la DDR (FDDR), khetha Mofuta oa Memori ho tsoa lethathamong le theoha (Setšoantšo sa 2-2).

Setšoantšo sa 2-2 • Memori ea Kantle ea MSS

O tlameha ho:

1. Khetha mofuta oa DDR (DDR2, DDR3 kapa LPDDR).
2. Hlalosa nako ea ho lokisa memori ea DDR. Sheba Litlhaloso tsa memori ea hau ea kantle ea DDR ho seta nako e nepahetseng ea ho seta memori. Memori ea DDR e kanna ea hloleha ho qala ka nepo haeba nako ea ho lokisa memori e sa hlophisoa hantle.
3. Eka kenya data ea tlhophiso ea ngoliso ea DDR kapa u behe Memori ea hau ea DDR. Bakeng sa lintlha, sheba ho Microsemi SmartFusion2 High Speed ​​Serial le DDR Interfaces Tataiso ea Basebelisi.

Lintlha tsena li sebelisetsoa ho hlahisa rejisetara ea DDR BFM le tlhophiso ea firmware files joalokaha ho hlalositsoe ho “Ho Etsa le ho Kopanya Kopo ea Firmware” leqepheng la 26 le “BFM Files E Sebelisitsoe Bakeng sa ho Etsisa Moralo” leqepheng la 27. Bakeng sa lintlha tse mabapi le lirejistara tsa tlhophiso ea taolo ea DDR, sheba ho Microsemi SmartFusion2 High Speed ​​Serial le DDR Interfaces Tataiso ea Basebelisi.
Mohlankanaample ea tlhophiso file syntax e bontšoa ho Setšoantšo sa 2-3. Mabitso a rejisetara a sebelisitsoeng ho sena file li tšoana le tse hlalositsoeng ho Microsemi SmartFusion2 High Speed ​​Serial le DDR Interfaces Tataiso ea Basebelisi

Setšoantšo sa 2-3 • Tlhophiso File Syntax Example
Leqephe la Lisebelisoa tsa Sehahi sa Sistimi
Leqepheng la Peripherals, bakeng sa molaoli e mong le e mong oa DDR ho etsoa sistimi e ka thoko (Fabric DDR Subsystem bakeng sa FDDR le MSS DDR FIC Subsystem bakeng sa MDDR). U ka eketsa Fabric AMBA Master (e hlophisitsoeng e le AXI / AHBLite) ho e 'ngoe le e' ngoe ea litsamaiso tsena ho etsa hore masela a fihle ho balaoli ba DDR. Ha e ntse e hlahisa, System Builder e kenya li-cores tsa libese ka bo eona (ho itšetlehile ka mofuta oa AMBA Master e kenyelelitsoeng) 'me e pepesa BIF ea mantlha ea libese le oache le lithapo tsa ho tsosolosa li-subsystems tse lumellanang (FDDR/MDDR) tlas'a lihlopha tse loketseng tsa pini. holimo. Seo u tlamehang ho se etsa feela ke ho hokahanya li-BIF ho li-cores tse nepahetseng tsa Fabric Master tseo u ka li tiisang moralong. Tabeng ea MDDR, ke boikhethelo ho eketsa Fabric AMBA Master core ho MSS DDR FIC Subsystem; Cortex-M3 ke setsebi sa kamehla ho subsystem ena. Setšoantšo sa 2-4 se bonts'a Leqephe la Lisebelisoa tsa Sehahi sa Tsamaiso.

Setšoantšo sa 2-4 • Leqephe la Sehahi sa Tsamaiso

Leqephe la Litlhophiso tsa Oache ea Sehahi sa Sistimi
Leqepheng la Litlhophiso tsa Oache, bakeng sa molaoli e mong le e mong oa DDR, o tlameha ho hlakisa maqhubu a oache a amanang le sistimi e nyane ea DDR (MDDR le/kapa FDDR).
Bakeng sa MDDR, o tlameha ho hlakisa:

• MDDR_CLK - Oache ena e khetholla maqhubu a ts'ebetso ea DDR Controller mme e lokela ho ts'oana le maqhubu a oache eo u lakatsang hore memori ea hau ea kantle ea DDR e sebetse ho eona. Oache ena e hlalosoa e le multiple M3_CLK (Cortex-M3 le MSS Main Clock, Figure 2-5). MDDR_CLK e tlameha ho ba ka tlase ho 333 MHz.
• DDR_FIC_CLK - Haeba u khethile ho fihlella MDDR ho tsoa lesela la FPGA, u hloka ho hlakisa DDR_FIC_CLK. Maqhubu ana a oache a hlalosoa e le karo-karolelano ea MDDR_CLK 'me e lokela ho ts'oana le makhetlo ao sistimi e nyane ea FPGA e kenang ho MDDR e sebetsang ho eona.

Setšoantšo sa 2-5 • Cortex-M3 le MSS Main Clock; Lioache tsa MDDR

Bakeng sa FDDR, o tlameha ho hlakisa:

• FDDR_CLK - E khetholla maqhubu a ts'ebetso ea DDR Controller mme e lokela ho ts'oana le maqhubu a oache eo u lakatsang hore memori ea hau ea kantle ea DDR e sebetse. Hlokomela hore oache ena e hlalosoa e le multiple M3_CLK (MSS le Cortex-M3 oache, Figure 2-5). FDDR_CLK e tlameha ho ba ka har'a 20 MHz le 333 MHz.
• FDDR_SUBSYSTEM_CLK - Leqhubu lena la oache le hlalosoa e le karo-karolelano ea FDDR_CLK 'me e lokela ho ts'oana le makhetlo ao tsamaiso e nyenyane ea lesela la FPGA e kenang FDDR e sebetsang ka eona.

Setšoantšo sa 2-6 • Lesela la DDR Lioache
SERDESIF Configuration
Li-block tsa SERDESIF ha li thehoe ka har'a moralo o hlahisitsoeng oa Sehahi sa Sistimi. Leha ho le joalo, bakeng sa li-blocks tsohle tsa SERDESIF, matšoao a ho qala a fumaneha ho sebopeho sa motheo oa System Builder 'me a ka kopanngoa le li-cores tsa SERDESIF boemong bo latelang ba bolaoli, joalokaha ho bontšitsoe setšoantšong sa 2-7.Setšoantšo sa 2-7 • SERDESIF Peripheral Initialization Connection
Joalo ka lirejistara tsa tlhophiso ea DDR, block e 'ngoe le e' ngoe ea SERDES e boetse e na le li-registerer tsa tlhophiso tse tlamehang ho kengoa ka nako ea ts'ebetso. O ka kenya boleng bona ba ngoliso kapa oa sebelisa High Speed ​​Serial Interface Configurator (Setšoantšo sa 2-8) ho kenya li-parameter tsa PCIe kapa EPCS ea hau 'me boleng ba rejisetara bo balloa uena ka bo eona. Bakeng sa lintlha, sheba ho Tataiso ea mosebelisi ea SERDES Configurator.Setšoantšo sa 2-8 • High Speed ​​Serial Interface Configurator
Hang ha u se u kopantse logic ea hau ea mosebedisi le thibela ea System Builder le SERDES block, u ka hlahisa SmartDesign ea hau ea boemo bo holimo. Sena se hlahisa HDL le BFM tsohle files tse hlokahalang ho kenya ts'ebetsong le ho etsisa moralo oa hau. Joale u ka tsoela pele ka Phallo e setseng ea Moralo.

Ho Sebelisa SmartDesign ho Etsa Moralo o Sebelisa Li-DDR le SERDESIF Blocks

Karolo ena e hlalosa mokhoa oa ho kopanya tharollo e felletseng ea 'ho qala' ntle le ho sebelisa SmartFusion2 System Builder. Sepheo ke ho u thusa ho utloisisa seo u lokelang ho se etsa haeba u sa batle ho sebelisa System Builder. Karolo ena e boetse e hlalosa hore na sesebelisoa sa System Builder se u hlahisetsa eng. Karolo ena e hlalosa mokhoa oa ho:

• Kenya lintlha tsa tlhophiso bakeng sa molaoli oa DDR le lirejistara tsa tlhophiso tsa SERDESIF.
• Etsa bonnete ba le ho hokahanya Li-Core tsa Lesela tse hlokehang ho fetisetsa lintlha tsa tlhophiso ho balaoli ba DDR le lirejistara tsa tlhophiso ea SERDESIF.

Sebopeho sa DDR Controller
Li-control tsa MSS DDR (MDDR) le Fabric DDR (FDDR) li tlameha ho hlophisoa ka matla (ka nako ea ho sebetsa) ho tsamaisana le litlhoko tsa tlhophiso ea memori ea DDR e kantle (mokhoa oa DDR, bophara ba PHY, mokhoa oa ho phatloha, ECC, joalo-joalo). Lintlha tse kentsoeng ho configurator ea MDDR/FDDR li ngolloa lirejistara tsa tlhophiso ea molaoli oa DDR ka mosebetsi oa CMSIS SystemInit(). Configurator e na le li-tab tse tharo tse fapaneng tsa ho kenya mefuta e fapaneng ea data ea tlhophiso:

• Lintlha tse akaretsang (mokhoa oa DDR, Bophara ba Data, Maqhubu a Oache, ECC, Sehokelo sa Lesela, Matla a Drive)
• Lintlha tsa ho qala Memori (Bolelele ba Ho phatloha, ho phatloha ha Order, Mokhoa oa Nako, Nako ea ho lieha, joalo-joalo)
• Lintlha tsa nako ea memori

Sheba lintlha tsa memori ea hau ea kantle ea DDR 'me u hlophise DDR Controller ho tsamaisana le litlhoko tsa memori ea hau ea kantle ea DDR.
Bakeng sa lintlha tse mabapi le tlhophiso ea DDR, sheba ho SmartFusion2 MSS DDR Configuration User Guide.
SERDESIF Configuration
Tobetsa habeli boloko ba SERDES ka har'a seile sa SmartDesign ho bula Configurator ho lokisa SERDES (Setšoantšo sa 3-1). O ka reka kantle ho naha ena ea boleng kapa oa sebelisa setlhophiso sa SEDES ho kenya li-parameter tsa PCIe kapa EPCS ea hau, 'me boleng ba rejisetara e balloa uena ka bo eona. Bakeng sa lintlha, sheba ho Tataiso ea mosebelisi ea SERDES Configurator.Setšoantšo sa 3-1 • High Speed ​​Serial Interface Configurator
Ho theha FPGA Design Initialization Sub-System
Ho qala li-block tsa DDR le SERDESIF, u tlameha ho theha tsamaiso e nyane ea ho qala lesela la FPGA. Sesebelisoa sa FPGA sa ho qala lesela se tsamaisa data ho tloha ho Cortex-M3 ho ea ho lirekoto tsa tlhophiso tsa DDR le SERDESIF, e laola tatellano e hlokahalang hore li-block tsena li sebetse le matšoao ha li-blocks li se li loketse ho buisana le moralo oa hau kaofela. Ho theha subsystem ea ho qala, o tlameha ho:

• Lokisa FIC_2 ka har'a MSS
• Kenya le ho lokisa li-cores tsa CoreConfigP le CoreResetP
• Kenya on-chip 25/50MHz RC oscillator
• Kenya sistimi ea Reset (SYSRESET) macro
• Hokela likarolo tsena ho sehokelo se seng le se seng sa tlhophiso, lioache, litlhophiso le likou tsa senotlolo sa PLL.

MSS FIC_2 APB Configuration
Ho lokisa MSS FIC_2:

1. Bula FIC_2 configurator dialog box ho tswa ho MSS configurator (Figure 3-2).
2. Khetha Qala lisebelisoa tse sebelisang Cortex-M3.
3. Ho ipapisitse le sistimi ea hau, tšoaea lebokose le le leng kapa a mabeli a latelang:
   - MSS DDR
   - Lesela la DDR le/kapa li-block tsa SEDES
4. Tobetsa OK 'me u tsoele pele ho hlahisa MSS (o ka chechisa ketso ena ho fihlela u se u lokiselitse MSS ka botlalo litlhoko tsa moralo oa hau). Likou tsa FIC_2 (FIC_2_APB_MASTER, FIC_2_APB_M_PCLK le FIC_2_APB_M_RESET_N) joale li pepesitsoe ho MSS interface 'me li ka hokeloa ho CoreConfigP le CoreResetP cores.

Setšoantšo sa 3-2 • MSS FIC_2 Configurator

CoreConfigP
Ho lokisa CoreConfigP:

1. Kenya CoreConfigP ho SmartDesign ea hau (hangata moo MSS e kengoang teng).
   Konokono ena e ka fumanoa ho Libero Catalog (tlas'a Peripherals).
2. Tobetsa habeli konokono ho bula configurator.
3. Hlophisa mantlha ho hlakisa hore na ke li-peripheral life tse lokelang ho qalisoa (Setšoantšo sa 3-3)

Setšoantšo sa 3-3 • Lebokose la Puisano la CoreConfigP

CoreResetP
Ho lokisa CoreResetP:

1. Kenya CoreResetP ho SmartDesign ea hau (hangata moo MSS e kentsoeng teng).
   Moko-taba ona o ka fumanoa ho Libero Catalog, tlas'a Peripherals.
2. Tobetsa habeli konokono ka har'a SmartDesign Canvas ho bula Configurator (Setšoantšo sa 3-4).
3. Lokisa mantlha ho:
   - Hlalosa boits'oaro bo bocha ba kantle (EXT_RESET_OUT bo tiisitsoe). Khetha e 'ngoe ho tse' nè:
   o EXT_RESET_OUT ha ho mohla e boleloang
   o EXT_RESET_OUT e tiisitsoe haeba motlakase o setiloe bocha (POWER_ON_RESET_N)
   o EXT_RESET_OUT e tiisitsoe haeba FAB_RESET_N e tiisitsoe
   o EXT_RESET_OUT e tiisitsoe haeba motlakase o setiloe bocha (POWER_ON_RESET_N) kapa FAB_RESET_N e tiisitsoe
   – Hlalosa Sesebediswa Voltage. Boleng bo khethiloeng bo lokela ho lumellana le voltage u khethileng lebokoseng la lipuisano la Litlhophiso tsa Morero oa Libero.
   - Sheba mabokose a nepahetseng ho bontša hore na u sebelisa li-peripherals life moralong oa hau.
   - Hlalosa nako ea ho seta memori ea DDR kantle. Ona ke boleng bo holimo bakeng sa mehopolo eohle ea DDR e sebelisitsoeng ts'ebelisong ea hau (MDDR le FDDR). Sheba database ea morekisi oa memori ea DDR ho hlophisa paramethara ena. 200us ke boleng bo botle ba kamehla bakeng sa mehopolo ea DDR2 le DDR3 e sebetsang ho 200MHz. Ena ke paramente ea bohlokoa haholo ho netefatsa papiso e sebetsang le sistimi e sebetsang ho silicon. Theko e fosahetseng bakeng sa nako ea ho lokisa e ka baka liphoso tsa papiso. Sheba database ea morekisi oa DDR ho lokisa paramethara ena.
   - Bakeng sa block e 'ngoe le e' ngoe ea SERDES moralong oa hau, sheba mabokose a nepahetseng ho bontša hore na:
   o PCIe e sebelisoa
   o Ts'ehetso ea PCIe Hot Reset ea hlokahala
   o Ts'ehetso ea PCIe L2/P2 ea hlokahala

Hlokomela: Haeba u sebelisa 090 die(M2S090) mme moralo oa hau o sebelisa SEDESIF, ha ho hlokahale hore u hlahlobe leha e le efe ea mabokose a latelang a tlhahlobo: 'E sebelisoa bakeng sa PCIe', 'Kenyelletsa tšehetso ea PCIe HotReset' le 'Kenyelletsa tšehetso ea PCIe L2/P2'. Ha o sebedisa sesebediswa sefe kapa sefe seo e seng sa 090 mme o sebedisa boloko e le nngwe kapa ho feta tsa SERDESIF, o lokela ho tshwaya mabokose a mane a tjheke tlasa karolo e nepahetseng ya SERDESIF.
Hlokomela: Bakeng sa lintlha tse mabapi le likhetho tse fumanehang ho setlhophiso sena, sheba ho CoreResetP Handbook.

Setšoantšo sa 3-4 • CoreResetPCConfigurator

25/50MHz Instantiation ea Oscillator
CoreConfigP le CoreResetP li ts'episitsoe ke on-chip 25/50MHz RC oscillator. U tlameha ho kenya Oscillator ea 25/50MHz ebe u e hokahanya le li-cores tsena.

1. Kenya li-cores tsa Chip Oscillators ho SmartDesign ea hau (hangata ke moo MSS e kentsoeng teng). Konokono ena e ka fumanoa ho Libero Catalog tlasa Clock & Management.
2. Lokisa setsi sena e le hore RC oscillator e khanne lesela la FPGA, joalokaha ho bontšitsoe setšoantšong sa 3-5.

Setšoantšo sa 3-5 • Chip Oscillators Configurator

Sistimi ea Reset (SYSRESET) Instantiation
SYSRESET macro e fana ka ts'ebetso ea ho seta boemo ba sesebelisoa molemong oa hau. Letšoao la POWER_ON_RESET_N le tiisitsoe/ha le tiisetsoe neng kapa neng ha chip e matlafatsoa kapa phini ea kantle ea DEVRST_N e tiisitsoe/e hlakisoa (Setšoantšo sa 3-6).
Kenya SYSRESET macro ho SmartDesign ea hau (hangata ke eona moo MSS e kentsoeng teng). Macro ena e ka fumanoa ho Libero Catalogue tlas'a Macro Library.Ha ho tlhophiso ea macro ena e hlokahalang.

Setšoantšo sa 3-6 • SYSRESET Macro

Kakaretso ea Khokahano
Ka mor'a hore u kenye le ho lokisa li-cores tsa MSS, FDDR, SERDESIF, OSC, SYSRESET, CoreConfigP le CoreResetP moralong oa hau, u lokela ho li hokahanya ho theha tsamaiso e nyenyane ea Peripheral Initialization. Ho nolofatsa tlhaloso ea khokahanyo tokomaneng ena, e arotsoe ka APB3 e lumellanang le tsela ea khokahanyo ea data e amanang le CoreConfigP le likhokahano tse amanang le CoreResetP.
Khokahano ea Tsela ea Boitsebiso
Setšoantšo sa 3-7 se bonts'a mokhoa oa ho hokela CoreConfigP ho mats'oao a MSS FIC_2 le likhokahano tsa APB3 tse lumellanang le lipehelo.
Lethathamo la 3-1 • Configuration Data Path Port / BIF Connections

TSOA Port/Bus Interface (BIF)/ Karolo	TSA Port/Bus Interface (BIF)/Component
APB S PRESET N/ CoreConfigP	APB S PRESET N/ SDIF<0/1/2/3>	APB S PRESET N/ FDDR	MDDR APB S PRESE TN/MSS
APB S PCLK/ CoreConfigP	APB S PCLK/SDIF	APB S PCLK/FDDR	MDDR APB S POLK/ MSS
MDDR APBslave/ CoreConfig			MDDR APB LEKHOBA (BIF)/MSS
SDIF<0/1/2/ 3> APBmslave/Config	APB LEKHOBA (BIF)/ SDIF<0/1/2/3>
FDDR APB makhoba		APB LEKHOBA (BIF)/ FDDR
FIC 2 APBmmaster/ CoreConfigP			FIC 2 APB MASTER/ MSS

Setšoantšo sa 3-7 • FIC_2 APB3 Sub-System Khokahano

Lioache le Seta Botjha Khokelo
Setšoantšo sa 3-8 se bonts'a mokhoa oa ho hokahanya CoreResetP ho mehloli ea ho tsosolosa e ka ntle le matšoao a mantlha a reset ea peripherals. E boetse e bonts'a mokhoa oa ho hokela CoreResetP ho matšoao a boemo ba ho hokahanya oache ea lioache (matšoao a senotlolo sa PLL). Ntle le moo, e bonts'a hore na CoreConfigP le CoreResetP li hokahane joang.

Setšoantšo sa 3-8 • Core SF2Reset Khokahano ea Sub-System

Ho theha le ho hlophisa ts'ebeliso ea Firmware

Ha o romela firmware ho tloha LiberoSoC (Design Flow Window> Export Firmware> Export Firmware), Libero e hlahisa tse latelang. files ho /firmware/drivers_config/ sys_config foldara:

• sys_config.c - E na le libopeho tsa data tse bolokang boleng ba lirejisete tsa peripheral.
• sys_config.h - E na le lipolelo tsa #define tse hlalosang hore na ke lisebelisoa life tse sebelisoang moahong 'me li hloka ho qalisoa.
• sys_config_mddr_define.h - E na le data ea tlhophiso ea taolo ea MDDR e kentsoeng lebokoseng la puisano la Registar Configuration.
• sys_config_fddr_define.h - E na le data ea tlhophiso ea taolo ea FDDR e kentsoeng lebokoseng la puisano la Registas Configuration.
• sys_config_mss_clocks.h – Sena file e na le maqhubu a lioache a MSS joalo ka ha a hlalositsoe ho setlhophiso sa MSS CCC. Maqhubu ana a sebelisoa ke khoutu ea CMSIS ho fana ka tlhahisoleseding e nepahetseng ea oache ho bakhanni ba bangata ba MSS ba tlamehang ho ba le phihlello ea maqhubu a bona a Peripheral Clock (PCLK) (mohlala, li-divisor tsa MSS UART baud rate ke ts'ebetso ea sekhahla sa baud le frequency ea PCLK. ).
• sys_config_SERDESIF_ .c – E na le SERDESIF_ Ngolisa lintlha tsa tlhophiso tse fanoeng nakong ea SEDESIF_ block configuration pōpong ea moralo.
• sys_config_SERDESIF_ .h - E na le liphatlalatso tsa #define tse hlalosang palo ea li-pair tsa tlhophiso ea ngoliso le nomoro ea lane e lokelang ho etsoa bakeng sa PMA_READY (feela ka mokhoa oa PCIe).

Tsena files lia hlokahala hore khoutu ea CMSIS e bokelle hantle 'me e be le tlhahisoleseling mabapi le moralo oa hau oa hajoale, ho kenyeletsoa data ea tlhophiso ea peripheral le tlhaiso-leseling ea lioache tsa MSS.
Se ke oa hlophisa tsena files ka letsoho; li bōpiloe ho lihlopha tse tsamaellanang tsa likarolo / peripheral nako le nako ha lisebelisoa tsa SmartDesign tse nang le lisebelisoa tse fapaneng li hlahisoa. Haeba liphetoho leha e le life li etsoa ho data ea tlhophiso ea leha e le efe ea peripherals, o hloka ho romela hape merero ea firmware e le hore firmware e nchafalitsoeng. files (sheba lenane le ka holimo) li romelloa kantle ho naha ho ea / firmware/drivers_config/sys_config foldara.
Ha o romella firmware, Libero SoC e theha merero ea firmware: laebrari moo moralo oa hau o hlophisitsoeng teng files le bakhanni ba hlophisoa.
Haeba u sheba morero oa Create Lebokose la ho hlahloba ha o romela firmware, ho entsoe projeke ea software ea SoftConsole/IAR/Keil ho tšoara morero oa kopo moo o ka hlophisang main.c le mosebelisi C/H files. Bula projeke ea SoftConSole/IAR/Keil ho bokella khoutu ea CMSIS ka nepo le ho etsa hore sesebelisoa sa hau sa firmware se lokisoe hantle hore se tsamaisane le moralo oa hau oa thepa.

BFM Files E Sebelisitsoe Bakeng sa ho Etsisa Moralo

Ha o hlahisa lisebelisoa tsa SmartDesign tse nang le lisebelisoa tse amanang le moralo oa hau, ketsiso files e tsamaellanang le peripherals fapaneng ba generated ka / directory ea mohlala:

• teko.bfm - BFM ea boemo bo holimo file e qala ho etsoa nakong ea papiso efe kapa efe e sebelisang processor ea SmartFusion2 MSS Cortex-M3. E etsa peripheral_init.bfm le user.bfm, ka tatellano eo.
• MDDR_init.bfm - Haeba moralo oa hau o sebelisa MDDR, Libero e hlahisa sena file; e na le litaelo tsa ho ngola tsa BFM tse etsisang mongolo oa data ea rejisetara ea tlhophiso ea MSS DDR eo u e kentseng (o sebelisa lebokose la lipuisano la Edit Registers kapa ho MSS_MDDR GUI) lirejiseteng tsa MSS DDR Controller.
• FDDR_init.bfm - Haeba moralo oa hau o sebelisa FDDR, Libero e hlahisa sena file; e na le litaelo tsa ho ngola tsa BFM tse etsisang mongolo oa data ea Rejisetara ea tlhophiso ea Lesela la DDR eo u e kentseng (o sebelisa lebokose la lipuisano la Edit Registers kapa ho FDDR GUI) lirejiseteng tsa Fabric DDR Controller.
• SEDESIF_ _init.bfm - Haeba moralo oa hau o sebelisa li-block tsa SERDESIF tse le 'ngoe kapa ho feta, Libero e hlahisa sena file bakeng sa e 'ngoe le e 'ngoe ea SEDESIF_ li-blocks tse sebelisitsoeng; e na le litaelo tsa ho ngola tsa BFM tse etsisang sengoloa sa data ea SERDESIF configuration registering eo u e kentseng (u sebelisa lebokose la lipuisano la Edit Registers kapa ho SERDESIF_ GUI) ho SERDESIF_ diresetara. Haeba block ea SERDESIF e hlophisoa joalo ka PCIe, sena file e boetse e na le lipolelo tse ling tsa #define tse laolang ts'ebetso ea mekhahlelo ea tlhophiso ea 2 ka tatellano e phethahetseng.
• mosebedisi.bfm - E na le litaelo tsa basebelisi. Litaelo tsena li etsoa ka mor'a hore peripheral_init.bfm e phethe. Fetola sena file ho kenya litaelo tsa hau tsa BFM.
• SERDESIF_ _mosebelisi.bfm - E na le litaelo tsa basebelisi. Fetola sena file ho kenya litaelo tsa hau tsa BFM. Sebelisa sena haeba u lokiselitse SEDESIF_ thibela ka mokhoa oa ho etsisa oa BFM PCIe hape e le setsebi sa AXI/AHBLite. Haeba u hlophisitse SEDESIF_ thibela ka mokhoa oa papiso ea RTL, u ke ke ua hloka sena file.

Ha o kopa ketsiso nako le nako, ketsiso e latelang e 'meli files li bopiloe bocha ho / directory ea ketsiso e nang le litaba tse ntlafalitsoeng:

• tsamaiso e nyenyane.bfm - E na le #define statements bakeng sa peripheral e 'ngoe le e 'ngoe e sebelisitsoeng moralong oa hau, e hlalosang karolo e itseng ea peripheral_init.bfm e lokelang ho etsoa e tsamaellanang le peripheral ka 'ngoe.
• operipheral_init.bfm - E na le ts'ebetso ea BFM e etsisang CMSIS:: SystemInit() ts'ebetso e tsamaisoang ho Cortex-M3 pele o kenya ts'ebetso ea mantlha (). E kopitsa lintlha tsa tlhophiso bakeng sa peripheral efe kapa efe e sebelisitsoeng moralong ho lirejisetara tse nepahetseng tsa tlhophiso ebe e emela hore li-peripheral tsohle li be malala-a-laotsoe pele e tiisa hore u ka sebelisa li-peripherals tsena. E phetha MDDR_init.bfm le FDDR_init.bfm.

Ho sebelisa lisebelisoa tsena tse entsoeng files, balaoli ba DDR moralong oa hau ba hlophisoa ka bohona, ba etsisa se ka etsahalang sesebelisoa sa SmartFusion2. U ka fetola user.bfm file ho eketsa litaelo tse hlokahalang ho etsisa moralo oa hau (Cortex-M3 ke eona e ka sehloohong). Litaelo tsena li phethoa ka mor'a hore li-peripheral li qalisoe. Se ke oa fetola test.bfm, subsystem.bfm, peripheral_init.bfm, MDDR_init.bfm, FDDR_init.bfm files le SEDESIF_ _init.bfm files.

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Litokomane / Lisebelisoa

Microsemi SmartFusion2 DDR Controller le Serial High Speed ​​Controller [pdf] Bukana ea Mosebelisi SmartFusion2 DDR Controller le Serial High Speed ​​Controller, SmartFusion2 DDR, Controller le Serial High Speed ​​Controller, High Speed ​​Controller

Litšupiso

• Bukana ea Mosebelisi