SmartFusion2
DDR Controller na Serial High Speed ​​Controller
Usoro mmalite
Ntuziaka onye ọrụ

Okwu mmalite

Mgbe ị na-emepụta ihe eji eme ihe site na iji ngwaọrụ SmartFusion2, ọ bụrụ na ị na-eji otu n'ime ndị na-ahụ maka DDR abụọ (FDDR ma ọ bụ MDDR) ma ọ bụ nke ọ bụla nke Serial High Speed ​​Controller (SERDESIF), ị ga-amalite ịmalite ndekọ nhazi nke ihe mgbochi ndị a na-agba ọsọ tupu oge eruo. enwere ike iji ha mee ihe. Maka example, maka onye na-ahụ maka DDR, ị ga-edozi ọnọdụ DDR (DDR3/DDR2/LPDDR), obosara PHY, ọnọdụ gbawara na ECC.
N'otu aka ahụ, maka ngọngọ SERDESIF ejiri dị ka njedebe PCIe, ị ga-edozirịrị PCIE BAR na windo AXI (ma ọ bụ AHB).
Akwụkwọ a na-akọwa usoro ndị dị mkpa iji mepụta ụdị Libero nke na-amalite na-akpaghị aka onye njikwa DDR na SERDESIF blocks na ike elu. Ọ na-akọwakwa otu esi emepụta koodu firmware site na Libero SOC nke a na-eji na nhazi nhazi agbakwunyere.
A na-ebu ụzọ nye nkọwa zuru ezu nke tiori nke arụmọrụ.
Akụkụ na-esote na-akọwa otu esi emepụta ụdị ihe ahụ site na iji Libero SoC System Builder, ngwá ọrụ dị ike nke na-emepụta ihe ngwọta 'mmalite' maka gị ma ọ bụrụ na ị na-eji DDR ma ọ bụ SERDESIF blocks na nhazi gị.
Akụkụ na-esote na-akọwa otu esi etinye ngwọta 'mmalite' zuru ezu ọnụ na-ejighị SmartFusion2 System Builder. Nke a na-enyere aka ịkọwa ihe ekwesịrị ime ma ọ bụrụ na ịchọghị iji Sistemụ Nrụpụta, ma kọwakwa ihe ngwaọrụ Nrụpụta Sistemụ na-ewepụtara gị n'ezie. Akụkụ a na-ekwu:

• Mepụta data nhazi maka onye njikwa DDR na ndekọ nhazi SERDESIF
• Ihe okike nke mgbagha FPGA chọrọ iji nyefee data nhazi na ndekọ nhazi ASIC dị iche iche

N'ikpeazụ, anyị na-akọwa ihe emepụtara filemetụtara:

• Ịmepụta ngwa ngwa 'initialization' ngwọta.
• Simulation nke imewe maka DDR 'ịmalite' ngwọta.

Maka nkọwa gbasara onye njikwa DDR na ndekọ nhazi SERDESIF, rụtụ aka na Microsemi SmartFusion2 High Speed ​​Serial na DDR Interfaces Guide User.

Ozizi nke Ọrụ

Ngwọta mmalite mmalite nke Peripheral na-eji akụkụ ndị a bụ isi:

• Ọrụ CMSIS SystemInit(), nke na-arụ na Cortex-M3 ma na-ahazi usoro mmalite.
• CoreConfigP dị nro IP isi, nke na-ebido ndekọ nhazi nke akụkụ.
• CoreResetP soft IP core, nke na-ejikwa usoro nrụpụta nke MSS, ndị na-ahụ maka DDR, na ngọngọ SERDESIF.

Usoro mmalite nke mpụta na-arụ ọrụ dị ka ndị a:

1. Mgbe emegharịrị, Cortex-M3 na-arụ ọrụ CMSIS SystemInit(). A na-arụ ọrụ a na-akpaghị aka tupu arụ ọrụ isi () ngwa ahụ.
   A na-ekwupụta akara ngosi CoreResetP MSS_HPMS_READY na mmalite nke usoro mmalite, na-egosi na MSS na akụkụ niile (ma ewezuga MDR) dị njikere maka nkwukọrịta.
2. Ọrụ SystemInit() na-edera data nhazi na ndị na-ahụ maka DDR yana ndekọ nhazi SERDESIF site na bọs MSS FIC_2 APB3. Ejikọtara interface a na isi CoreConfigP dị nro ozugbo na akwa FPGA.
3. Mgbe ahaziri ndekọ niile, ọrụ SystemInit () na-edegara aha njikwa njikwa CoreConfigP iji gosi mmecha nke nhazi nhazi aha; A na-ekwupụtakwa akara ngosi CoreConfigP CONFIG1_DONE na CONIG2_DONE.
   Enwere usoro nhazi ndekọ aha abụọ (CONFIG1 na CONFIG2) dabere na mpụta ejiri na nhazi ahụ.
4. Ọ bụrụ na ejiri otu ma ọ bụ abụọ nke MDR/FDDR mee ihe, ma ọ nweghị nke SERDESIF blocks ejiri mee ihe na nhazi ahụ, enwere naanị otu nhazi nhazi ndekọ aha. Ma akara ngosi CoreConfigP CONFIG1_DONE na CONIG2_DONE ka agbadoro otu n'otu na-enweghị nchere/ igbu oge.
   Ọ bụrụ na ejiri otu ma ọ bụ karịa SERDESIF blocks na-abụghị PCIe mode na-eji na imewe, e nwere nanị otu akụkụ nke aha nhazi. CONFIG1_DONE na CONIG2_DONE na-ekwusi ike otu otu na-enweghị nchere/ igbu oge.
   Ọ bụrụ na-eji otu ma ọ bụ karịa SERDESIF blocks na PCIe mode na-eji na imewe, e nwere abụọ usoro nke aha nhazi. Ekwuputara CONFIG1_DONE ka emechara akụkụ mbụ nke nhazi ndekọ aha. Ahaziri sistemụ SERDESIF na ndekọ okporo ụzọ n'oge a. Ọ bụrụ na ahaziri SERDESIF na ọnọdụ na-abụghị PCIE, CONFIG2_DONE na-egosipụtakwa ozugbo.
5. Usoro nke abụọ nke nhazi ndekọ aha na-esote (ọ bụrụ na ahaziri SERDESIF na ọnọdụ PCIE). Ihe ndị a bụ ihe omume dị iche iche na-eme na nkeji nke abụọ:
   – CoreResetP de-asserts PHY_RESET_N na CORE_RESET_N akara dabara na nke ọ bụla n'ime SERDESIF blocks eji. Ọ na-ekwupụtakwa mgbama mmepụta SDIF_RELEASED mgbe ihe mgbochi SERDESIF akwụsịbeghị. A na-eji akara SDIF_RELEASED a gosi CoreConfigP na isi SERDESIF akwụsịla ma dị njikere maka nhazi ndekọ aha nke abụọ.
   - Ozugbo enwetara akara SDIF_RELEASED, ọrụ SystemInit() na-amalite ntuli aka maka nkwuputa PMA_READY n'okporo ụzọ SERDESIF kwesịrị ekwesị. Ozugbo enwetara PMA_READY, ọrụ SystemInit() ahaziri/dere nke abụọ nke SERDESIF rejista (PCIIE registers).
6. Mgbe ahaziri akwụkwọ ndekọ PCIE niile, ọrụ SystemInit () na-ede akwụkwọ ndekọ aha njikwa CoreConfigP iji gosi mmecha nke usoro nke abụọ nke nhazi aha; akara ngosi mmepụta CoreConfigP CONIG2_DONE ka etinyeziri ya.
7. Ewezuga nkwuputa mgbaàmà/de-nkwuputa ndị a dị n'elu, CoreResetP na-ejikwa mmalite nke ngọngọ dị iche iche site na ịrụ ọrụ ndị a:
   - Wepụ nrụpụta ntọala FDDR isi
   - Wepụ SERDESIF na-egbochi nrụpụta PHY na CORE
   - Nleba anya nke mgbaama mkpọchi FDDR PLL (FPLL). Ọ ga-abụrịrị na akpọchiri FPLL iji kwe nkwa na interface data FDDR AXI/AHBlite yana akwa FPGA nwere ike ịkparịta ụka nke ọma.
   - Nleba anya nke SERDESIF block PLL (SPLL) mgbaama mkpọchi. Ọ ga-abụrịrị na akpọchiri SPLL iji kwe nkwa na SERDESIF na-egbochi AXI/AHBlite interface (PCIe mode) ma ọ bụ interface XAUI nwere ike iji akwa FPGA kpakọrịta nke ọma.
   - Ichere ka ncheta DDR dị n'èzí dozie ma dịrị njikere ịnweta ndị na-ahụ maka DDR.
8. Mgbe akụkụ niile mechachara mmalite ha, CoreResetP na-ekwupụta akara INIT_DONE; A na-ekwupụta ndekọ aha ime CoreConfigP INIT_DONE.
   Ọ bụrụ na ejiri otu ma ọ bụ abụọ nke MDR/FDDR mee ihe, na oge mmalite DDR ruru, CoreResetP mmepụta akara DDR_READY na-ekwupụta. Enwere ike nyochaa nkwupụta nke mgbaama a DDR_READY dị ka ihe na-egosi na DDR (MDDR/FDDR) dị njikere maka nkwurịta okwu.
   Ọ bụrụ na ejiri otu SERDESIF blocks ma ọ bụ karịa, na usoro nke abụọ nke nhazi ndekọ aha agwụla nke ọma, CoreResetP mmepụta mgbaama SDIF_READY ga-ekwenye. Enwere ike nyochaa nkwupụta nke mgbaama a SDIF_READY dị ka ihe na-egosi na mgbochi SERDESIF niile adịla njikere maka nkwurịta okwu.
9. Ọrụ SystemInit(), nke nọ na-eche INIT_DONE ka ekwupụta ya, mechaa, ma arụkwa ọrụ isi () nke ngwa ahụ. N'oge ahụ, ebidola ndị njikwa DDR niile na SERDESIF blocks, yana ngwa ngwa ngwa na mgbagha FPGA nwere ike soro ha kparịta ụka.

Usoro akọwara n'ime akwụkwọ a dabere na Cortex-M3 na-eme usoro mmalite dị ka akụkụ nke koodu mmalite sistemụ arụrụ tupu ọrụ isi () ngwa ahụ.
Hụ eserese ngosi na eserese 1-1, eserese 1-2 na eserese 1-3 maka usoro mmalite nke FDDR/MDDR, SEREDES (ụdị na-abụghị PCIe) na SERDES (ụdị PCIe).
Onyonyo 1-4 na-egosi eserese oge mmalite nke dị n'akụkụ.

Ọgụgụ 1-3 • SERDESIF (PCIe) Chart mmalite mmalite
Usoro mmalite nke akọwara na akwụkwọ a chọrọ ka ị na-agba Cortex-M3 n'oge usoro mmalite, ọ bụrụgodị na ị naghị eme atụmatụ ịme koodu ọ bụla na Cortex-M3. Ị ga-emepụta ngwa ngwa ngwa ngwa na-adịghị eme ihe ọ bụla (akara aka dị mfe, maka example) na ibu nke enwere ike ime na agbakwunyere Non Volatile Memory (eNVM) yabụ na-ebido ndị na-ahụ maka DDR na ihe mgbochi SERDESIF mgbe akpụkpọ ụkwụ Cortex-M3.

Iji Ihe Nrụpụta Sistemu Mepụta Nhazi Iji DDR na SERDESIF Blocks

SmartFusion2 Sistemụ Nrụpụta bụ ngwa nrụpụta siri ike nke na-enyere gị aka ijide ihe ị chọrọ n'ọkwa sistemụ wee mepụta atụmatụ na-emejuputa ihe ndị ahụ. Ọrụ dị oke mkpa nke Onye Nrụpụta Sistemụ bụ imepụta akpaka nke sistemu ihe mmalite nke Peripheral. "Iji SmartDesign iji Mepụta Nhazi Iji DDR na SERDESIF Blocks" na ibe 17 na-akọwa n'ụzọ zuru ezu otu esi emepụta ngwọta dị otú ahụ na-enweghị Onye Nrụpụta Sistemu.
Ọ bụrụ na ị na-eji Sistemụ Nrụpụta, ị ga-arụrịrị ọrụ ndị a iji mepụta atụmatụ na-ebido ndị na-ahụ maka DDR gị na ihe mgbochi SERDESIF na ike elu:

1. Na ibe njirimara ngwaọrụ (Njirimara 2-1), kọwapụta ndị njikwa DDR ejiri yana ole SERDESIF blocks ejiri mee ihe na imewe gị.
2. Na ibe ebe nchekwa, ezipụta ụdị DDR (DDR2/DDR3/LPDDR) yana data nhazi maka ebe nchekwa DDR gị. Lee ngalaba ebe nchekwa maka nkọwa.
3. Na ibe Peripherals, tinye ndị isi akwa ahaziri dị ka AHBlite/AXI na Fabric DDR Subsystem na/ma ọ bụ MSS DDR FIC Subsystem (nhọrọ).
4. Na ibe Ntọala elekere, kọwapụta ugboro elekere maka sistemụ sistemụ DDR.
5. Mezue nkọwapụta imewe gị wee pịa Mechaa. Nke a na-ebute ihe nrụpụta Sistemụ mepụtara, gụnyere mgbagha dị mkpa maka ngwọta 'mmalite'.
6. Ọ bụrụ na ị na-eji SERDESIF blocks, ị ga-emerịrị ihe mgbochi SERDESIF n'ime imewe gị wee jikọọ ọdụ ụgbọ mmiri mmalite ha na nke ndị nrụpụta Sistemụ mepụtara.

Ibe Njirimara Ngwaọrụ Onye Nrụpụta Ihe
Na ibe njirimara ngwaọrụ, kọwapụta ndị na-ahụ maka DDR (MDDR na/ma ọ bụ FDDR) na ole SERDESIF blocks ejiri mee ihe n'ime ime gị (Ọgụgụ 2-1).

Ọgụgụ 2-1 • Ibe Njirimara Ngwaọrụ Onye Nrụpụta Sistemu

Ibe ebe nchekwa Sistemu
Iji jiri MSS DDR (MDDR) ma ọ bụ Fabric DDR (FDDR), họrọ Ụdị ebe nchekwa site na ndetu adadata (Foto 2-2).

Foto 2-2 • Ebe nchekwa MSS

Ị ga-emerịrị ya:

1. Họrọ ụdị DDR (DDR2, DDR3 ma ọ bụ LPDDR).
2. Kọwaa oge nhazi ebe nchekwa DDR. Gaa na nkọwapụta ebe nchekwa DDR mpụga gị ka ịtọọ oge ntọala ebe nchekwa ziri ezi. Ebe nchekwa DDR nwere ike ghara ibido nke ọma ma ọ bụrụ na edobeghi oge nhazi ebe nchekwa nke ọma.
3. Bubata data nhazi ndekọ aha DDR ma ọ bụ tọọ ebe nchekwa DDR gị. Maka nkọwa, rụtụ aka na Microsemi SmartFusion2 High Speed ​​Serial na DDR Interfaces Guide User.

A na-eji data a iji mepụta ndebanye aha DDR BFM na nhazi ngwa ngwa files dị ka akọwara na "Ịmepụta na Ịchịkọta Ngwa Firmware" na ibe 26 na "BFM Files Eji maka ịmegharị atụmatụ ahụ” na ibe 27. Maka nkọwa zuru ezu na ndekọ nhazi nhazi DDR, rụtụ aka na Microsemi SmartFusion2 High Speed ​​Serial na DDR Interfaces Guide User.
Onye bụbuample nke nhazi file egosiri syntax na eserese 2-3. Aha ndekọ aha eji na nke a file bụ otu ihe ahụ ka akọwara na Microsemi SmartFusion2 High Speed ​​Serial na DDR Interfaces Guide User

Ọgụgụ 2-3 • Nhazi File Syntax Example
Ibe Ihe Nrụpụta Sistemu
Na ibe Peripherals, maka onye na-ahụ maka DDR nke ọ bụla, a na-emepụta sistemu dị iche iche (Fabric DDR Subsystem for FDDR na MSS DDR FIC Subsystem for MDR). Ị nwere ike ịgbakwunye Fabric AMBA Master (ahaziri dị ka AXI/AHBlite) isi na nke ọ bụla n'ime usoro ndị a iji mee ka nna ukwu akwa nweta ndị na-ahụ maka DDR. N'elu ọgbọ, Onye nrụpụta Sistemụ na-ewepụta cores ụgbọ ala na-akpaghị aka (dabere n'ụdị AMBA Master agbakwunyere) wee kpughee nna ukwu BIF nke isi ụgbọ ala na elekere wee tọgharịa pin nke subsystems kwekọrọ (FDDR/MDDR) n'okpuru otu pin kwesịrị ekwesị, na n'elu. Naanị ihe ị ga - eme bụ ijikọ BIF na cores Fabric Master kwesịrị ekwesị nke ị ga - eme ozugbo na imewe. N'ihe banyere MDR, ọ bụ nhọrọ ịgbakwunye Fabric AMBA Master core na MSS DDR FIC Subsystem; Cortex-M3 bụ nna ukwu ndabara na sistemụ ala a. Onyonyo 2-4 na-egosi ibe Peripherals Sistemu.

Ọgụgụ 2-4 • Ibe Ihe Nrụpụta Sistemu

Ibe Ntọala elekere Sistemu
Na ibe Ntọala elekere, maka onye na-ahụ maka DDR ọ bụla, ị ga-ederịrị usoro elekere nke metụtara sistemụ DDR (MDDR na/ma ọ bụ FDDR) ọ bụla.
Maka MDR, ị ga-ezipụta:

• MDR_CLK - Elekere a na-ekpebi oge ọrụ nke DDR Controller na kwesịrị dakọtara ugboro elekere ịchọrọ ka ebe nchekwa DDR mpụga gị na-agba ọsọ. A kọwapụtara elekere a dị ka otutu nke M3_CLK (Cortex-M3 na MSS Main Clock, Figure 2-5). MDR_CLK ga-enwerịrị ihe na-erughị 333 MHz.
• DDR_FIC_CLK - Ọ bụrụ na ị họrọla ịnweta MDR site na akwa FPGA, ịkwesịrị ịkọwapụta DDR_FIC_CLK. A kọwapụtara ugboro elekere a dị ka oke nke MDDR_CLK ma kwekọọ na ugboro nke sistemụ FPGA na-abanye na MDR na-agba ọsọ.

Ọgụgụ 2-5 • Cortex-M3 na MSS Isi elekere; Oge MDR

Maka FDDR, ị ga-ezipụta:

• FDDR_CLK - Na-ekpebi oge ọrụ nke DDR Controller ma kwekọọ na elekere elekere nke ịchọrọ ka ebe nchekwa DDR mpụga gị na-agba. Rịba ama na a kọwapụtara elekere a dị ka ọnụọgụ nke M3_CLK (MSS na Cortex-M3 elekere, eserese 2-5). FDDR_CLK ga-abụrịrị n'ime 20 MHz na 333 MHz.
• FDDR_SUBSYSTEM_CLK - A na-akọwa ugboro elekere a dị ka oke nke FDDR_CLK ma kwekọọ ugboro ugboro nke sistemụ FPGA nke na-abanye na FDDR na-agba ọsọ.

Onyonyo 2-6 • Akwa DDR Elekere
Nhazi SERDESIF
A naghị ewepụta ihe mgbochi SERDESIF n'ụdị nrụpụta Sistemụ Nrụpụta. Agbanyeghị, maka ihe mgbochi SERDESIF niile, akara mmalite dị na interface nke isi ihe nrụpụta sistemụ ma nwee ike jikọọ ya na cores SERDESIF na ọkwa ọkwa ọzọ, dị ka egosiri na eserese 2-7.Ọgụgụ 2-7 • SERDESIF Peripheral Initialization Connectivity
N'otu aka ahụ na ndekọ nhazi DDR, ngọngọ SERDES ọ bụla nwekwara ndekọ nhazi nke a ga-ebunye n'oge ọ na-agba ọsọ. Ị nwere ike ibubata ụkpụrụ ndebanye aha ndị a ma ọ bụ jiri High Speed ​​​​Serial Interface Configurator (Onyonyo 2-8) ịbanye PCIe ma ọ bụ EPCS paramita gị na ụkpụrụ ndekọ aha na-agbakọ ozugbo maka gị. Maka nkọwa, rụtụ aka na Ntuziaka onye ọrụ SERDES Configurator.Foto 2-8 • Ọsọ Ọsọ Oghere Usoro Nhazi Interface
Ozugbo i jikọtara echiche onye ọrụ gị na ngọngọ Sistemụ Nrụpụta na ngọngọ SERDES, ị nwere ike iwepụta ọkwa SmartDesign gị kachasị elu. Nke a na-emepụta HDL na BFM niile files ndị dị mkpa iji mejuputa na simulate gị imewe. Ị nwere ike ịga n'ihu na-aga n'ihu na Flow Design.

Iji SmartDesign iji Mepụta Nhazi Iji DDR na SERDESIF Blocks

Akụkụ a na-akọwa otu esi etinye ngwọta 'mmalite' zuru ezu ọnụ na-ejighị SmartFusion2 System Builder. Ebumnuche bụ inyere gị aka ịghọta ihe ị ga-eme ma ọ bụrụ na ịchọghị iji Sistemụ Nrụpụta. Akụkụ a na-akọwakwa ihe ngwa Sistemụ Nrụpụta na-ewepụtara gị n'ezie. Akụkụ a na-akọwa otu esi eme:

• Tinye data nhazi maka onye njikwa DDR yana ndekọ nhazi SERDESIF.
• Mee ngwa ngwa ma jikọọ Cores Fabric achọrọ iji nyefee data nhazi na ndị na-ahụ maka DDR na ndekọ nhazi SERDESIF.

Nhazi njikwa DDR
A ga-ahazirịrị ndị na-ahụ maka MSS DDR (MDDR) na Fabric DDR (FDDR) n'ike n'ike (n'oge ọ na-agba ọsọ) iji kwekọọ na nhazi ebe nchekwa DDR mpụga (ụdịDDR, obosara PHY, ọnọdụ mgbawa, ECC, wdg). Edere data etinyere na nhazi MDR/FDDR na ndekọ nhazi njikwa DDR site na ọrụ CMSIS SystemInit(). Onye nhazi ahụ nwere taabụ atọ dị iche iche maka itinye ụdị data nhazi dị iche iche:

• Data izugbe (Ụdị DDR, obosara data, ugboro elekere, ECC, Interface Fabric, Strength Drive)
• Data mmalite mmalite ebe nchekwa ( Ogologo mgbawa, usoro mgbawa, ọnọdụ oge, nkwụsị, wdg)
• Data oge ebe nchekwa

Rụtụ aka na nkọwapụta nke ebe nchekwa DDR mpụga gị wee hazie DDR Controller ka ọ dabara ihe achọrọ nke ebe nchekwa DDR mpụga gị.
Maka nkọwa gbasara nhazi DDR, rụtụ aka na SmartFusion2 MSS DDR ntuziaka onye ọrụ nhazi.
Nhazi SERDESIF
Pịa ngọngọ SERDES ugboro abụọ na kanvas SmartDesign ka imepe Configurator ka ịhazi SErdES (Ọnụ ọgụgụ 3-1). Ị nwere ike ibubata ụkpụrụ ndekọ aha ndị a ma ọ bụ jiri SERDES configurator tinye PCIe ma ọ bụ EPCS paramita gị ma na-agbakọ ụkpụrụ ndekọ aha na-akpaghị aka maka gị. Maka nkọwa, rụtụ aka na Ntuziaka onye ọrụ SERDES Configurator.Foto 3-1 • Ọsọ Ọsọ Oghere Usoro Nhazi Interface
Ịmepụta Sub-Sistemụ mbido imewe FPGA
Iji bido ngọngọ DDR na SERDESIF, ị ga-emerịrị sistemụ mmalite na akwa FPGA. Usoro mmalite akwa FPGA na-ebuga data sitere na Cortex-M3 gaa na ndekọ nhazi DDR na SERDESIF, na-ejikwa usoro nrụpụta achọrọ ka ihe mgbochi ndị a rụọ ọrụ yana akara mgbe ihe mgbochi ndị a dị njikere iso ndị ọzọ imewe gị kparịta ụka. Iji mepụta subsystem mmalite, ị ga-:

• Hazie FIC_2 n'ime MSS
• Mee ngwa ngwa ma hazie cores CoreConfigP na CoreResetP
• Mee ngwa ngwa ngwa oscillator 25/50MHz RC
• Mee ngwa nrụpụta sistemụ (SYSRESET) nnukwu
• Jikọọ akụrụngwa ndị a na oghere nhazi akụkụ nke ọ bụla, elekere, nrụpụta na ọdụ ụgbọ mmiri PLL.

MSS FIC_2 APB Nhazi
Iji hazie MSS FIC_2:

1. Mepee igbe okwu nhazi FIC_2 site na nhazi MSS (Ọnọdụ 3-2).
2. Họrọ bido peripherals site na iji Cortex-M3.
3. Dabere na sistemụ gị, lelee otu ma ọ bụ abụọ n'ime igbe nlele ndị a:
   - MSS DDR
   - Ihe nchekwa DDR na / ma ọ bụ SERDES
4. Pịa OK wee gaa n'ihu ịmepụta MSS (ịnwere ike ịkwụsị ọrụ a ruo mgbe ị haziela MSS n'ụzọ zuru ezu na ihe ị chọrọ). Ọdụ ụgbọ mmiri FIC_2 (FIC_2_APB_MASTER, FIC_2_APB_M_PCLK na FIC_2_APB_M_RESET_N) ekpughere ugbu a na interface MSS na enwere ike jikọọ ya na CoreConfigP na CoreResetP.

Ọgụgụ 3-2 • MSS FIC_2 Configurator

CoreConfigP
Iji hazie CoreConfigP:

1. Tinye CoreConfigP ngwa ngwa n'ime SmartDesign gị (nke a na-ahụkarị MSS ozugbo).
   Enwere ike ịchọta isi a na katalọgụ Libero (n'okpuru Peripherals).
2. Pịa isi ugboro abụọ iji mepee nhazi.
3. Hazie isi iji kọwapụta mpụta mpụta kwesịrị ibido (Fig 3-3)

Ọgụgụ 3-3 • Igbe mkparịta ụka CoreConfigP

CoreResetP
Iji hazie CoreResetP:

1. Mee ngwa ngwa CoreResetP n'ime SmartDesign gị (nke a na-ahụkarị MSS ozugbo).
   Enwere ike ịchọta isi a na katalọgụ Libero, n'okpuru Peripherals.
2. Pịa isi ugboro abụọ n'ime SmartDesign Canvas ka imepe Configurator (Figure 3-4).
3. Hazie isi ka ọ bụrụ:
   - Ezipụta omume nrụpụta mpụga (EXT_RESET_OUT kwuputara). Họrọ otu n'ime nhọrọ anọ:
   o EXT_RESET_OUT anaghị ekwuputa ya
   o EXT_RESET_OUT ka agbadoro ma ọ bụrụ na agbanyere nrụpụta ike (POWER_ON_RESET_N)
   o EXT_RESET_OUT ka ekwuputara ma ọ bụrụ na agbanyere FAB_RESET_N
   o EXT_RESET_OUT ka agbadoro ma ọ bụrụ na agbanyere nrụpụta ike (POWER_ON_RESET_N) ma ọ bụ FAB_RESET_N
   – Ezipụta ngwaọrụ Voltage. Uru ahọpụtara kwesịrị dabara na voltage ị họọrọ na Libero Project Settings dialog igbe.
   - Lelee igbe nlele kwesịrị ekwesị iji gosi akụkụ ndị ị na-eji na imewe gị.
   - Ezipụta oge ntọala ebe nchekwa DDR mpụga. Nke a bụ uru kachasị maka ncheta DDR niile ejiri na ngwa gị (MDDR na FDDR). Rụtụ aka na mpempe akwụkwọ data onye na-ere ebe nchekwa DDR ka ị hazie oke a. 200us bụ ezigbo uru ndabere maka DDR2 na DDR3 na-agba ọsọ na 200MHz. Nke a bụ oke dị oke mkpa iji kwe nkwa ịme anwansị na-arụ ọrụ yana sistemụ arụ ọrụ na silicon. Uru ezighi ezi maka oge nhazi nwere ike bute mperi simulation. Rụtụ aka na akwụkwọ data onye na-ere ebe nchekwa DDR iji hazie oke a.
   - Maka ngọngọ SErdES ọ bụla na imewe gị, lelee igbe kwesịrị ekwesị iji gosi ma:
   o PCIe na-eji
   o Nkwado maka PCIe Hot nrụpụta achọrọ
   o Nkwado maka PCIe L2/P2 chọrọ

Mara: Ọ bụrụ na ị na-eji 090 die(M2S090) na imewe gị na-eji SERDESIF, ịgaghị elele igbe nrịbama ọ bụla: 'Eji maka PCIe', 'Gụnye nkwado PCIe HotReset' na 'Tinye nkwado PCIe L2/P2'. Ọ bụrụ na ị na-eji ngwaọrụ ọ bụla na-abụghị 090 ma na-eji otu ma ọ bụ karịa SERDESIF blocks, ị ga-elele igbe nlele anọ n'okpuru ngalaba SERDESIF kwesịrị ekwesị.
Mara: Maka nkọwa gbasara nhọrọ dị gị na nhazi a, rụtụ aka na akwụkwọ ntuziaka CoreResetP.

Ọgụgụ 3-4 • CoreResetPConfigurator

25/50MHz Oscillator Instantiation
CoreConfigP na CoreResetP bụ ihe on-chip 25/50MHz RC oscillator kpuchiri ya. Ị ga-emerịrị Oscillator 25/50MHz wee jikọọ ya na cores ndị a.

1. Wepụta isi ihe mgbawa Chip n'ime SmartDesign gị (nke a na-ahụkarị MSS ozugbo). Enwere ike ịchọta isi a na katalọgụ Libero n'okpuru elekere & njikwa.
2. Hazie isi ihe a ka oscillator RC na-ebugharị akwa FPGA, dịka egosiri na eserese 3-5.

Ọgụgụ 3-5 • Chip Oscillators Configurator

Ntọgharị sistemụ (SYSRESET) ngwa ngwa
Nnukwu SYSRESET na-enye ọrụ nrụpụta ọkwa ngwaọrụ maka imewe gị. A na-ekwuputa akara ngosi POWER_ON_RESET_N mgbe ọ bụla agbanyere mgbawa ma ọ bụ ntụtụ mpụga DEVRST_N kwadoro/ depụta ya (Foto 3-6).
Mee ngwa ngwa SYSRESET n'ime SmartDesign gị (nke a na-ahụkarị MSS ozugbo). Enwere ike ịhụ nnukwu macro a na katalọgụ Libero n'okpuru ọbá akwụkwọ Macro. Ọ nweghị nhazi nnukwu nnukwu a dị mkpa.

Ọgụgụ 3-6 • SYSRESET nnukwu

Njikọta mkpokọta
Mgbe ịmechara ngwa ngwa ma hazie MSS, FDDR, SERDESIF, OSC, SYSRESET, CoreConfigP na CoreResetP n'ime imewe gị, ịkwesịrị ijikọ ha ka ọ bụrụ sistemu Initialization Peripheral. Iji mee ka nkọwa njikọ dị mfe dị na akwụkwọ a, agbajiri ya na njikọ data nhazi nhazi nke APB3 jikọtara ya na njikọ CoreConfigP na CoreResetP.
Njikọ Data Ụzọ nhazi
Ọgụgụ 3-7 na-egosi otu esi ejikọta CoreConfigP na akara ngosi MSS FIC_2 yana oghere 'APB3 na-akwado nhazi nhazi.
Tebụl 3-1 • Nhazi Data Ụzọ Port/njikọ BIF

SITE Interface Port/Bus (BIF) / Akụkụ	TO Interface Port/Bus (BIF)/Component
APB S PRESET N/ CoreConfigP	APB S PRESET N/ SDIF <0/1/2/3>	APB S PRESET N/ FDDR	MDR APB S PRESE TN/MSS
APB S PCLK/CoreConfigP	APB S PCLK/SDIF	APB S PCLK/FDDR	MDR APB S POLK/ MSS
MDR APBmslave/CoreConfig			MDR APB ohu (BIF)/MSS
SDIF <0/1/2/ 3> APBmslave/Config	APB ohu (BIF)/ SDIF <0/1/2/3>
FDDR APBmslave		APB ohu (BIF) / FDDR
FIC 2 APBmmaster/CoreConfigP			FIC 2 APB MASTER/MSS

Ọgụgụ 3-7 • FIC_2 APB3 Njikọta Sistemụ Sistemụ

Elekere ma malitegharịa Njikọta
Ọgụgụ 3-8 na-egosi otu esi ejikọta CoreResetP na isi mmalite nrụpụta mpụga yana mgbama nrụpụta isi nke mpụta. Ọ na-egosikwa otu esi ejikọta CoreResetP na akara ọkwa mmekọrịta elekere (PLL lock signals). Na mgbakwunye, ọ na-egosi ka esi jikọọ CoreConfigP na CoreResetP.

Ọgụgụ 3-8 • Isi SF2Reset Njikọ Njikọ

Ịmepụta na Ịchịkọta Ngwa Firmware

Mgbe ị na-ebupụ ngwa ngwa site na LiberoSoC (Ohere Flow Design> Export Firmware> Export Firmware), Libero na-emepụta ihe ndị a. files n'ime /firmware/drivers_config/sys_config nchekwa:

• sys_config.c - Nwere ihe owuwu data na-ejide ụkpụrụ maka ndekọ mpụta.
• sys_config.h - Nwere okwu #define nke na-akọwapụta akụkụ ndị a na-eji na nhazi ahụ ma ọ dị mkpa ibido ya.
• sys_config_mddr_define.h - Nwere data nhazi njikwa nke MDDR etinyere na igbe mkparịta ụka nhazi ndekọ aha.
• sys_config_fddr_define.h - Nwere data nhazi njikwa FDDR etinyere na igbe mkparịta ụka nhazi ndekọ aha.
• sys_config_mss_clocks.h – Nke a file nwere ugboro elekere MSS dị ka akọwara na nhazi MSS CCC. Koodu CMSIS na-eji ugboro ndị a iji nye ozi elekere ziri ezi nye ọtụtụ ndị ọkwọ ụgbọ ala MSS ga-enwerịrị ike ịnweta elekere Peripheral (PCLK) ha (dịka ọmụmaatụ, MSS UART baud rate divisors bụ ọrụ nke ọnụego baud na ugboro PCLK. ).
• sys_config_SERDESIF_ .c - Nwere SERDESIF_ debanye aha nhazi data enyere n'oge SERDESIF_ ngọngọ nhazi na imewe e kere eke.
• sys_config_SERDESIF_ .h - Nwere nkwupụta #define nke na-akọwapụta ọnụọgụ abụọ nhazi aha aha yana ọnụọgụ ụzọ achọrọ ka a ga-enyocha maka PMA_READY (naanị na ọnọdụ PCIe).

Ndị a files ka achọrọ maka koodu CMSIS iji chịkọta nke ọma ma nwee ozi gbasara imewe gị ugbu a, gụnyere data nhazi mpaghara yana ozi nhazi elekere maka MSS.
Dezie ihe ndị a files aka; A na-emepụta ha na akwụkwọ ndekọ aha / mpaghara kwekọrọ na oge ọ bụla a na-emepụta ihe ndị SmartDesign nwere akụkụ dị iche iche. Ọ bụrụ na emere mgbanwe ọ bụla na data nhazi nke akụkụ ọ bụla, ịkwesịrị ibupụ ọrụ firmware ahụ ka emelitere firmware. files (lee ndepụta dị n'elu) na-ebupụ na / firmware/drivers_config/sys_config nchekwa.
Mgbe ị na-ebupụ ngwa ngwa, Libero SoC na-emepụta ọrụ firmware: ọbá ​​akwụkwọ ebe nhazi nhazi gị files na ndị ọkwọ ụgbọala na-achịkọta.
Ọ bụrụ na ịlele ọrụ Mepụta igbe nrịbama mgbe ị na-ebupụ ngwa ngwa, a na-emepụta SoftConsole/IAR/Keil software iji jide ọrụ ngwa ebe ị nwere ike dezie main.c na onye ọrụ C/H. files. Mepee ọrụ SoftConSole/IAR/Keil iji chịkọta koodu CMSIS nke ọma ma hazie ngwa ngwa ngwa gị nke ọma ka ọ dabara na ngwaike gị.

BFM FileA na-eji maka ịmegharị atụmatụ ahụ

Mgbe ị na-emepụta ihe ndị SmartDesign nwere ihe jikọrọ ya na imewe gị, simulation files kwekọrọ na akụkụ dị iche iche na-emepụta na / ndekọ ndekọ:

• nwale.bfm - BFM dị elu file nke a na-ebu ụzọ gbuo n'oge ịme anwansị ọ bụla na-eme ihe nhazi SmartFusion2 MSS Cortex-M3. Ọ na-eme peripheral_init.bfm na user.bfm, n'usoro ahụ.
• MDR_init.bfm - Ọ bụrụ na imewe gị na-eji MDR, Libero na-emepụta nke a file; o nwere iwu ide BFM nke na-eme ka ọ dee data ndebanye aha nhazi MSS DDR nke ị banyere (iji Dezie dialogbox ma ọ bụ na MSS_MDDR GUI) n'ime ndebanye aha MSS DDR Controller.
• FDDR_init.bfm - Ọ bụrụ na imewe gị na-eji FDDR, Libero na-emepụta nke a file; o nwere iwu ide BFM nke na-eme ka edebanye aha data nhazi Fabric DDR nke ị banyere (iji Dezie dialogbox ma ọ bụ na FDDR GUI) n'ime ndekọ Fabric DDR Controller.
• SERDESIF_ _init.bfm - Ọ bụrụ na imewe gị na-eji otu ma ọ bụ karịa SERDESIF blocks, Libero na-emepụta nke a file maka SERDESIF_ nke ọ bụla ihe mgbochi eji; o nwere iwu ide BFM nke na-eme ka ọ dee data ndekọ aha nhazi SERDESIF nke ị debanyere (iji igbe okwu Dezie Register ma ọ bụ na SERDESIF_ GUI) banye na SERDESIF_ ndebanye aha. Ọ bụrụ na ahaziri ngọngọ SERDESIF dị ka PCIe, nke a file nwekwara ụfọdụ #define nkwupụta na-achịkwa mmezu nke usoro nhazi ndekọ aha abụọ n'usoro zuru oke.
• onye ọrụ.bfm – Nwere iwu onye ọrụ. A na-eme iwu ndị a ka emechara peripheral_init.bfm. Dezie nke a file itinye iwu BFM gị.
• SERDESIF_ _onye ọrụ.bfm – Nwere iwu onye ọrụ. Dezie nke a file itinye iwu BFM gị. Jiri nke a ma ọ bụrụ na ị haziela SERDESIF_ igbochi na BFM PCIe simulation mode yana dị ka onye isi AXI/AHBlite. Ọ bụrụ na ị haziela SERDESIF_ igbochi na RTL mode simulation, ị gaghị achọ nke a file.

Mgbe ị na-akpọ simulation oge ọ bụla, ịme anwansị abụọ ndị a files na-re-kere ka / akwụkwọ ndekọ simulation nwere ọdịnaya emelitere:

• usoro.bfm - Nwere nkwupụta #define maka akụkụ ọ bụla ejiri na imewe gị, nke na-akọwapụta akụkụ nke peripheral_init.bfm ka a ga-egbu nke kwekọrọ na mpaghara ọ bụla.
• operipheral_init.bfm - Nwere usoro BFM nke na-eṅomi CMSIS :: SystemInit () ọrụ na-agba ọsọ na Cortex-M3 tupu ịbanye na isi () usoro. Ọ na-eṅomi data nhazi maka akụkụ ọ bụla ejiri na nhazi ahụ gaa na ndekọ nhazi akụkụ ziri ezi wee chere ka akụkụ niile dị njikere tupu ị kwupụta na ị nwere ike iji akụkụ ndị a. Ọ na-eme MDR_init.bfm na FDDR_init.bfm.

Iji ndị a emepụtara files, a na-ahazi ndị na-ahụ maka DDR na imewe gị na-akpaghị aka, na-eme ka ihe ga-eme na ngwaọrụ SmartFusion2. Ị nwere ike dezie user.bfm file ịgbakwunye iwu ọ bụla achọrọ iji megharịa atụmatụ gị (Cortex-M3 bụ nna ukwu). A na-eme iwu ndị a ka ebidochara ihe ndị a. Edokwala test.bfm, subsystem.bfm, peripheral_init.bfm, MDDR_init.bfm, FDDR_init.bfm files na SERDESIF_ _init.bfm files.

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Microsemi Corporation (NASDAQ: MSCC) na-enye Pọtụfoliyo zuru oke nke ngwọta semiconductor maka: ikuku ikuku, nchekwa na nchekwa; ụlọ ọrụ na nkwukọrịta; na ụlọ ọrụ mmepụta ihe na ahịa ike ọzọ. Ngwaahịa gụnyere arụmọrụ dị elu, ngwa analọg ntụkwasị obi dị elu na ngwaọrụ RF, mgbama agwakọtara yana sekit agbakwunyere RF, SoC nwere ike ịhazi ya, FPGA, yana sistemụ mpaghara zuru oke. Microsemi bụ onye isi na Aliso Viejo, Calif. Mụtakwuo na www.microsemi.com.
© 2014 Microsemi Corporation. Ikike niile echekwabara. Microsemi na akara Microsemi bụ ụghalaahịa nke ụlọ ọrụ Microsemi. Ụghalaahịa niile na akara ọrụ bụ ihe nke ndị nwe ha.

5-02-00384-1/08.14Ụlọ ọrụ Microsemi Corporate
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Microsemi SmartFusion2 DDR Controller na Serial High Speed ​​Controller [pdf] Ntuziaka onye ọrụ SmartFusion2 DDR Controller na Serial High Speed ​​Controller, SmartFusion2 DDR, Controller and Serial High Speed ​​Controller, High Speed ​​Controller.

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