SmartFusion2
Mai Sarrafa DDR da Mai Sarrafa Babban Sauri
Hanyar farawa
Jagorar Mai Amfani

Gabatarwa

Lokacin ƙirƙirar ƙira ta amfani da na'urar SmartFusion2, idan kun yi amfani da ɗaya daga cikin masu sarrafa DDR guda biyu (FDDR ko MDDR) ko kowane shingen Serial High Speed ​​(SERDESIF), dole ne ku fara rajistar daidaitawar waɗannan tubalan a lokacin gudu kafin. ana iya amfani da su. Don misaliample, don mai sarrafa DDR, dole ne ku saita yanayin DDR (DDR3/DDR2/LPDDR), faɗin PHY, yanayin fashewa da ECC.
Hakazalika, don shingen SERDESIF da aka yi amfani da shi azaman ƙarshen PCIe, dole ne ka saita PCIE BAR zuwa taga AXI (ko AHB).
Wannan takaddar tana bayyana matakan da suka wajaba don ƙirƙirar ƙirar Libero wanda ke fara sarrafa DDR ta atomatik da tubalan SERDESIF a sama. Hakanan yana bayyana yadda ake samar da lambar firmware daga Libero SOC wanda ake amfani da shi a cikin ƙirar ƙira.
An ba da cikakken bayanin ka'idar aiki da farko.
Sashe na gaba yana bayanin yadda ake ƙirƙirar irin wannan ƙira ta amfani da Libero SoC System Builder, kayan aikin ƙira mai ƙarfi wanda, a tsakanin sauran fasalulluka, ya haifar muku da mafita na 'farawa' idan kuna amfani da tubalan DDR ko SERDESIF a cikin ƙirar ku.
Sashe na gaba yana bayanin yadda ake haɗa cikakkiyar mafita ta 'farawa' tare ba tare da amfani da SmartFusion2 System Builder ba. Wannan yana taimakawa bayyana abin da ake buƙatar yi idan ba kwa son yin amfani da Mai Gina Tsarin, kuma yana bayyana abin da ainihin kayan aikin Tsarin Tsarin ke haifar muku. Wannan sashe yana magana:

• Ƙirƙirar bayanan daidaitawa don mai sarrafa DDR da rajistar sanyi na SERDESIF
• Ƙirƙirar ma'anar FPGA da ake buƙata don canja wurin bayanan daidaitawa zuwa rijistar daidaitawar ASIC daban-daban

A ƙarshe mun bayyana abubuwan da aka haifar filedangane da:

• Ƙirƙirar maganin 'farawar' firmware.
• Simulation na ƙira don mafita na 'farawa' DDR.

Don cikakkun bayanai game da mai sarrafa DDR da rajista na SERDESIF, koma zuwa Microsemi SmartFusion2 High Speed ​​Serial da DDR Interfaces Jagorar Mai Amfani.

Ka'idar Aiki

Maganin farawa na Peripheral yana amfani da manyan abubuwa masu zuwa:

• Aikin CMSIS SystemInit(), wanda ke gudana akan Cortex-M3 kuma yana tsara tsarin farawa.
• CoreConfigP mai laushi IP core, wanda ke fara yin rajistar daidaitawar mahaɗan.
• CoreResetP soft IP core, wanda ke kula da tsarin sake saiti na MSS, masu sarrafa DDR, da SERDESIF.

Tsarin farawa na gefe yana aiki kamar haka:

1. Bayan sake saiti, Cortex-M3 yana gudanar da aikin CMSIS SystemInit(). Ana aiwatar da wannan aikin ta atomatik kafin aiwatar da babban () aikin aikace-aikacen.
   An tabbatar da siginar fitarwa na CoreResetP MSS_HPMS_READY a farkon tsarin farawa, yana nuna cewa MSS da duk abubuwan da ke kewaye (sai MDDR) a shirye suke don sadarwa.
2. Aikin SystemInit() yana rubuta bayanan daidaitawa zuwa ga masu sarrafa DDR da rijistar saitin SERDESIF ta hanyar bas ɗin MSS FIC_2 APB3. An haɗa wannan haɗin kai zuwa ainihin CoreConfigP mai laushi wanda ke nan take a cikin masana'anta na FPGA.
3. Bayan an daidaita duk rajistar, aikin SystemInit () ya rubuta zuwa ga rajistar sarrafawa na CoreConfigP don nuna ƙarshen lokacin daidaitawar rajista; Ana tabbatar da siginar fitarwa na CoreConfigP CONFIG1_DONE da CONIG2_DONE.
   Akwai matakai biyu na saitin rijista (CONFIG1 da CONFIG2) dangane da abubuwan da aka yi amfani da su a cikin ƙira.
4. Idan an yi amfani da ɗaya ko duka biyu na MDDR/FDDR, kuma babu ɗaya daga cikin tubalan SERDESIF da aka yi amfani da su a cikin ƙira, akwai lokacin daidaitawar rajista ɗaya kawai. Dukkan siginonin fitarwa na CoreConfigP CONFIG1_DONE da CONIG2_DONE ana tabbatar dasu daya bayan daya ba tare da wani jinkiri ba.
   Idan an yi amfani da tubalan SERDESIF ɗaya ko fiye a cikin yanayin da ba na PCIe ba a cikin ƙira, akwai lokaci ɗaya na saitin rajista. CONFIG1_DONE da CONIG2_DONE ana tabbatar da su daya bayan daya ba tare da wani bata lokaci ba.
   Idan ana amfani da tubalan SERDESIF ɗaya ko fiye a cikin yanayin PCIe a cikin ƙira, akwai matakai biyu na daidaitawar rajista. CONFIG1_DONE an tabbatar da shi bayan an kammala matakin farko na daidaita rajista. An tsara tsarin SERDESIF da rajistar layi a wannan lokaci. Idan an saita SERDESIF a yanayin da ba na PCIE ba, ana tabbatar da siginar CONFIG2_DONE nan take.
5. Kashi na biyu na saitin rijista sannan ya biyo baya (idan an saita SERDESIF a yanayin PCIE). Wadannan su ne abubuwan da suka faru a kashi na biyu:
   - CoreResetP yana ƙaddamar da sigina PHY_RESET_N da CORE_RESET_N daidai da kowane tubalan SERDESIF da aka yi amfani da su. Hakanan yana tabbatar da siginar fitarwa SDIF_RELEASED bayan duk tubalan SERDESIF ba su sake saiti ba. Ana amfani da wannan siginar SDIF_RELEASED don nunawa ga CoreConfigP cewa ainihin SERDESIF bai sake saiti ba kuma yana shirye don tsari na biyu na daidaitawar rajista.
   - Da zarar an tabbatar da siginar SDIF_RELEASED, aikin SystemInit() zai fara jefa kuri'a don tabbatar da PMA_READY akan layin SERDESIF da ya dace. Da zarar an tabbatar da PMA_READY, saitin na biyu na rajistar SERDESIF (rejiyoyin PCIE) ana daidaita su/ rubuta ta aikin SystemInit().
6. Bayan an daidaita duk rajistar PCIE, aikin SystemInit () yana rubutawa ga rajistar sarrafawa na CoreConfigP don nuna ƙarshen tsari na biyu na tsarin rajista; an tabbatar da siginar fitarwa na CoreConfigP CONIG2_DONE.
7. Baya ga siginar siginar da ke sama / de-assertions, CoreResetP kuma yana sarrafa farawar tubalan daban-daban ta hanyar aiwatar da ayyuka masu zuwa:
   – De-tabbatar da FDDR core sake saiti
   - Rashin tabbatar da SERDESIF yana toshe PHY da sake saitin CORE
   - Kula da siginar kulle FDDR PLL (FPLL). FPLL dole ne ya kulle don tabbatar da cewa FDDR AXI/AHBlite ke dubawa bayanai da masana'anta na FPGA na iya sadarwa daidai.
   - Kula da siginar kulle SERDESIF block PLL (SPLL). SPLL dole ne ya kulle don tabbatar da cewa SERDESIF yana toshe AXI/AHBlite interface (Yanayin PCIe) ko XAUI na iya sadarwa da kyau tare da masana'anta na FPGA.
   - Jiran ƙwaƙwalwar DDR na waje don daidaitawa kuma a shirye don samun damar masu sarrafa DDR.
8. Lokacin da duk abubuwan da ke kewaye suka gama farawa, CoreResetP yana tabbatar da siginar INIT_DONE; An tabbatar da rijistar ciki na CoreConfigP INIT_DONE.
   Idan an yi amfani da ɗaya ko duka biyu na MDDR/FDDR, kuma lokacin ƙaddamarwar DDR ya kai, an tabbatar da siginar fitarwa na CoreResetP DDR_READY. Tabbatar da wannan siginar DDR_READY za a iya sa ido a matsayin alamar cewa DDR (MDDR/FDDR) a shirye yake don sadarwa.
   Idan aka yi amfani da tubalan SERDESIF ɗaya ko sama da haka, kuma kashi na biyu na tsarin rijistar ya cika cikin nasara, an tabbatar da siginar fitarwa na CoreResetP SDIF_READY. Tabbatar da wannan siginar SDIF_READY za a iya sa ido a matsayin alamar cewa duk tubalan SERDESIF a shirye suke don sadarwa.
9. Aikin SystemInit(), wanda aka dade ana jiran INIT_DONE ya tabbatar, ya cika, kuma ana aiwatar da babban aikin () na aikace-aikacen. A wancan lokacin, duk masu sarrafa DDR da aka yi amfani da su an fara farawa da SERDESIF, kuma aikace-aikacen firmware da dabarar masana'anta na FPGA na iya dogaro da dogaro da su.

Hanyar da aka bayyana a cikin wannan takarda ta dogara da Cortex-M3 aiwatar da tsarin farawa azaman wani ɓangare na lambar ƙaddamar da tsarin da aka aiwatar kafin babban aikin () aikace-aikacen.
Duba Taswirar Tafiya a Hoto na 1-1, Hoto 1-2 da Hoto 1-3 don matakan farawa na FDDR/MDDR, SEREDES(yanayin da ba PCIe ba) da SERDES (yanayin PCIe).
Hoto na 1-4 yana nuna zane-zanen lokacin farawa na gefe.

Hoto 1-3 • SERDESIF (PCIe) Taswirar Farawa
Hanyar ƙaddamarwa da aka kwatanta a cikin wannan takaddar tana buƙatar ka gudanar da Cortex-M3 yayin aiwatar da farawa, koda kuwa ba kwa shirin aiwatar da kowace lamba akan Cortex-M3. Dole ne ku ƙirƙiri ainihin aikace-aikacen firmware wanda ba ya yin komai (madaidaicin madauki, misaliample) da kuma lodin da za'a iya aiwatarwa a cikin Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwaƙwalwa na Ƙaƙwalwa na Ƙaƙa ) don haka an fara farawa da masu sarrafa DDR da SERDESIF lokacin da takalma na Cortex-M3.

Amfani da Mai Gina Tsari don Ƙirƙirar Zane ta Amfani da DDR da SERDESIF Blocks

SmartFusion2 System Builder shine kayan aikin ƙira mai ƙarfi wanda ke taimaka muku kama buƙatun matakin tsarin ku kuma samar da ƙira mai aiwatar da waɗannan buƙatun. Wani muhimmin aiki mai mahimmanci na Mai Gina Tsarin shine ƙirƙirar atomatik na Ƙarƙashin Ƙarƙashin Ƙarƙashin Ƙarfafawa. "Amfani da SmartDesign don Ƙirƙirar Zane ta Amfani da DDR da SERDESIF Blocks" a shafi na 17 ya bayyana dalla-dalla yadda za a ƙirƙiri irin wannan bayani ba tare da Mai Gina Tsarin ba.
Idan kana amfani da System Builder, dole ne ka yi ayyuka masu zuwa don ƙirƙirar ƙira wanda ya fara farawa da masu sarrafa DDR naka da shingen SERDESIF a sama:

1. A cikin Shafi na Siffofin Na'ura (Hoto 2-1), ƙididdige waɗanne masu sarrafa DDR aka yi amfani da su da adadin tubalan SERDESIF da ake amfani da su a ƙirar ku.
2. A cikin shafi na Ƙwaƙwalwar ajiya, ƙididdige nau'in DDR (DDR2/DDR3/LPDDR) da bayanan daidaitawa don ƙwaƙwalwar DDR na waje. Duba sashin Shafin Ƙwaƙwalwar ajiya don cikakkun bayanai.
3. A cikin Peripherals shafi, ƙara masana'anta da aka saita azaman AHBlite/AXI zuwa Fabric DDR Subsystem da/ko MSS DDR FIC Subsystem (na zaɓi).
4. A cikin shafin Saitunan Agogo, saka mitocin agogo don ƙananan tsarin DDR.
5. Kammala ƙayyadaddun ƙirar ku kuma danna Gama. Wannan yana haifar da ƙira mai gina Tsarin Tsarin, gami da dabaru da suka wajaba don maganin 'farawa'.
6. Idan kuna amfani da tubalan SERDESIF, dole ne ku aiwatar da tubalan SERDESIF a cikin ƙirar ku kuma ku haɗa tashar jiragen ruwa na farko zuwa waɗanda aka ƙirƙira na Maginin Tsarin.

Shafin Fasalolin Na'urar Mai Gina Tsarin
A cikin Shafi na Siffofin Na'ura, saka waɗanne masu sarrafa DDR (MDDR da/ko FDDR) ake amfani da su da adadin tubalan SERDESIF da aka yi amfani da su a ƙirar ku (Hoto 2-1).

Hoto 2-1 • Shafi na Na'urar Mai Gina Tsarin

Shafin Maginin Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwaƙwalwa
Don amfani da MSS DDR (MDDR) ko Fabric DDR (FDDR), zaɓi Nau'in Ƙwaƙwalwar ajiya daga jerin abubuwan da aka saukar (Hoto 2-2).

Hoto 2-2 • MSS Ƙwaƙwalwar Ƙwaƙwalwar Waje

Dole ne ku:

1. Zaɓi nau'in DDR (DDR2, DDR3 ko LPDDR).
2. Ƙayyade lokacin daidaita ƙwaƙwalwar ajiyar DDR. Tuntuɓi Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar DDR na waje don saita daidai lokacin saitin ƙwaƙwalwar ajiya. Ƙwaƙwalwar ajiyar DDR na iya gaza farawa daidai idan ba a saita lokacin daidaita ƙwaƙwalwar ajiya daidai ba.
3. Ko dai shigo da bayanan sanyi na rijistar DDR ko saita ma'aunin ƙwaƙwalwar ajiyar DDR na ku. Don cikakkun bayanai, koma zuwa Microsemi SmartFusion2 High Speed ​​Serial da DDR Interfaces Jagorar Mai Amfani.

Ana amfani da wannan bayanan don samar da rajistar DDR BFM da tsarin firmware files kamar yadda aka bayyana a cikin "Ƙirƙirar da Haɗa Aikace-aikacen Firmware" a shafi na 26 da "BFM". Files An yi amfani da shi don Simulating da Zane" a shafi na 27. Don cikakkun bayanai kan rajistar masu sarrafa DDR, koma zuwa Microsemi SmartFusion2 High Speed ​​Serial da DDR Interfaces Jagorar Mai Amfani.
Tsohonample na daidaitawa file An nuna syntax a cikin hoto na 2-3. Sunayen rajista da aka yi amfani da su a cikin wannan file daidai suke da waɗanda aka bayyana a cikin Microsemi SmartFusion2 High Speed ​​Serial da DDR Interfaces Jagorar Mai Amfani

Hoto 2-3 • Kanfigareshan File Syntax Example
Shafin Maginin Tsarin Tsarin
A cikin Peripherals shafi, ga kowane mai sarrafa DDR an ƙirƙiri wani tsarin na daban (Tsarin Fabric DDR na FDDR da MSS DDR FIC Subsystem na MDDR). Kuna iya ƙara Fabric AMBA Master (wanda aka saita azaman AXI/AHBLite) ga kowane ɗayan waɗannan tsarin don ba da damar sarrafa masana'anta zuwa masu sarrafa DDR. A kan tsarawa, Mai Gina Tsarin yana ɗaukar muryoyin bas ta atomatik (dangane da nau'in AMBA Master da aka ƙara) kuma yana fallasa babban BIF na cibiyar bas da agogo da sake saita fil na tsarin da suka dace (FDDR/MDDR) a ƙarƙashin ƙungiyoyin fil masu dacewa, zuwa ga saman. Abin da kawai za ku yi shi ne haɗa BIFs zuwa madaidaitan Fabric Master cores waɗanda za ku iya ɗauka a cikin ƙira. Game da MDDR, zaɓi ne don ƙara Fabric AMBA Master core zuwa MSS DDR FIC Subsystem; Cortex-M3 tsoho master ne akan wannan tsarin ƙasa. Hoto na 2-4 yana nuna Shafi na Ƙirar Mai Gina Tsarin.

Hoto 2-4 • Shafi na Maginin Tsari

Shafin Saitunan Agogon Mai Gina
A cikin shafin Saitunan Agogo, ga kowane mai sarrafa DDR, dole ne ku ƙididdige mitocin agogo masu alaƙa da kowane tsarin DDR (MDDR da/ko FDDR).
Don MDDR, dole ne ku saka:

• MDDR_CLK - Wannan agogon yana ƙayyade mitar aiki na Mai Kula da DDR kuma yakamata ya dace da mitar agogon da kuke fatan ƙwaƙwalwar DDR ɗinku ta waje ta yi aiki. An ayyana wannan agogon azaman maɓalli na M3_CLK (Cortex-M3 da MSS Babban Agogon, Hoto 2-5). Dole ne MDDR_CLK ya kasance ƙasa da 333 MHz.
• DDR_FIC_CLK - Idan kun zaɓi don samun dama ga MDR daga masana'anta na FPGA, kuna buƙatar saka DDR_FIC_CLK. Wannan mitar agogo an ayyana shi azaman rabo na MDDR_CLK kuma yakamata ya dace da mitar da ƙaramin tsarin masana'anta na FPGA wanda ke samun dama ga MDR ke gudana.

Hoto 2-5 • Cortex-M3 da MSS Babban Agogo; Farashin MDR

Don FDDR, dole ne ku saka:

• FDDR_CLK - Yana ƙayyade mitar aiki na Mai Kula da DDR kuma yakamata ya dace da mitar agogo wanda kuke fatan ƙwaƙwalwar DDR ɗinku ta waje ta gudana. Lura cewa an ayyana wannan agogon azaman maɓalli na M3_CLK (Agogon MSS da Cortex-M3, Hoto 2-5). FDDR_CLK dole ne ya kasance tsakanin 20 MHz da 333 MHz.
• FDDR_SUBSYSTEM_CLK - Wannan mitar agogo an bayyana shi azaman rabo na FDDR_CLK kuma yakamata ya dace da mitar da ƙaramin tsarin masana'anta na FPGA da ke shiga FDDR ke gudana.

Hoto 2-6 • Fabric DDR Clocks
Kanfigareshan SERDESIF
Tubalan SERDESIF ba a nan take ba a cikin ƙirar da aka ƙirƙiro na Maginin Tsarin. Koyaya, ga duk shingen SERDESIF, ana samun siginar farawa a mahaɗin Tsarin Tsarin Tsarin Tsarin kuma ana iya haɗa su da muryoyin SERDESIF a matakin matsayi na gaba, kamar yadda aka nuna a Hoto na 2-7.Hoto 2-7 • SERDESIF Haɗin Farawa Na Wuta
Hakazalika da rijistar daidaitawar DDR, kowane shingen SERDES shima yana da rajistar daidaitawa waɗanda dole ne a loda su a lokacin aiki. Za ka iya ko dai shigo da waɗannan ƙimar rijistar ko amfani da Babban Mai Haɗawa Serial Interface Configurator (Hoto 2-8) don shigar da sigogi na PCIe ko EPCS kuma ana ƙididdige ƙimar rajista ta atomatik gare ku. Don cikakkun bayanai, koma zuwa SERDES Jagorar Mai Amfani Kanfigurator.Hoto 2-8 • Babban Gudun Serial Interface Configurator
Da zarar kun haɗa dabarar mai amfani da ku tare da toshe mai ginawa da kuma shingen SERDES, zaku iya samar da babban matakin SmartDesign. Wannan yana haifar da duk HDL da BFM files waɗanda suke da mahimmanci don aiwatarwa da kwaikwayi ƙirar ku. Sannan zaku iya ci gaba da sauran Tsarin Zane.

Amfani da SmartDesign don Ƙirƙirar Zane ta Amfani da DDR da SERDESIF Blocks

Wannan sashe yana bayyana yadda ake haɗa cikakkiyar mafita ta 'farawa' tare ba tare da amfani da SmartFusion2 System Builder ba. Manufar ita ce ta taimaka muku fahimtar abin da dole ne ku yi idan ba ku son amfani da Mai Gina Tsarin. Wannan sashe kuma yana bayyana abin da ainihin kayan aikin Mai Gina Tsarin ke haifar muku. Wannan sashe yana bayyana yadda ake:

• Shigar da bayanan daidaitawa don mai sarrafa DDR da rajistar sanyi na SERDESIF.
• Ƙaddara kuma haɗa Ƙwayoyin Fabric da ake buƙata don canja wurin bayanan sanyi zuwa masu kula da DDR da rajistar sanyi na SERDESIF.

DDR Controller Kanfigareshan
Dole ne a daidaita masu sarrafa MSS DDR (MDDR) da Fabric DDR (FDDR) da ƙarfi (a lokacin aiki) don dacewa da buƙatun ƙirar ƙwaƙwalwar DDR na waje (yanayin DDR, faɗin PHY, yanayin fashe, ECC, da sauransu). Bayanan da aka shigar a cikin na'urar daidaitawa ta MDDR/FDDR an rubuta su zuwa ga rijistar daidaitawar mai sarrafa DDR ta aikin CMSIS SystemInit(). Configurator yana da shafuka daban-daban guda uku don shigar da bayanan daidaitawa daban-daban:

• Gabaɗaya bayanan (Yanayin DDR, Faɗin Bayanai, Mitar Agogo, ECC, Fabric Interface, Ƙarfin Tuƙi)
• Bayanan Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwa)
• Bayanan Lokacin Ƙwaƙwalwa

Koma zuwa ƙayyadaddun ƙwaƙwalwar ajiyar DDR ɗin ku na waje kuma saita Mai Kula da DDR don dacewa da buƙatun ƙwaƙwalwar DDR ɗin ku na waje.
Don cikakkun bayanai kan daidaitawar DDR, koma zuwa SmartFusion2 MSS DDR Jagorar Kanfigareshan Mai Amfani.
Kanfigareshan SERDESIF
Danna maɓallin SERDES sau biyu a cikin zane na SmartDesign don buɗe Configurator don daidaita SERDES (Hoto 3-1). Kuna iya shigo da waɗannan ƙimar rijistar ko amfani da daidaitawar SERDES don shigar da sigogi na PCIe ko EPCS kuma ana ƙididdige ƙimar rajista ta atomatik a gare ku. Don cikakkun bayanai, koma zuwa SERDES Jagorar Mai Amfani Kanfigurator.Hoto 3-1 • Babban Gudun Serial Interface Configurator
Ƙirƙirar Ƙirƙirar Ƙirƙirar Ƙirƙirar Ƙirƙirar Ƙirƙirar Ƙirƙirar FPGA
Don fara tubalan DDR da SERDESIF, dole ne ku ƙirƙiri tsarin ƙaddamarwa a cikin masana'antar FPGA. Ƙarƙashin ƙaddamar da masana'anta na FPGA yana motsa bayanai daga Cortex-M3 zuwa DDR da SERDESIF rijistar daidaitawa, yana sarrafa jerin sake saiti da ake buƙata don waɗannan tubalan suyi aiki da sigina lokacin da waɗannan tubalan ke shirye don sadarwa tare da sauran ƙirar ku. Don ƙirƙirar tsarin ƙaddamarwa, dole ne ku:

• Sanya FIC_2 a cikin MSS
• Nan take kuma saita CoreConfigP da CoreResetP
• Ƙaddamar da kan-guntu 25/50MHz RC oscillator
• Ƙaddamar da Sake saitin Tsarin (SYSRESET) macro
• Haɗa waɗannan abubuwan haɗin zuwa kowane mahalli na daidaitawa, agogo, sake saiti da tashoshin kulle PLL.

MSS FIC_2 Kanfigareshan APB
Don saita MSS FIC_2:

1. Bude akwatin maganganu na saitin FIC_2 daga mai saita MSS (Hoto 3-2).
2. Zaɓi Ƙaddamar da kayan aiki ta amfani da Cortex-M3.
3. Dangane da tsarin ku, duba ɗaya ko duka waɗannan akwatuna masu zuwa:
   - MSS DDR
   - Fabric DDR da/ko Tubalan SERDES
4. Danna Ok kuma ci gaba don samar da MSS (zaka iya jinkirta wannan aikin har sai kun daidaita MSS zuwa abubuwan da kuke buƙata). Tashar jiragen ruwa na FIC_2 (FIC_2_APB_MASTER, FIC_2_APB_M_PCLK da FIC_2_APB_M_RESET_N) yanzu an fallasa su a wurin MSS kuma ana iya haɗa su da CoreConfigP da CoreResetP.

Hoto 3-2 • MSS FIC_2 Configurator

CoreConfigP
Don saita CoreConfigP:

1. Nan take CoreConfigP cikin SmartDesign ɗin ku (yawanci inda MSS ke nan take).
   Ana iya samun wannan ainihin a cikin Kundin Labero (a ƙarƙashin Ƙarƙashin Ƙarƙashin Ƙarƙashin Ƙarƙashin Ƙarƙashin Ƙarƙashin Ƙarƙashin Ƙarƙashin Ƙarƙashin Ƙarƙashin Ƙarƙashin Ƙarƙashin Ƙarƙashin Ƙarƙashin Ƙarƙashin Ƙarƙashin Ƙarƙashin Ƙarƙashin Ƙarƙashin Ƙarƙashin Ƙarƙashin Ƙarƙashin Ƙarƙashin Ƙarƙashin Ƙarƙashin Ƙarƙashin Ƙarƙashin Ƙarƙashin Ƙarƙashin Ƙarƙashin Ƙarƙashin Ƙarƙashin Ƙarƙashin Ƙarƙashin Ƙarƙashin Ƙarƙashin Ƙarƙashin Ƙarƙashin Ƙarƙashin Ƙarƙashin Ƙarƙashin Ƙarƙashin Ƙarƙashin Ƙarƙa ))
2. Danna maɓallin tsakiya sau biyu don buɗe mai daidaitawa.
3. Saita ainihin don tantance waɗanne keɓaɓɓun abubuwan da ake buƙatar farawa (Hoto 3-3)

Hoto 3-3 • Akwatin Magana na CoreConfigP

CoreResetP
Don saita CoreResetP:

1. Nan take CoreResetP a cikin SmartDesign ɗin ku (yawanci inda MSS ke nan take).
   Ana iya samun wannan jigon a cikin Kundin Labero, ƙarƙashin Peripherals.
2. Danna maɓallin tsakiya sau biyu a cikin SmartDesign Canvas don buɗe Configurator (Hoto 3-4).
3. A saita ainihin zuwa:
   - Ƙayyade halayen sake saitin waje (EXT_RESET_OUT an tabbatar). Zaɓi ɗayan zaɓuɓɓuka huɗu:
   o EXT_RESET_OUT ba a taɓa tabbatarwa ba
   Ana tabbatar da EXT_RESET_OUT idan an tabbatar da sake saita wutar lantarki (POWER_ON_RESET_N)
   o An tabbatar da EXT_RESET_OUT idan an tabbatar da FAB_RESET_N
   Ana tabbatar da EXT_RESET_OUT idan an sake saita wutar lantarki (POWER_ON_RESET_N) ko FAB_RESET_N
   – Ƙayyade Na'urar Voltage. Ya kamata darajar da aka zaɓa ta dace da voltage ka zaba a cikin akwatin maganganu na Saitunan Ayyukan Libero.
   - Bincika akwatunan rajistan da suka dace don nuna abubuwan da kuke amfani da su a cikin ƙirar ku.
   – Ƙayyade lokacin saitin ƙwaƙwalwar ajiyar DDR na waje. Wannan ita ce madaidaicin ƙimar ga duk abubuwan ƙwaƙwalwar ajiyar DDR da aka yi amfani da su a cikin aikace-aikacenku (MDDR da FDDR). Koma zuwa bayanan mai siyar da ƙwaƙwalwar ajiyar DDR na waje don saita wannan siga. 200us kyakkyawan ƙimar tsoho ne don ƙwaƙwalwar DDR2 da DDR3 waɗanda ke gudana a 200MHz. Wannan siga ce mai mahimmanci don tabbatar da simintin aiki da tsarin aiki akan silicon. Ƙimar da ba daidai ba don lokacin daidaitawa na iya haifar da kurakuran kwaikwayo. Koma zuwa bayanan mai siyar da ƙwaƙwalwar ajiyar DDR don saita wannan siga.
   - Ga kowane shingen SErdES a cikin ƙirar ku, duba akwatunan da suka dace don nuna ko:
   Ana amfani da PCIe
   o Ana buƙatar goyon bayan PCIe Hot Sake saitin
   o Ana buƙatar tallafi don PCIe L2/P2

Lura: Idan kuna amfani da 090 die(M2S090) kuma ƙirar ku tana amfani da SERDESIF, ba dole ba ne ku duba kowane ɗayan akwatunan rajista masu zuwa: 'Amfani da PCIe', 'Hada goyon bayan PCIe HotReset' da 'Haɗa goyon bayan PCIe L2/P2'. Idan kana amfani da kowace na'urar da ba ta 090 ba kuma tana amfani da tubalan SERDESIF ɗaya ko fiye, dole ne ka duba duk akwatuna huɗu a ƙarƙashin sashin SERDESIF da ya dace.
Lura: Don cikakkun bayanai kan zaɓuɓɓukan da ke gare ku a cikin wannan mai daidaitawa, koma zuwa CoreResetP Handbook.

Hoto 3-4 • CoreResetPCConfigurator

25/50MHz Instantiation Oscillator
CoreConfigP da CoreResetP ana rufe su ta hanyar oscillator 25/50MHz RC akan guntu. Dole ne ku hanzarta Oscillator na 25/50MHz kuma ku haɗa shi zuwa waɗannan muryoyin.

1. Nuna ainihin Chip Oscillators a cikin SmartDesign ɗin ku (yawanci inda MSS ke nan take). Ana iya samun wannan jigon a cikin Kasidar Libero a ƙarƙashin Agogo & Gudanarwa.
2. Saita wannan cibiya kamar yadda RC oscillator ke tafiyar da masana'anta na FPGA, kamar yadda aka nuna a hoto 3-5.

Hoto 3-5 • Chip Oscillators Configurator

Sake saitin tsarin (SYSRESET) Nan take
SYSRESET macro yana ba da aikin sake saitin matakin na'urar zuwa ƙirar ku. Ana tabbatar da siginar fitarwa na POWER_ON_RESET_N/ba a tabbatar da ita a duk lokacin da aka kunna guntu ko kuma an tabbatar da fitin DEVRST_N na waje/de-tabbace (Hoto 3-6).
Ƙaddamar da SYSRESET macro a cikin SmartDesign (yawanci inda MSS ke nan take). Ana iya samun wannan macro a cikin Kundin Libaro a ƙarƙashin Laburaren Macro.Babu saitin wannan macro da ya zama dole.

Hoto 3-6 • SYSRESET Macro

Gabaɗaya Haɗuwa
Bayan kun kunna kuma saita MSS, FDDR, SERDESIF, OSC, SYSRESET, CoreConfigP da CoreResetP a cikin ƙirar ku, kuna buƙatar haɗa su don samar da tsarin ƙaddamarwa na Peripheral. Don sauƙaƙe bayanin haɗin kai a cikin wannan takaddar, an karye shi cikin hanyar haɗin bayanan daidaitawa na APB3 mai alaƙa da CoreConfigP da haɗin haɗin CoreResetP.
Haɗin Hanyar Bayanan Kanfiguration
Hoto na 3-7 yana nuna yadda ake haɗa CoreConfigP zuwa sigina na MSS FIC_2 da mu'amalar daidaitawa na APB3 masu dacewa.
Tebur 3-1 • Haɗin Kanfigareshan Tafarkin Bayanai na Port/Haɗin BIF

DAGA Interface Port/Bas (BIF) / Bangaren	TO Interface Port/Bas (BIF)/Kashi
APB S PRESET N/ CoreConfigP	APB S PRESET N/ SDIF <0/1/2/3>	APB S PRESET N/ FDDR	MDR APB S Prese TN/MSS
APB S PCLK/CoreConfigP	APB S PCLK/SDIF	APB S PCLK/FDDR	MDDr APB S POLK/ MSS
MDDR APBmslave/CoreConfig			MDR APB BAYI (BIF)/MSS
SDIF <0/1/2/ 3> APBmslave/Config	APB BAYI (BIF)/ SDIF <0/1/2/3>
FDDR APBmslave		APB BAYI (BIF) / FDDR
FIC 2 APBmmaster/CoreConfigP			FIC 2 APB MASTER/ MSS

Hoto 3-7 • FIC_2 APB3 Babban Haɗin Tsari

Agogo da Sake saita Haɗuwa
Hoto na 3-8 yana nuna yadda ake haɗa CoreResetP zuwa tushen sake saiti na waje da siginonin sake saiti na zahiri. Hakanan yana nuna yadda ake haɗa CoreResetP zuwa siginar aiki tare na agogo na gefe (siginonin kulle PLL). Bugu da ƙari, yana nuna yadda ake haɗa CoreConfigP da CoreResetP.

Hoto 3-8 • Core SF2Reset Sub-System Connectivity

Ƙirƙirar da Haɗa Aikace-aikacen Firmware

Lokacin da kuka fitar da firmware daga LiberoSoC (Window Flow Design> Firmware Export> Firmware Export), Libero yana haifar da masu zuwa. files a cikin /firmware/drivers_config/ sys_config babban fayil:

• sys_config.c - Ya ƙunshi tsarin bayanan da ke riƙe ƙima don rajistar na gefe.
• sys_config.h - Ya ƙunshi # ƙayyadaddun bayanai waɗanda ke ƙayyadaddun abubuwan da ake amfani da su a cikin ƙira kuma suna buƙatar farawa.
• sys_config_mddr_define.h - Ya ƙunshi bayanan daidaitawar mai sarrafa MDDR da aka shigar a cikin akwatin Magana Kanfigareshan Rijista.
• sys_config_fddr_define.h - Ya ƙunshi bayanan daidaitawar mai sarrafa FDDR da aka shigar a cikin akwatin Magana Kanfigareshan Rijista.
• sys_config_mss_clocks.h – Wannan file ya ƙunshi mitocin agogon MSS kamar yadda aka ayyana a cikin na'urar daidaitawa ta MSS CCC. Ana amfani da waɗannan mitoci ta lambar CMSIS don samar da bayanan agogo daidai ga yawancin direbobin MSS waɗanda dole ne su sami damar yin amfani da mitar Agogon su (PCLK). ).
• sys_config_SERDESIF_ .c - Ya ƙunshi SERDESIF_ bayanan sanyi da aka bayar lokacin SERDESIF_ toshe sanyi a cikin ƙirar ƙira.
• sys_config_SERDESIF_ .h - Ya ƙunshi kalamai na #bayyana waɗanda ke ƙayyadad da adadin nau'ikan daidaitawar rajista da lambar layin da ke buƙatar yin zabe don PMA_READY (kawai a cikin yanayin PCIe).

Wadannan files ana buƙatar lambar CMSIS don tattarawa yadda ya kamata kuma ya ƙunshi bayanai game da ƙirar ku na yanzu, gami da bayanan daidaitawa da bayanan sanyi na agogo don MSS.
Kar a gyara waɗannan files da hannu; an ƙirƙira su zuwa ga madaidaitan kundayen adireshi/na gefe a duk lokacin da aka samar da abubuwan SmartDesign waɗanda ke ɗauke da abubuwan da suka dace. Idan an yi wasu canje-canje ga bayanan daidaitawa na kowane yanki, kuna buƙatar sake fitar da ayyukan firmware don sabunta firmware ɗin. files (duba lissafin da ke sama) ana fitar dashi zuwa ga / firmware/drivers_config/sys_config babban fayil.
Lokacin da kuka fitar da firmware, Libero SoC yana ƙirƙirar ayyukan firmware: ɗakin karatu inda tsarin ƙirar ku files da direbobi suna harhada.
Idan ka duba aikin Ƙirƙiri akwati lokacin da kuke fitarwa firmware, an ƙirƙiri aikin SoftConsole/IAR/Keil software don riƙe aikin aikace-aikacen inda zaku iya gyara babban.c da mai amfani C/H files. Bude aikin SoftConSole/IAR/Keil don tattara lambar CMSIS daidai kuma a daidaita aikace-aikacen firmware ɗin ku da kyau don dacewa da ƙirar kayan aikin ku.

BFM Files An yi amfani da shi don simintin ƙira

Lokacin da kuka ƙirƙira abubuwan SmartDesign waɗanda ke ɗauke da abubuwan da ke da alaƙa da ƙirar ku, simulation files daidai da na'urorin da aka samar a cikin / directory na simulations:

• gwada.bfm - Babban matakin BFM file wanda aka fara aiwatar da shi yayin kowane siminti da ke sarrafa na'urar sarrafa SmartFusion2 MSS Cortex-M3. Yana aiwatar da peripheral_init.bfm da user.bfm, a cikin wannan tsari.
• MDR_init.bfm - Idan ƙirar ku tana amfani da MDDR, Libero yana haifar da wannan file; yana ƙunshe da umarnin rubuta BFM waɗanda ke kwatanta rubutattun bayanan rajistar sanyi na MSS DDR da kuka shigar (ta amfani da akwatin maganganu na Editan Rajista ko a cikin MSS_MDDR GUI) cikin rajistar MSS DDR Controller.
• FDDR_init.bfm - Idan ƙirar ku tana amfani da FDDR, Libero yana haifar da wannan file; ya ƙunshi rubutattun umarni na BFM waɗanda ke kwatanta rubutattun bayanan rajista na Fabric DDR da kuka shigar (ta amfani da akwatin maganganu na Editan Rajista ko a cikin FDDR GUI) cikin rajistar Fabric DDR Controller.
• SERDESIF_ _init.bfm - Idan ƙirar ku ta yi amfani da shingen SERDESIF ɗaya ko fiye, Libero yana haifar da wannan file ga kowane SERDESIF_ tubalan amfani; yana ƙunshe da umarnin rubuta BFM waɗanda ke kwaikwayi rubutawa na bayanan rajistar tsarin SERDESIF da kuka shigar (ta amfani da akwatin maganganu na Editan Rajista ko a cikin SERDESIF_ GUI) cikin SERDESIF_ yin rajista. Idan an saita toshe SERDESIF azaman PCIe, wannan file Hakanan yana da wasu # ayyana kalamai waɗanda ke sarrafa aiwatar da matakan daidaita tsarin rajista guda 2 cikin tsari mai kyau.
• mai amfani.bfm – Ya ƙunshi umarnin mai amfani. Ana aiwatar da waɗannan umarni bayan an gama peripheral_init.bfm. Gyara wannan file don shigar da umarnin BFM ku.
• SERDESIF_ _mai amfani.bfm – Ya ƙunshi umarnin mai amfani. Gyara wannan file don shigar da umarnin BFM ku. Yi amfani da wannan idan kun saita SERDESIF_ toshe a cikin yanayin kwaikwayo na BFM PCIe kuma azaman mai sarrafa AXI/AHBlite. Idan kun saita SERDESIF_ toshe a cikin yanayin kwaikwayo na RTL, ba za ku buƙaci wannan ba file.

Lokacin da kuka kira simulation kowane lokaci, simulation biyu masu zuwa files an sake halitta zuwa ga Littafin littafin kwaikwayo tare da sabunta abubuwan ciki:

• tsarin subsystem.bfm - Ya ƙunshi #bayyana kalamai na kowane yanki da aka yi amfani da su a cikin ƙirar ku, waɗanda ke ƙayyadad da takamaiman yanki na peripheral_init.bfm don aiwatar da su daidai da kowane yanki.
• operipheral_init.bfm - Ya ƙunshi tsarin BFM wanda ke kwaikwayon aikin CMSIS :: SystemInit () da ke gudana akan Cortex-M3 kafin shigar da babbar hanyar (). Yana kwafin bayanan daidaitawa don kowane yanki da aka yi amfani da shi a cikin ƙira zuwa daidaitattun rajistar saitin saitin sannan yana jira duk abubuwan da ke kewaye su kasance a shirye kafin tabbatar da cewa za ku iya amfani da waɗannan abubuwan. Yana aiwatar da MDR_init.bfm da FDDR_init.bfm.

Amfani da waɗannan da aka haifar files, ana daidaita masu sarrafa DDR a cikin ƙirar ku ta atomatik, suna kwaikwayon abin da zai faru akan na'urar SmartFusion2. Kuna iya shirya mai amfani.bfm file don ƙara kowane umarni da ake buƙata don kwaikwayi ƙirar ku (Cortex-M3 shine maigidan). Ana aiwatar da waɗannan umarni bayan an fara abubuwan da ke kewaye. Kar a gyara test.bfm, subsystem.bfm, peripheral_init.bfm, MDDR_init.bfm, FDDR_init.bfm files da SERDESIF_ _init.bfm files.

Tallafin samfur

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Website
Kuna iya bincika bayanai na fasaha iri-iri da marasa fasaha akan shafin gida na SoC, a www.microsemi.com/soc.
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Takardu / Albarkatu

Microsemi SmartFusion2 DDR Mai Sarrafa da Mai Kula da Babban Gudun Serial [pdf] Jagorar mai amfani SmartFusion2 DDR Mai Sarrafa da Mai Sarrafa Babban Sauri, SmartFusion2 DDR, Mai Sarrafa da Mai Kula da Babban Gudun Gudun, Mai Sarrafa Mai Sauri.

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