SmartFusion2
Umlawuli we-DDR kunye noMlawuli oPhezulu oPhezulu
Indlela yokuQalisa
Isikhokelo somsebenzisi

Intshayelelo

Xa usenza uyilo usebenzisa isixhobo SmartFusion2, ukuba usebenzisa omnye abalawuli DDR ezimbini (FDDR okanye MDDR) okanye nayiphi na iibhloko Uthotho High isantya isilawuli (SERDESIF), kufuneka uqalise iirejista uqwalaselo ezi blocks ngexesha lokuqhuba phambi kokuba zinokusetyenziswa. Umzekeloample, kumlawuli we-DDR, kufuneka ubeke imo ye-DDR (DDR3/DDR2/LPDDR), ububanzi be-PHY, imo yokuqhuma kunye ne-ECC.
Ngokufanayo, kwibhloko yeSERDESIF esetyenziswa njengesiphelo sePCIe, kufuneka usete iPCIE BAR kwi-AXI (okanye i-AHB) yefestile.
Olu xwebhu luchaza amanyathelo ayimfuneko ukwenza uyilo lwe-Libero oluqalisa ngokuzenzekelayo umlawuli we-DDR kunye neebhloko ze-SERDESIF kumandla aphezulu. Ikwachaza indlela yokuvelisa ikhowudi ye-firmware esuka kwi-Libero SOC esetyenziswa kwi-embedded design flow flow.
Inkcazo ecacileyo yethiyori yokusebenza inikwe kuqala.
Icandelo elilandelayo lichaza indlela yokwenza uyilo olunjalo usebenzisa i-Libero SoC System Builder, isixhobo esinamandla soyilo, phakathi kwezinye izinto, senze isisombululo 'sokuqala' kuwe ukuba usebenzisa i-DDR okanye i-SERDESIF iibhloko kuyilo lwakho.
Icandelo elilandelayo lichaza indlela yokubeka isisombululo 'sokuqalisa' esipheleleyo kunye ngaphandle kokusebenzisa iSmartFusion2 System Builder. Oku kunceda ukucacisa ukuba yintoni ekufuneka yenziwe ukuba awunqweneli ukusebenzisa i-System Builder, kwaye ichaza ukuba yintoni isixhobo soMakhi weNkqubo esikwenzela yona. Eli candelo lijongene:

• Ukwenziwa kwedatha yoqwalaselo lwe-DDR isilawuli kunye neerejista zoqwalaselo zeSERDESIF
• Ukwenziwa kwengqiqo yeFPGA efunekayo ukudlulisa idatha yoqwalaselo kwiirejista zoqwalaselo ezahlukeneyo ze-ASIC.

Ekugqibeleni sichaza into eyenziwe fileinxulumene ne:

• Ukwenziwa kwesisombululo 'sokuqalisa' kwe-firmware.
• Ukulinganisa uyilo lwe-DDR 'ukuqaliswa' kwesisombululo.

Ngeenkcukacha malunga nomlawuli we-DDR kunye neerejista zoqwalaselo ze-SERDESIF, bhekisa ku I-Microsemi SmartFusion2 iSpeed ​​​​Speed ​​seSerial kunye ne-DDR Interfaces Isikhokelo somsebenzisi.

Ithiyori yokuSebenza

Isisombululo sokuqalisa sePeripheral sisebenzisa ezi zixhobo zilandelayo:

• CMSIS SystemInit () umsebenzi, osebenza kwi-Cortex-M3 kunye ne-orchestrate inkqubo yokuqalisa.
• I-CoreConfigP ethambileyo engundoqo ye-IP, eqalisa iirejista zoqwalaselo lweperipherals.
• I-CoreResetP engundoqo ye-IP ethambileyo, elawula ukusetwa kwakhona kwe-MSS, abalawuli be-DDR, kunye neebhloko ze-SERDESIF.

Inkqubo yokuqaliswa kweperipheral isebenza ngolu hlobo lulandelayo:

1. Emva kokusetha kwakhona, i-Cortex-M3 iqhuba umsebenzi we-CMSIS SystemInit (). Lo msebenzi uyenziwa ngokuzenzekelayo phambi kokuba isicelo esingundoqo () siphunyezwe.
   Isignali yemveliso ye-CoreResetP MSS_HPMS_READY igxininiswe ekuqaleni kwenkqubo yokuqalisa, ebonisa ukuba i-MSS kunye nazo zonke iiperipherals (ngaphandle kwe-MDDR) zilungele ukunxibelelana.
2. Umsebenzi we-SystemInit () ubhala idatha yoqwalaselo kubalawuli beDDR kunye neerejista zoqwalaselo zeSERDESIF nge-MSS FIC_2 APB3 ibhasi. Olu jongano luqhagamshelwe kwisiseko esithambileyo seCoreConfigP emiliselwe kwilaphu leFPGA.
3. Emva kokuba zonke iirejista ziqwalaselwe, i-SystemInit () umsebenzi ubhalela kwiirejista zolawulo zeCoreConfigP ukubonisa ukugqitywa kwesigaba soqwalaselo lwerejista; Iimpawu zemveliso zeCoreConfigP CONFIG1_DONE kunye neCONIG2_DONE ziyaqinisekiswa.
   Kukho izigaba ezibini zolungiselelo lwerejista (CONFIG1 kunye neCONFIG2) ngokuxhomekeke kwiiperipherals ezisetyenzisiweyo kuyilo.
4. Ukuba enye okanye zombini ze-MDDR/FDDR zisetyenzisiwe, kwaye akukho nanye kwiibhloko ze-SERDESIF ezisetyenziswayo kuyilo, kukho kuphela isigaba soqwalaselo lwerejista. Zombini iimpawu zemveliso zeCoreConfigP CONFIG1_DONE kunye neCONIG2_DONE ziqinisekiswa enye emva kwenye ngaphandle kokulinda/ukulibazisa.
   Ukuba enye okanye ezininzi iibhloko ze-SERDESIF kwimodi engeyiyo ye-PCIe zisetyenziswa kuyilo, kukho isigaba esinye kuphela sokucwangciswa kwerejista. CONFIG1_DONE kunye neCONIG2_DONE ziqinisekiswa enye emva kwenye ngaphandle kokulinda/ukulibazisa.
   Ukuba ibhloko enye okanye ngaphezulu ye-SERDESIF kwimo ye-PCIe isetyenziswa kuyilo, kukho izigaba ezibini zokucwangciswa kwerejista. CONFIG1_DONE igxininiswa emva kokuba isigaba sokuqala solungiselelo lobhaliso lugqityiwe. Inkqubo yeSERDESIF kunye neerejista zomzila zilungiselelwe kwesi sigaba. Ukuba i-SERDESIF ibunjwe ngendlela engeyiyo eye-PCIE, i-CONFIG2_DONE isignali nayo iyagonywa ngoko nangoko.
5. Isigaba sesibini solungiselelo lwerejista silandela emva koko (ukuba iSERDESIF iqwalaselwe kwimo yePCIE). Ezi zilandelayo ziziganeko ezahlukeneyo ezenzeka kwisigaba sesibini:
   -I-CoreResetP de-asserts PHY_RESET_N kunye ne-CORE_RESET_N iimpawu ezihambelana neebhloko nganye zeSERDESIF ezisetyenzisiweyo. Ikwaqinisekisa umqondiso wemveliso SDIF_RELEASED emva kokuba zonke iibhloko zeSERDESIF ziphumile ekusetweni ngokutsha. Lo mqondiso we-SDIF_RELEASED usetyenziselwa ukubonisa kwi-CoreConfigP ukuba undoqo we-SERDESIF uphumile ekusetweni ngokutsha kwaye ulungele isigaba sesibini sokucwangciswa kwerejista.
   – Nje ukuba i-SDIF_RELEASED isignali iqinisekisiwe, i-SystemInit () umsebenzi uqala ukuvotela ukuqinisekiswa kwe-PMA_READY kwindlela efanelekileyo ye-SERDESIF. Nje ukuba i-PMA_READY ibasiwe, iseti yesibini yeerejista ze-SERDESIF (iirejista zePCIE) ziqwalaselwe/zibhalwe ngu-SystemInit() umsebenzi.
6. Emva kokuba zonke iirejista zePCIE ziqwalaselwe, umsebenzi weSystemInit () ubhalela iirejista zolawulo lweCoreConfigP ukubonisa ukugqitywa kwesigaba sesibini soqwalaselo lwerejista; i-CoreConfigP yemveliso yesiginali CONIG2_DONE iyaqinisekiswa.
7. Ngaphandle kwezi ngqinisiso/ziqinisekiso ezingentla, iCoreResetP ikwalawula ukuqaliswa kweebhloko ezahlukeneyo ngokwenza le misebenzi ilandelayo:
   -Ukuqinisekisa ukusetwa okungundoqo kwe-FDDR
   – Ukuqinisekisa ukuba i-SERDESIF ibhloka i-PHY kunye ne-CORE
   -Ukubeka iliso kwisignali yokutshixa i-FDDR PLL (FPLL). I-FPLL kufuneka itshixiwe ukuqinisekisa ukuba i-FDDR AXI/AHBLite ujongano lwedatha kunye nelaphu leFPGA linokunxibelelana ngokuchanekileyo.
   – Ukubekwa esweni kweempawu zokutshixa ze-SERDESIF block PLL (SPLL). I-SPLL kufuneka itshixiwe ukuqinisekisa ukuba i-SERDESIF ivimba i-AXI/AHBLite ujongano (imo yePCIe) okanye i-XAUI interface inokunxibelelana ngokufanelekileyo ngelaphu leFPGA.
   -Ukulinda iinkumbulo ze-DDR zangaphandle ukuba zizinze kwaye zilungele ukufikelelwa ngabalawuli be-DDR.
8. Xa zonke iiperipherals zigqibile ukuqaliswa kwazo, i-CoreResetP iqinisekisa i-INIT_DONE isignali; irejista yeCoreConfigP yangaphakathi INIT_DONE iyaqinisekiswa.
   Ukuba enye okanye zombini ze-MDDR/FDDR zisetyenzisiwe, kwaye ixesha lokuqalisa i-DDR lifikelelwe, isignali yemveliso ye-CoreResetP engu-DDR_READY iyaqinisekiswa. Ukuqinisekiswa kolu phawu DDR_READY kunokujongwa njengento ebonisa ukuba i-DDR (MDDR/FDDR) ilungele unxibelelwano.
   Ukuba ibhloko enye okanye ezininzi zeSERDESIF zisetyenzisiwe, kwaye isigaba sesibini sokucwangciswa kwerejista sigqitywe ngempumelelo, i-CoreResetP yesignali yemveliso SDIF_READY iqinisekisiwe. Ukuqinisekiswa kolu phawu SDIF_READY kunokujongwa njengophawu lokuba zonke iibhloko zeSERDESIF zilungele unxibelelwano.
9. Umsebenzi we-SystemInit (), olinde i-INIT_DONE ukuba ingqinwe, igqibezele, kunye nowona msebenzi wesicelo () uphunyeziwe. Ngelo xesha, bonke abalawuli be-DDR abasetyenzisiweyo kunye neebhloko ze-SERDESIF ziqalisiwe, kwaye isicelo se-firmware kunye ne-FPGA ye-logic yelaphu inokunxibelelana nabo ngokuthembekileyo.

Indlela yokusebenza echazwe kolu xwebhu ixhomekeke kwi-Cortex-M3 eqhuba inkqubo yokuqalisa njengenxalenye yekhowudi yokuqalisa inkqubo eyenziwe ngaphambi kowona msebenzi ()ongundoqo wesicelo.
Jonga i-Flow Charts kwi-Figure 1-1, i-Figure 1-2 kunye ne-Figure 1-3 kumanyathelo okuQalisa i-FDDR / MDDR, i-SEREDES (i-non-PCIe mode) kunye ne-SERDES (i-PCIe mode).
Umzobo 1-4 ubonisa umzobo wexesha lokuqalisa wePeripheral Initialization.

Umfanekiso 1-3 • Itshathi yokuQuqana okuQala kweSERDESIF (PCIe)
Inkqubo yokuqalisa echazwe kolu xwebhu ifuna ukuba usebenzise i-Cortex-M3 ngexesha lenkqubo yokuqalisa, nokuba awucwangcisi ukusebenzisa nayiphi na ikhowudi kwi-Cortex-M3. Kuya kufuneka wenze usetyenziso olusisiseko lwe-firmware olungenzi nto (i-loop elula, ye-example) kwaye ulayishe oko kuphunyezwayo kwiMemori engaguquguqukiyo elungisiweyo (eNVM) ukuze abalawuli beDDR kunye neebhloko zeSERDESIF ziqaliswe xa iibhutsi zeCortex-M3.

Ukusebenzisa i-System umakhi ukwenza uYilo usebenzisa i-DDR kunye neebhloko ze-SERDESIF

I-SmartFusion2 System Builder sisixhobo soyilo esinamandla esikunceda ukuba ubambe iimfuno zenqanaba lenkqubo kwaye uvelise uyilo oluphumeza ezo mfuno. Umsebenzi obaluleke kakhulu we-System Builder yindalo ezenzekelayo ye-Peripheral Initialization sub-system. "Ukusebenzisa i-SmartDesign ukwenza i-Design usebenzisa i-DDR kunye neebhloko ze-SERDESIF" kwiphepha le-17 lichaza ngokucacileyo indlela yokudala isisombululo esinjalo ngaphandle koMakhi weNkqubo.
Ukuba usebenzisa i-System Builder, kufuneka wenze le misebenzi ilandelayo ukwenza uyilo oluqalisa abalawuli bakho be-DDR kunye neebhloko ze-SERDESIF kumandla aphezulu:

1. Kwiphepha leMicimbi yeDivaysi (Umfanekiso 2-1), cacisa ukuba zeziphi izilawuli ze-DDR ezisetyenzisiweyo kwaye zingaphi iibhloko ze-SERDESIF ezisetyenziselwa ukuyila kwakho.
2. Kwiphepha leMemori, khankanya uhlobo lwe-DDR (DDR2/DDR3/LPDDR) kunye nedatha yoqwalaselo yeenkumbulo zakho zangaphandle ze-DDR. Jonga icandelo leMemori yePhepha ngeenkcukacha.
3. Kwiphepha leeperipherals, yongeza iinkosi zelaphu eziqwalaselwe njenge-AHBLite/AXI kwiFabric DDR Subsystem kunye/okanye iMSS DDR FIC Subsystem (ukhetho).
4. Kwi Useto lweClock phepha, khankanya iifrikhwensi zewotshi kwii-DDR sub-systems.
5. Gqibezela iinkcukacha zoyilo lwakho kwaye ucofe kuGqiba. Oku kuvelisa uyilo oluyiliweyo loMakhi weNkqubo, kuquka ingqiqo eyimfuneko kwisisombululo 'sokuqalisa'.
6. Ukuba usebenzisa iibhloko zeSERDESIF, kufuneka uqinisekise iibhloko zeSERDESIF kuyilo lwakho kwaye uqhagamshele izibuko zazo zokuqalisa kwezo zeNdlela yoMakhi weNkqubo engundoqo.

Iphepha leempawu zeSixhobo soMakhi weNkqubo
Kwiphepha leMicimbi yesiXhobo, cacisa ukuba zeziphi izilawuli ze-DDR (MDDR kunye/okanye i-FDDR) ezisetyenzisiweyo kwaye zingaphi iibhloko zeSERDESIF ezisetyenzisiweyo kuyilo lwakho (Umfanekiso 2-1).

Umzobo 2-1 • Iphepha leempawu zeSixhobo soMakhi weNkqubo

Iphepha leMemori yoMakhi weNkqubo
Ukusebenzisa i-MSS DDR (MDDR) okanye iFabric DDR (FDDR), khetha uhlobo lweMemori kuluhlu oluhlayo (Umfanekiso 2-2).

Umfanekiso 2-2 • IMemori yaNgaphandle ye-MSS

Kufuneke u:

1. Khetha uhlobo lwe-DDR (DDR2, DDR3 okanye LPDDR).
2. Chaza ixesha lokumisa imemori ye-DDR. Jongana neNgcaciso yeMemori ye-DDR yakho yangaphandle ukuseta ixesha elichanekileyo lokuseta imemori. Imemori ye-DDR inokusilela ukuqalisa ngokuchanekileyo ukuba ixesha lokumisa imemori alicwangciswanga kakuhle.
3. Nokuba ungenisa idatha yoqwalaselo lwerejista ye-DDR okanye usete i-DDR Memory Parameters yakho. Ngeenkcukacha, jonga kwi I-Microsemi SmartFusion2 iSpeed ​​​​Speed ​​seSerial kunye ne-DDR Interfaces Isikhokelo somsebenzisi.

Le datha isetyenziselwa ukuvelisa irejista ye-DDR BFM kunye noqwalaselo lwe-firmware files njengoko kuchaziwe “Ukwenza kunye nokuQeqesha iSicelo seFirmware” kwiphepha lama-26 kunye ne “BFM Files Isetyenziselwa ukulinganisa uYilo” kwiphepha lama-27. Ukufumana iinkcukacha kwiirejista zoqwalaselo lwesilawuli se-DDR, bhekisa ku I-Microsemi SmartFusion2 iSpeed ​​​​Speed ​​seSerial kunye ne-DDR Interfaces Isikhokelo somsebenzisi.
Umdalaample yoqwalaselo file I-syntax iboniswe kuMfanekiso 2-3. Amagama erejista asetyenziswe apha file ziyafana nezo zichazwe kwi I-Microsemi SmartFusion2 iSpeed ​​​​Speed ​​seSerial kunye ne-DDR Interfaces Isikhokelo somsebenzisi

Umzobo 2-3 • Ulungelelwaniso File Isintaksi Eksample
Iphepha leeperipherals zomakhi weNkqubo
Kwiphepha le-Peripherals, kumlawuli ngamnye we-DDR kwenziwa isistim esezantsi esecaleni (Fabric DDR Subsystem ye-FDDR kunye ne-MSS DDR FIC Subsystem ye-MDDR). Unokongeza iFabric AMBA Master (eqwalaselwe njenge-AXI/AHBLite) engundoqo kwindlela nganye kwezi zisezantsi ukwenzela ukuba ilaphu likwazi ukufikelela kubalawuli be-DDR. Ekuveliseni, i-System Builder iqinisekisa ngokuzenzekelayo ii-core cores (kuxhomekeke kuhlobo lwe-AMBA Master eyongeziweyo) kwaye iveza i-BIF yomgaqo webhasi kunye newotshi kunye nezikhonkwane zokuseta ngokutsha kweendlela ezisezantsi ezihambelanayo (FDDR/MDDR) phantsi kwamaqela eephini ezifanelekileyo, ukuya phezulu. Konke okufuneka ukwenze kukudibanisa ii-BIFs kwii-Fabric Master cores ezifanelekileyo onokuthi uzifake kuyilo. Kwimeko ye-MDDR, kuyakhethwa ukongeza iFabric AMBA Master core kwi-MSS DDR FIC Subsystem; Cortex-M3 yinkosi engagqibekanga kule subsystem. Umzobo we-2-4 ubonisa i-System Builder Peripherals Page.

Umfanekiso 2-4 • Iphepha leeperipherals zomakhi weNkqubo

Iphepha leeSetingi zewotshi yomakhi weNkqubo
Kwizicwangciso zeClock kwiphepha, kumlawuli ngamnye weDDR, kufuneka ukhankanye iifrikhwensi zewotshi ezinxulumene ne-DDR (MDDR kunye/okanye FDDR) sub-system nganye.
Kwi-MDDR, kufuneka ucacise:

• MDDR_CLK -Le wotshi imisela amaxesha okusebenza koMlawuli we-DDR kwaye kufuneka ihambelane nesantya sewotshi onqwenela ukuba imemori yakho ye-DDR isebenze kuyo. Le wotshi ichazwa njenge-multiple ye-M3_CLK (i-Cortex-M3 kunye ne-MSS Main Clock, i-Figure 2-5). I-MDDR_CLK kufuneka ibe ngaphantsi kwe-333 MHz.
• DDR_FIC_CLK - Ukuba ukhethe ukufikelela kwi-MDDR kwilaphu le-FPGA, kufuneka ucacise i-DDR_FIC_CLK. Lo mqukumbelo wewotshi uchazwa njengomlinganiselo we-MDDR_CLK kwaye kufuneka ihambelane namaxesha apho i-FPGA ilaphu esezantsi inkqubo efikelela kwi-MDDR isebenza.

Umfanekiso 2-5 • I-Cortex-M3 kunye ne-MSS Iwashi engundoqo; Iiwotshi ze-MDDR

Kwi-FDDR, kufuneka ucacise:

• I-FDDR_CLK-Imisela i-frequency yokusebenza ye-DDR Controller kwaye kufuneka ifanise i-clock frequency apho unqwenela ukuba imemori yakho ye-DDR yangaphandle iqhube. Qaphela ukuba le wotshi ichazwa njenge-multiple ye-M3_CLK (i-MSS kunye ne-Cortex-M3 clock, i-Figure 2-5). I-FDDR_CLK kufuneka ibe ngaphakathi kwe-20 MHz kunye ne-333 MHz.
• FDDR_SUBSYSTEM_CLK – Le wotshi rhoqo ichazwa njengomlinganiselo we FDDR_CLK kwaye kufuneka ihambelane namaxesha apho inkqubo yelaphu yeFPGA ephantsi efikelela kwi-FDDR isebenza.

Umzobo 2-6 • Iiwotshi ze-DDR zelaphu
Uqwalaselo lwe-SERDESIF
Iibhloko zeSERDESIF aziqiniswanga kuyilo oluveliswe nguMakhi weNkqubo. Nangona kunjalo, kuzo zonke iibhloko ze-SERDESIF, iimpawu zokuqalisa zifumaneka kwi-interface ye-System Builder core kwaye inokudibaniswa ne-SERDESIF cores kwinqanaba elilandelayo le-hierarchy, njengoko kuboniswe kwi-Figure 2-7.Umfanekiso 2-7 • UQhagamshelwano lokuQaliswa koMda we-SERDESIF
Ngokufana neerejista zokumisela i-DDR, ibhloko nganye ye-SERDES nayo ineerejista zokumisela ekufuneka zilayishwe ngexesha lokusebenza. Ungangenisa ngaphandle la maxabiso erejista okanye usebenzise isiNxulumanisi esiPhakamileyo seSijongana soBuninzi (Umfanekiso 2-8) ukufaka iiparamitha zePCIe okanye zeEPCS kwaye amaxabiso erejista abalelwa wena ngokuzenzekelayo. Ngeenkcukacha, jonga kwi Isikhokelo soMsebenzisi woMsebenzisi weSERDES.Umfanekiso 2-8 • IsiQinisekiso soNxibelelwano oluPhezulu lweSyiri esiPhezulu
Nje ukuba udibanise i-logic yakho yomsebenzisi kunye nebhloko ye-System Builder kunye ne-SERDES block, unokuvelisa inqanaba lakho eliphezulu le-SmartDesign. Oku kuvelisa yonke i-HDL kunye ne-BFM files eziyimfuneko ukuphumeza kunye nokulinganisa uyilo lwakho. Emva koko ungaqhubeka nalo lonke uYilo lokuQuquza.

Ukusebenzisa i-SmartDesign ukwenza uYilo usebenzisa i-DDR kunye neebhloko ze-SERDESIF

Eli candelo lichaza indlela yokubeka isisombululo 'sokuqalisa' esipheleleyo kunye ngaphandle kokusebenzisa iSmartFusion2 System Builder. Injongo kukukunceda uqonde into ekufuneka uyenzile ukuba awunqweneli ukusebenzisa i-System Builder. Eli candelo likwachaza ukuba isixhobo soMakhi weNkqubo sikwenzela ntoni. Eli candelo lichaza indlela yokwenza:

• Faka idatha yoqwalaselo ye-DDR isilawuli kunye neerejista zoqwalaselo zeSERDESIF.
• Qinisekisa kwaye uqhagamshele i-Fabric Cores efunekayo ukudlulisa idatha yoqwalaselo kubalawuli be-DDR kunye neerejista zokucwangcisa i-SERDESIF.

Uqwalaselo loMlawuli we-DDR
I-MSS DDR (MDDR) kunye neFabric DDR (FDDR) abalawuli kufuneka baqwalaselwe ngokuguquguqukayo (ngexesha lokuqhuba) ukuze batshatise iimfuno zoqwalaselo lwememori ye-DDR yangaphandle (imo ye-DDR, ububanzi be-PHY, imo yokuqhuma, i-ECC, njl.). Idatha efakwe kwi-MDDR/FDDR configurator ibhaliwe kwirejista yoqwalaselo lomlawuli we-DDR ngumsebenzi weCMSIS SystemInit (). I-Configurator ineethebhu ezintathu ezahlukeneyo zokungenisa iindidi ezahlukeneyo zedatha yoqwalaselo:

• Idatha ngokubanzi (imowudi ye-DDR, Ububanzi beDatha, iClock Frequency, i-ECC, i-Fabric Interface, Amandla okuqhuba)
• Idatha yokuQalisa iMemori (uBubude bokuQhutywa, uKuqhunyiswa koMyalelo, iMowudi yeXesha, ukubambezeleka, njl.njl.)
• Idatha yeXesha leMemori

Jonga kwiinkcukacha zememori yakho yangaphandle ye-DDR kwaye uqwalasele uMlawuli we-DDR ukuhambelana neemfuno zememori yakho yangaphandle ye-DDR.
Ngeenkcukacha malunga noqwalaselo lwe-DDR, jonga kwi SmartFusion2 MSS DDR Configuration User Guide.
Uqwalaselo lwe-SERDESIF
Cofa kabini ibhloko ye-SERDES kwi-SmartDesign canvas ukuvula uMcwangcisi ukuqwalasela i-SERDES (Umfanekiso 3-1). Ungangenisa la maxabiso erejista okanye usebenzise iSERDES configurator ukufaka iiparamitha zePCIe okanye zeEPCS kwaye amaxabiso erejista abalelwa wena ngokuzenzekelayo. Ngeenkcukacha, jonga kwi Isikhokelo soMsebenzisi woMsebenzisi weSERDES.Umfanekiso 3-1 • IsiQinisekiso soNxibelelwano oluPhezulu lweSyiri esiPhezulu
Ukudala i-FPGA yokuQalisa uYilo lweNkqutyana
Ukuqalisa i-DDR kunye neebhloko ze-SERDESIF, kufuneka udale inkqubo esezantsi yokuqalisa kwilaphu leFPGA. Inkqubo ephantsi yokuqaliswa kwelaphu yeFPGA ihambisa idatha ukusuka kwiCortex-M3 ukuya kwiDDR kunye neerejista zokucwangcisa zeSERDESIF, ilawula ulandelelwano lokusetha ngokutsha olufunekayo ukuze ezi bloko zisebenze kunye nemiqondiso xa ezi bloko zilungele ukunxibelelana nalo lonke uyilo lwakho. Ukwenza inkqubo esezantsi yokuqaliswa, kufuneka:

• Qwalasela FIC_2 ngaphakathi kwe-MSS
• Qinisekisa kwaye uqwalasele iCoreConfigP kunye neCoreResetP cores
• Faka i-on-chip 25/50MHz RC oscillator
• Faka kwakhona iNkqubo yokuSeta kwakhona (SYSRESET) macro
• Qhagamshela la macandelo kujongano loqwalaselo lweperipheral nganye, iiwotshi, ukusetha ngokutsha kunye ne PLL yokutshixa izibuko.

MSS FIC_2 APB Uqwalaselo
Ukumisela i-MSS FIC_2:

1. Vula ibhokisi yencoko yababini ye-FIC_2 ukusuka kwi-MSS configurator (Umfanekiso 3-2).
2. Khetha Qalisa iiperipherals usebenzisa iCortex-M3.
3. Kuxhomekeka kwindlela yakho, khangela enye okanye zombini kwezi bhokisi zilandelayo:
   – MSS DDR
   – Ilaphu le-DDR kunye/okanye iibhloko zeSERDES
4. Cofa u-Kulungile kwaye uqhubeke ukuvelisa i-MSS (ungalibazisa eli nyathelo ude ube uyiqwalasele ngokupheleleyo i-MSS kwiimfuno zakho zoyilo). Izibuko ze-FIC_2 (FIC_2_APB_MASTER, FIC_2_APB_M_PCLK kunye ne-FIC_2_APB_M_RESET_N) ngoku ziveziwe kujongano lwe-MSS kwaye zinokuqhagamshelwa kwii-CoreConfigP kunye ne-CoreResetP cores.

Isazobe 3-2 • MSS FIC_2 Configurator

I-CoreConfigP
Ukumisela i-CoreConfigP:

1. Faka i-CoreConfigP kwi-SmartDesign yakho (eqhelekile yileyo apho i-MSS imiselwe).
   Lo ngundoqo unokufumaneka kwiKhathalogi yeLibero (phantsi kweeperipherals).
2. Cofa kabini undoqo ukuvula umlungiseleli.
3. Qwalasela undoqo ukucacisa ukuba yeyiphi iperipherals ekufuneka iqaliswe (Figure 3-3)

Umfanekiso 3-3 • CoreConfigP Dialog Box

CoreResetP
Ukumisela i-CoreResetP:

1. Faka i-CoreResetP kwi-SmartDesign yakho (ngokuqhelekileyo leyo apho i-MSS imiselwe).
   Lo ngundoqo unokufumaneka kwikhathalogu yeLibero, phantsi kweeperipherals.
2. Cofa kabini undoqo ngaphakathi kwe-SmartDesign Canvas ukuvula i-Configurator (Umfanekiso 3-4).
3. Qwalasela undoqo ukuze:
   - Cacisa indlela yokuziphatha yangaphandle yokusetha kwakhona (EXT_RESET_OUT iqinisekisiwe). Khetha ibe nye kwezine onokukhetha kuzo:
   o EXT_RESET_OUT ayibaniswa
   o EXT_RESET_OUT iyabaniswa ukuba ukusetwa kwakhona kombane (POWER_ON_RESET_N) kubangisiwe
   o EXT_RESET_OUT iyabaniswa ukuba FAB_RESET_N iyabaniswa
   o EXT_RESET_OUT iyabaniswa ukuba umbane usetwe ngokutsha (POWER_ON_RESET_N) okanye FAB_RESET_N kubangisiwe
   – Chaza isixhobo Voltage. Ixabiso elikhethiweyo kufuneka lihambelane nomthamotage oyikhethileyo kwi Libero Project Izicwangciso zebhokisi yencoko yababini.
   - Jonga iibhokisi ezifanelekileyo ukubonisa ukuba zeziphi iiperipherals ozisebenzisayo kuyilo lwakho.
   - Cacisa ixesha lokuseta imemori ye-DDR yangaphandle. Eli lixabiso eliphezulu kuzo zonke iinkumbulo zeDDR ezisetyenziswa kwisicelo sakho (MDDR kunye neFDDR). Jonga kumthengisi wememori ye-DDR yangaphandle ukuqwalasela le parameter. I-200us lixabiso elihle elingagqibekanga le-DDR2 kunye neenkumbulo ze-DDR3 ezisebenza kwi-200MHz. Le yiparameter ebaluleke kakhulu ukuqinisekisa ukulinganisa okusebenzayo kunye nenkqubo yokusebenza kwi-silicon. Ixabiso elingachanekanga lexesha lokulungisa linokubangela iimpazamo zokulinganisa. Jonga kwimemori yomthengisi we-DDR yedata ukuze uqwalasele le parameter.
   Kwibhloko nganye yeSERDES kuyilo lwakho, jonga iibhokisi ezifanelekileyo ukubonisa ukuba:
   o PCIe isetyenziswa
   o Inkxaso yokuSeta ngokutsha i-PCIe eshushu iyafuneka
   o Inkxaso yePCIe L2/P2 iyafuneka

Phawula: Ukuba usebenzisa i-090 die(M2S090) kwaye uyilo lwakho lusebenzisa i-SERDESIF, akuyomfuneko ukuba ukhangele nayiphi na kwezi bhokisi zilandelayo: 'Isetyenziselwa i-PCIe', 'Bandakanya inkxaso ye-PCIe HotReset' kunye ne-'Bandakanya inkxaso ye-PCIe L2/P2'. Ukuba usebenzisa nasiphi na isixhobo esingeso-090 kwaye usebenzisa ibhloko enye okanye ezingaphezulu zeSERDESIF, kufuneka ukhangele zone iibhokisi zokukhangela phantsi kwecandelo elifanelekileyo leSERDESIF.
Phawula: Ukufumana iinkcukacha malunga nokhetho olukhoyo kuwe kulo configurator, jonga kwi-CoreResetP Handbook.

Umzobo 3-4 • CoreResetPCConfigurator

25/50MHz iOscillator Instantiation
I-CoreConfigP kunye ne-CoreResetP zivaliwe nge-on-chip 25/50MHz RC oscillator. Kufuneka uqinisekise i-Oscillator ye-25/50MHz kwaye uyiqhagamshele kwezi core.

1. Qinisekisa iChip Oscillators engundoqo kwi-SmartDesign yakho (ngokuqhelekileyo leyo apho i-MSS iqinisekisiwe). Lo ngundoqo unokufumaneka kwiKhathalogu yeLibero phantsi kweClock & Management.
2. Qwalasela le ngundoqo ukuze i-oscillator ye-RC iqhube i-FPGA ilaphu, njengoko kuboniswe kwi-Figure 3-5.

Umfanekiso 3-5 • I-Chip Oscillators Configurator

Ukusetha kwakhona inkqubo (SYSRESET) Instantiation
I-SYSRESET macro ibonelela ngenqanaba lokusetwa ngokutsha kwesixhobo kuyilo lwakho. I-POWER_ON_RESET_N isignali yemveliso iyabangwa/iyaqinisekiswa nanini na xa itshiphu inikwe amandla okanye iqhosha langaphandle DEVRST_N liyabaniswa/liyaqinisekiswa (Figure 3-6).
Faka i-SYSRESET macro kwi-SmartDesign yakho (ngokuqhelekileyo leyo apho i-MSS imiselwe). Le macro inokufumaneka kwiKhathalogu yeLibero phantsi kweThala leencwadi leMacro.Akukho lungiselelo lwale macro luyimfuneko.

Umfanekiso 3-6 • SYSRESET Macro

UQhagamshelwano lulonke
Emva kokuba umisele kwaye uqwalasele i-MSS, FDDR, SERDESIF, OSC, SYSRESET, CoreConfigP kunye neCoreResetP cores kuyilo lwakho, kufuneka uzidibanise zenze inkqubo esezantsi yokuQalisa yePeripheral. Ukwenza lula inkcazo yoqhagamshelo kolu xwebhu, yaphulwe kwi-APB3 ethobelayo yoqwalaselo lwendlela yoqhagamshelwano enxulunyaniswa neCoreConfigP kunye neCoreResetP enxulumene nemidibaniso.
UQhagamshelwano lweNdlela yoLungiso lweDatha
Umzobo 3-7 ubonisa indlela yokudibanisa i-CoreConfigP kwi-MSS FIC_2 iisignali kunye ne-peripherals' APB3 ujongano oluhambelanayo loqwalaselo.
Uluhlu 3-1 • Uqwalaselo lweNdlela yeDatha yeNdlela/uQhagamshelwano lweBIF

UKUSUKA Port/Bus Interface (BIF)/ Icandelo	KUYA I-Port/Bus Interface (BIF)/Component
I-APB S UKUSETHWA NGAPHAMBILI N/ CoreConfigP	I-APB S ISETYENZISWA NGAPHAMBILI N/ SDIF <0/1/2/3>	I-APB S ISETYENZISWA NGENXA N/ FDDR	MDDR APB S PRESE TN/MSS
APB S PCLK/CoreConfigP	APB S PCLK/SDIF	APB S PCLK/FDDR	MDDR APB S POLK/ MSS
MDDR APBslave/ CoreConfig			MDDR APB SLAVE (BIF)/MSS
SDIF<0/1/2/ 3> APBsslave/Config	I-APB KHOBOKA (BIF)/ SDIF<0/1/2/3>
FDDR APBkhoboka		Ikhoboka le-APB (BIF) / FDDR
FIC 2 APBmmaster/ CoreConfigP			FIC 2 APB MASTER/MSS

Umfanekiso 3-7 • FIC_2 APB3 uQhagamshelwano lweSistim engaphantsi

Iiwotshi kunye noSeta kwakhona uQhagamshelwano
Umzobo we-3-8 ubonisa indlela yokudibanisa i-CoreResetP kwimithombo yangaphandle yokusetha kwakhona kunye neempawu ze-peripherals zokusetha kwakhona. Ikwabonisa indlela yokudibanisa i-CoreResetP kwiimpawu zesimo songqamaniso lwewotshi ye-peripherals (imiqondiso yokutshixa i-PLL). Ukongeza, ibonisa ukuba iCoreConfigP kunye neCoreResetP ziqhagamshelwe njani.

Umfanekiso 3-8 • I-Core SF2Seta ngokutsha uQhagamshelwano lweSistim engaphantsi

Ukudala kunye nokuhlanganisa iSicelo seFirmware

Xa uthumela ngaphandle i-firmware esuka kwi-LiberoSoC (iWindow Flow yoyilo> iFirmware yokuThumela ngaphandle> iFirmware yokuThumela ngaphandle), iLibero ivelisa oku kulandelayo. files kwi /i-firmware/driver_config/ sys_config ifolda:

• sys_config.c – Iqulethe izakhiwo zedatha ezibambe amaxabiso kwiirejista zeperipheral.
• sys_config.h -Iqulethe #define iingxelo ezichaza ukuba zeziphi iiperipherals ezisetyenziselwa ukuyila kwaye kufuneka ziqaliswe.
• sys_config_mddr_define.h – Iqulethe idatha yoqwalaselo yomlawuli we-MDDR efakwe kwibhokisi yencoko yababini yokuLungiselela iiRejista.
• sys_config_fddr_define.h -Iqulethe idatha yoqwalaselo yomlawuli we-FDDR efakwe kwiiRejista zokucwangcisa ibhokisi yencoko yababini.
• sys_config_mss_clocks.h – Oku file iqulathe amaza ewotshi ye-MSS njengoko ichaziwe kwi-MSS CCC configurator. Ezi zihlandlo zisetyenziswa yikhowudi ye-CMSIS ukubonelela ngolwazi oluchanekileyo lwewotshi kuninzi lwabaqhubi be-MSS ekufuneka babenokufikelela kwi-Pripheral Clock (PCLK) frequency (umzekelo, i-MSS UART abahluli bezinga le-baud ngumsebenzi wezinga le-baud kunye ne-PCLK frequency ).
• sys_config_SERDESIF_ .c – Iqulathe iSERDESIF_ Ubhaliso lwedatha enikezelweyo ngexesha le-SERDESIF_ uqwalaselo lwebhloko kwindalo yoyilo.
• sys_config_SERDESIF_ .h -Iqulethe #define izitetimenti ezichaza inani lezibini zokucwangciswa kwerejista kunye nenombolo yendlela efuna ukuvotelwa i-PMA_READY (kuphela kwimodi ye-PCIe).

Ezi files ziyafuneka ukuze ikhowudi yeCMSIS iqulunqe ngokufanelekileyo kwaye iqulathe ulwazi malunga noyilo lwakho lwangoku, ukuquka idatha yoqwalaselo lweperipheral kunye nolwazi loqwalaselo lwewotshi ye-MSS.
Sukuzihlela ezi files ngesandla; zidalwe kuluhlu oluhambelanayo/abalawuli beeperipheral ngalo lonke ixesha amacandelo e-SmartDesign aqulathe iiperipherals ezifanelekileyo zenziwe. Ukuba kukho naluphi na utshintsho olwenziwayo kwidatha yoqwalaselo yayo nayiphi na iperipherals, kufuneka uphinde ukhuphele ngaphandle iiprojekthi ze-firmware ukuze i-firmware ehlaziyiweyo. files (jonga uluhlu olungasentla) zithunyelwa ngaphandle kwi / firmware/drivers_config/sys_config ifolda.
Xa uthumela ngaphandle i-firmware, i-Libero SoC yenza iiprojekthi ze-firmware: ithala leencwadi apho ulungelelwaniso lwakho loyilo files nabaqhubi ziqokelelwe.
Ukuba ujonga iYenza iprojekthi ibhokisi yokukhangela xa uthumela ngaphandle i-firmware, isoftware yeSoftConsole/IAR/Keil yeprojekthi iyadalwa ukubamba iprojekthi yesicelo apho unokuhlela khona i-main.c kunye nomsebenzisi C/H files. Vula iprojekthi yeSoftConSole/IAR/Keil ukuze uqokelele ikhowudi ye-CMSIS ngokuchanekileyo kwaye ube nesicelo sakho se-firmware esilungiselelwe ngokufanelekileyo ukuhambelana noyilo lwakho lwe-hardware.

BFM Files Isetyenziselwa ukulinganisa uYilo

Xa uvelisa izinto zeSmartDesign eziqulathe iiperipherals ezinxulumene noyilo lwakho, ukulinganisa files ezihambelana neeperipherals ezichaphazelekayo ziveliswa kwi /ukulinganisa ulawulo:

• uvavanyo.bfm – Inqanaba eliphezulu BFM file eqala ukwenziwa ngalo naluphi na ufaniso olusebenzisa iprosesa yeSmartFusion2 MSS Cortex-M3. Iphumeza peripheral_init.bfm kunye ne-user.bfm, ngaloo ndlela.
• MDDR_init.bfm Ukuba uyilo lwakho lusebenzisa i-MDDR, iLibero ivelisa oku file; iqulethe imiyalelo yokubhala ye-BFM elinganisa ukubhalwa kwedatha yerejista yoqwalaselo ye-MSS DDR oyifakileyo (usebenzisa i-Hlela iirejista zeebhokisi yencoko yababini okanye kwi-MSS_MDDR GUI) kwiirejista zoMlawuli we-MSS DDR.
• FDDR_init.bfm Ukuba uyilo lwakho lusebenzisa i-FDDR, i-Libero ivelisa oku file; iqulethe imiyalelo yokubhala ye-BFM elinganisa ukubhalwa kwedatha yerejista yoqwalaselo lweFabric DDR oyifakileyo (usebenzisa ibhokisi yencoko yababini yokuHlela iirejista okanye kwi-FDDR GUI) kwiirejista zoMlawuli weFabric DDR.
• I-SERDESIF_ _init.bfm -Ukuba uyilo lwakho lusebenzisa ibhloko enye okanye ngaphezulu kweSERDESIF, iLibero ivelisa oku file kwiSERDESIF_ nganye iibhloko ezisetyenzisiweyo; iqulethe imiyalelo yokubhala ye-BFM elinganisa ukubhalwa kwedatha yerejista yoqwalaselo ye-SERDESIF oyifakileyo (usebenzisa ibhokisi yencoko yababini yokuHlela iirejista okanye kwiSERDESIF_ GUI) kwiSERDESIF_ iirejista. Ukuba ibhloko yeSERDESIF iqwalaselwe njengePCIe, oku file kwakhona inezinye #define iingxelo ezilawula ukuphunyezwa kwezigaba ze-2 zoqwalaselo lwerejista ngolungelelwano olugqibeleleyo.
• umsebenzisi.bfm -Iqulethe imiyalelo yomsebenzisi. Le miyalelo iyenziwa emva kokuba peripheral_init.bfm igqityiwe. Hlela oku file ukufaka imiyalelo yakho ye-BFM.
• I-SERDESIF_ _umsebenzisi.bfm -Iqulethe imiyalelo yomsebenzisi. Hlela oku file ukufaka imiyalelo yakho ye-BFM. Sebenzisa oku ukuba uqwalasele iSERDESIF_ ibhlokhi kwimodi yokulinganisa ye-BFM PCIe kwaye njengenkosi ye-AXI/AHBLite. Ukuba uqwalasele iSERDESIF_ block kwimo yokulinganisa ye-RTL, awuyi kufuna oku file.

Xa ubiza ukulinganisa ngalo lonke ixesha, ezi zifaniso zimbini zilandelayo files zenziwe kwakhona kwi /umfanekiso weefayili onemixholo ehlaziyiweyo:

• inkqubo engaphantsi.bfm -Iqulethe #define iinkcazo zeperipheral nganye esetyenziswe kuyilo lwakho, echaza icandelo elithile leperipheral_init.bfm ekufuneka iphunyezwe ngokuhambelana neperipheral nganye.
• operipheral_init.bfm – Iqulethe inkqubo ye-BFM exelisa i-CMSIS :: SystemInit () umsebenzi oqhutywa kwi-Cortex-M3 phambi kokuba ufake inkqubo engundoqo (). Ikhuphela idatha yoqwalaselo yayo nayiphi na iperipheral esetyenziswe kuyilo kwiirejista zoqwalaselo ezichanekileyo ze peripheral ize ilinde zonke iiperipherals ukuba zilungile phambi kokuba iqinisekise ukuba ungasebenzisa ezi peripherals. Iqhuba i-MDDR_init.bfm kunye ne-FDDR_init.bfm.

Ukusebenzisa ezi zenziwe files, abalawuli be-DDR kuyilo lwakho baqwalaselwe ngokuzenzekelayo, belinganisa oko kuya kwenzeka kwisixhobo se-SmartFusion2. Ungahlela umsebenzisi.bfm file ukongeza nayiphi na imiyalelo efunekayo ukulinganisa uyilo lwakho (iCortex-M3 yinkosi). Le miyalelo iyenziwa emva kokuba iiperipherals ziqalisiwe. Sukuhlela test.bfm, subsystem.bfm, peripheral_init.bfm, MDDR_init.bfm, FDDR_init.bfm files kunye neSERDESIF_ _init.bfm files.

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UMlawuli we-Microsemi SmartFusion2 DDR kunye noMlawuli oPhezulu weSyri [pdf] Isikhokelo somsebenzisi I-SmartFusion2 DDR isiLawuli kunye nesiLawuli esiPhezulu esiPhezulu, iSmartFusion2 DDR, isiLawuli kunye nesiLawuli esiPhezulu esiPhezulu, isiLawuli esiPhezulu esiPhezulu.

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