SmartFusion2
DDR Controller ndi Serial High Speed ​​​​Controller
Initialization Methodology
Wogwiritsa Ntchito

Mawu Oyamba

Mukapanga mapangidwe pogwiritsa ntchito chipangizo cha SmartFusion2, ngati mugwiritsa ntchito imodzi mwa olamulira awiri a DDR (FDDR kapena MDDR) kapena midadada iliyonse ya seri High speed controller (SERDESIF), muyenera kuyambitsa kaundula kasinthidwe ka midadadayi pa nthawi yothamanga isanafike. atha kugwiritsidwa ntchito. Za example, kwa DDR controller, muyenera kukhazikitsa DDR mode (DDR3/DDR2/LPDDR), PHY m'lifupi, njira yophulika ndi ECC.
Mofananamo, pa chipika cha SERDESIF chomwe chimagwiritsidwa ntchito ngati pomaliza PCIe, muyenera kukhazikitsa PCIE BAR ku zenera la AXI (kapena AHB).
Chikalatachi chikufotokoza njira zofunika kuti mupange mapangidwe a Libero omwe amangoyambitsa owongolera a DDR ndipo SERDESIF imatchinga pamagetsi. Ikufotokozanso momwe mungapangire khodi ya firmware kuchokera ku Libero SOC yomwe imagwiritsidwa ntchito pamapangidwe ophatikizidwa.
Kufotokozera mwatsatanetsatane kwa chiphunzitso cha ntchito kumaperekedwa poyamba.
Gawo lotsatira likufotokoza momwe mungapangire mapangidwe otere pogwiritsa ntchito Libero SoC System Builder, chida champhamvu chojambula chomwe, pakati pa zinthu zina, chimakupangirani yankho la 'kuyambitsa' ngati mukugwiritsa ntchito DDR kapena SERDESIF midadada pakupanga kwanu.
Gawo lotsatira likufotokoza momwe mungayikitsire yankho lathunthu "loyambitsa" popanda kugwiritsa ntchito SmartFusion2 System Builder. Izi zimathandiza kufotokoza zomwe muyenera kuchita ngati simukufuna kugwiritsa ntchito System Builder, komanso kufotokozera zomwe chida cha System Builder chimakupangirani. Gawoli likunena:

• Kupanga deta yosinthira kwa DDR controller ndi SERDESIF configuration registry
• Kupanga malingaliro a FPGA ofunikira kusamutsa zosintha kumakaundula osiyanasiyana a ASIC.

Pomaliza tikufotokozera zomwe zidapangidwa filezikugwirizana ndi:

• Kupanga kwa firmware 'initialization' yankho.
• Kuyerekeza kwa mapangidwe a yankho la DDR 'initialization'.

Kuti mudziwe zambiri za DDR controller ndi SERDESIF kasinthidwe kaundula, onani Microsemi SmartFusion2 High Speed ​​​​Seri ndi DDR Interfaces User's Guide.

Chiphunzitso cha Ntchito

The Peripheral initialization solution imagwiritsa ntchito zigawo zikuluzikulu izi:

• Ntchito ya CMSIS SystemInit(), yomwe imayenda pa Cortex-M3 ndikuwongolera njira yoyambira.
• CoreConfigP yofewa IP core, yomwe imayambitsa zolembera zosinthira zotumphukira.
• CoreResetP yofewa IP core, yomwe imayang'anira kukonzanso kwa ma MSS, olamulira a DDR, ndi ma block a SERDESIF.

Njira yoyambira yolumikizira imagwira ntchito motere:

1. Mukayambiranso, Cortex-M3 imayendetsa ntchito ya CMSIS SystemInit (). Izi zimangochitika zokha ntchito yayikulu () ya pulogalamuyo isanapangidwe.
   Chizindikiro cha CoreResetP chotulutsa MSS_HPMS_READY chimatsimikiziridwa kumayambiriro kwa ndondomeko yoyambira, kusonyeza kuti MSS ndi zotumphukira zonse (kupatula MDDR) ndi okonzeka kulankhulana.
2. Ntchito ya SystemInit() imalemba zosunga zobwezeretsera kwa owongolera a DDR ndi kaundula wa kasinthidwe ka SERDESIF kudzera pa basi ya MSS FIC_2 APB3. Mawonekedwewa amalumikizidwa ndi CoreConfigP yofewa yokhazikika munsalu ya FPGA.
3. Ma regista onse atakonzedwa, ntchito ya SystemInit () imalemba ku ma registala owongolera a CoreConfigP kuwonetsa kutha kwa gawo lokonzekera kaundula; zotulutsa za CoreConfigP CONFIG1_DONE ndi CONIG2_DONE zimatsimikiziridwa.
   Pali magawo awiri a kasinthidwe ka registry (CONFIG1 ndi CONFIG2) kutengera zotumphukira zomwe zimagwiritsidwa ntchito popanga.
4. Ngati chimodzi kapena zonse za MDDR/FDDR zikugwiritsidwa ntchito, ndipo palibe midadada ya SERDESIF yomwe imagwiritsidwa ntchito popanga, pali gawo limodzi lokha lokonzekera kaundula. Zizindikiro zonse za CoreConfigP CONFIG1_DONE ndi CONIG2_DONE zimatsitsidwa chimodzi pambuyo pa chimzake popanda kudikirira/kuchedwa.
   Ngati midadada imodzi kapena zingapo za SERDESIF mumayendedwe osakhala a PCIe zimagwiritsidwa ntchito popanga, pali gawo limodzi lokha la kasinthidwe ka registry. CONFIG1_DONE ndi CONIG2_DONE amatsimikiziridwa chimodzi pambuyo pa chimzake popanda kudikirira/kuchedwa.
   Ngati midadada imodzi kapena zingapo za SERDESIF mu PCIe zikugwiritsidwa ntchito pakupanga, pali magawo awiri a kasinthidwe ka registry. CONFIG1_DONE imatsimikiziridwa kuti gawo loyamba la kasinthidwe kaundula litatha. Dongosolo la SERDESIF ndi zolembera zamsewu zakonzedwa mugawoli. Ngati SERDESIF isinthidwa mwanjira yomwe si PCIE, chizindikiro cha CONFIG2_DONE chimatsimikiziridwanso nthawi yomweyo.
5. Gawo lachiwiri la kasinthidwe ka kaundula kenaka limatsatira (ngati SERDESIF yakhazikitsidwa mu PCIE mode). Zotsatirazi ndi zochitika zosiyanasiyana zomwe zimachitika mu gawo lachiwiri:
   - CoreResetP imatsimikizira PHY_RESET_N ndi CORE_RESET_N ma siginecha ofanana ndi midadada iliyonse ya SERDESIF yomwe imagwiritsidwa ntchito. Imatsimikiziranso chizindikiro chotulutsa SDIF_RELEASED midadada yonse ya SERDESIF itayimitsidwa. Chizindikiro cha SDIF_RELEASEDchi chimagwiritsidwa ntchito kusonyeza ku CoreConfigP kuti phata la SERDESIF lathetsedwa ndipo lakonzekera gawo lachiwiri la kasinthidwe ka registry.
   - Chizindikiro cha SDIF_RELEASED chikatsimikiziridwa, ntchito ya SystemInit() imayamba kuvota kuti PMA_READY iwonetsere njira yoyenera ya SERDESIF. PMA_READY ikangotsimikiziridwa, gulu lachiwiri la zolembera za SERDESIF (PCIE registas) zimakonzedwa/zolembedwa ndi SystemInit() ntchito.
6. Ma regista onse a PCIE atakonzedwa, ntchito ya SystemInit () imalemba ku registry control ya CoreConfigP kuwonetsa kutha kwa gawo lachiwiri la kasinthidwe ka registry; chizindikiro cha CoreConfigP CONIG2_DONE chimatsimikiziridwa.
7. Kupatula zomwe zanenedwa pamwambapa, CoreResetP imayang'aniranso kukhazikitsidwa kwa midadada yosiyanasiyana pochita izi:
   - Kutsimikizira kukonzanso koyambira kwa FDDR
   - Kutsutsa SERDESIF kumatchinga PHY ndi CORE kukonzanso
   - Kuyang'anira chizindikiro cha loko ya FDDR PLL (FPLL). FPLL iyenera kuti idatseka kuti itsimikizire kuti mawonekedwe a data a FDDR AXI/AHBLite ndi nsalu ya FPGA imatha kulumikizana bwino.
   - Kuyang'anira zikwangwani za SERDESIF block PLL (SPLL). SPLL iyenera kukhala yotseka kutsimikizira kuti SERDESIF imatchinga mawonekedwe a AXI/AHBLite (PCIe mode) kapena mawonekedwe a XAUI amatha kulumikizana bwino ndi nsalu ya FPGA.
   - Kudikirira zokumbukira zakunja za DDR kuti zikhazikike ndikukhala okonzeka kupezeka ndi olamulira a DDR.
8. Zotumphukira zonse zikamaliza kuyambitsa, CoreResetP imatsimikizira chizindikiro cha INIT_DONE; kaundula wamkati wa CoreConfigP INIT_DONE amatsimikiziridwa.
   Ngati imodzi kapena onse a MDDR/FDDR agwiritsidwa ntchito, ndipo nthawi yoyambitsa DDR yafika, chizindikiro cha CoreResetP DDR_READY chimatsimikiziridwa. Kutsimikizira kwa chizindikiro ichi DDR_READY kutha kuyang'aniridwa ngati chisonyezero chakuti DDR (MDDR/FDDR) ndiyokonzeka kulankhulana.
   Ngati midadada imodzi kapena zingapo za SERDESIF zitagwiritsidwa ntchito, ndipo gawo lachiwiri la kasinthidwe kaundula wamalizidwa bwino, CoreResetP yotulutsa chizindikiro SDIF_READY imatsimikiziridwa. Kutsimikizira kwa chizindikiro ichi SDIF_READY kutha kuyang'aniridwa ngati chisonyezero chakuti midadada yonse ya SERDESIF ili okonzeka kulankhulana.
9. Ntchito ya SystemInit (), yomwe yakhala ikudikirira INIT_DONE kuti inenedwe, itsirizidwe, ndipo ntchito yayikulu () ya pulogalamuyo ichitike. Panthawiyo, olamulira onse a DDR ogwiritsidwa ntchito ndi midadada ya SERDESIF adayambitsidwa, ndipo pulogalamu ya firmware ndi logic ya nsalu ya FPGA imatha kulankhulana nawo modalirika.

Njira yomwe yafotokozedwa m'chikalatachi imadalira Cortex-M3 poyambitsa njira yoyambira ngati gawo lachikhazikitso cha dongosolo lomwe lidakhazikitsidwa ntchito isanayambe ()kugwiritsa ntchito.
Onani Mawonekedwe Oyenda mu Chithunzi 1-1, Chithunzi 1-2 ndi Chithunzi 1-3 pamayendedwe oyambira a FDDR/MDDR, SEREDES(non-PCIe mode) ndi SERDES (PCIe mode).
Chithunzi 1-4 chikuwonetsa chojambula cha nthawi yoyambira.

Chithunzi 1-3 • SerdESIF (PCIe) Tchati Choyambitsa Kuyenda
Njira yoyambira yomwe yafotokozedwa m'chikalatachi ikufuna kuti muthamangitse Cortex-M3 panthawi yoyambira, ngakhale simukukonzekera kuyendetsa khodi iliyonse pa Cortex-M3. Muyenera kupanga pulogalamu yoyambira ya firmware yomwe sichita kalikonse (lopu yosavuta, mwachitsanzoample) ndikuyika zomwe zingatheke mu Non Volatile Memory (eNVM) kuti olamulira a DDR ndi ma block a SERDESIF ayambitsidwe pomwe Cortex-M3 iyamba.

Kugwiritsa Ntchito System Builder Kupanga Design Pogwiritsa Ntchito DDR ndi SERDESIF Blocks

SmartFusion2 System Builder ndi chida champhamvu chopangira chomwe chimakuthandizani kujambula zomwe mukufuna pamakina anu ndikupanga mapangidwe kuti akwaniritse zomwe mukufuna. Ntchito yofunikira kwambiri ya System Builder ndikudzipangira yokha ya Peripheral Initialization sub-system. "Kugwiritsa Ntchito SmartDesign Kupanga Mapangidwe Pogwiritsa Ntchito DDR ndi SERDESIF Blocks" patsamba 17 limafotokoza mwatsatanetsatane momwe mungapangire yankho lotere popanda Wopanga System.
Ngati mukugwiritsa ntchito System Builder, muyenera kuchita zotsatirazi kuti mupange mapangidwe omwe amayambira owongolera anu a DDR ndi ma block a SERDESIF pakukweza:

1. Patsamba la Zida Zachipangizo (Chithunzi 2-1), tchulani olamulira a DDR omwe amagwiritsidwa ntchito ndi ma block angati a SERDESIF omwe amagwiritsidwa ntchito pakupanga kwanu.
2. Patsamba la Memory, tchulani mtundu wa DDR (DDR2/DDR3/LPDDR) ndi zosintha zamakumbukiro anu akunja a DDR. Onani gawo la Memory Page kuti mumve zambiri.
3. Patsamba la Peripherals, onjezani makina opanga nsalu opangidwa ngati AHBLite/AXI ku Fabric DDR Subsystem ndi/kapena MSS DDR FIC Subsystem (posankha).
4. Patsamba la Zikhazikiko za Clock, tchulani maulendo a wotchi ya DDR sub-systems.
5. Malizitsani mapangidwe anu ndikudina Finish. Izi zimapanga mapangidwe opangidwa ndi System Builder, kuphatikiza malingaliro ofunikira pa yankho la 'kuyambitsa'.
6. Ngati mukugwiritsa ntchito midadada ya SERDESIF, muyenera kuyika midadada ya SERDESIF pakupanga kwanu ndikulumikiza madoko awo oyambira ndi omwe apangidwa ndi System Builder.

Tsamba la Zida Zomanga Zadongosolo
Patsamba la Zida Zachipangizo, tchulani zowongolera za DDR (MDDR ndi/kapena FDDR) zomwe zimagwiritsidwa ntchito komanso midadada ingati ya SERDESIF yomwe imagwiritsidwa ntchito pakupanga kwanu (Chithunzi 2-1).

Chithunzi 2-1 • Tsamba la Zida Zopangira Zomangamanga

Tsamba la Memory Builder System
Kuti mugwiritse ntchito MSS DDR (MDDR) kapena Fabric DDR (FDDR), sankhani Mtundu wa Memory kuchokera pamndandanda wotsitsa (Chithunzi 2-2).

Chithunzi 2-2 • Kukumbukira Kwakunja kwa MSS

Mukuyenera:

1. Sankhani mtundu wa DDR (DDR2, DDR3 kapena LPDDR).
2. Fotokozani nthawi yokhazikika ya DDR. Onani Zofotokozera za Memory Memory yanu yakunja ya DDR kuti mukhazikitse nthawi yoyenera kukumbukira. Memory DDR ikhoza kulephera kuyambitsa bwino ngati nthawi yokhazikitsira kukumbukira sinakhazikitsidwe bwino.
3. Kapena lowetsani zambiri za kasinthidwe ka DDR kapena ikani DDR Memory Parameters. Kuti mudziwe zambiri, onani Microsemi SmartFusion2 High Speed ​​​​Seri ndi DDR Interfaces User's Guide.

Deta iyi imagwiritsidwa ntchito kupanga kaundula wa DDR BFM ndi kasinthidwe ka firmware files monga momwe zafotokozedwera mu "Kupanga ndi Kupanga Pulogalamu ya Firmware" patsamba 26 ndi "BFM Files Amagwiritsidwa Ntchito Pakufanizira Mapangidwe” patsamba 27. Kuti mudziwe zambiri za kaundula wa kasinthidwe ka DDR, onani Microsemi SmartFusion2 High Speed ​​​​Seri ndi DDR Interfaces User's Guide.
Wakaleample la kasinthidwe file mawu akuwonetsedwa mu Chithunzi 2-3. Mayina olembetsa omwe amagwiritsidwa ntchito mu izi file ndizofanana ndi zomwe zafotokozedwa m'nkhaniyi Microsemi SmartFusion2 High Speed ​​​​Seri ndi DDR Interfaces User's Guide

Chithunzi 2-3 • Kukonzekera File Syntax Example
Tsamba la System Builder Peripherals
Patsamba la Peripherals, kwa wowongolera aliyense wa DDR kagawo kakang'ono kamapangidwa (Nsalu DDR Subsystem ya FDDR ndi MSS DDR FIC Subsystem ya MDDR). Mutha kuwonjezera Fabric AMBA Master (yosinthidwa ngati AXI/AHBLite) pachimake pa chilichonse mwazinthuzi kuti muthe kugwiritsa ntchito bwino nsalu kwa olamulira a DDR. Pam'badwo, System Builder imangoyambitsa ma cores (kutengera mtundu wa AMBA Master wowonjezera) ndikuwulula master BIF wapakati pa basi ndi wotchi ndikukhazikitsanso ma pini a subsystems (FDDR/MDDR) pansi pamagulu oyenera a pini, ku pamwamba. Zomwe muyenera kuchita ndikulumikiza ma BIF ku ma cores a Fabric Master oyenera omwe mungawakhazikitse pamapangidwewo. Pankhani ya MDDR, ndizosankha kuwonjezera Chisalu cha AMBA Master pachimake ku MSS DDR FIC Subsystem; Cortex-M3 ndi mbuye wokhazikika pa subsystem iyi. Chithunzi 2-4 chikuwonetsa Tsamba la Zomangamanga Zomangamanga.

Chithunzi 2-4 • Tsamba la Zomangamanga Zomangamanga

Tsamba la Zikhazikiko za Clock Builder System
Patsamba la Zikhazikiko za Clock, pa wowongolera aliyense wa DDR, muyenera kufotokozera mawotchi okhudzana ndi kachitidwe kakang'ono ka DDR (MDDR ndi/kapena FDDR).
Kwa MDDR, muyenera kufotokoza:

• MDDR_CLK - Wotchi iyi imatsimikizira kuchuluka kwa ntchito kwa DDR Controller ndipo iyenera kufanana ndi mawotchi omwe mukufuna kuti DDR yanu yakunja igwire. Wotchi iyi imatanthauzidwa ngati yochulukitsa ya M3_CLK (Cortex-M3 ndi MSS Main Clock, Chithunzi 2-5). MDDR_CLK ikuyenera kukhala yochepera 333 MHz.
• DDR_FIC_CLK - Ngati mwasankha kupezanso MDDR kuchokera ku nsalu ya FPGA, muyenera kufotokoza DDR_FIC_CLK. Mafupipafupi a wotchiyi amatanthauzidwa ngati chiŵerengero cha MDDR_CLK ndipo akuyenera kufanana ndi mafupipafupi omwe makina a FPGA omwe amapeza MDDR akuyenda.

Chithunzi 2-5 • Cortex-M3 ndi MSS Main Clock; Mawotchi a MDDR

Kwa FDDR, muyenera kufotokoza:

• FDDR_CLK - Imatsimikizira kuchuluka kwa magwiridwe antchito a DDR Controller ndipo iyenera kufanana ndi ma frequency a wotchi yomwe mukufuna kuti kukumbukira kwanu kwa DDR kuyendetse. Dziwani kuti wotchiyi imatanthauzidwa ngati yochulukitsa ya M3_CLK (MSS ndi Cortex-M3 wotchi, Chithunzi 2-5). FDDR_CLK iyenera kukhala mkati mwa 20 MHz ndi 333 MHz.
• FDDR_SUBSYSTEM_CLK - Mafupipafupi a wotchiyi amatanthauzidwa ngati chiŵerengero cha FDDR_CLK ndipo amayenera kufanana ndi mafupipafupi omwe FPGA sub-system yomwe imapeza FDDR ikugwira ntchito.

Chithunzi 2-6 • Nsalu DDR Mawotchi
Kusintha kwa SERDESIF
Ma block a SERDESIF samakhazikika pamapangidwe opangidwa ndi System Builder. Komabe, pazitsulo zonse za SERDESIF, zizindikiro zoyambira zimapezeka pa mawonekedwe a System Builder pachimake ndipo akhoza kulumikizidwa ku SERDESIF cores pa mlingo wotsatira wa utsogoleri, monga momwe tawonetsera pa Chithunzi 2-7.Chithunzi 2-7 • Kulumikizana kwa SERDESIF Peripheral Initialization
Mofanana ndi ma DDR kasinthidwe kaundula, chipika chilichonse cha SERDES chilinso ndi zolembera zosinthira zomwe ziyenera kuyikidwa panthawi yothamanga. Mutha kuitanitsa zolembetsa izi kapena kugwiritsa ntchito High Speed ​​Serial Interface Configurator (Chithunzi 2-8) kuti mulowetse magawo anu a PCIe kapena EPCS ndipo ma registanti amakuwerengerani zokha. Kuti mudziwe zambiri, onani SERDES Configurator User Guide.Chithunzi 2-8 • High Speed ​​Serial Interface Configurator
Mukaphatikiza malingaliro anu ogwiritsa ntchito ndi chipika cha System Builder ndi SERDES block, mutha kupanga SmartDesign yanu yapamwamba. Izi zimapanga HDL zonse ndi BFM filezomwe ndizofunikira kuti mugwiritse ntchito ndikufanizira kapangidwe kanu. Mutha kupitiliza ndi zina zonse za Design Flow.

Kugwiritsa Ntchito SmartDesign Kupanga Mapangidwe Pogwiritsa Ntchito DDR ndi SERDESIF Blocks

Gawoli likufotokoza momwe mungayikitsire yankho lathunthu "loyambitsa" popanda kugwiritsa ntchito SmartFusion2 System Builder. Cholinga chake ndikukuthandizani kumvetsetsa zomwe muyenera kuchita ngati simukufuna kugwiritsa ntchito System Builder. Gawoli likufotokozeranso zomwe chida cha System Builder chimakupangirani. Gawoli likufotokoza momwe:

• Lowetsani zosintha za DDR controller ndi SERDESIF configuration registry.
• Yambitsani ndikugwirizanitsa Zida Zopangira Zofunika kuti mutumize deta yokonzekera kwa olamulira a DDR ndi SERDESIF configuration registry.

Kukonzekera kwa DDR Controller
Olamulira a MSS DDR (MDDR) ndi Nsalu DDR (FDDR) ayenera kukonzedwa mwamphamvu (pa nthawi yothamanga) kuti agwirizane ndi zofunikira za kasinthidwe ka DDR (DDR mode, PHY wide, burst mode, ECC, etc.). Deta yomwe yalowetsedwa mu MDDR/FDDR configurator imalembedwa ku DDR configuration registry ndi CMSIS SystemInit() ntchito. Configurator ili ndi ma tabo atatu osiyanasiyana olowetsa mitundu yosiyanasiyana yamasinthidwe:

• Zambiri (DDR mode, Deta Width, Clock Frequency, ECC, Fabric Interface, Drive Strength)
• Memory Initialization data (Utali Wophulika, Kuphulika Kwadongosolo, Nthawi Yanthawi, Kuchedwa, ndi zina zotero)
• Memory Time Data

Fotokozerani zomwe mumakumbukira za DDR yanu yakunja ndikukonza DDR Controller kuti igwirizane ndi zofunikira za DDR yanu yakunja.
Kuti mumve zambiri pakusintha kwa DDR, onani tsamba la SmartFusion2 MSS DDR Configuration User Guide.
Kusintha kwa SERDESIF
Dinani kawiri chipika cha SERDES mu SmartDesign canvas kuti mutsegule Configurator kuti mukonze SERDES (Chithunzi 3-1). Mutha kuitanitsa zinthu zolembetsera izi kapena kugwiritsa ntchito kasinthidwe ka SEDES kuti mulowetse magawo anu a PCIe kapena EPCS ndipo misinkhu yolembetsa imakuwerengerani zokha. Kuti mudziwe zambiri, onani SERDES Configurator User Guide.Chithunzi 3-1 • High Speed ​​Serial Interface Configurator
Kupanga FPGA Design Initialization Sub-System
Kuti muyambitse midadada ya DDR ndi SERDESIF, muyenera kupanga makina oyambira pansalu ya FPGA. Dongosolo loyambitsa nsalu la FPGA limasuntha deta kuchokera ku Cortex-M3 kupita ku DDR ndi kaundula wa kasinthidwe ka SERDESIF, imayang'anira kukonzanso kofunikira kuti midadada iyi igwire ntchito ndi ma sign pamene midadada iyi yakonzeka kulumikizana ndi mapangidwe anu onse. Kuti mupange subsystem yoyambira, muyenera:

• Konzani FIC_2 mkati mwa MSS
• Yambitsani ndi kukonza CoreConfigP ndi CoreResetP cores
• Yambitsani pa-chip 25/50MHz RC oscillator
• Yambitsani System Reset (SYSRESET) macro
• Gwirizanitsani zigawo izi ku mawonekedwe a zotumphukira zilizonse, mawotchi, kukonzanso ndi madoko a PLL.

Kukonzekera kwa MSS FIC_2 APB
Kukonza MSS FIC_2:

1. Tsegulani FIC_2 configurator dialog box kuchokera ku MSS configurator (Chithunzi 3-2).
2. Sankhani Yambitsani zotumphukira pogwiritsa ntchito Cortex-M3.
3. Kutengera ndi kachitidwe kanu, chongani chimodzi kapena onse awiri mwamabokosi otsatirawa:
   - MSS DDR
   - Nsalu za DDR ndi/kapena SERDES Blocks
4. Dinani Chabwino ndikupitiriza kupanga MSS (mukhoza kuchedwetsa izi mpaka mutakonza MSS kuti igwirizane ndi zomwe mukufuna). Madoko a FIC_2 (FIC_2_APB_MASTER, FIC_2_APB_M_PCLK ndi FIC_2_APB_M_RESET_N) tsopano ali powonekera pa mawonekedwe a MSS ndipo akhoza kulumikizidwa ku CoreConfigP ndi CoreResetP cores.

Chithunzi 3-2 • MSS FIC_2 Configurator

CoreConfigP
Kusintha CoreConfigP:

1. Yambitsani CoreConfigP mu SmartDesign yanu (makamaka yomwe MSS imakhazikitsidwa).
   Pachimake ichi chikhoza kupezeka mu Libero Catalogue (pansi pa Peripherals).
2. Dinani kawiri pachimake kuti mutsegule configurator.
3. Konzani pachimake kuti mutchule zotumphukira zomwe zikuyenera kukhazikitsidwa (Chithunzi 3-3)

Chithunzi 3-3 • CoreConfigP Dialog Bokosi

CoreResetP
Kusintha CoreResetP:

1. Yambitsani CoreResetP mu SmartDesign yanu (makamaka yomwe MSS imakhazikitsidwa).
   Pachimake ichi chikhoza kupezeka mu Libero Catalogue, pansi pa Peripherals.
2. Dinani kawiri pachimake mkati mwa SmartDesign Canvas kuti mutsegule Configurator (Chithunzi 3-4).
3. Konzani core kukhala:
   - Tchulani machitidwe obwezeretsanso akunja (EXT_RESET_OUT atsimikiza). Sankhani chimodzi mwa zosankha zinayi:
   o EXT_RESET_OUT sichinatsimikizidwe
   o EXT_RESET_OUT imatsimikiziridwa ngati kuyimitsanso kuyimitsa (POWER_ON_RESET_N) kutsimikiziridwa
   o EXT_RESET_OUT imatsimikiziridwa ngati FAB_RESET_N itsimikiziridwa
   o EXT_RESET_OUT imatsimikiziridwa ngati kuyimitsanso (POWER_ON_RESET_N) kapena FAB_RESET_N kutsimikiziridwa
   - Tchulani Chipangizo Voltage. Mtengo wosankhidwa uyenera kufanana ndi voliyumutage mwasankha mu bokosi la zokambirana la Libero Project Settings.
   - Chongani mabokosi oyenerera kuti muwonetse zotumphukira zomwe mukugwiritsa ntchito pakupanga kwanu.
   - Tchulani nthawi yakunja ya kukumbukira kwa DDR. Uwu ndiye mtengo wapamwamba pazokumbukira zonse za DDR zomwe zimagwiritsidwa ntchito mu pulogalamu yanu (MDDR ndi FDDR). Onani ku data yakunja ya DDR memory vedor kuti mukonze izi. 200us ndi mtengo wabwino wosasinthika wa kukumbukira kwa DDR2 ndi DDR3 komwe kukuyenda pa 200MHz. Ichi ndi gawo lofunikira kwambiri lotsimikizira kuyerekezera kogwira ntchito komanso kachitidwe kogwira ntchito pa silicon. Mtengo wolakwika wa nthawi yokhazikika ukhoza kubweretsa zolakwika zofananira. Onani tsatanetsatane wa DDR memory vedor kuti mukonze izi.
   - Pa block iliyonse ya SERDES pamapangidwe anu, chongani mabokosi oyenerera kuti muwonetse ngati:
   o PCIe amagwiritsidwa ntchito
   o Kuthandizira kwa PCIe Hot Reset ndikofunikira
   o Kuthandizira kwa PCIe L2/P2 ndikofunikira

Zindikirani: Ngati mukugwiritsa ntchito 090 die(M2S090) ndipo kapangidwe kanu kamagwiritsa ntchito SEDESIF, simukuyenera kuchonga chilichonse mwamabokosi otsatirawa: 'Ogwiritsidwa Ntchito pa PCIe', 'Phatikizani chithandizo cha PCIe HotReset' ndi 'Phatikizani chithandizo cha PCIe L2/P2'. Ngati mukugwiritsa ntchito chipangizo chilichonse chomwe si-090 ndikugwiritsa ntchito midadada imodzi kapena zingapo za SERDESIF, muyenera kuyang'ana mabokosi onse anayi pansi pa gawo loyenera la SERDESIF.
Zindikirani: Kuti mumve zambiri pazomwe mungapeze mu kasinthidwe aka, onani buku la CoreResetP Handbook.

Chithunzi 3-4 • CoreResetPCConfigurator

25/50MHz Oscillator Instantiation
CoreConfigP ndi CoreResetP zili ndi wotchi ya on-chip 25/50MHz RC oscillator. Muyenera kukhazikitsa 25/50MHz Oscillator ndikuyilumikiza kuzinthu izi.

1. Yambitsani Chip Oscillators pachimake mu SmartDesign yanu (makamaka yomwe MSS imakhazikitsidwa). Pachimake ichi chikhoza kupezeka mu Libero Catalog pansi pa Clock & Management.
2. Konzani pachimake ichi kuti RC oscillator imayendetsa nsalu ya FPGA, monga momwe tawonetsera pa Chithunzi 3-5.

Chithunzi 3-5 • Chip Oscillators Configurator

Kukhazikitsanso System (SYSRESET) Instantiation
SYSRESET macro imapereka magwiridwe antchito a chipangizocho pamapangidwe anu. Chizindikiro cha POWER_ON_RESET_N chimatsimikiziridwa / sichitsimikiziridwa nthawi iliyonse chip ikayatsidwa kapena pini yakunja DEVRST_N itsimikiziridwa / kutsimikiziridwa (Chithunzi 3-6).
Tsimikizirani ma SYSRESET macro mu SmartDesign yanu (makamaka yomwe MSS imakhazikitsidwa). Ma macro awa angapezeke mu Libero Catalog pansi pa Macro Library.Palibe kusinthidwa kwa macro ndikofunikira.

Chithunzi 3-6 • SYSRESET Macro

Kulumikizana konse
Mukakhazikitsa ndikusintha ma cores a MSS, FDDR, SERDESIF, OSC, SYSRESET, CoreConfigP ndi CoreResetP pamapangidwe anu, muyenera kuwalumikiza kuti apange dongosolo laling'ono la Peripheral Initialization. Kuti muchepetse kufotokozera kwa kulumikizana mu chikalatachi, chaphwanyidwa munjira yogwirizana ndi APB3 yolumikizana ndi CoreConfigP ndi kulumikizana kogwirizana ndi CoreResetP.
Kulumikizana kwa Njira ya Zosintha
Chithunzi 3-7 chikuwonetsa momwe mungalumikizire CoreConfigP ku siginecha za MSS FIC_2 ndi ma APB3 olumikizana ndi zotumphukira.
Gulu 3-1 • Kusintha Data Path Port/BIF Connections

KUCHOKERA Port/Bus Interface (BIF)/ Chigawo	KWA Port/Bus Interface (BIF)/Component
APB S PRESET N/ CoreConfigP	APB S PRESET N/ SDIF<0/1/2/3>	APB S PRESET N/ FDDR	MDDR APB S PRESE TN/MSS
APB S PCLK/ CoreConfigP	APB S PCLK/SDIF	APB S PCLK/FDDR	MDDR APB S POLK/ MSS
MDDR APBslave/ CoreConfig			MDDR APB SLAVE (BIF)/MSS
SDIF<0/1/2/ 3> APBmslave/Config	APB SLAVE (BIF)/ SDIF<0/1/2/3>
FDDR APBukapolo		APB SLAVE (BIF)/ FDDR
FIC 2 APBmmaster/ CoreConfigP			FIC 2 APB MASTER/ MSS

Chithunzi 3-7 • FIC_2 APB3 Kulumikizika kwa Sub-System

Mawotchi ndi Kukhazikitsanso Kulumikizana
Chithunzi 3-8 chikuwonetsa momwe mungalumikizire CoreResetP kuzinthu zotsitsimutsa zakunja ndi ma peripherals' core reset signatures. Ikuwonetsanso momwe mungalumikizire CoreResetP kuzizindikiro za mawotchi olumikizana ndi mawotchi (zizindikiro za loko ya PLL). Kuphatikiza apo, ikuwonetsa momwe CoreConfigP ndi CoreResetP zimalumikizidwa.

Chithunzi 3-8 • Core SF2Reset Sub-System Connectivity

Kupanga ndi Kupanga Pulogalamu ya Firmware

Mukatumiza firmware kuchokera ku LiberoSoC (Design Flow Window> Export Firmware> Export Firmware), Libero imapanga zotsatirazi. files mu /firmware/drivers_config/ sys_config chikwatu:

• sys_config.c - Muli ndi ma data omwe amasunga ma register ozungulira.
• sys_config.h - Lili ndi mawu a #define omwe amatchula zotumphukira zomwe zimagwiritsidwa ntchito popanga ndipo ziyenera kukhazikitsidwa.
• sys_config_mddr_define.h - Muli ndi chidziwitso cha kasinthidwe ka MDDR chomwe chalowetsedwa m'bokosi la Register Configuration.
• sys_config_fddr_define.h - Ili ndi zosintha zowongolera za FDDR zomwe zidalowetsedwa mubokosi la Register Configuration.
• sys_config_mss_clocks.h - Izi file ili ndi ma frequency a MSS wotchi monga momwe amafotokozera mu MSS CCC configurator. Mafupipafupiwa amagwiritsidwa ntchito ndi code ya CMSIS kuti apereke chidziwitso cholondola cha wotchi kwa madalaivala ambiri a MSS omwe ayenera kukhala ndi maulendo awo a Peripheral Clock (PCLK) (mwachitsanzo, MSS UART baud rate divisors ndi ntchito ya baud rate ndi PCLK pafupipafupi. ).
• sys_config_SERDESIF_ .c - Ili ndi SEDESIF_ kulembetsa zosintha zomwe zaperekedwa pa SEDESIF_ block kasinthidwe pakupanga mapangidwe.
• sys_config_SERDESIF_ .h - Muli ndi #define mawu omwe amafotokoza kuchuluka kwa ma registry olembetsa ndi nambala ya mseu yomwe ikufunika kufufuzidwa pa PMA_READY (pokhapokha mu PCIe).

Izi filema CMSIS amafunikira kuti khodi ya CMSIS isanjidwe bwino ndikukhala ndi chidziwitso chokhudza kapangidwe kanu kamakono, kuphatikiza zotumphukira za kasinthidwe ndi chidziwitso cha mawotchi a MSS.
Osasintha izi files pamanja; amapangidwa ku zigawo zofananira / zotumphukira nthawi iliyonse pomwe zida za SmartDesign zomwe zili ndi zotumphukira zomwe zimapangidwira. Ngati kusintha kulikonse kupangidwa pazida zosinthira za zotumphukira zilizonse, muyenera kutumizanso ma projekiti a firmware kuti firmware yosinthidwa. files (onani mndandanda pamwambapa) amatumizidwa ku / firmware/drivers_config/sys_config chikwatu.
Mukatumiza firmware, Libero SoC imapanga mapulojekiti a firmware: laibulale komwe mungasinthire mapangidwe anu files ndi madalaivala akuphatikizidwa.
Ngati muyang'ana Pangani polojekiti bokosi loyang'ana mukamatumiza fimuweya, pulojekiti ya SoftConsole/IAR/Keil imapangidwa kuti ikhale ndi pulojekiti yomwe mungasinthe main.c ndi wogwiritsa C/H files. Tsegulani pulojekiti ya SoftConSole/IAR/Keil kuti muphatikize kachidindo ka CMSIS molondola ndikukonzekera pulogalamu yanu ya firmware kuti igwirizane ndi kapangidwe kanu ka hardware.

Mtengo BFM Files Amagwiritsidwa Ntchito Poyerekeza Mapangidwe

Mukapanga zida za SmartDesign zomwe zili ndi zotumphukira zomwe zimalumikizidwa ndi kapangidwe kanu, kuyerekezera files zogwirizana ndi zotumphukira zomwe zimapangidwira mu / chikwatu chofananira:

• mayeso.bfm - BFM yapamwamba kwambiri file yomwe imayamba kuchitidwa panthawi iliyonse yoyerekeza yomwe imagwiritsa ntchito purosesa ya SmartFusion2 MSS Cortex-M3. Imayendetsa peripheral_init.bfm ndi user.bfm, motere.
• MDDR_init.bfm - Ngati mapangidwe anu amagwiritsa ntchito MDDR, Libero amapanga izi file; ili ndi malamulo olembera a BFM omwe amatsanzira zolemba za kaundula wa kasinthidwe ka MSS DDR zomwe mudalemba (pogwiritsa ntchito bokosi la zokambirana la Edit Registers kapena mu MSS_MDDR GUI) m'marejista a MSS DDR Controller.
• FDDR_init.bfm - Ngati mapangidwe anu amagwiritsa ntchito FDDR, Libero amapanga izi file; ili ndi malamulo olembera a BFM omwe amatsanzira zolemba za Register yosinthira ya Fabric DDR yomwe mudayika (pogwiritsa ntchito bokosi la zokambirana la Edit Registers kapena mu FDDR GUI) m'marejista a Fabric DDR Controller.
• SEDESIF_ _init.bfm - Ngati kapangidwe kanu kamagwiritsa ntchito midadada imodzi kapena zingapo za SERDESIF, Libero amapanga izi file pa chilichonse cha SEDESIF_ midadada yogwiritsidwa ntchito; ili ndi malamulo olembera a BFM omwe amafanana ndi zolemba za SERDESIF configuration registry data yomwe mudayika (pogwiritsa ntchito bokosi la zokambirana la Edit Registers kapena mu SEDESIF_ GUI) mu SEDESIF_ olembetsa. Ngati chipika cha SERDESIF chisinthidwa kukhala PCIe, izi file ilinso ndi mawu ena #define omwe amawongolera kuchitidwa kwa magawo a kasinthidwe a 2 mwadongosolo labwino.
• wosuta.bfm - Muli ndi malamulo ogwiritsa ntchito. Malamulowa amachitidwa peripheral_init.bfm ikatha. Sinthani izi file kuti mulowetse malamulo anu a BFM.
• SEDESIF_ _user.bfm - Muli ndi malamulo ogwiritsa ntchito. Sinthani izi file kuti mulowetse malamulo anu a BFM. Gwiritsani ntchito izi ngati mwakonza SEDESIF_ block mu BFM PCIe simulation mode komanso ngati mbuye wa AXI/AHBLite. Ngati mwakonza SEDESIF_ block mu RTL simulation mode, simudzasowa izi file.

Mukapempha kayeseleledwe nthawi zonse, kayeseleledwe kawiri kotsatira files amapangidwanso ku / chikwatu choyerekeza chokhala ndi zomwe zasinthidwa:

• dongosolo.bfm - Lili ndi mawu a #define pamtundu uliwonse womwe umagwiritsidwa ntchito pamapangidwe anu, omwe amatchula gawo linalake la peripheral_init.bfm lomwe likuyenera kuchitidwa mogwirizana ndi zotumphukira zilizonse.
• operipheral_init.bfm - Ili ndi njira ya BFM yomwe imatsanzira CMSIS :: SystemInit() ntchito yoyendetsedwa pa Cortex-M3 musanalowe main() ndondomeko. Imakopera zosintha zamtundu uliwonse wogwiritsidwa ntchito popanga zolembera zolondola zokhazikika ndikudikirira kuti zotumphukira zonse zikhale zokonzeka musananene kuti mutha kugwiritsa ntchito zotumphukira izi. Imagwira MDDR_init.bfm ndi FDDR_init.bfm.

Kugwiritsa ntchito izi files, zowongolera za DDR mu kapangidwe kanu zimasinthidwa zokha, kutengera zomwe zingachitike pa chipangizo cha SmartFusion2. Mutha kusintha user.bfm file kuti muwonjezere malamulo aliwonse ofunikira kutengera kapangidwe kanu (Cortex-M3 ndiye mbuye). Malamulowa amachitidwa pambuyo poyambitsa zotumphukira. Osasintha test.bfm, subsystem.bfm, peripheral_init.bfm, MDDR_init.bfm, FDDR_init.bfm files ndi SEDESIF_ _init.bfm files.

Product Support

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Zolemba / Zothandizira

Microsemi SmartFusion2 DDR Controller ndi Serial High Speed ​​​​Controller [pdf] Buku Logwiritsa Ntchito SmartFusion2 DDR Controller ndi Serial High Speed ​​Controller, SmartFusion2 DDR, Controller and Serial High Speed ​​Controller, High Speed ​​Controller

Maumboni

• Buku Logwiritsa Ntchito