HDMI Arria 10 FPGA IP Dhizaini Example
User GuideHDMI Intel® Arria 10 FPGA IP
Design Example User Guide
Yakagadziridzwa yeIntel®Quartus®
Prime Dhizaini Suite: 22.4
IP Shanduro: 19.7.1

HDMI Intel® FPGA IP Dhizaini Example Quick Start Guide yeIntel® Arria® 10 Devices

Iyo HDMI Intel® 10 zvishandiso zvine yekutevedzera testbench uye dhizaini yehardware inotsigira kuunganidza uye kuyedza Hardware.
FPGA IP dhizaini exampyeIntel Arria®
Iyo HDMI Intel FPGA IP inopa inotevera dhizaini exampzvishoma:

• HDMI 2.1 RX-TX retransmit dhizaini ine fixed rate link (FRL) modhi inogoneswa
• HDMI 2.0 RX-TX retransmit dhizaini ine FRL modhi yakaremara
• HDCP pamusoro peHDMI 2.0 dhizaini

Cherechedza: Iyo HDCP ficha haina kubatanidzwa muIntel® Quartus Prime Pro Edition software.
Kuti uwane iyo HDCP chimiro, bata Intel pa https://www.intel.com/content/www/us/en/broadcast/products/programmable/applications/connectivity-solutions.html.
Kana iwe ukagadzira dhizaini example, iyo parameter editor inogadzira iyo fileinodiwa kutevedzera, kuunganidza, uye kuyedza dhizaini muhardware.
Mufananidzo 1. Matanho EkuvandudzaRelated Information
HDMI Intel FPGA IP User Guide
1.1. Kugadzira Dhizaini
Shandisa iyo HDMI Intel FPGA IP paramende mupepeti muIntel Quartus Prime software kugadzira dhizaini examples. Intel Corporation. Kodzero dzese dzakachengetwa. Intel, iyo Intel logo, uye mamwe maIntel mamaki zviratidzo zveIntel Corporation kana vatsigiri vayo. Intel inobvumidza kuita kwayo FPGA uye semiconductor zvigadzirwa kune zvazvino zvirevo zvinoenderana neIntel's standard waranti, asi inochengetera kodzero yekuita shanduko kune chero zvigadzirwa nemasevhisi chero nguva pasina chiziviso. Intel haitore mutoro kana mutoro unobva mukushandisa kana kushandiswa kwechero ruzivo, chigadzirwa, kana sevhisi inotsanangurwa pano kunze kwekunge yakabvumiranwa nekunyora neIntel. Vatengi veIntel vanorairwa kuti vawane yazvino vhezheni yezvakatemwa zvemudziyo vasati vavimba nechero ruzivo rwakaburitswa uye vasati vaisa maodha ezvigadzirwa kana masevhisi. *Mamwe mazita nemhando zvinogona kunzi ndezvevamwe.
Kutanga naNios® II EDS muIntel Quartus Prime Pro Edition software vhezheni 19.2 uye Intel Quartus Prime Standard Edition software vhezheni 19.1, Intel yakabvisa chikamu cheCygwin muWindows* vhezheni yeNios II EDS, ichichitsiva neWindows* Subsytem yeLinux (WSL). Kana iwe uri mushandisi weWindows*, unofanirwa kuisa WSL usati wagadzira yako yekare dhizainiample.
Mufananidzo 2. Kugadzira Kuyerera Kwekugadzira

1. Gadzira purojekiti yakanangana neIntel Arria 10 mudziyo mhuri uye sarudza yaunoda mudziyo.
2. MuI IP Catalog, tsvaga uye tinya kaviri Interface Protocols ➤ Audio & Vhidhiyo ➤ HDMI Intel FPGA IP. The New IP Variant kana New IP Variation hwindo rinoonekwa.
3. Rondedzera zita repamusoro-soro kune yako tsika IP musiyano. Iyo parameter mupepeti inochengetedza iyo IP kusiyanisa marongero mune a file zita .ip kana .qsys.
4. Dzvanya OK. Iyo parameter editor inooneka.
5. PaI IP tab, gadzira maparamita anodiwa ezvose zviri zviviri TX uye RX.
6. Batidza Rutsigiro FRL paramende kuti ugadzire iyo HDMI 2.1 dhizaini exampuye mune FRL mode. Idzima kuti igadzire iyo HDMI 2.0 dhizaini examppasina FRL.
7. Pamusoro peDesign Exampuye tab, sarudza Arria 10 HDMI RX-TX Retransmit.
8. Sarudza Simulation kugadzira testbench, uye sarudza Synthesis kugadzira iyo hardware dhizaini example.Unofanirwa kusarudza imwe yeiyi sarudzo kuti ugadzire iyo yekare dhizainiample files. Kana ukasarudza zvose zviri zviviri, nguva yechizvarwa irefu.
9. For Gadzira File Fomati, sarudza Verilog kana VHDL.
10. YeTarget Development Kit, sarudza Intel Arria 10 GX FPGA Development Kit. Kana ukasarudza kit yekuvandudza, ipapo iyo inonangwa mudziyo (yakasarudzwa munhanho 4) inochinja kuti ienderane nemudziyo uri pabhodhi rakanangwa. YeIntel Arria 10 GX FPGA Development Kit, mudziyo wakasarudzika ndeye 10AX115S2F4I1SG.
11. Dzvanya Gadzira Example Design.

Related Information
Maitiro ekuisa iyo Windows * Subsystem yeLinux * (WSL) paWindows * OS?
1.2. Kutevedzera Magadzirirwo
Iyo HDMI testbench inoteedzera serial loopback dhizaini kubva kuTX muenzaniso kuenda kuRX muenzaniso. Yemukati vhidhiyo pateni jenareta, odhiyo sample jenareta, sideband data jenareta, uye anobatsira data jenareta modules anotyaira iyo HDMI TX muenzaniso uye serial inobuda kubva kuTX muenzaniso inobatanidza kune iyo RX muenzaniso muye testbench.
Mufananidzo 3. Dhizaini Simulation Flow

1. Enda kune yaunoda simulation folda.
2. Mhanya iyo simulation script yeiyo inotsigirwa simulator yesarudzo yako. Iyo script inounganidza uye inomhanyisa testbench mune simulator.
3. Ongorora zvabuda.

Tafura 1. Matanho ekumhanya Simulation

Simulator	Working Directory	Mirayiridzo
Riviera-PRO*	/simulation/aldec	Mumutsara wekuraira, nyora
		vsim -c -do aldec.do
ModelSim*	/simulation/mentor	Mumutsara wekuraira, nyora
		vsim -c -do mentor.do
VCS*	/simulation/synopsy/vcs	Mumutsara wekuraira, nyora
		tsime vcs_sim.sh
VCS MX	/simulation/synopsy/ vcsmx	Mumutsara wekuraira, nyora
		kunobva vcsmx_sim.sh
Xcelium* Parallel	/simulation/xcelium	Mumutsara wekuraira, nyora
		tsime xcelium_sim.sh

Simulation yakabudirira inopera neshoko rinotevera:
# SYMBOLS_PER_CLOCK = 2
#VIC = 4
# FRL_RATE = 0
# BPP = 0
# AUDIO_FREQUENCY (kHz) = 48
# AUDIO_CHANNEL = 8
# Simulation pass
1.3. Kunyora uye Kuedza Dhizaini

Kuunganidza uye kumhanyisa bvunzo yekuratidzira pane Hardware example design, tevera matanho aya:

1. Ita shuwa kuti hardware example design generation yapera.
2. Uparure Intel Quartus Prime software uye vhura iyo .qpf file.
   • HDMI 2.1 dhizaini example nerutsigiro FRL yakagoneswa: dhairekitori reprojekiti/quartus/a10_hdmi21_frl_demo.qpf
   • HDMI 2.0 dhizaini example nerutsigiro FRL yakaremara: projectd irectory/quartus/a10_hdmi2_demo.qpf
3. Tinya Kugadzirisa ➤ Tanga Kuunganidza.
4. Mushure mekubudirira kuunganidza, a .sof file ichagadzirwa mu quartus/output_files directory.
5. Batanidza kune-pane-bhodhi FMC port B (J2):
   • HDMI 2.1 dhizaini example nerutsigiro FRL yakagoneswa: Bitec HDMI 2.1 FMC Mwanasikana Kadhi Rev 9
   Cherechedza: Iwe unogona kusarudza kudzokororwa kweBitec HDMI mwanasikana wako kadhi. Pasi peDesign Example tab, isa HDMI Mwanasikana Kadhi Revision kune imwe Revision 9, Revision kana pasina mwanasikana kadhi. Iyo yakasarudzika kukosha ndeye Revision 9.
   • HDMI 2.0 dhizaini example nerutsigiro FRL yakaremara: Bitec HDMI 2.0 FMC Mwanasikana Kadhi Rev 11
6. Batanidza TX (P1) yeBitec FMC mwanasikana kadhi kune yekunze vhidhiyo sosi.
7. Batanidza RX (P2) yeBitec FMC mwanasikana kadhi kune yekunze vhidhiyo sink kana vhidhiyo analyzer.
8. Ita shuwa kuti zvese zvinochinja pabhodhi rekuvandudza zviri munzvimbo yekusarudzika.
9. Gadzirisa iyo yakasarudzwa Intel Arria 10 mudziyo pabhodhi rekuvandudza uchishandisa yakagadzirwa .sof file (Zvishandiso ➤ Mugadziri).
10. Iyo analyzer inofanirwa kuratidza vhidhiyo inogadzirwa kubva kwainobva.

Related Information
Intel Arria 10 FPGA Yekuvandudza Kit Mushandisi Guide
1.4. HDMI Intel FPGA IP Dhizaini Example Parameters
Tafura 2.
HDMI Intel FPGA IP Dhizaini Example Parameters yeIntel Arria 10 Devices Idzi sarudzo dziripo kune Intel Arria 10 zvishandiso chete.

Parameter	Value	Tsanangudzo
Inowanikwa Dhizaini Example
Sarudza Dhizaini	Arria 10 HDMI RX-TX Retransmit	Sarudza dhizaini exampkuti igadzirwe.

Design Example Files
Simulation	Vhura, Bvisa	Batidza iyi sarudzo kuti uite zvinodiwa files yekufananidza testbench.
Synthesis	Vhura, Bvisa	Batidza iyi sarudzo kuti uite zvinodiwa files yeIntel Quartus Prime kuunganidza uye hardware kuratidzira.

Yakagadzirwa HDL Format
Gadzira File Format	Verilog, VHDL	Sarudza yako yaunofarira HDL fomati yeyakagadzirwa dhizaini example fileset. Cherechedza: Iyi sarudzo inongotarisa iyo fomati yeiyo yakagadzirwa yepamusoro level IP files. Zvimwe zvese files (semuenzanisoample testbenches uye yepamusoro-soro files yekuratidzira kwehardware) ari muVerilog HDL fomati

Target Development Kit
Sarudza Bhodhi	Hapana Developer Kit,	Sarudza bhodhi yezvakanangwa dhizaini example.
	Arria 10 GX FPGA Development Kit, Custom Development Kit	• No Development Kit: Iyi sarudzo haisanganisi zvinhu zvese zvehardware zvedesign example. Iyo IP musimboti inoseta ese mapini ekupa kune chaiwo mapini. • Arria 10 GX FPGA Development Kit: Iyi sarudzo inosarudza otomatiki mudziyo wakanangana nepurojekiti kuti uenderane nemudziyo uri paiyi kit yekuvandudza. Unogona kushandura chipfuro mudziyo uchishandisa Shandura Chinangwa Chishandiso parameter kana yako bhodhi redhiyo ine akasiyana mudziyo musiyano. Iyo IP musimboti inoseta ese pini migove zvinoenderana nebudiriro kit.
		•Custom Development Kit: Iyi sarudzo inobvumira dhizaini example yekuedzwa pane yechitatu bato yekuvandudza kit ine Intel FPGA. Ungangoda kuseta mapini ekuita uri wega.

Target Device
Shandura Chinangwa Chishandiso	Vhura, Bvisa	Batidza iyi sarudzo uye sarudza yaunofarira mudziyo musiyano weti yekuvandudza.

HDMI 2.1 Dhizaini Example (Kutsigira FRL = 1)

Iyo HDMI 2.1 dhizaini example muFRL modhi inoratidza imwe HDMI muenzaniso parallel loopback inosanganisira ina RX chiteshi uye ina TX chiteshi.
Tafura 3. HDMI 2.1 Dhizaini Example yeIntel Arria 10 Devices

Design Example	Data Rate	Chiteshi Mamiriro	Loopback Type
Arria 10 HDMI RX-TX Retransmit	• 12 Gbps (FRL) • 10 Gbps (FRL) • 8Gbps (FRL) • 6 Gbps (FRL) • 3 Gbps (FRL) • <6 Gbps (TMDS)	Simplex	Parallel neFIFO buffer

Features

• Iyo dhizaini inosimudzira FIFO buffers kuti iite yakananga HDMI vhidhiyo rukova kupfuura pakati peHDMI 2.1 sink uye sosi.
• Iyo dhizaini inokwanisa kushandura pakati peFRL modhi uye TMDS modhi panguva yekumhanya nguva.
• Iyo dhizaini inoshandisa LED mamiriro ekutanga debugging stage.
• Iyo dhizaini inouya neHDMI RX uye TX zviitiko.
• Dhizaini yacho inoratidza kuiswa uye kusefa kweDynamic Range uye Mastering (HDR) InfoFrame muRX-TX link module.
• Dhizaini inotaurirana chiyero cheFRL pakati pekunyura kwakabatana neTX uye sosi yakabatana neRX. Iyo dhizaini inopfuura neiyo EDID kubva kune yekunze singi kuenda kune-bhodhi RX mukumisikidzwa kwekumisikidza. Iyo Nios II processor inotaurirana iyo yekubatanidza base pane kugona kwe sink yakabatana neTX. Iwe unogona zvakare kushandura iyo user_dipsw pa-bhodhi switch kuti udzore nemaoko iyo TX uye RX FRL kugona.
• Iyo dhizaini inosanganisira akati wandei debugging maficha.
  Iyo RX muenzaniso inogamuchira vhidhiyo sosi kubva kune yekunze vhidhiyo jenareta, uye iyo data yobva yaenda kuburikidza loopback FIFO isati yaendeswa kune iyo TX muenzaniso. Iwe unofanirwa kubatanidza yekunze vhidhiyo analyzer, yekutarisa, kana terevhizheni ine HDMI yekubatanidza kune iyo TX musimboti kuti uone kushanda.

2.1. HDMI 2.1 RX-TX Retransmit Dhizaini Dhizaini Dhizaini
Iyo HDMI RX-TX retransmit dhizaini example inoratidza parallel loopback pane simplex chiteshi modhi yeHDMI 2.1 ine Tsigiro FRL inogoneswa.
Mufananidzo 4. HDMI 2.1 RX-TX Retransmit Block Diagram2.2. Kugadzira RX-chete kana TX-chete Designs
Kune vashandisi vepamberi, unogona kushandisa HDMI 2.1 dhizaini kugadzira TX- kana RX-chete dhizaini.
Mufananidzo 5. Zvikamu Zvinodiwa zveRX-Chete kana TX-Chete DhizainiKuti ushandise RX- kana TX-chete zvikamu, bvisa zvidhinha zvisina basa kubva padhizaini.
Tafura 4. RX-Chete uye TX-Chete Dhizaini Zvinodiwa

Mushandisi Zvinodiwa	Chengetedza	Bvisa	Wedzera
HDMI RX chete	RX Pamusoro	• TX Pamusoro • RX-TX Link • CPU Subsystem • Transceiver Arbiter	-
HDMI TX chete	•TX Pamusoro •CPU Sub-System	•RX Pamusoro • RX-TX Link •Transceiver Arbiter	Vhidhiyo Patani Jenareta (yakasarudzika module kana yakagadzirwa kubva kuVhidhiyo uye Image Processing (VIP) Suite)

Kunze kwekuchinja kweRTL, unodawo kugadzirisa main.c script.
• Nezve HDMI TX-magadzirirwo chete, bvisa kumirira kweHDMI RX kukiya mamiriro nekubvisa mitsara inotevera uye chinja
tx_xcvr_reconfig(tx_frl_rate);
rx_hdmi_lock = READ_PIO(PIO_IN0_BASE, PIO_RX_LOCKED_OFFSET,
PIO_RX_LOCKED_WIDTH);
apo (rx_hdmi_lock == 0) {
kana (check_hpd_isr()) {break; }
// rx_vid_lock = READ_PIO(PIO_IN0_BASE, PIO_VID_LOCKED_OFFSET,
PIO_VID_LOCKED_WIDTH);
rx_hdmi_lock = READ_PIO(PIO_IN0_BASE, PIO_RX_LOCKED_OFFSET,
PIO_RX_LOCKED_WIDTH);
// Reconfig Tx mushure mekunge rx yakavharwa
kana (rx_hdmi_lock == 1) {
kana (READ_PIO(PIO_IN0_BASE, PIO_LOOPBACK_MODE_OFFSET,
PIO_LOOPBACK_MODE_WIDTH) == 1) {
rx_frl_rate = READ_PIO(PIO_IN0_BASE, PIO_RX_FRL_RATE_OFFSET,
PIO_RX_FRL_RATE_WIDTH);
tx_xcvr_reconfig(rx_frl_rate);
} zvimwe {
tx_xcvr_reconfig(tx_frl_rate);
}}}
• Pamagadzirirwo eHDMI RX-chete, chengeta mitsara inotevera chete mune main.c script:
REDRIVER_INIT();
hdmi_rx_init();
2.3. Hardware uye Software Zvinodiwa
Intel inoshandisa iyi inotevera Hardware uye software kuyedza iyo dhizaini example.
Hardware

• Intel Arria 10 GX FPGA Development Kit
• HDMI 2.1 Source (Quantum Data 980 48G Jenareta)
• HDMI 2.1 Sink (Quantum Data 980 48G Analyzer)
• Bitec HDMI FMC 2.1 mwanasikana kadhi (Revision 9)
• HDMI 2.1 Category 3 tambo (dzakaedzwa neBelkin 48Gbps HDMI 2.1 Cable)

Software

• Intel Quartus Prime Pro Edition software shanduro 20.1

2.4. Directory Structure
Madhairekitori ane akagadzirwa files yeHDMI Intel FPGA IP dhizaini example.
Mufananidzo 6. Dhairekitori Mamiriro Ezvakagadzirwa ExampleTafura 5. Yakagadzirwa RTL Files

Folders	Files/Madhodha
common	clock_control.ip
	clock_crosser.v
	dcfifo_inst.v
	kumucheto_detector.sv
	fifo.ip
	output_buf_i2c.ip

	test_pattern_gen.v
	tpg.v
	tpg_data.v
gxb	gxb_rx.ip
	gxb_rx_reset.ip
	gxb_tx.ip
	gxb_tx_fpll.ip
	gxb_tx_reset.ip
hdmi_rx	hdmi_rx.ip
	hdmi_rx_top.v
	Panasonic.hex
hdmi_tx	hdmi_tx.ip
	hdmi_tx_top.v
i2c_muranda	i2c_avl_mst_intf_gen.v
	i2c_clk_cnt.v
	i2c_condt_det.v
	i2c_databuffer.v
	i2c_rxshifter.v
	i2c_slvfsm.v
	i2c_spksup.v
	i2c_txout.v
	i2c_txshifter.v
	i2cslave_to_avlmm_bridge.v
pll	pll_hdmi_reconfig.ip
	pll_frl.ip
	pll_reconfig_ctrl.v
	pll_tmds.ip
	pll_vidclk.ip
	quartus.ini
rxtx_link	altera_hdmi_hdr_infoframe.v
	aux_mux.qsys
	aux_retransmit.v
	aux_src_gen.v
	ext_aux_filter.v

	rxtx_link.v
	scfifo_vid.ip
reconfig	mr_rx_iopll_tmds/
	mr_rxphy/
	mr_tx_fpll/
	altera_xcvr_functions.sv
	mr_compare.sv
	mr_rate_detect.v
	mr_rx_rate_detect_top.v
	mr_rx_rcfg_ctrl.v
	mr_rx_reconfig.v
	mr_tx_rate_detect_top.v
	mr_tx_rcfg_ctrl.v
	mr_tx_reconfig.v
	rcfg_array_streamer_iopll.sv
	rcfg_array_streamer_rxphy.sv
	rcfg_array_streamer_rxphy_xn.sv
	rcfg_array_streamer_txphy.sv
	rcfg_array_streamer_txphy_xn.sv
	rcfg_array_streamer_txpll.sv
sdc	a10_hdmi2.sdc
	jtag.sdc

Tafura 6. Yakagadzirwa Simulation Files
Tarisa kune Simulation Testbench chikamu kuti uwane rumwe ruzivo

Folders	Files
aldec	/aldec.do
	/rivierapro_setup.tcl
cadence	/cds.lib
	/hdl.var
mentor	/mentor.do
	/msim_setup.tcl
synopsys	/vcs/filelist.f
	/vcs/vcs_setup.sh

	/vcs/vcs_sim.sh
	/vcsmx/synopsys_sim_setup
	/vcsmx/vcsmx_setup.sh
	/vcsmx/vcsmx_sim.sh
xcelium	/cds.lib
	/hdl.var
	/xcelium_setup.sh
	/xcelium_sim.sh
common	/modelsim_files.tcl
	/riviera_files.tcl
	/vcs_files.tcl
	/vcsmx_files.tcl
	/xcelium_files.tcl
hdmi_rx	/hdmi_rx.ip
	/Panasonic.hex
hdmi_tx	/hdmi_tx.ip

Tafura 7. Yakagadzirwa Software Files

Folders	Files
tx_control_src Cherechedza: Iyo tx_control folda zvakare ine zvakapetwa zveizvi files.	global.h
	hdmi_rx.c
	hdmi_rx.h
	hdmi_tx.c
	hdmi_tx.h
	hdmi_tx_read_edid.c
	hdmi_tx_read_edid.h
	intel_fpga_i2c.c
	intel_fpga_i2c.h
	main.c
	pio_read_write.c
	pio_verenga_nyora.h

2.5. Dhizaini Zvikamu
Iyo HDMI Intel FPGA IP dhizaini example inoumbwa neyakajairwa yepamusoro-level zvikamu uye HDMI TX uye RX yepamusoro zvikamu.
2.5.1. HDMI TX Zvikamu
Iyo HDMI TX yepamusoro zvikamu zvinosanganisira iyo TX yepakati-yepamusoro-level zvikamu, uye IOPLL, transceiver PHY reset controller, transceiver native PHY, TX PLL, TX reconfiguration manejimendi, uye inobuda buffer block.
Mufananidzo 7. HDMI TX Top ComponentsTafura 8. HDMI TX Pamusoro Zvikamu

Module	Tsanangudzo
HDMI TX Core	Iyo IP inogamuchira data yevhidhiyo kubva padanho repamusoro uye inoita yekubatsira data encoding, odhiyo data encoding, vhidhiyo data encoding, kupuruzira, TMDS encoding kana packetization.
IOPLL	Iyo IOPLL (iopll_frl) inogadzira iyo FRL wachi yeTX musimboti. Iyi wachi yekurevera inogamuchira iyo TX FPLL yekubuda wachi. FRL wachi frequency = Chiyero chedhata panzira x 4 / (FRL mavara pawachi x 18)
Transceiver PHY Reset Controller	Iyo Transceiver PHY reset controller inovimbisa yakavimbika kutanga kweTX transceivers. Kuiswa patsva kwemutongi uyu kunokonzereswa kubva padanho repamusoro, uye inogadzira inoenderana analog uye digital reset siginecha kuTransceiver Native PHY block zvinoenderana nekutevedzana kwekugadzirisa mukati me block. Iyo tx_ready inobuda siginecha kubva mubhuroka ino inoshandawo sechiratidzo chekugadzirisazve kuHDMI Intel FPGA IP kuratidza kuti transceiver yasimuka uye inoshanda, uye yakagadzirira kugamuchira data kubva pakati.
Transceiver Native PHY	Yakaoma transceiver block inogamuchira iyo yakafanana data kubva kuHDMI TX musimboti uye inoteedzera iyo data kubva mukuifambisa. Cherechedza: Kuti usangane neHDMI TX inter-channel skew chinodiwa, isa iyo TX chiteshi bonding modhi sarudzo muIntel Arria 10 Transceiver Native PHY parameter mupepeti kuti. PMA uye PCS kubatana. Iwe zvakare unofanirwa kuwedzera iyo yakanyanya skew (set_max_skew) inomanikidza inodiwa kune dijitari reset chiratidzo kubva kune transceiver reset controller (tx_digitalreset) sezvakakurudzirwa mune Intel Arria 10 Transceiver PHY User Guide.
TX PLL	Iyo transmitter PLL block inopa serial inokurumidza wachi kune Transceiver Native PHY block. Kune iyi HDMI Intel FPGA IP dhizaini example, fPLL inoshandiswa seTX PLL. TX PLL ine mareferensi wachi mbiri. • Reference clock 0 yakabatanidzwa kune programmable oscillator (ine TMDS clock frequency) ye TMDS mode. Muchirongwa ichi example, RX TMDS wachi inoshandiswa kubatanidza kune referensi wachi 0 yeTMDS modhi. Intel inokurudzira kuti ushandise programmable oscillator ine TMDS wachi frequency yereferensi wachi 0. • Reference wachi 1 yakabatana kune yakatarwa 100 MHz wachi yeFRL modhi.
TX Reconfiguration Management	•Mumodhi yeTMDS, TX reconfiguration management block inogadzirisa zvakare TX PLL kune yakasiyana yakabuda yewachi frequency zvichienderana neTMDS wachi frequency yevhidhiyo chaiyo. •MuFRL mode, TX reconfiguration management block inogadzirisa zvakare TX PLL kuti ipe serial fast clock ye 3 Gbps, 6 Gbps, 8 Gbps, 10 Gbps uye 12 Gbps maererano neFRL_Rate ndima murejista ye0x31 SCDC. •The TX reconfiguration management block inochinja TX PLL referensi wachi pakati pereferensi wachi 0 yeTMDS mode uye referensi wachi 1 yeFRL modhi.
Output buffer	Iyi buffer inoita senge interface yekudyidzana iyo I2C interface yeHDMI DDC uye yedhiraivha zvikamu.

Tafura 9.Transceiver Data Rate uye OversampChimiro Chese Clock Frequency Range

Mode	Data Rate	Oversampchikamu 1 (2x pamusoroampLe)	Oversampchikamu 2 (4x pamusoroampLe)	Oversample Factor	OversampLed Data Rate (Mbps)
TMDS	250–1000	On	On	8	2000–8000
TMDS	1000–6000	On	Off	2	2000–12000
FRL	3000	Off	Off	1	3000
FRL	6000	Off	Off	1	6000

FRL	8000	Off	Off	1	8000
FRL	10000	Off	Off	1	10000
FRL	12000	Off	Off	1	12000

Mufananidzo 8. TX Reconfiguration Sequence Flow2.5.2. HDMI RX Zvikamu
Iyo HDMI RX yepamusoro zvikamu zvinosanganisira iyo RX yepakati-yepamusoro-level zvikamu, yakasarudzika I²C muranda uye EDID RAM, IOPLL, transceiver PHY reset controller, RX native PHY, uye RX reconfiguration manejimendi mabhuroko.
Mufananidzo 9. HDMI RX Top ComponentsTafura 10. HDMI RX Pamusoro Zvikamu

Module	Tsanangudzo
HDMI RX Core	Iyo IP inogamuchira serial data kubva kuTransceiver Native PHY uye inoita data align, chiteshi deskew, TMDS decoding, yekubatsira data decoding, vhidhiyo decoding, odhiyo data decoding, uye kudhiza.
I2C Muranda	I2C ndiyo interface inoshandiswa Sink Display Data Channel (DDC) uye Status uye Data Channel (SCDC). Iyo HDMI sosi inoshandisa iyo DDC kuona kugona uye hunhu hwesingi nekuverenga Iyo Yakawedzeredzwa Yakawedzera Display Identification Data (E-EDID) data chimiro. Iyo 8-bit I2C kero yevaranda yeE-EDID ndeye 0xA0 uye 0xA1. Iyo LSB inoratidza mhando yekuwana: 1 yekuverenga uye 0 yekunyora. Kana chiitiko cheHPD chikaitika, muranda weI2C anopindura E-EDID data nekuverenga kubva pa-chip Iyo I2C muranda-chete controller inotsigirawo SCDC yeHDMI 2.0 uye 2.1 Iyo 9-bit I2C kero yemuranda yeSCDC ndeye 0xA8 uye 0xA9. Kana chiitiko cheHPD chikaitika, muranda weI2C anoita kunyora kana kuverenga kutengeserana kuenda kana kubva kuSCDC interface yeHDMI RX musimboti. Batanidza maitiro ekudzidziswa kweFixed Rate Link (FRL) zvakare inoitika kuburikidza neI2C Panguva yechiitiko cheHPD kana sosi inonyora chiyero chakasiyana cheFRL kurejista yeFRL Rate (SCDC inonyoresa 0x31 bit[3: 0]), iyo nzira yekudzidzisa yekubatanidza inotanga. Cherechedza: Iyi I2C muranda-chete controller yeSCDC haidiwe kana HDMI 2.0 kana HDMI 2.1 isina kuitirwa.

EDID RAM

Dhizaini inochengeta iyo EDID ruzivo uchishandisa iyo RAM 1-Port IP. Yakajairika mbiri-waya (wachi uye data) serial bhazi protocol (I2C muranda-chete controller) inotamisa iyo CEA-861-D Inopindirana E-EDID data chimiro. Iyi EDID RAM inochengeta iyo E-EDID ruzivo. • Kana iri muTMDS mode, dhizaini inotsigira EDID kupfuura kubva kuTX kuenda kuRX. Munguva yeEDID yekupfuura, kana TX yakabatana kune sink yekunze, Nios II processor inoverenga EDID kubva kune sink yekunze uye inonyorera kuEDID RAM. • Kana iri muFRL mode, Nios II processor inonyora pre-yakagadzirirwa EDID yereti yega yega yekubatanidza zvichienderana neHDMI_RX_MAX_FRL_RATE parameter muglobal.h script. Shandisa zvinotevera HDMI_RX_MAX_FRL_RATE zvekuisa pachiyero chinotsigirwa cheFRL: • 1: 3G 3 Lanes • 2: 6G 3 Lanes •3: 6G 4 Lanes • 4: 8G 4 Lanes •5: 10G 4 Lanes (default) •6: 12G 4 Lanes

IOPLL

Iyo HDMI RX inoshandisa maIOPLL maviri. • IOPLL yekutanga (pll_tmds) inogadzira RX CDR referensi wachi. Iyi IOPLL inoshandiswa chete muTMDS mode. Iyo referensi wachi yeIOPLL iyi inogamuchira iyo TMDS wachi. Iyo TMDS modhi inoshandisa iyi IOPLL nekuti CDR haigone kugashira wachi dziri pasi pe50 MHz uye TMDS wachi frequency inotangira pa25 MHz kusvika 340 MHz. IOPLL iyi inopa wachi frequency inova nguva 5 dzeyekuisa referensi wachi ye frequency renji pakati pe25 MHz kusvika 50 MHz uye inopa yakafanana wachi yewachi seyekuisa referensi wachi ye frequency pakati pe50 MHz kusvika 340 MHz. •IOPLL yechipiri (iopll_frl) inogadzira wachi yeFRL yeRX core. Iyi wachi yereferenzi inogamuchira CDR yakadzoserwa wachi. FRL wachi frequency = Chiyero chedhata panzira x 4 / (FRL mavara pawachi x 18)

Transceiver PHY Reset Controller	Iyo Transceiver PHY reset controller inovimbisa yakavimbika kutanga kweiyo RX transceivers. Kuiswa patsva kwemutongi uyu kunokonzereswa neRX reconfiguration, uye inogadzira inoenderana analog uye digital reset siginecha kuTransceiver Native PHY block zvinoenderana nekuteedzeranazve mukati me block.
RX Native PHY	Yakaoma transceiver block iyo inogamuchira iyo serial data kubva kune yekunze vhidhiyo sosi. Iyo inobvisa iyo serial data kuti ienderane data isati yapfuudza iyo data kuHDMI RX musimboti. Iyi block inomhanya paEnhanced PCS yeFRL modhi. RX CDR ine mareferensi wachi mbiri. • Chireferensi wachi 0 yakabatana newachi inobuda yeIOPLL TMDS (pll_tmds), inotorwa kubva pawachi yeTMDS. • Reference wachi 1 yakabatana kune yakatarwa 100 MHz wachi. Mune TMDS modhi, RX CDR inogadziridzwa zvakare kuti isarudze referensi wachi 0, uye muFRL modhi, RX CDR inogadziridzwa zvakare kusarudza referensi wachi 1.
RX Reconfiguration Management	Mune TMDS modhi, iyo RX reconfiguration manejimendi chivharo chinoisa chiyero chekuona dunhu neHDMI PLL kutyaira iyo RX transceiver kuti ishande chero ipi zvayo yekubatanidza mitengo kubva pa250 Mbps kusvika 6,000 Mbps. Mune FRL mode, iyo RX reconfiguration management block inogadzirisazve RX transceiver kuti ishande pa3 Gbps, 6 Gbps, 8 Gbps, 10 Gbps, kana 12 Gbps zvichienderana nechiyero cheFRL muSCDC_FRL_RATE rejista ndima (0x31 [3: 0]). Iyo RX reconfiguration manejimendi block inochinja pakati peStandard PCS/RX ye TMDS mode uye Enhanced PCS yeFRL modhi Mufananidzo 10 papeji 22.

Mufananidzo 10. RX Reconfiguration Sequence Flow
Iyo nhamba inotaridza iyo yakawanda-yeti reconfiguration sequence kuyerera kwemutongi kana agamuchira yekupinda data rwizi uye referensi wachi frequency, kana kana transceiver yavhurwa.2.5.3. Top-Level Common Blocks
Iwo epamusoro-chikamu akajairwa zvidhinha anosanganisira transceiver arbiter, iyo RX-TX yekubatanidza zvikamu, uye CPU subsystem.
Tafura 11. Top-Level Common Blocks

Module

Tsanangudzo

Transceiver Arbiter

Iyi generic inoshanda block inodzivirira transceivers kubva pakudzokorora panguva imwe chete kana RX kana TX transceivers mukati meiyo imwechete yemuviri chiteshi inoda kugadziridzwa. Kudzokorodza panguva imwe chete kunokanganisa maapplication uko RX neTX transceivers mukati meiyo chiteshi inopihwa kune yakazvimirira IP kuita. Iyi transceiver arbiter ndeyewedzero kune chigadziro chakakurudzirwa kubatanidza simplex TX uye simplex RX mune imwecheteyo yemuviri chiteshi. Iyi transceiver arbiter inobatsirawo mukubatanidza nekugadzirisa iyo Avalon® memory-mapped RX uye TX zvikumbiro zvekugadzirisa zvakare zvinonangana simplex RX uye TX transceivers mukati mechiteshi sezvo reconfiguration interface chiteshi chevachinjiki chinogona kuwanikwa chete sequentially. Iyo interface yekubatanidza pakati peiyo transceiver arbiter uye TX/RX Native PHY/PHY Reset Controller inovharira mune ino dhizaini ex.ample inoratidza generic modhi inoshanda kune chero IP musanganiswa uchishandisa transceiver arbiter. Transceiver arbiter haidiwe kana chete RX kana TX transceiver ichishandiswa muchiteshi. Iyo transceiver arbiter inozivisa mukumbi wegadziriso kuburikidza neayo Avalon memory-mapped reconfiguration interfaces uye inova nechokwadi chekuti inoenderana tx_reconfig_cal_busy kana rx_reconfig_cal_busy inogezwa saizvozvo. YeHDMI maapplication, RX chete ndiyo inotanga kugadzirisa zvakare. Nekuisa iyo Avalon memory-mapped reconfiguration chikumbiro kuburikidza nearbiter, arbiter anoratidza kuti chikumbiro chekugadzirisa chinobva kuRX, iyo inobva yavhara tx_reconfig_cal_busy kubva pakusimbisa uye inobvumira rx_reconfig_cal_busy kutaura. Iyo gedhi inodzivirira iyo TX transceiver kubva kuendeswa kune calibration mode usingazivi. Cherechedza: Nekuti HDMI inongoda RX kugadziridzwa, iyo tx_reconfig_mgmt_* masaini akasungwa. Zvakare, iyo Avalon memory-mapped interface haidiwe pakati pearbiter neTX Native PHY block. Iwo mabhuroki anopihwa kune iyo interface mudhizaini example kuratidza generic transceiver arbiter yekubatanidza kuTX/RX Native PHY/PHY Reset Controller

RX-TX Link

• Vhidhiyo data inobuda uye masiginecha ekubatanidza kubva kuHDMI RX core loop kuburikidza neDCFIFO mhiri kweRX neTX vhidhiyo wachi madhomeini. • Iyo yebetsero data port yeHDMI TX core inodzora data yebetsero inoyerera kuburikidza neDCFIFO kuburikidza nebackpressure. Iyo backpressure inovimbisa kuti hapana isina kukwana yekubatsira pakiti pane yekubatsira data port. • Chibhuroko ichi chinoitawo kusefa kwekunze: -Inosefa data redhiyo uye odhiyo wachi yekuvandudza pakiti kubva kune yekubatsira data rwizi isati yaendesa kuHDMI TX yakakosha data port. -Inosefa Iyo Yakakwira Dynamic Range (HDR) InfoFrame kubva kuHDMI RX yekubatsira data uye inoisa ex.ample HDR InfoFrame kune iyo yekubatsira data yeHDMI TX kuburikidza neAvalon inotenderera yakawanda.

CPU Subsystem

Iyo CPU subsystem inoshanda seSCDC neDDC controller, uye sosi reconfiguration controller. • Nzvimbo yeSCDC controller ine I2C master controller. Iyo I2C master controller inotamisa iyo SCDC data chimiro kubva kuFPGA sosi kuenda kune yekunze singi yeHDMI 2.0 mashandiro. For exampLe, kana iyo data inobuda iri 6,000 Mbps, iyo Nios II processor inoraira I2C master controller kuti ivandudze TMDS_BIT_CLOCK_RATIO uye SCRAMBLER_ENABLE bits ye sink TMDS gadziriso regisheni kusvika 1. • Iyo imwechete I2C tenzi inotamisawo iyo DDC data chimiro (E-EDID) pakati peHDMI sosi uye kunze sink. • Iyo Nios II CPU inoshanda semugadziri wekugadzirisa zvakare weiyo HDMI sosi. Iyo CPU inovimba neiyo periodic rate yekuona kubva kuRX Reconfiguration Management module kuona kana iyo TX inoda kugadziridzwazve. Iyo Avalon memory-mapped muranda mushanduri inopa chinongedzo pakati peNios II processor Avalon memory-mapped master interface uye yeAvalon memory-mapped muranda nzvimbo yekunze yakamisikidzwa HDMI sosi IOPLL uye TX Native PHY. • Ita kudzidziswa kwekubatanidza kuburikidza neI2C master interface ine sink yekunze

2.6. Dynamic Range uye Mastering (HDR) InfoFrame Insertion uye Kusefa
Iyo HDMI Intel FPGA IP dhizaini example inosanganisira kuratidzwa kwekuiswa kweHDR InfoFrame muRX-TX loopback system.
HDMI Tsanangudzo vhezheni 2.0b inobvumira Dynamic Range uye Mastering InfoFrame kuti ifambiswe kuburikidza neHDMI yekubatsira rwizi. Mukuratidzira, iyo Auxiliary Packet Generator block inotsigira iyo HDR kuiswa. Iwe unongoda kufometa iyo yakanangwa HDR InfoFrame packet sekutsanangurwa kweiyo module yechiratidzo tafura tafura uye kuiswa kweHDR InfoFrame kunoitika kamwe chete vhidhiyo furemu.
Mune example gadziriso, muzviitiko apo iyo inouya yekubatsira rwizi inotosanganisira HDR InfoFrame, iyo yakafambiswa HDR yemukati inosefa. Iko kusefa kunodzivirira kupokana HDR InfoFrames kuti ifambiswe uye inova nechokwadi chekuti chete hunhu hunotsanangurwa muHDR S.ample Data module inoshandiswa.
Mufananidzo 11. RX-TX Batanidza neDynamic Range uye Mastering InfoFrame Insertion
Nhamba yacho inoratidza dhizaini yeRX-TX link inosanganisira Dynamic Range uye Mastering InfoFrame kuisirwa muHDMI TX musimboti wekubatsira rukova.Tafura 12. Mubatsiri Data Insertion Block (aux_retransmit) Zviratidzo

Signal	Direction	Upamhi	Tsanangudzo
Clock uye Reset
clk	Input	1	Kuisa wachi. Wachi iyi inofanirwa kubatana newachi yevhidhiyo.
reset	Input	1	Reset input.

Anobatsira Packet Signals
tx_aux_data	Output	72	TX Inobatsira packet kubuda kubva kune multiplexer.
tx_aux_valid	Output	1
tx_aux_ready	Output	1
tx_aux_sop	Output	1
tx_aux_eop	Output	1
rx_aux_data	Input	72	RX Yekubatsira data yakapfuudzwa kune packet filter module isati yapinda mu multiplexer.
rx_aux_valid	Input	1
rx_aux_sop	Input	1
rx_aux_eop	Input	1

Chengetedza Chiratidzo
hdmi_tx_vsync	Input	1	HDMI TX Vhidhiyo Vsync. Chiratidzo ichi chinofanirwa kuwiriraniswa kune chinongedzo chewachi dhomeini.Musi uyu unoisa HDR InfoFrame kune yekubatsira kumucheto kunokwira kwechiratidzo ichi.

Tafura 13. HDR Data Module (altera_hdmi_hdr_infoframe) Zviratidzo

Signal	Direction	Upamhi	Tsanangudzo
hb0	Output	8	Header byte 0 yeDynamic Range uye Mastering InfoFrame: InfoFrame mhando kodhi.
hb1	Output	8	Header byte 1 yeDynamic Range uye Mastering InfoFrame: InfoFrame vhezheni nhamba.
hb2	Output	8	Header byte 2 yeDynamic Range uye Mastering InfoFrame: Kureba kweInfoFrame.
pb	Input	224	Data byte yeDynamic Range uye Mastering InfoFrame.

Tafura 14. Dynamic Range uye Mastering InfoFrame Data Byte Bundle Bit-Fields

Bit-Field	Tsanangudzo	Static Metadata Type 1
7:0	Data Byte 1: {5'h0, EOTF[2:0]}
15:8	Data Byte 2: {5'h0, Static_Metadata_Descriptor_ID[2:0]}
23:16	Data Byte 3: Static_Metadata_Descriptor	display_primaries_x[0], LSB
31:24	Data Byte 4: Static_Metadata_Descriptor	display_primaries_x[0], MSB
39:32	Data Byte 5: Static_Metadata_Descriptor	display_primaries_y[0], LSB
47:40	Data Byte 6: Static_Metadata_Descriptor	display_primaries_y[0], MSB
55:48	Data Byte 7: Static_Metadata_Descriptor	display_primaries_x[1], LSB
63:56	Data Byte 8: Static_Metadata_Descriptor	display_primaries_x[1], MSB
71:64	Data Byte 9: Static_Metadata_Descriptor	display_primaries_y[1], LSB
79:72	Data Byte 10: Static_Metadata_Descriptor	display_primaries_y[1], MSB
87:80	Data Byte 11: Static_Metadata_Descriptor	display_primaries_x[2], LSB
95:88	Data Byte 12: Static_Metadata_Descriptor	display_primaries_x[2], MSB
103:96	Data Byte 13: Static_Metadata_Descriptor	display_primaries_y[2], LSB
111:104	Data Byte 14: Static_Metadata_Descriptor	display_primaries_y[2], MSB
119:112	Data Byte 15: Static_Metadata_Descriptor	white_point_x, LSB
127:120	Data Byte 16: Static_Metadata_Descriptor	white_point_x, MSB
135:128	Data Byte 17: Static_Metadata_Descriptor	white_point_y, LSB
143:136	Data Byte 18: Static_Metadata_Descriptor	white_point_y, MSB
151:144	Data Byte 19: Static_Metadata_Descriptor	max_display_mastering_luminance, LSB

159:152	Data Byte 20: Static_Metadata_Descriptor	max_display_mastering_luminance, MSB
167:160	Data Byte 21: Static_Metadata_Descriptor	min_display_mastering_luminance, LSB
175:168	Data Byte 22: Static_Metadata_Descriptor	min_display_mastering_luminance, MSB
183:176	Data Byte 23: Static_Metadata_Descriptor	Maximum Content Light Level, LSB
191:184	Data Byte 24: Static_Metadata_Descriptor	Maximum Content Light Level, MSB
199:192	Data Byte 25: Static_Metadata_Descriptor	Maximum Frame-average Light Level, LSB
207:200	Data Byte 26: Static_Metadata_Descriptor	Maximum Frame-average Light Level, MSB
215:208	Reserved
223:216	Reserved

Kudzima HDR Kupinza uye kusefa
Kudzima kuisirwa HDR uye sefa kunoita kuti iwe ugone kuona kudzoreredzwa kweHDR zvirimo zvatovepo murukova rwekubatsira pasina kana shanduko muRX-TX Retransmit dhizaini ex.ample.
Kudzima kuisa HDR InfoFrame uye kusefa:

1. Isa block_ext_hdr_infoframe kuita 1'b0 mu rxtx_link.v file kudzivirira kusefa kweHDR InfoFrame kubva parukova rweKubatsira.
2. Seta multiplexer_in0_valid yeiyo avalon_st_multiplexer muenzaniso mu altera_hdmi_aux_hdr.v file kusvika ku1'b0 kudzivirira iyo Auxiliary Packet Jenareta kubva pakugadzira uye kuisa imwe HDR InfoFrame muTX Auxiliary stream.

2.7. Dhizaina Software Flow
Mune dhizaini huru software kuyerera, iyo Nios II processor inogadzirisa iyo TI yekudhiraivha kuseta uye inotanga iyo TX neRX nzira pane simba-kumusoro.
Mufananidzo 12. Kuyerera kweSoftware mu main.c Script
Iyo software inoita chinguva loop yekutarisa kunyura uye sosi shanduko, uye kuita kune shanduko. Iyo software inogona kukonzeresa TX reconfiguration, TX yekubatanidza kudzidziswa uye kutanga kufambisa vhidhiyo.
Mufananidzo 13. TX Path Initialization Flowchart Kutanga TX PathMufananidzo 14. RX Path Initialization FlowchartMufananidzo 15. TX Reconfiguration uye Link Training FlowchartMufananidzo 16. Batanidza Kudzidzisa LTS: 3 Maitiro pane Yakananga FRL Rate FlowchartMufananidzo 17. HDMI TX Video Transmission Flowchart2.8. Kumhanyisa Dhizaini mune Yakasiyana FRL Matengo
Iwe unogona kumhanyisa dhizaini yako mune akasiyana FRL mitengo, kunze kweiyo yekunze sink's default FRL mwero.
Kumhanyisa dhizaini mune akasiyana FRL mitengo:

1. Shandura iyo on-board user_dipsw0 chinja kune ON chinzvimbo.
2. Vhura iyo Nios II yekuraira shell, wobva wanyora nios2-terminal
3. Kiyi mumirairo inotevera uye tinya Enter kuti uite.

Command	Tsanangudzo
h	Ratidza menyu yekubatsira.
r0	Gadziridza iyo RX yakakura FRL kugona kune FRL mwero 0 (TMDS chete).
r1	Gadziridza iyo RX yakakura FRL kugona kune FRL mwero 1 (3 Gbps).
r2	Gadziridza iyo RX yakakura FRL kugona kune FRL mwero 2 (6 Gbps, 3 nzira).
r3	Gadziridza iyo RX yakakura FRL kugona kune FRL mwero 3 (6 Gbps, 4 nzira).
r4	Gadziridza iyo RX yakakura FRL kugona kune FRL mwero 4 (8 Gbps).
r5	Gadziridza iyo RX yakakura FRL kugona kune FRL mwero 5 (10 Gbps).
r6	Gadziridza iyo RX yakakura FRL kugona kune FRL mwero 6 (12 Gbps).
t1	TX inogadzirisa chiyero chekubatanidza kune FRL chiyero 1 (3 Gbps).
t2	TX inogadzirisa chiyero chekubatanidza kune FRL chiyero 2 (6 Gbps, 3 nzira).
t3	TX inogadzirisa chiyero chekubatanidza kune FRL chiyero 3 (6 Gbps, 4 nzira).
t4	TX inogadzirisa chiyero chekubatanidza kune FRL chiyero 4 (8 Gbps).
t5	TX inogadzirisa chiyero chekubatanidza kune FRL chiyero 5 (10 Gbps).
t6	TX inogadzirisa chiyero chekubatanidza kune FRL chiyero 6 (12 Gbps).

2.9. Clock Scheme
Chirongwa chewachi chinoratidza madomasi ewachi muHDMI Intel FPGA IP dhizaini example.
Mufananidzo 18. HDMI 2.1 Dhizaini Example Clock SchemeTafura 15. Kuvhara Scheme Zviratidzo

Clock	Zita rechiratidzo muKugadzira	Tsanangudzo
Management Clock	mgmt_clk	Yemahara inomhanya 100 MHz wachi yezvikamu izvi: • Avalon-MM interfaces yekugadzirisa zvakare - Iyo frequency renji inodiwa iri pakati pe100-125 MHz. • PHY reset controller ye transceiver reset kutevedzana - Iyo frequency renji inodiwa iri pakati pe1-500 MHz. • IOPLL Reconfiguration - Iyo yakanyanya wachi frequency ndeye 100 MHz. • RX Reconfiguration Management • TX Reconfiguration Management • CPU • I2C Master
I2C Clock	i2c_clk	Iyo 100 MHz wachi yekuisa iyo inovhara I2C muranda, inobuda mabhafa, SCDC marejista, uye yekubatanidza maitiro ekudzidzisa muHDMI RX musimboti, uye EDID RAM.
TX PLL Reference Clock 0	tx_tmds_clk	Reference wachi 0 kuTX PLL. Iyo wachi frequency yakafanana neinotarisirwa TMDS wachi frequency kubva kuHDMI TX TMDS wachi chiteshi. Iyi wachi yereferenzi inoshandiswa muTMDS mode. Kune iyi HDMI dhizaini example, wachi iyi yakabatana neRX TMDS wachi yekuratidzira chinangwa. Mukushandisa kwako, unofanirwa kupa wachi yakatsaurirwa ine TMDS wachi frequency kubva kune programmable oscillator kuti uite zvirinani jitter.

		Cherechedza: Usashandise transceiver RX pini seTX PLL referensi wachi. Dhizaini yako inotadza kukwana kana ukaisa iyo HDMI TX refclk paRX pini.
TX PLL Reference Clock 1	txfpll_refclk1/ rxphy_cdr_refclk1	Reference wachi kuTX PLL uye RX CDR, pamwe neIOPLL yevid_clk. Wachi frequency ndeye 100 MHz.
TX PLL Serial Clock	tx_bonding_clocks	Seri inokurumidza wachi inogadzirwa neTX PLL. Nguva yewachi inotarwa zvichienderana nehuwandu hwe data.
TX Transceiver Clock Out	tx_clk	Wachi yekubuda yakadzoserwa kubva kune transceiver, uye frequency inosiyana zvichienderana nehuwandu hwe data uye zviratidzo pawachi. TX transceiver wachi kunze frequency = Transceiver data rate/ Transceiver wide Kune iyi HDMI dhizaini example, iyo TX transceiver wachi kubva muchiteshi 0 inovhara iyo TX transceiver core input (tx_coreclkin), yekubatanidza kumhanya IOPLL (pll_hdmi) referensi wachi, uye vhidhiyo uye FRL IOPLL (pll_vid_frl) referensi wachi.
Vhidhiyo Clock	tx_vid_clk/rx_vid_clk	Vhidhiyo wachi kuenda kuTX uye RX musimboti. Wachi inomhanya pane yakatarwa frequency ye225 MHz.
TX/RX FRL Clock	tx_frl_clk/rx_frl_clk	FRL wachi kuenda kuTX uye RX musimboti.
RX TMDS Clock	rx_tmds_clk	TMDS clock channel kubva kuHDMI RX connector uye inobatana neIOPLL kuti ibudise wachi yereferensi yeCDR referensi wachi 0. Nheyo inoshandisa wachi iyi kana iri mu TMDS mode.
RX CDR Reference Clock 0	rxphy_cdr_refclk0	Reference wachi 0 kuenda kuRX CDR. Wachi iyi inotorwa kubva kuRX TMDS wachi. Iyo RX TMDS wachi frequency inotangira pa25 MHz kusvika 340 MHz ukuwo RX CDR shoma referensi wachi frequency iri 50 MHz. IOPLL inoshandiswa kugadzira 5 wachi frequency ye TMDS wachi pakati pe 25 MHz kusvika 50 MHz uye inogadzira imwecheteyo wachi frequency yewachi yeTMDS pakati pe50 MHz - 340 MHz.
RX Transceiver Clock Out	rx_clk	Clock out yakadzoserwa kubva kune transceiver, uye frequency inosiyana zvichienderana nehuwandu hwe data uye transceiver hupamhi. RX transceiver wachi kunze frequency = Transceiver data rate/ Transceiver wide Kune iyi HDMI dhizaini example, iyo RX transceiver wachi kunze kubva kuchiteshi 1 inovhara iyo RX transceiver core input (rx_coreclkin) uye FRL IOPLL (pll_frl) referensi wachi.

2.10. Interface Signals
Iwo matafura anonyora masaini eiyo HDMI dhizaini example ne FRL yakagoneswa.
Tafura 16. Pamusoro-Chiratidzo chepamusoro

Signal	Direction	Upamhi	Tsanangudzo
Pa-bhodhi Oscillator Chiratidzo
clk_fpga_b3_p	Input	1	100 MHz yemahara inomhanya wachi yepakati referensi wachi.
refclk4_p	Input	1	100 MHz yemahara inomhanya wachi ye transceiver referensi wachi.

Mushandisi Push Mabhatani uye LEDs
mushandisi_pb	Input	3	Batanidza bhatani kudzora iyo HDMI Intel FPGA IP dhizaini mashandiro.
cpu_resetn	Input	1	Global reset.
user_led_g	Output	8	Green LED kuratidza. Tarisa kune Hardware Setup papeji 48 kune rumwe ruzivo nezve ma LED mabasa.
user_dipsw	Input	1	Mushandisi-inotsanangurwa DIP switch. Tarisa kune Hardware Setup papeji 48 kune rumwe ruzivo nezve DIP chinja mabasa.

HDMI FMC Mwanasikana Kadhi Pini paFMC Port B
fmcb_gbtclk_m2c_p_0	Input	1	HDMI RX TMDS wachi.
fmcb_dp_m2c_p	Input	4	HDMI RX wachi, tsvuku, girini, uye bhuruu data chiteshi.
fmcb_dp_c2m_p	Output	4	HDMI TX wachi, tsvuku, girini, uye bhuruu data chiteshi.
fmcb_la_rx_p_9	Input	1	HDMI RX +5V simba rekuona.
fmcb_la_rx_p_8	Output	1	HDMI RX inopisa plug inoona.
fmcb_la_rx_n_8	Input	1	HDMI RX I2C SDA yeDDC uye SCDC.
fmcb_la_tx_p_10	Input	1	HDMI RX I2C SCL yeDDC uye SCDC.
fmcb_la_tx_p_12	Input	1	HDMI TX inopisa plug inoona.
fmcb_la_tx_n_12	Input	1	HDMI I2C SDA yeDDC uye SCDC.
fmcb_la_rx_p_10	Input	1	HDMI I2C SCL yeDDC uye SCDC.
fmcb_la_tx_n_9	Input	1	HDMI I2C SDA yekudzora dhiraivha.
fmcb_la_rx_p_11	Input	1	HDMI I2C SCL yekudzora dhiraivha.
fmcb_la_tx_n_13	Output	1	HDMI TX +5V Cherechedza: Inowanikwa chete kana Bitec HDMI Mwanasikana Kadhi Revision 9 inosarudzwa.

Tafura 17. HDMI RX Top-Level Zviratidzo

Signal	Direction	Upamhi	Tsanangudzo
Clock uye Reset Signals
mgmt_clk	Input	1	Kuiswa kwewachi yeSistimu (100 MHz).
reset	Input	1	System reset input.
rx_tmds_clk	Input	1	HDMI RX TMDS wachi.
i2c_clk	Input	1	Kuisa wachi yeDDC uye SCDC interface.

Clock uye Reset Signals
rxphy_cdr_refclk1	Input	1	Kupinza wachi yeRX CDR referensi wachi 1. Mafambiro ewachi ndeye 100 MHz.
rx_vid_clk	Output	1	Vhidhiyo wachi yakabuda.
sys_init	Output	1	Sisitimu yekutanga kugadzirisa zvakare sisitimu pane simba-kumusoro.

RX Transceiver uye IOPLL Zviratidzo
rxpll_tmds_locked	Output	1	Inoratidza wachi yeTMDS IOPLL yakavharwa.
rxpll_frl_locked	Output	1	Inoratidza wachi yeFRL IOPLL yakavharwa.
rxphy_serial_data	Input	4	HDMI serial data kune iyo RX Native PHY.
rxphy_ready	Output	1	Inoratidza iyo RX Native PHY yakagadzirira.
rxphy_cal_busy_raw	Output	4	RX Native PHY calibration yakabatikana kune transceiver arbiter.
rxphy_cal_busy_gated	Input	4	Calibration yakabatikana chiratidzo kubva kune transceiver arbiter kuenda kuRX Native PHY.
rxphy_rcfg_slave_write	Input	4	Transceiver reconfiguration Avalon memory-mapped interface kubva kuRX Native PHY kuenda kune transceiver arbiter.
rxphy_rcfg_slave_read	Input	4
rxphy_rcfg_slave_address	Input	40
rxphy_rcfg_slave_writedata	Input	128
rxphy_rcfg_slave_readdata	Output	128
rxphy_rcfg_slave_waitrequest	Output	4

RX Reconfiguration Management
rxphy_rcfg_busy	Output	1	RX Reconfiguration yakabatikana chiratidzo.
rx_tmds_freq	Output	24	HDMI RX TMDS wachi frequency kuyerwa (mu 10 ms).
rx_tmds_freq_valid	Output	1	Inoratidza iyo RX TMDS wachi frequency kuyerwa kuri kushanda.
rxphy_os	Output	1	Oversampling factor: •0: 1x pamusoroampling • 1: 5× pamusoroampling
rxphy_rcfg_master_write	Output	1	RX reconfiguration manejimendi Avalon memory-mapped interface kune transceiver arbiter.
rxphy_rcfg_master_read	Output	1
rxphy_rcfg_master_address	Output	12
rxphy_rcfg_master_writedata	Output	32
rxphy_rcfg_master_readdata	Input	32
rxphy_rcfg_master_waitrequest	Input	1

HDMI RX Core Zviratidzo
rx_vid_clk_locked	Input	1	Inoratidza kuti vid_clk yakagadzikana.
rxcore_frl_rate	Output	4	Inoratidza chiyero cheFRL icho RX musimboti uri kushanda. • 0: Legacy Mode (TMDS) • 1: 3 Gbps 3 nzira • 2: 6 Gbps 4 nzira • 3: 6 Gbps 4 nzira • 4: 8 Gbps 4 nzira • 5: 10 Gbps 4 nzira • 6: 12 Gbps 4 nzira • 7-15: Zvakachengetwa
rxcore_frl_locked	Output	4	Imwe neimwe bhiti inoratidza chaiyo nzira yakawana FRL kukiya. FRL yakavharwa kana iyo RX musimboti ikabudirira kuita kurongeka, deskew, uye kuwana nzira yekukiya. • Kune 3-lane mode, kukiya kwenzira kunowanikwa apo RX core inogamuchira Scrambler Reset (SR) kana Start-Super-Block (SSB) yenguva yega yega 680 FRL yemavara kanenge ka3. • Kune 4-lane mode, kukiya kwenzira kunowanikwa apo RX core inogamuchira Scrambler Reset (SR) kana Start-Super-Block (SSB) yenguva yega yega 510 FRL yemavara kanenge ka3.
rxcore_frl_ffe_levels	Output	4	Inoenderana neFFE_level bit muSCDC 0x31 register bit [7:4] muRX core.
rxcore_frl_flt_ready	Input	1	Asserts kuratidza iyo RX yakagadzirira iyo link yekudzidzisa maitiro kutanga. Kana zvichinzi, FLT_ready bit muSCDC rejista 0x40 bit 6 inosimbiswa zvakare.
rxcore_frl_src_test_config	Input	8	Inotsanangura magadzirirwo ebvunzo kwakabva. Hukoshi hwakanyorwa muSCDC Test Configuration rejista muSCDC rejista 0x35.
rxcore_tbcr	Output	1	Inoratidza iyo TMDS zvishoma kune wachi reshiyo; inoenderana neTMDS_Bit_Clock_Ratio rejista muSCDC rejista 0x20 bit 1. • Paunenge uchimhanya muHDMI 2.0 mode, iyi bit inosimbiswa. Inoratidza iyo TMDS bit to wachi reshiyo ye40:1. • Paunenge uchimhanya muHDMI 1.4b, chidimbu ichi hachina kusimbiswa. Inoratidza iyo TMDS bit kune wachi reshiyo ye10: 1. • Ichi chidimbu hachishandiswe kuFRL modhi.
rxcore_scrambler_enable	Output	1	Inoratidza kana iyo data yakagamuchirwa yakadzvanywa; inoenderana neScrambling_Enable ndima muSCDC rejista 0x20 bit 0.
rxcore_audio_de	Output	1	HDMI RX musimboti audio interfaces Tarisa kune Sink Interfaces chikamu mu HDMI Intel FPGA IP User Guide kuti uwane rumwe ruzivo.
rxcore_audio_data	Output	256
rxcore_audio_info_ai	Output	48

rxcore_audio_N	Output	20
rxcore_audio_CTS	Output	20
rxcore_audio_metadata	Output	165
rxcore_audio_format	Output	5
rxcore_aux_pkt_data	Output	72	HDMI RX musimboti wekubatsira interfaces Tarisa kune Sink Interfaces chikamu mu HDMI Intel FPGA IP User Guide kuti uwane rumwe ruzivo.
rxcore_aux_pkt_addr	Output	6
rxcore_aux_pkt_wr	Output	1
rxcore_aux_data	Output	72
rxcore_aux_sop	Output	1
rxcore_aux_eop	Output	1
rxcore_aux_valid	Output	1
rxcore_aux_error	Output	1
rxcore_gcp	Output	6	HDMI RX musimboti webhendi masaini Tarisa kune Sink Interfaces chikamu mu HDMI Intel FPGA IP User Guide kuti uwane rumwe ruzivo.
rxcore_info_avi	Output	123
rxcore_info_vsi	Output	61
rxcore_locked	Output	1	HDMI RX yakakosha vhidhiyo ports Cherechedza: N = pixels pawachi Tarisa kune Sink Interfaces chikamu mu HDMI Intel FPGA IP User Guide kuti uwane rumwe ruzivo.
rxcore_vid_data	Output	N*48
rxcore_vid_vsync	Output	N
rxcore_vid_hsync	Output	N
rxcore_vid_de	Output	N
rxcore_vid_valid	Output	1
rxcore_vid_lock	Output	1
rxcore_mode	Output	1	HDMI RX musimboti kudzora uye mamiriro ports. Cherechedza: N = zviratidzo pawachi Tarisa kune Sink Interfaces chikamu mu HDMI Intel FPGA IP User Guide kuti uwane rumwe ruzivo.
rxcore_ctrl	Output	N*6
rxcore_color_depth_sync	Output	2
hdmi_5v_detect	Input	1	HDMI RX 5V inoona uye hotplug yekuona. Tarisa kune Sink Interfaces chikamu mu HDMI Intel FPGA IP User Guide kuti uwane rumwe ruzivo.
hdmi_rx_hpd	Output	1
rx_hpd_trigger	Input	1

I2C Signals
hdmi_rx_i2c_sda	Input	1	HDMI RX DDC uye SCDC interface.
hdmi_rx_i2c_scl	Input	1

RX EDID RAM Zviratidzo
edid_ram_access	Input	1	HDMI RX EDID RAM yekuwana interface.

edid_ram_address	Input	8	Bvunza edid_ram_access kana uchida kunyora kana kuverenga kubva paEDID RAM, ukasadaro chiratidzo ichi chinofanira kugara chakaderera. Kana iwe uchiti edid_ram_access, hotplug siginecha dhizari kubvumidza kunyora kana kuverenga kune EDID RAM. Kana EDID RAM yekuwana yapedzwa, iwe unofanirwa kubvisa edid_ram_assess uye hotplug chiratidzo chekutaura. Iyo sosi ichaverenga iyo itsva EDID nekuda kweiyo hotplug siginecha yekubatisa.
edid_ram_write	Input	1
edid_ram_read	Input	1
edid_ram_readdata	Output	8
edid_ram_writedata	Input	8
edid_ram_waitrequest	Output	1

Tafura 18.HDMI TX Top-Level Signals

Signal	Direction	Upamhi	Tsanangudzo
Clock uye Reset Signals
mgmt_clk	Input	1	Kuiswa kwewachi yeSistimu (100 MHz).
reset	Input	1	System reset input.
tx_tmds_clk	Input	1	HDMI RX TMDS wachi.
txfpll_refclk1	Input	1	Kupinza wachi yeTX PLL referensi wachi 1. Mafambiro ewachi ndeye 100 MHz.
tx_vid_clk	Output	1	Vhidhiyo wachi yakabuda.
tx_frl_clk	Output	1	FRL wachi kubuda.
sys_init	Input	1	Sisitimu yekutanga kugadzirisa zvakare sisitimu pane simba-kumusoro.
tx_init_done	Input	1	TX kutanga kugadzirisa zvakare TX reconfiguration management block uye transceiver reconfiguration interface.

TX Transceiver uye IOPLL Zviratidzo
txpll_frl_locked	Output	1	Inoratidza chinongedzo chekumhanyisa wachi uye FRL wachi IOPLL yakavharwa.
txfpll_locked	Output	1	Inoratidza kuti TX PLL yakavharwa.
txphy_serial_data	Output	4	HDMI serial data kubva kuTX Native PHY.
txphy_ready	Output	1	Inoratidza kuti TX Native PHY yakagadzirira.
txphy_cal_busy	Output	1	TX Native PHY calibration yakabatikana chiratidzo.
txphy_cal_busy_raw	Output	4	Calibration yakabatikana chiratidzo kune transceiver arbiter.
txphy_cal_busy_gated	Input	4	Calibration yakabatikana chiratidzo kubva kune transceiver arbiter kuenda kuTX Native PHY.
txphy_rcfg_busy	Output	1	Inoratidza kuti TX PHY reconfiguration iri kuitika.
txphy_rcfg_slave_write	Input	4	Transceiver reconfiguration Avalon memory-mapped interface kubva kuTX Native PHY kuenda kune transceiver arbiter.
txphy_rcfg_slave_read	Input	4
txphy_rcfg_slave_address	Input	40
txphy_rcfg_slave_writedata Input 128 txphy_rcfg_slave_readdata Output 128 txphy_rcfg_slave_waitrequest Output 4

TX Reconfiguration Management
tx_tmds_freq	Input	24	HDMI TX TMDS wachi frequency kukosha (mu 10 ms).
tx_os	Output	2	Oversampling factor: • 0: 1x pamusoroampling •1: 2× pamusoroampling •2: 8x pamusoroampling
txphy_rcfg_master_write	Output	1	TX reconfiguration management Avalon memory-mapped interface kune transceiver arbiter.
txphy_rcfg_master_read	Output	1
txphy_rcfg_master_address	Output	12
txphy_rcfg_master_writedata	Output	32
txphy_rcfg_master_readdata	Input	32
txphy_rcfg_master_waitrequest	Input	1
tx_reconfig_done	Output	1	Inoratidza kuti TX reconfiguration process yapera.

HDMI TX Core Signals
tx_vid_clk_locked	Input	1	Inoratidza kuti vid_clk yakagadzikana.
txcore_ctrl	Input	N*6	HDMI TX core control interfaces. Cherechedza: N = pixels pawachi Tarisa kune Source Interfaces chikamu mu HDMI Intel FPGA IP User Guide kuti uwane rumwe ruzivo.
txcore_mode	Input	1
txcore_audio_de	Input	1	HDMI TX musimboti audio interfaces. Tarisa kune Source Interfaces chikamu mu HDMI Intel FPGA IP User Guide kuti uwane rumwe ruzivo.
txcore_audio_mute	Input	1
txcore_audio_data	Input	256
txcore_audio_info_ai	Input	49
txcore_audio_N	Input	20
txcore_audio_CTS	Input	20
txcore_audio_metadata	Input	166
txcore_audio_format	Input	5
txcore_aux_ready	Output	1	HDMI TX musimboti wekubatsira nzvimbo. Tarisa kune Source Interfaces chikamu mu HDMI Intel FPGA IP User Guide kuti uwane rumwe ruzivo.
txcore_aux_data	Input	72
txcore_aux_sop	Input	1
txcore_aux_eop	Input	1

txcore_aux_valid	Input	1
txcore_gcp	Input	6	HDMI TX musimboti webhendi masaini. Tarisa kune Source Interfaces chikamu mu HDMI Intel FPGA IP User Guide kuti uwane rumwe ruzivo.
txcore_info_avi	Input	123
txcore_info_vsi	Input	62
txcore_i2c_master_write	Input	1	TX I2C tenzi Avalon memory-mapped interface kune I2C tenzi mukati meTX musimboti. Cherechedza: Aya masaini anowanikwa chete kana iwe ukabatidza Kusanganisira I2C parameter.
txcore_i2c_master_read	Input	1
txcore_i2c_master_address	Input	4
txcore_i2c_master_writedata	Input	32
txcore_i2c_master_readdata	Output	32
txcore_vid_data	Input	N*48	HDMI TX yakakosha vhidhiyo ports. Cherechedza: N = pixels pawachiRef er kune Source Interfaces chikamu mu HDMI Intel FPGA IP User Guide kuti uwane rumwe ruzivo.
txcore_vid_vsync	Input	N
txcore_vid_hsync	Input	N
txcore_vid_de	Input	N
txcore_vid_ready	Output	1
txcore_vid_overflow	Output	1
txcore_vid_valid	Input	1
txcore_frl_rate	Input	4	SCDC rejista interfaces.
txcore_frl_pattern	Input	16
txcore_frl_start	Input	1
txcore_scrambler_enable	Input	1
txcore_tbcr	Input	1

I2C Signals
nios_tx_i2c_sda_in	Output	1	TX I2C Master interface yeSCDC neDDC kubva kuNios II processor kusvika kune inobuda buffer. Cherechedza: Kana ukabatidza Kusanganisira I2C parameter, aya masaini achaiswa mukati meiyo TX musimboti uye haazoonekwi padanho iri.
nios_tx_i2c_scl_in	Output	1
nios_tx_i2c_sda_oe	Input	1
nios_tx_i2c_scl_oe	Input	1
nios_ti_i2c_sda_in	Output	1	TX I2C Master interface kubva kuNios II processor kuenda kune inobuda buffer yekudzora TI redriver paBitec HDMI 2.1 FMC mwanasikana kadhi.
nios_ti_i2c_scl_in	Output	1
nios_ti_i2c_sda_oe	Input	1
nios_ti_i2c_scl_oe	Input	1
hdmi_tx_i2c_sda	Input	1	TX I2C inopindirana yeSCDC neDDC inopindirana kubva kune inobuda buffer kuenda kuHDMI TX yekubatanidza.
hdmi_tx_i2c_scl	Input	1
hdmi_tx_ti_i2c_sda	Input	1	TX I2C inopindirana kubva painobuda buffer kuenda kuTI redriver paBitec HDMI 2.1 FMC mwanasikana kadhi.
hdmi_tx_ti_i2c_scl	Input	1

tx_hpd_req	Output	1	HDMI TX hotplug inoona nzvimbo dzekupindirana.
hdmi_tx_hpd_n	Input	1

Tafura 19. Transceiver Arbiter Signals

Signal	Direction	Upamhi	Tsanangudzo
clk	Input	1	Reconfiguration wachi. Wachi iyi inofanirwa kugovera wachi imwe chete nemabhuroki ekugadzirisa zvakare.
reset	Input	1	Reset chiratidzo. Iyi reset inofanirwa kugovera iyo yakafanana kuseta nemabhuroko ekugadzirisa manejimendi.
rx_rcfg_en	Input	1	RX reconfiguration inogonesa chiratidzo.
tx_rcfg_en	Input	1	TX reconfiguration inogonesa chiratidzo.
rx_rcfg_ch	Input	2	Inoratidza kuti ndeipi chiteshi chinogadziriswa paRX musimboti. Ichi chiratidzo chinofanira kugara chakasimbiswa.
tx_rcfg_ch	Input	2	Inoratidza kuti ndeipi chiteshi chinogadziriswa paTX core. Ichi chiratidzo chinofanira kugara chakasimbiswa.
rx_reconfig_mgmt_write	Input	1	Reconfiguration Avalon memory-mapped interfaces kubva kuRX reconfiguration manejimendi.
rx_reconfig_mgmt_read	Input	1
rx_reconfig_mgmt_address	Input	10
rx_reconfig_mgmt_writedata	Input	32
rx_reconfig_mgmt_readdata	Output	32
rx_reconfig_mgmt_waitrequest	Output	1
tx_reconfig_mgmt_write	Input	1	Reconfiguration Avalon memory-mapped interfaces kubva kuTX reconfiguration manejimendi.
tx_reconfig_mgmt_read	Input	1
tx_reconfig_mgmt_address	Input	10
tx_reconfig_mgmt_writedata	Input	32
tx_reconfig_mgmt_readdata	Output	32
tx_reconfig_mgmt_waitrequest	Output	1
reconfig_write	Output	1	Reconfiguration Avalon memory-mapped interfaces kune transceiver.
reconfig_read	Output	1
reconfig_address	Output	10
reconfig_writedata	Output	32
rx_reconfig_readdata	Input	32
rx_reconfig_waitrequest	Input	1
tx_reconfig_readdata	Input	1
tx_reconfig_waitrequest	Input	1

rx_cal_busy	Input	1	Calibration chimiro chiratidzo kubva kuRX transceiver.
tx_cal_busy	Input	1	Calibration chimiro chiratidzo kubva kuTX transceiver.
rx_reconfig_cal_busy	Output	1	Calibration chimiro chiratidzo kune RX transceiver PHY reset control.
tx_reconfig_cal_busy	Output	1	Calibration chimiro chiratidzo kubva kuTX transceiver PHY reset control.

Tafura 20. RX-TX Link Signals

Signal	Direction	Upamhi	Tsanangudzo
vid_clk	Input	1	HDMI vhidhiyo wachi.
rx_vid_lock	Input	3	Inoratidza HDMI RX vhidhiyo kukiya mamiriro.
rx_vid_valid	Input	1	HDMI RX vhidhiyo interfaces.
rx_vid_de	Input	N
rx_vid_hsync	Input	N
rx_vid_vsync	Input	N
rx_vid_data	Input	N*48
rx_aux_eop	Input	1	HDMI RX yekubatsira interfaces.
rx_aux_sop	Input	1
rx_aux_valid	Input	1
rx_aux_data	Input	72
tx_vid_de	Output	N	HDMI TX vhidhiyo interfaces. Cherechedza: N = pixels pawachi
tx_vid_hsync	Output	N
tx_vid_vsync	Output	N
tx_vid_data	Output	N*48
tx_vid_valid	Output	1
tx_vid_ready	Input	1
tx_aux_eop	Output	1	HDMI TX yekubatsira interfaces.
tx_aux_sop	Output	1
tx_aux_valid	Output	1
tx_aux_data	Output	72
tx_aux_ready	Input	1

Tafura 21. Platform Designer System Signals

Signal	Direction	Upamhi	Tsanangudzo
cpu_clk_in_clk_clk	Input	1	CPU wachi.
cpu_rst_in_reset_reset	Input	1	CPU reset.

edid_ram_slave_translator_avalon_anti_slave_0_address	Output	8	EDID RAM yekuwana interfaces.
edid_ram_slave_translator_avalon_anti_slave_0_write	Output	1
edid_ram_slave_translator_avalon_anti_slave_0_read	Output	1
edid_ram_slave_translator_avalon_anti_slave_0_readdata	Input	8
edid_ram_slave_translator_avalon_anti_slave_0_writedata	Output	8
edid_ram_slave_translator_avalon_anti_slave_0_waitrequest	Input	1
hdmi_i2c_master_i2c_serial_sda_in	Input	1	I2C Master inopindirana kubva kuNios II processor kune inobuda buffer yeDDC uye SCDC kutonga.
hdmi_i2c_master_i2c_serial_scl_in	Input	1
hdmi_i2c_master_i2c_serial_sda_oe	Output	1
hdmi_i2c_master_i2c_serial_scl_oe	Output	1
redriver_i2c_master_i2c_serial_sda_in	Input	1	I2C Master inopindirana kubva kuNios II processor kuenda kune inobuda buffer yeTI redriver yekumisikidza kumisikidzwa.
redriver_i2c_master_i2c_serial_scl_in	Input	1
redriver_i2c_master_i2c_serial_sda_oe	Output	1
redriver_i2c_master_i2c_serial_scl_oe	Output	1
pio_in0_external_connection_export	Input	32	Parallel input output interfaces. • Bit 0: Yakabatanidzwa kune user_dipsw siginecha kudzora EDID passthrough mode. •Bit 1: TX HPD chikumbiro •Bit 2: TX transceiver yakagadzirira •Bits 3: TX reconfiguration yaitwa •Bits 4–7: Zvakachengetwa • Bits 8–11: RX FRL rate • Bit 12: RX TMDS bit clock ratio • Bits 13–16: RX FRL yakakiyiwa • Bits 17–20: RX FFE mazinga • Bit 21: RX kurongeka kwakavharwa

Signal	Direction	Upamhi	Tsanangudzo
			•Bit 22: RX kukiya vhidhiyo • Bit 23: Mushandisi push bhatani 2 kuverenga SCDC marejista kubva kunze singi •Bits 24–31: Zvakachengetwa
pio_out0_external_connection_export	Output	32	Parallel input output interfaces. •Bit 0: TX HPD kubvuma •Bit 1: TX kutanga kwaitwa • Bits 2–7: Zvakachengetwa • Bits 8–11: TX FRL mwero •Bits 12–27: TX FRL link yekudzidzira maitiro • Bit 28: TX FRL kutanga • Bits 29–31: Zvakachengetwa
pio_out1_external_connection_export	Output	32	Parallel input output interfaces. • Bit 0: RX EDID RAM kuwana • Bit 1: RX FLT yakagadzirira • Bits 2–7: Zvakachengetwa • Bits 8–15: RX FRL source test configuration •Bits 16–31: Zvakachengetwa

2.1. 1. Gadzira RTL Parameters
Shandisa HDMI TX uye RX Pamusoro RTL paramita kugadzirisa dhizaini example.
Zvizhinji zvemagadzirirwo parameters anowanikwa mu Design Example tebhu yeHDMI Intel FPGA IP parameter mupepeti. Iwe unogona zvakare kushandura dhizaini example marongero awakagadzira muparameter mupepeti kuburikidza neRTL paramita.
Tafura 22. HDMI RX Top Parameters

Parameter	Value	Tsanangudzo
SUPPORT_DEEP_COLOR	• 0: Hapana ruvara rwakadzika • : Ruvara rwakadzama	Inosarudza kana iyo yakakosha inogona encode yakadzika mavara mafomati.
SUPPORT_AUXILIARY	• 0: Hapana AUX •1: AUX	Inotarisa kana iyo yekubatsira chiteshi encoding inosanganisirwa.
SYMBOLS_PER_CLOCK	8	Inotsigira 8 zviratidzo pawachi yeIntel Arria 10 zvishandiso.
SUPPORT_AUDIO	• 0: Hapana audio • 1: Audio	Inoona kana musimboti uchikwanisa kukodha odhiyo.

EDID_RAM_ADDR_WIDTH	8 (Default kukosha)	Log base 2 yeEDID RAM saizi.
BITEC_DAUGHTER_CARD_REV	•0: Kwete kunanga chero Bitec HDMI mwanasikana kadhi •4: Inotsigira Bitec HDMI mwanasikana kadhi kudzokorora 4 • 6: Targeting Bitec HDMI mwanasikana kadhi revision 6 • 11: Targeting Bitec HDMI mwanasikana kadhi revision 11 (default)	Inotsanangura kudzokororwa kweBitec HDMI mwanasikana kadhi rakashandiswa. Paunoshandura gadziriso, dhizaini inogona kuchinjanisa ma transceiver chiteshi uye kushandura polarity zvinoenderana neBitec HDMI mwanasikana kadhi zvinodiwa. Kana ukaisa BITEC_DAUGHTER_CARD_REV parameter kusvika 0, magadzirirwo acho haaiti chero shanduko kumatanho etransceiver uye polarity.
POLARITY_INVERSION	• 0: Invert polarity 1: Usapindure polarity	Gadzirisa iyi parameter kune 1 kuti inverted kukosha kwechimwe nechimwe che data yekupinza. Kuseta iyi parameter kune 1 inopa 4'b1111 kune rx_polinv chiteshi cheiyo RX transceiver.

Tafura 23. HDMI TX Top Parameters

Parameter	Value	Tsanangudzo
USE_FPLL	1	Inotsigira fPLL seTX PLL chete yeIntel Arria 10 zvishandiso. Gara uchiisa iyi parameter ku1.
SUPPORT_DEEP_COLOR	•0: Hapana ruvara rwakadzika • 1: Ruvara rwakadzama	Inosarudza kana iyo yakakosha inogona encode yakadzika mavara mafomati.
SUPPORT_AUXILIARY	• 0: Hapana AUX • 1: AUX	Inotarisa kana iyo yekubatsira chiteshi encoding inosanganisirwa.
SYMBOLS_PER_CLOCK	8	Inotsigira 8 zviratidzo pawachi yeIntel Arria 10 zvishandiso.
SUPPORT_AUDIO	• 0: Hapana audio • 1: Audio	Inoona kana musimboti uchikwanisa kukodha odhiyo.
BITEC_DAUGHTER_CARD_REV	• 0: Kwete kunanga chero Bitec HDMI mwanasikana kadhi • 4: Inotsigira Bitec HDMI mwanasikana kadhi kudzokorora 4 • 6: Targeting Bitec HDMI mwanasikana kadhi revision 6 • 11: Targeting Bitec HDMI mwanasikana kadhi revision 11 (default)	Inotsanangura kudzokororwa kweBitec HDMI mwanasikana kadhi rakashandiswa. Paunoshandura gadziriso, dhizaini inogona kuchinjanisa ma transceiver chiteshi uye kushandura polarity zvinoenderana neBitec HDMI mwanasikana kadhi zvinodiwa. Kana ukaisa BITEC_DAUGHTER_CARD_REV parameter kusvika 0, magadzirirwo acho haaiti chero shanduko kumatanho etransceiver uye polarity.
POLARITY_INVERSION	• 0: Invert polarity 1: Usapindure polarity	Gadzirisa iyi parameter kune 1 kuti inverted kukosha kwechimwe nechimwe che data yekupinza. Kuseta iyi parameter kune 1 inopa 4'b1111 kune tx_polinv chiteshi cheTX transceiver.

2.12. Hardware Setup
Iyo HDMI FRL-inogonesa dhizaini exampiyo HDMI 2.1 inokwanisa uye inoita loopthrough kuratidzira kune yakajairwa HDMI vhidhiyo rwizi.
Kuti umhanye bvunzo dzehardware, batanidza mudziyo unogoneswa neHDMI-senge kadhi remifananidzo rine HDMI interface- kune HDMI sink yekupinda. Dhizaini inotsigira ese HDMI 2.1 kana HDMI 2.0/1.4b sosi uye kunyura.

1. Iyo HDMI sink inodhidha chiteshi kuita yakajairwa vhidhiyo rwizi uye inotumira kune wachi yekudzoreredza musimboti.
2. Iyo HDMI RX musimboti inosarudza vhidhiyo, yebetsero, uye odhiyo data kuti idzoserwe kumashure inoenderana neiyo HDMI TX musimboti kuburikidza neDCFIFO.
3. Iyo HDMI sosi chiteshi cheFMC mwanasikana kadhi inoendesa chifananidzo kune chekutarisa.

Cherechedza:
Kana iwe uchida kushandisa imwe Intel FPGA yekuvandudza bhodhi, iwe unofanirwa kushandura iyo migove yemuchina uye pini yekupihwa. Iyo transceiver analog kuseta inoedzwa iyo Intel Arria 10 FPGA yekuvandudza kit uye Bitec HDMI 2.1 mwanasikana kadhi. Iwe unogona kugadzirisa zvirongwa zvebhodhi rako pachako.
Tafura 24. Pa-bhodhi Push Button uye User LED Mabasa

Push Bhatani / LED	Function
cpu_resetn	Dzvanya kamwe kuti uite system reset.
user_dipsw	Mushandisi-inotsanangurwa DIP switch yekushandura iyo passthrough modhi. • OFF (default position) = Passthrough HDMI RX paFPGA inowana iyo EDID kubva kunyura yekunze uye inoiisa kune yekunze sosi iyo yakabatana nayo. • ON = Unogona kudzora RX yepamusoro FRL chiyero kubva kuNios II terminal. Iwo murairo unogadzirisa iyo RX EDID nekushandisa iyo yakanyanya FRL chiyero kukosha. Tarisa kuKumhanyisa Dhizaini mune Yakasiyana FRL Mareti ari papeji 33 kuti uwane rumwe ruzivo nezve kuseta akasiyana FRL mareti.
mushandisi_pb[0]	Dzvanya kamwe chete kushandura chiratidzo cheHPD kune yakajairwa HDMI sosi.
mushandisi_pb[1]	Reserved.
mushandisi_pb[2]	Dzvanya kamwe kuti uverenge SCDC marejista kubva padhishi yakabatana neTX yeBitec HDMI 2.1 FMC mwanasikana kadhi. Cherechedza: Kuti ugone kuverenga, unofanirwa kuseta DEBUG_MODE kune 1 musoftware.
USER_LED[0]	RX TMDS wachi PLL kukiya mamiriro. •0 = Yakakiyiwa • 1 = Yakakiyiwa
USER_LED[1]	RX transceiver yakagadzirira chimiro. •0 = Haina kugadzirira • 1 = Yakagadzirira
USER_LED[2]	RX yekubatanidza yekumhanyisa wachi PLL, uye RX vhidhiyo uye FRL wachi PLL kukiya mamiriro. • 0 = Imwe yeRX wachi PLL yakavhurwa • 1 = Zvose RX wachi PLLs dzakakiyiwa
USER_LED[3]	RX HDMI musimboti kurongeka uye deskew kukiya mamiriro. • 0 = Kanenge 1 channel inokiyiwa • 1 = Zviteshi zvose zvakakiyiwa
USER_LED[4]	RX HDMI vhidhiyo kukiya mamiriro. • 0 = Yakakiyiwa • 1 = Yakakiyiwa
USER_LED[5]	TX yekubatanidza yekumhanyisa wachi PLL, uye TX vhidhiyo uye FRL wachi PLL kukiya mamiriro. •0 = Imwe yeTX wachi PLL yakavhurwa • 1 = Zvose TX wachi PLLs dzakakiyiwa
USER_LED[6] USER_LED[7]	TX transceiver yakagadzirira chimiro. • 0 = Haina kugadzirira • 1 = Yakagadzirira TX yekubatanidza mamiriro ekudzidziswa. • 0 = Yakundikana • 1 = Yakapfuura

2.13. Simulation Testbench
Iyo simulation testbench inoteedzera iyo HDMI TX serial loopback kune iyo RX musimboti.
Cherechedza:
Iyi yekunyepedzera testbench haitsigirwe magadzirirwo ane Include I2C parameter yakagoneswa.
Mufananidzo 19. HDMI Intel FPGA IP Simulation Testbench Block DiagramTafura 25. Testbench Zvikamu

Chikamu	Tsanangudzo
Vhidhiyo TPG	Iyo vhidhiyo bvunzo pateni jenareta (TPG) inopa vhidhiyo inosimudzira.
Audio Sample Gen	Iyo audio sample jenareta inopa odhiyo sample stimulus. Iyo jenareta inogadzira iyo inowedzera bvunzo data pateni kuti ifambiswe kuburikidza neodhiyo chiteshi.
Aux Sample Gen	The aux sample jenareta inopa ebetsero sample stimulus. Iyo jenareta inogadzira data rakagadziriswa kuti rifambiswe kubva kune transmitter.

CRC Tarisa	Iyi yekutarisa inoongorora kana iyo TX transceiver yakadzoreredza wachi frequency ichienderana neinodiwa data data.
Audio Data Check	Iyo yekuteerera dhata cheki inofananidza kana iyo inowedzera bvunzo data patani inogamuchirwa uye yakadhindwa nemazvo.
Aux Data Check	Iyo aux data cheki inofananidza kana iyo inotarisirwa aux data inogamuchirwa uye yakatemwa nemazvo padivi rekugamuchira.

Iyo HDMI simulation testbench inoita zvinotevera bvunzo bvunzo:

HDMI Feature	Verification
Vhidhiyo data	• Testbench inoshandisa CRC ichitarisa pakupinda nekubuda kwevhidhiyo. • Inotarisa kukosha kweCRC ye data yakatumirwa kuCRC yakaverengerwa muvhidhiyo yakagamuchirwa data. • Testbench inobva yaita cheki mushure mekuona 4 yakagadzikana V-SYNC zviratidzo kubva kune anogamuchira.
Auxiliary data	• Nyaya sample jenareta inogadzira data rakagadziriswa kuti rifambiswe kubva kune transmitter. • Padivi rekugamuchira, jenareta inoenzanisa kana data inotarisirwa yebetsero inogamuchirwa uye yakadhindwa nemazvo.
Audio data	•Odhiyo sample jenareta inogadzira iyo inowedzera bvunzo data pateni kuti ifambiswe kuburikidza neodhiyo chiteshi. • Kudivi rekugamuchira, redhiyo data cheki inotarisa uye inoenzanisa kana iyo incrementing test data pateni inogamuchirwa uye yakatemwa nemazvo.

Simulation yakabudirira inopera neshoko rinotevera:
# SYMBOLS_PER_CLOCK = 2
#VIC = 4
# FRL_RATE = 0
# BPP = 0
# AUDIO_FREQUENCY (kHz) = 48
# AUDIO_CHANNEL = 8
# Simulation pass
Tafura 26. HDMI Intel FPGA IP Dhizaini Example Inotsigirwa Simulators

Simulator	Verilog HDL	VHDL
ModelSim - Intel FPGA Edition / ModelSim - Intel FPGA Starter Edition	Ehe	Ehe
VCS/VCS MX	Ehe	Ehe
Riviera-PRO	Ehe	Ehe
Xcelium Parallel	Ehe	Aihwa

2.14. Design Limitations
Iwe unofanirwa kufunga nezve zvimwe zvisingakwanisi kana uchisimbisa iyo HDMI 2.1 dhizaini example.

• TX haikwanise kushanda muTMDS modhi kana isiri-passthrough mode. Kuti uedze muTMDS modhi, chinja user_dipsw chinja uchidzokera kupassthrough mode.
• Iyo Nios II processor inofanirwa kushandira iyo TX yekubatanidza kudzidziswa kuti ipedze pasina chero kukanganisa kubva kune mamwe maitiro.

2.15. Debugging Features
Iyi dhizaini example inopa mamwe maitiro ekugadzirisa kuti akubatsire.
2.15.1. Software Debugging Message
Iwe unogona kubatidza meseji yedebugging musoftware kuti ikupe iwe-run-time rubatsiro.
Kuti ubatidze meseji yedebugging musoftware, tevera matanho aya:

1. Chinja DEBUG_MODE kuita 1 muglobal.h script.
2. Mhanya script/build_sw.sh paNios II Raira Shell.
3. Rongazve iyo yakagadzirwa software/tx_control/tx_control.elf file nekumhanyisa rairo paNios II Command Shell:
   nios2-download -r -g software/tx_control/tx_control.elf
4. Mhanya iyo Nios II terminal command paNios II Command Shell:
   nios2-terminal

Paunobatidza meseji yekubvisa, ruzivo rwunotevera rwunodhinda kunze:

• TI redriver marongero pane ese ari maviri TX uye RX anoverengwa uye anoratidzwa kamwe mushure mechirongwa ELF file.
• Status meseji yeRX EDID kumisikidzwa uye hotplug maitiro
• Resolution ine kana isina FRL rutsigiro ruzivo rwakatorwa kubva kuEDID pane singi yakabatana neTX. Ruzivo urwu runoratidzwa kune yega hotplug yeTX.
• Status meseji yeTX link yekudzidziswa maitiro panguva yeTX link yekudzidziswa.

2.15.2. SCDC Ruzivo kubva kuSink Yakabatanidzwa kuTX
Unogona kushandisa chinhu ichi kuwana SCDC ruzivo.

1. Mhanya iyo Nios II terminal command paNios II Command Shell: nios2-terminal
2. Dzvanya user_pb[2] paIntel Arria 10 FPGA yekuvandudza kit.

Iyo software inoverenga uye inoratidza iyo SCDC ruzivo pane singi yakabatana neTX pane Nios II terminal.
2.15.3. Clock Frequency Measurement
Shandisa chimiro ichi kutarisa frequency yewachi dzakasiyana.

1. Mune hdmi_rx_top uye hdmi_tx_top files, uncomment "//` define DEBUG_EN 1".
2. Wedzera refclock_measure siginecha kubva kune yega yega mr_rate_detect muenzaniso kune Signal Tap Logic Analyzer kuti uwane kuwanda kwewachi yega yega (mune gumi ms nguva).
3. Unganidza dhizaini neSignal Tap Logic Analyzer.
4. Purogiramu yeSOF file uye mhanya iyo Signal Tap Logic Analyzer.

Tafura 27. Mawachi

Module	mr_rate_detect Instance	Wachi ichayerwa
hdmi_rx_top	rx_pll_tmds	RX CDR referensi wachi 0
	rx_clk0_freq	RX transceiver wachi kunze kubva kuchiteshi 0
	rx_vid_clk_freq	RX vhidhiyo wachi
	rx_frl_clk_freq	RX FRL wachi
	rx_hsync_freq	Hsync frequency yeiyo yakagamuchirwa vhidhiyo furemu
hdmi_tx_top	tx_clk0_freq	TX transceiver wachi kunze kubva kuchiteshi 0
	vid_clk_freq	TX vhidhiyo wachi
	frl_clk_freq	TX FRL wachi
	tx_hsync_freq	Hsync frequency yevhidhiyo furemu kuti ifambiswe

2.16. Kuvandudza Dhizaini Yako
Tafura 28. HDMI Dhizaini Example Kuenderana neYapfuura Intel Quartus Prime Pro Edition Software Version

Design Example Variant	Kugona Kukwidziridza kuIntel Quartus Prime Pro Edition 20.3
HDMI 2.1 Dhizaini Example (Kutsigira FRL = 1)	Aihwa

Kune chero isingaenderane dhizaini exampkana, iwe unofanirwa kuita zvinotevera:

1. Gadzira imwe dhizaini example mune yazvino Intel Quartus Prime Pro Edition software vhezheni uchishandisa magadzirirwo akafanana edhizaini yako iripo.
2. Enzanisa yose dhizaini example directory ine dhizaini exampinogadzirwa uchishandisa yakapfuura Intel Quartus Prime Pro Edition software vhezheni. Port pamusoro pekuchinja kwawanikwa.

HDMI 2.0 Dhizaini Example (Kutsigira FRL = 0)

Iyo HDMI Intel FPGA IP dhizaini example inoratidza imwe HDMI muenzaniso yakafanana loopback inosanganisira matatu RX chiteshi uye ina TX chiteshi.
Tafura 29. HDMI Intel FPGA IP Dhizaini Example yeIntel Arria 10 Devices

Design Example	Data Rate	Chiteshi Mamiriro	Loopback Type
Arria 10 HDMI RX-TX Retransmit	<6,000 Mbps	Simplex	Parallel neFIFO buffer

Features

• Iyo dhizaini inosimudzira FIFO buffers kuti iite yakananga HDMI vhidhiyo rukova kupfuura pakati peHDMI singi uye sosi.
  
• Iyo dhizaini inoshandisa LED mamiriro ekutanga debugging stage.
• Iyo dhizaini inouya neRX uye TX chete sarudzo.
• Dhizaini yacho inoratidza kuiswa uye kusefa kweDynamic Range uye Mastering (HDR) InfoFrame muRX-TX link module.
• Iyo dhizaini inoratidza manejimendi eEDID passthrough kubva kune yekunze HDMI kunyura kune yekunze HDMI sosi kana yakonzerwa neTX inopisa-plug chiitiko.
• Dhizaini inobvumira kumhanya-nguva kutonga kuburikidza neDIP switch uye push-bhatani kubata iyo HDMI TX masiginecha epakati:
  - modhi chiratidzo chekusarudza DVI kana HDMI encoded vhidhiyo furemu
  — info_avi[47], info_vsi[61], uye audio_info_ai [48] masiginecha ekusarudza ebetsero packet kutapurirana kuburikidza nemabhandi epadivi kana anobatsira data zviteshi

Iyo RX muenzaniso inogamuchira vhidhiyo sosi kubva kune yekunze vhidhiyo jenareta, uye iyo data yobva yaenda kuburikidza loopback FIFO isati yaendeswa kune iyo TX muenzaniso.
Iwe unofanirwa kubatanidza yekunze vhidhiyo analyzer, yekutarisa, kana terevhizheni ine HDMI yekubatanidza kune iyo TX musimboti kuti uone kushanda.
3.1. HDMI 2.0 RX-TX Retransmit Dhizaini Dhizaini Dhizaini
Iyo HDMI 2.0 RX-TX retransmit dhizaini example inoratidza parallel loopback pane simplex chiteshi modhi yeHDMI Intel FPGA IP.
Mufananidzo 20. HDMI RX-TX Retransmit Block Diagram (Intel Quartus Prime Pro Edition)Mufananidzo 21. HDMI RX-TX Retransmit Block Diagram (Intel Quartus Prime Standard Edition)Related Information
Jitter yePLL Cascading kana Isina-Dedicated Clock Path yeArria 10 PLL Reference Clock Rejera kune iyi mhinduro ye workaround kana madhizaini wachi yako akawana mamwe.
jitter.
3.2. Hardware uye Software Zvinodiwa
Intel inoshandisa iyi inotevera Hardware uye software kuyedza iyo dhizaini example.
Hardware

• Intel Arria 10 GX FPGA Development Kit
• HDMI Source (Graphics Processor Unit (GPU))
• HDMI Sink (Monitor)
• Bitec HDMI FMC 2.0 mwanasikana kadhi (Revision 11)
• HDMI tambo

Cherechedza:
Iwe unogona kusarudza kudzokororwa kweBitec HDMI mwanasikana wako kadhi. Isa iyo parameter yenzvimbo BITEC_DAUGHTER_CARD_REV kusvika 4, 6, kana 11 muchikamu chepamusoro. file (a10_hdmi2_demo.v). Paunochinja gadziriso, dhizaini inogona kuchinjanisa machaneli etransceiver uye nekutenderedza polarity zvinoenderana neBitec HDMI mwanasikana kadhi zvinodiwa. Kana ukaseta BITEC_DAUGHTER_CARD_REV parameter kusvika 0, magadzirirwo acho haaite chero shanduko kumatanho etransceiver uye polarity. YeHDMI 2.1 dhizaini exampzvishoma, pasi peDesign Example tab, isa HDMI Mwanasikana Kadhi Revision kune imwe Revision 9, Revision 4, kana pasina mwanasikana kadhi. Iyo yakasarudzika kukosha ndeye Revision 9.
Software

• Intel Quartus Prime version 18.1 uye gare gare (yekuongorora hardware)
• ModelSim – Intel FPGA Edition, ModelSim – Intel FPGA Starter Edition, , RivieraPRO, VCS (Verilog HDL chete)/VCS MX, kana Xcelium Parallel simulator

3.3. Directory Structure
Madhairekitori ane akagadzirwa files yeHDMI Intel FPGA IP dhizaini example.
Mufananidzo 22. Dhairekitori Mamiriro Ezvakagadzirwa ExampleTafura 30. Yakagadzirwa RTL Files

Folders	Files
gxb	• /gxb_rx.qsys (Intel Quartus Prime Standard Edition) • /gxb_rx.ip (Intel Quartus Prime Pro Edition)
	• /gxb_rx_reset.qsys (Intel Quartus Prime Standard Edition) • /gxb_rx_reset.ip (Intel Quartus Prime Pro Edition)
	• /gxb_tx.qsys (Intel Quartus Prime Standard Edition) • /gxb_tx.ip (Intel Quartus Prime Pro Edition)
	• /gxb_tx_fpll.qsys (Intel Quartus Prime Standard Edition) • /gxb_tx_fpll.ip (Intel Quartus Prime Pro Edition)
	• /gxb_tx_reset.qsys (Intel Quartus Prime Standard Edition) • /gxb_tx_reset.ip (Intel Quartus Prime Pro Edition)
hdmi_rx	•/hdmi_rx.qsys (Intel Quartus Prime Standard Edition) •/hdmi_rx.ip (Intel Quartus Prime Pro Edition)
	/hdmi_rx_top.v
	/mr_clock_sync.v (Intel Quartus Prime Standard Edition)
	/mr_hdmi_rx_core_top.v (Intel Quartus Prime Standard Edition)
	/mr_rx_oversample.v (Intel Quartus Prime Standard Edition)
	/symbol_aligner.v
	Panasonic.hex (Intel Quartus Prime Pro Edition)
hdmi_tx	• /hdmi_tx.qsys (Intel Quartus Prime Standard Edition) •/hdmi_tx.ip (Intel Quartus Prime Pro Edition)

	/hdmi_tx_top.v
	/mr_ce.v (Intel Quartus Prime Standard Edition)
	/mr_hdmi_tx_core_top.v (Intel Quartus Prime Standard Edition)
	/mr_tx_oversample.v (Intel Quartus Prime Standard Edition)
i2c_master (Intel Quartus Prime Standard Edition)	/i2c_master_bit_ctrl.v
	/i2c_master_byte_ctrl.v
	/i2c_master_defines.v
	/i2c_master_top.v
	/oc_i2c_master.v
	/oc_i2c_master_hw.tcl
	/timescale.v
i2c_muranda	/edid_ram.qsys (Intel Quartus Prime Standard Edition)
	/Panasonic.hex (Intel Quartus Prime Standard Edition)
	/i2c_avl_mst_intf_gen.v
	/i2c_clk_cnt.v
	/i2c_condt_det.v
	/i2c_databuffer.v
	/i2c_rxshifter.v
	/i2c_slvfsm.v
	/i2c_spksuppp.v
	/i2c_txout.v
	/i2c_txshifter.v
	/i2cslave_to_avlmm_bridge.v
pll	• /pll_hdmi.qsys (Intel Quartus Prime Standard Edition) • /pll_hdmi.ip (Intel Quartus Prime Pro Edition)
	• /pll_hdmi_reconfig.qsys (Intel Quartus Prime Standard Edition) • /pll_hdmi_reconfig.ip (Intel Quartus Prime Pro Edition)
	quartus.ini
common	• /clock_control.qsys (Intel Quartus Prime Standard Edition) • /clock_control.ip (Intel Quartus Prime Pro Edition)
	• /fifo.qsys (Intel Quartus Prime Standard Edition) • /fifo.ip (Intel Quartus Prime Pro Edition)
	• /output_buf_i2c.qsys (Intel Quartus Prime Standard Edition) •/output_buf_i2c.ip (Intel Quartus Prime Pro Edition)
	/reset_controller.qsys (Intel Quartus Prime Standard Edition)
	/clock_crosser.v

	dcfifo_inst.v
	debouncer.sv (Intel Quartus Prime Pro Edition)
hdr	/altera_hdmi_aux_hdr.v
	/altera_hdmi_aux_snk.v
	/altera_hdmi_aux_src.v
	/altera_hdmi_hdr_infoframe.v
	/avalon_st_mutiplexer.qsys
reconfig_mgmt	/mr_compare_pll.v
	/mr_compare_rx.v
	/mr_rate_detect.v
	/mr_reconfig_master_pll.v
	/mr_reconfig_master_rx.v
	/mr_reconfig_mgmt.v
	/mr_rom_pll_dprioaddr.v
	/mr_rom_pll_valuemask_8bpc.v
	/mr_rom_pll_valuemask_10bpc.v
	/mr_rom_pll_valuemask_12bpc.v
	/mr_rom_pll_valuemask_16bpc.v
	/mr_rom_rx_dprioaddr_bitmask.v
	/mr_rom_rx_valuemask.v
	/mr_state_machine.v
sdc	/a10_hdmi2.sdc
	/mr_reconfig_mgmt.sdc
	/jtag.sdc
	/rxtx_link.sdc
	/mr_clock_sync.sdc (Intel Quartus Prime Standard Edition)

Tafura 31. Yakagadzirwa Simulation Files
Tarisa kuSimulation Testbench chikamu kuti uwane rumwe ruzivo.

Folders	Files
aldec	/aldec.do
	/rivierapro_setup.tcl
cadence	/cds.lib
	/hdl.var
	<cds_libs folda>

mentor	/mentor.do
	/msim_setup.tcl
synopsys	/vcs/filelist.f
	/vcs/vcs_setup.sh
	/vcs/vcs_sim.sh
	/vcsmx/vcsmx_setup.sh
	/vcsmx/vcsmx_sim.sh
	/vcsmx/synopsys_sim_setup
xcelium (Intel Quartus Prime Pro Edition)	/cds.lib
	/hdl.var
	/xcelium_setup.sh
	/xcelium_sim.sh
common (Intel Quartus Prime Pro Edition)	/modelsim_files.tcl
	/riviera_files.tcl
	/vcs_files.tcl
	/vcsmx_files.tcl
	/xcelium_files.tcl
hdmi_rx	• /hdmi_rx.qsys (Intel Quartus Prime Standard Edition) • /hdmi_rx.ip (Intel Quartus Prime Pro Edition)
	/hdmi_rx.sopcinfo (Intel Quartus Prime Standard Edition)
	/Panasonic.hex (Intel Quartus Prime Pro Edition)
	/symbol_aligner.v (Intel Quartus Prime Pro Edition)
hdmi_tx	• /hdmi_tx.qsys (Intel Quartus Prime Standard Edition) • /hdmi_tx.ip (Intel Quartus Prime Pro Edition)
	/hdmi_tx.sopcinfo (Intel Quartus Prime Standard Edition)

Tafura 32.Generated Software Files

Folders	Files
tx_control_src Cherechedza: Iyo tx_control folda zvakare ine zvakapetwa zveizvi files.	/intel_fpga_i2c.c (Intel Quartus Prime Pro Edition)
	/intel_fpga_i2c.h (Intel Quartus Prime Pro Edition)
	/i2c.c (Intel Quartus Prime Standard Edition)
	/i2c.h (Intel Quartus Prime Standard Edition)
	/main.c
	/xcvr_gpll_rcfg.c /xcvr_gpll_rcfg.h /ti_i2c.c (Intel Quartus Prime Standard Edition) /ti_i2c.h (Intel Quartus Prime Standard Edition)

3.4. Dhizaini Zvikamu
Iyo HDMI Intel FPGA IP dhizaini example inoda zvikamu izvi.
Tafura 33. HDMI RX Pamusoro Zvikamu

Module	Tsanangudzo
HDMI RX Core	Iyo IP inogamuchira serial data kubva kuTransceiver Native PHY uye inoita data align, chiteshi deskew, TMDS decoding, yekubatsira data decoding, vhidhiyo decoding, odhiyo data decoding, uye kudhiza.
I2	I2C ndiyo interface inoshandiswa Sink Display Data Channel (DDC) uye Status uye Data Channel (SCDC). Iyo HDMI sosi inoshandisa iyo DDC kuona kugona uye hunhu hwesingi nekuverenga Iyo Yakawedzeredzwa Yakawedzera Display Identification Data (E-EDID) data chimiro. • Kero dzevaranda dze8-bit I2C dzeE-EDID dzinoti 0xA0 uye 0xA1. Iyo LSB inoratidza mhando yekuwana: 1 yekuverenga uye 0 yekunyora. Kana chiitiko cheHPD chikaitika, muranda weI2C anopindura E-EDID data nekuverenga kubva pa-chip RAM. • I2C muranda-chete controller inotsigirawo SCDC yeHDMI 2.0 mashandiro. Iyo 8-bit I2C kero yemuranda yeSCDC ndeye 0xA8 uye 0xA9. Kana chiitiko cheHPD chikaitika, muranda weI2C anoita kunyora kana kuverenga kutengeserana kuenda kana kubva kuSCDC interface yeHDMI RX musimboti. Cherechedza: Iyi I2C muranda-chete controller yeSCDC haidiwe kana HDMI 2.0b isina kurongerwa. Kana ukabatidza Kusanganisira I2C parameter, iyi block ichaverengerwa mukati mepakati uye haizoonekwe padanho iri.
EDID RAM	Dhizaini inochengeta iyo EDID ruzivo uchishandisa iyo RAM 1-chiteshi IP musimboti. Yakajairika-waya mbiri (wachi uye data) serial bhazi protocol (I2C muranda-chete controller) inotamisa iyo CEA-861-D Inopindirana E-EDID data chimiro. Iyi EDID RAM inochengeta iyo E-EDID ruzivo. Cherechedza: Kana ukabatidza Sanganisira EDID RAM parameter, iyi block ichaverengerwa mukati mepakati uye haizoonekwe padanho iri.
IOPLL	Iyo IOPLL inogadzira iyo RX CDR referensi wachi, chinongedzo wachi, uye vhidhiyo wachi yeinouya TMDS wachi. • wachi inobuda 0 (CDR referensi wachi) • Wachi inoburitsa 1 (Link kasidhi wachi) • Wachi inoburitsa 2 (Vhidhiyo wachi) Cherechedza: Iyo yakasarudzika IOPLL kumisikidzwa haina basa kune chero HDMI resolution. Iyo IOPLL inogadziridzwa kune akakodzera marongero pamagetsi kumusoro.
Transceiver PHY Reset Controller	Iyo Transceiver PHY reset controller inovimbisa yakavimbika kutanga kweiyo RX transceivers. Kuiswa patsva kwemutongi uyu kunokonzereswa neRX reconfiguration, uye inogadzira inoenderana analog uye digital reset siginecha kuTransceiver Native PHY block zvinoenderana nekuteedzeranazve mukati me block.
RX Native PHY	Yakaoma transceiver block iyo inogamuchira iyo serial data kubva kune yekunze vhidhiyo sosi. Iyo inobvisa iyo serial data kuti ienderane data isati yapfuudza iyo data kuHDMI RX musimboti.
RX Reconfiguration Management	RX reconfiguration manejimendi iyo inoshandisa chiyero chekuona dunhu neHDMI PLL kutyaira iyo RX transceiver kuti ishande chero ipi zvayo yekubatanidza mareti kubva pa250 Mbps kusvika 6,000 Mbps. Tarisa mufananidzo 23 papeji 63 pazasi.

IOPLL Reconfiguration

IOPLL reconfiguration block inofambisa inoshanduka-chaiyo-nguva kugadziridzwa kwePLLs muIntel FPGAs. Ichi chivharo chinogadziridza inobuda wachi frequency uye PLL bandwidth munguva chaiyo, pasina kugadzirisa iyo yese FPGA. Iyi block inomhanya pa100 MHz muIntel Arria 10 zvishandiso. Nekuda kweIOPLL reconfiguration kudzikiswa, shandisa iyo Quartus INI permit_nf_pll_reconfig_out_of_lock=on panguva yeIOPLL yekugadziridzazve IP chizvarwa. Kuisa iyo Quartus INI, sanganisira "permit_nf_pll_reconfig_out_of_lock=on" mu quartus.ini file uye nzvimbo mu file iyo Intel Quartus Prime chirongwa dhairekitori. Iwe unofanirwa kuona meseji yambiro paunogadzirisa IOPLL reconfiguration block (pll_hdmi_reconfig) muQuartus Prime software ine INI. Cherechedza: Pasina iyi Quartus INI, IOPLL reconfiguration haigone kupedzwa kana IOPLL ikarasikirwa nekiyi panguva yekugadziriswazve.

PIO

Iyo parallel yekupinda / kubuda (PIO) block inoshanda sekutonga, chimiro uye reset interfaces kuenda kana kubva kuCPU sub-system.

Mufananidzo 23. Multi-Rate Reconfiguration Sequence Flow
Iyo nhamba inotaridza iyo yakawanda-yeti reconfiguration sequence kuyerera kwemutongi kana agamuchira yekupinda data rwizi uye referensi wachi frequency, kana kana transceiver yavhurwa.Tafura 34. HDMI TX Pamusoro Zvikamu

Module	Tsanangudzo
HDMI TX Core	Iyo IP musimboti inogamuchira vhidhiyo data kubva padanho repamusoro uye inoita TMDS encoding, yebetsero data encoding, odhiyo data encoding, vhidhiyo data encoding, uye kupuruzira.
I2C Master	I2C ndiyo interface inoshandiswa Sink Display Data Channel (DDC) uye Status uye Data Channel (SCDC). Iyo HDMI sosi inoshandisa iyo DDC kuona kugona uye hunhu hwesingi nekuverenga Iyo Yakawedzeredzwa Yakawedzera Display Identification Data (E-EDID) data chimiro. • SeDDC, I2C Master inoverenga EDID kubva kune sink yekunze kuti igadzirise ruzivo rweEDID EDID RAM muHDMI RX Pamusoro kana kuti mavhidhiyo ekugadzirisa. • SeSCDC, I2C tenzi inotamisa iyo SCDC data chimiro kubva kuFPGA sosi kuenda kune sink yekunze yeHDMI 2.0b kushanda. For exampLe, kana iyo inobuda data rwizi iri pamusoro pe3,400 Mbps, iyo Nios II processor inoraira I2C tenzi kuti agadzirise TMDS_BIT_CLOCK_RATIO uye SCRAMBLER_ENABLE bits ye sink SCDC yekumisikidza rejista kusvika 1.
IOPLL	Iyo IOPLL inopa chinongedzo chekumhanyisa wachi uye vhidhiyo wachi kubva kune iri kuuya TMDS wachi. • Wachi inoburitsa 1 (Link kasidhi wachi) • Wachi inoburitsa 2 (Vhidhiyo wachi) Cherechedza: Iyo yakasarudzika IOPLL kumisikidzwa haina basa kune chero HDMI resolution. Iyo IOPLL inogadziridzwa kune akakodzera marongero pamagetsi kumusoro.
Transceiver PHY Reset Controller	Iyo Transceiver PHY reset controller inovimbisa yakavimbika kutanga kweTX transceivers. Kuiswa patsva kwemutongi uyu kunokonzereswa kubva padanho repamusoro, uye inogadzira inoenderana analog uye digital reset siginecha kuTransceiver Native PHY block zvinoenderana nekutevedzana kwekugadzirisa mukati me block. Iyo tx_ready inobuda siginecha kubva mubhuroka ino inoshandawo sechiratidzo chekugadzirisazve kuHDMI Intel FPGA IP kuratidza kuti transceiver yasimuka uye inoshanda, uye yakagadzirira kugamuchira data kubva pakati.
Transceiver Native PHY	Yakaoma transceiver block inogamuchira iyo yakafanana data kubva kuHDMI TX musimboti uye inoteedzera iyo data kubva mukuifambisa. Reconfiguration interface inogoneswa muTX Native PHY block kuratidza kubatana pakati peTX Native PHY uye transceiver arbiter. Hapana kugadzirisa zvakare kunoitwa TX Native PHY. Cherechedza: Kuti usangane neHDMI TX inter-channel skew chinodiwa, isa iyo TX chiteshi bonding modhi sarudzo muIntel Arria 10 Transceiver Native PHY parameter mupepeti kuti. PMA uye PCS kubatana. Iwe zvakare unofanirwa kuwedzera iyo yakanyanya skew (set_max_skew) inomanikidza inodiwa kune dijitari reset chiratidzo kubva kune transceiver reset controller (tx_digitalreset) sezvakakurudzirwa mune Intel Arria 10 Transceiver PHY User Guide.
TX PLL	Iyo transmitter PLL block inopa serial inokurumidza wachi kune Transceiver Native PHY block. Kune iyi HDMI Intel FPGA IP dhizaini example, fPLL inoshandiswa seTX PLL.
IOPLL Reconfiguration	IOPLL reconfiguration block inofambisa inoshanduka-chaiyo-nguva kugadziridzwa kwePLLs muIntel FPGAs. Ichi chivharo chinogadziridza inobuda wachi frequency uye PLL bandwidth munguva chaiyo, pasina kugadzirisa iyo yese FPGA. Iyi block inomhanya pa100 MHz muIntel Arria 10 zvishandiso. Nekuda kweIOPLL reconfiguration kudzikiswa, shandisa iyo Quartus INI permit_nf_pll_reconfig_out_of_lock=on panguva yeIOPLL yekugadziridzazve IP chizvarwa. Kuisa iyo Quartus INI, sanganisira "permit_nf_pll_reconfig_out_of_lock=on" mu quartus.ini file uye nzvimbo mu file iyo Intel Quartus Prime chirongwa dhairekitori. Iwe unofanirwa kuona meseji yambiro paunogadzirisa IOPLL reconfiguration block (pll_hdmi_reconfig) muIntel Quartus Prime software ine INI. Cherechedza: Pasina iyi Quartus INI, IOPLL reconfiguration haigone kupedzwa kana IOPLL ikarasikirwa nekiyi panguva yekugadziriswazve.
PIO	Iyo parallel yekupinda / kubuda (PIO) block inoshanda sekutonga, chimiro uye reset interfaces kuenda kana kubva kuCPU sub-system.

Tafura 35. Transceiver Data Rate uye Oversampling Factor kune Imwe neimwe TMDS Clock Frequency Range

TMDS Clock Frequency (MHz)	TMDS Bit wachi Chiyero	Oversampling Factor	Transceiver Data Rate (Mbps)
85–150	1	Hazvigoneke	3400–6000
100–340	0	Hazvigoneke	1000–3400
50–100	0	5	2500–5000
35–50	0	3	1050–1500
30–35	0	4	1200–1400
25–30	0	5	1250–1500

Tafura 36. Top-Level Common Blocks

Module

Tsanangudzo

Transceiver Arbiter

Iyi generic inoshanda block inodzivirira transceivers kubva pakudzokorora panguva imwe chete kana RX kana TX transceivers mukati meiyo imwechete yemuviri chiteshi inoda kugadziridzwa. Kudzokorodza panguva imwe chete kunokanganisa maapplication uko RX neTX transceivers mukati meiyo chiteshi inopihwa kune yakazvimirira IP kuita. Iyi transceiver arbiter ndeyewedzero kune chigadziro chakakurudzirwa kubatanidza simplex TX uye simplex RX mune imwecheteyo yemuviri chiteshi. Iyi transceiver arbiter inobatsirawo mukubatanidza nekugadzirisa zvikumbiro zveAvalon-MM RX uye TX reconfiguration yakanangana ne simplex RX uye TX transceivers mukati mechiteshi sezvo reconfiguration interface chiteshi cheva transceivers inogona kuwanikwa chete sequentially. Iyo interface yekubatanidza pakati peiyo transceiver arbiter uye TX/RX Native PHY/PHY Reset Controller inovharira mune ino dhizaini ex.ample inoratidza generic modhi inoshanda kune chero IP musanganiswa uchishandisa iyo transceiver arbiter. Transceiver arbiter haidiwe kana chete RX kana TX transceiver ichishandiswa muchiteshi. Iyo transceiver arbiter inotaridza mukumbi wekugadzirisa zvakare kuburikidza neAvalon-MM reconfiguration interfaces uye inova nechokwadi chekuti inoenderana tx_reconfig_cal_busy kana rx_reconfig_cal_busy inogezwa saizvozvo. YeHDMI application, chete RX inotanga kugadzirisa zvakare. Nekuisa chikumbiro cheAvalon-MM reconfiguration kuburikidza nearbiter, arbiter anoratidza kuti chikumbiro chekugadzirisazve chinobva kuRX, iyo inobva yavhara tx_reconfig_cal_busy kubva pakusimbisa uye inobvumira rx_reconfig_cal_busy kutaura. Iyo gedhi inodzivirira iyo TX transceiver kubva kuendeswa kune calibration mode usingazivi.

	Cherechedza: Nekuti HDMI inongoda RX kugadziridzwa, iyo tx_reconfig_mgmt_* masaini akasungwa. Zvakare, iyo Avalon-MM interface haidiwe pakati peiyo arbiter neTX Native PHY block. Iwo mabhuroki anopihwa kune iyo interface mudhizaini example kuratidza generic transceiver arbiter yekubatanidza kuTX/RX Native PHY/PHY Reset Controller.
RX-TX Link	• Vhidhiyo data inobuda uye masiginecha ekubatanidza kubva kuHDMI RX core loop kuburikidza neDCFIFO mhiri kweRX neTX vhidhiyo wachi madhomeini. • The General Control Packet (GCP), InfoFrames (AVI, VSI neAI), data rebetsero, uye audio data loop kuburikidza neDCFIFOs mhiri kweRX neTX link speed clock domains. • Iyo yebetsero data port yeHDMI TX core inodzora data yebetsero inoyerera kuburikidza neDCFIFO kuburikidza nebackpressure. Iyo backpressure inovimbisa kuti hapana isina kukwana yekubatsira pakiti pane yekubatsira data port. • Chibhuroko ichi chinoita zvakare kusefa kwekunze: -Inosefa data redhiyo uye odhiyo wachi yekuvandudza pakiti kubva kune yekubatsira data rwizi isati yaendesa kuHDMI TX yakakosha data port. Cherechedza: Kudzima kusefa uku, dzvanya user_pb[2]. Ita kuti kusefa uku kuve nechokwadi kuti hapana kudzokororwa kwedhata reodhiyo uye redhiyo wachi yekuvandudza packet mune yakatumirwazve yebetsero data stream. -Inosefa Iyo Yakakwira Dynamic Range (HDR) InfoFrame kubva kuHDMI RX yekubatsira data uye inoisa ex.ample HDR InfoFrame kune iyo yekubatsira data yeHDMI TX kuburikidza neAvalon ST multiplexer.
CPU Sub-System	Iyo CPU sub-system inoshanda seSCDC uye DDC controller, uye sosi reconfiguration controller. • Nzvimbo yeSCDC controller ine I2C master controller. Iyo I2C tenzi controller inotamisa iyo SCDC data chimiro kubva kuFPGA sosi kuenda kune yekunze singi yeHDMI 2.0b mashandiro. For exampLe, kana iyo data inobuda iri 6,000 Mbps, iyo Nios II processor inoraira I2C master controller kuti ivandudze TMDS_BIT_CLOCK_RATIO uye SCRAMBLER_ENABLE bits ye sink TMDS gadziriso regisheni kusvika 1. • Iyo imwechete I2C tenzi inotamisawo iyo DDC data chimiro (E-EDID) pakati peHDMI sosi uye kunze sink. • Iyo Nios II CPU inoshanda semugadziri wekugadzirisa zvakare weiyo HDMI sosi. Iyo CPU inovimba neiyo periodic rate yekuona kubva kuRX Reconfiguration Management module kuona kana iyo TX inoda kugadziridzwazve. Iyo Avalon-MM muturikiri wenhapwa inopa iyo interface pakati peNios II processor Avalon-MM master interface uye iyo Avalon-MM muranda inotarisana neyekunze yakamisikidzwa HDMI sosi yeIOPLL uye TX Native PHY. • Kugadziriswa kwekugadzirisa kutenderera kweTX kwakafanana neRX, kunze kwekuti PLL uye transceiver reconfiguration uye reset sequence inoitwa sequentially. Ona Mufananidzo 24 papeji 67.

Mufananidzo 24. Reconfiguration Sequence Flow
Iyo nhamba inoratidza iyo Nios II software inoyerera inosanganisira zvinodzora zveI2C tenzi uye HDMI sosi.3.5. Dynamic Range uye Mastering (HDR) InfoFrame Insertion uye Kusefa
Iyo HDMI Intel FPGA IP dhizaini example inosanganisira kuratidzwa kwekuiswa kweHDR InfoFrame muRX-TX loopback system.
HDMI Tsanangudzo vhezheni 2.0b inobvumira Dynamic Range uye Mastering InfoFrame kuti ifambiswe kuburikidza neHDMI yekubatsira rwizi. Mukuratidzira, iyo Auxiliary Data Insertion block inotsigira iyo HDR kuiswa. Iwe unongoda kufometa iyo yakanangwa HDR InfoFrame packet sekutsanangurwa kweiyo module yechiratidzo tafura tafura uye shandisa yakapihwa AUX Insertion Control module kuronga kuiswa kweHDR InfoFrame kamwe chete vhidhiyo furemu.
Mune example gadziriso, muzviitiko apo iyo inouya yekubatsira rwizi inotosanganisira HDR InfoFrame, iyo yakafambiswa HDR yemukati inosefa. Iko kusefa kunodzivirira kupokana HDR InfoFrames kuti ifambiswe uye inova nechokwadi chekuti chete hunhu hunotsanangurwa muHDR S.ample Data module inoshandiswa.
Mufananidzo 25. RX-TX Batanidza neDynamic Range uye Mastering InfoFrame Insertion
Nhamba yacho inoratidza dhizaini yeRX-TX link inosanganisira Dynamic Range uye Mastering InfoFrame kuisirwa muHDMI TX musimboti wekubatsira rukova.
Tafura 37. Mubatsiri Data Insertion Block (altera_hdmi_aux_hdr) Zviratidzo

Signal	Direction	Upamhi	Tsanangudzo
Clock uye Reset
clk	Input	1	Kuisa wachi. Wachi iyi inofanirwa kubatana kune chinongedzo chekumhanyisa wachi.
reset	Input	1	Reset input.

Inobatsira Packet Generator uye Multiplexer Signals
multiplexer_out_data	Output	72	Avalon yekushambadzira inobuda kubva kune multiplexer.
multiplexer_out_valid	Output	1
multiplexer_out_ready	Output	1
multiplexer_out_startofpacket	Output	1
multiplexer_out_endofpacket	Output	1
multiplexer_out_channel	Output	11
multiplexer_in_data	Input	72	Avalon yekufambisa yekupinda kuIn1 chiteshi chemultiplexer. HDMI TX Vhidhiyo Vsync. Ichi chiratidzo chinofanirwa kuwiriraniswa kune chinongedzo chekumhanyisa wachi domain. Iyo musimboti inoisa iyo HDR InfoFrame kune yekubatsira rwizi kumucheto kunokwira kwechiratidzo ichi.
multiplexer_in_valid	Input	1
multiplexer_in_ready	Input	1
multiplexer_in_startofpacket	Input	1
multiplexer_in_endofpacket hdmi_tx_vsync	Input Input	1 1

Tafura 38. HDR Data Module (altera_hdmi_hdr_infoframe) Zviratidzo

Signal	Direction	Upamhi	Tsanangudzo
hb0	Output	8	Header byte 0 yeDynamic Range uye Mastering InfoFrame: InfoFrame mhando kodhi.
hb1	Output	8	Header byte 1 yeDynamic Range uye Mastering InfoFrame: InfoFrame vhezheni nhamba.
hb2	Output	8	Header byte 2 yeDynamic Range uye Mastering InfoFrame: Kureba kweInfoFrame.
pb	Input	224	Data byte yeDynamic Range uye Mastering InfoFrame.

Tafura 39. Dynamic Range uye Mastering InfoFrame Data Byte Bundle Bit-Fields

Bit-Field	Tsanangudzo	Static Metadata Type 1
7:0	Data Byte 1: {5'h0, EOTF[2:0]}
15:8	Data Byte 2: {5'h0, Static_Metadata_Descriptor_ID[2:0]}
23:16	Data Byte 3: Static_Metadata_Descriptor	display_primaries_x[0], LSB
31:24	Data Byte 4: Static_Metadata_Descriptor	display_primaries_x[0], MSB
39:32	Data Byte 5: Static_Metadata_Descriptor	display_primaries_y[0], LSB
47:40	Data Byte 6: Static_Metadata_Descriptor	display_primaries_y[0], MSB
55:48	Data Byte 7: Static_Metadata_Descriptor	display_primaries_x[1], LSB
63:56	Data Byte 8: Static_Metadata_Descriptor	display_primaries_x[1], MSB
71:64	Data Byte 9: Static_Metadata_Descriptor	display_primaries_y[1], LSB
79:72	Data Byte 10: Static_Metadata_Descriptor	display_primaries_y[1], MSB
87:80	Data Byte 11: Static_Metadata_Descriptor	display_primaries_x[2], LSB
95:88	Data Byte 12: Static_Metadata_Descriptor	display_primaries_x[2], MSB
103:96	Data Byte 13: Static_Metadata_Descriptor	display_primaries_y[2], LSB
111:104	Data Byte 14: Static_Metadata_Descriptor	display_primaries_y[2], MSB
119:112	Data Byte 15: Static_Metadata_Descriptor	white_point_x, LSB
127:120	Data Byte 16: Static_Metadata_Descriptor	white_point_x, MSB
135:128	Data Byte 17: Static_Metadata_Descriptor	white_point_y, LSB

143:136	Data Byte 18: Static_Metadata_Descriptor	white_point_y, MSB
151:144	Data Byte 19: Static_Metadata_Descriptor	max_display_mastering_luminance, LSB
159:152	Data Byte 20: Static_Metadata_Descriptor	max_display_mastering_luminance, MSB
167:160	Data Byte 21: Static_Metadata_Descriptor	min_display_mastering_luminance, LSB
175:168	Data Byte 22: Static_Metadata_Descriptor	min_display_mastering_luminance, MSB
183:176	Data Byte 23: Static_Metadata_Descriptor	Maximum Content Light Level, LSB
191:184	Data Byte 24: Static_Metadata_Descriptor	Maximum Content Light Level, MSB
199:192	Data Byte 25: Static_Metadata_Descriptor	Maximum Frame-average Light Level, LSB
207:200	Data Byte 26: Static_Metadata_Descriptor	Maximum Frame-average Light Level, MSB
215:208	Reserved
223:216	Reserved

Kudzima HDR Kupinza uye kusefa
Kudzima kuisirwa HDR uye sefa kunoita kuti iwe ugone kuona kudzoreredzwa kweHDR zvirimo zvatovepo murukova rwekubatsira pasina kana shanduko muRX-TX Retransmit dhizaini ex.ample.
Kudzima kuisa HDR InfoFrame uye kusefa:

1. Isa block_ext_hdr_infoframe kuita 1'b0 mu rxtx_link.v file kudzivirira kusefa kweHDR InfoFrame kubva parukova rweKubatsira.
2. Seta multiplexer_in0_valid yeiyo avalon_st_multiplexer muenzaniso mu altera_hdmi_aux_hdr.v file kusvika ku1'b0 kudzivirira iyo Auxiliary Packet Jenareta kubva pakugadzira uye kuisa imwe HDR InfoFrame muTX Auxiliary stream.
   

3.6. Clock Scheme
Chirongwa chewachi chinoratidza madomasi ewachi muHDMI Intel FPGA IP dhizaini example.
Mufananidzo 26. HDMI Intel FPGA IP Dhizaini Example Clock Scheme (Intel Quartus Prime Pro Edition)Mufananidzo 27. HDMI Intel FPGA IP Dhizaini Example Clock Scheme (Intel Quartus Prime Standard Edition)Tafura 40. Kuvhara Scheme Zviratidzo

Clock	Zita rechiratidzo muKugadzira	Tsanangudzo
TX IOPLL/TX PLL Reference Clock 1	hdmi_clk_in	Reference wachi kuTX IOPLL uye TX PLL. Iyo wachi frequency yakafanana neinotarisirwa TMDS wachi frequency kubva kuHDMI TX TMDS wachi chiteshi. Kune iyi HDMI Intel FPGA IP dhizaini example, wachi iyi yakabatana neRX TMDS wachi yekuratidzira chinangwa. Mukushandisa kwako, unofanirwa kupa wachi yakatsaurirwa ine TMDS wachi frequency kubva kune programmable oscillator kuti uite zvirinani jitter. Cherechedza: Usashandise transceiver RX pini seTX PLL referensi wachi. Dhizaini yako inotadza kukwana kana ukaisa iyo HDMI TX refclk paRX pini.
TX Transceiver Clock Out	tx_clk	Wachi yekubuda yakadzoserwa kubva kune transceiver, uye frequency inosiyana zvichienderana nehuwandu hwe data uye zviratidzo pawachi. TX transceiver wachi kunze frequency = Transceiver data rate/ (Chiratidzo pawachi*10)
TX PLL Serial Clock	tx_bonding_clocks	Seri inokurumidza wachi inogadzirwa neTX PLL. Nguva yewachi inotarwa zvichienderana nehuwandu hwe data.
TX/RX Link Speed ​​​​Clock	ls_clk	Link speed wachi. Iyo yekubatanidza yekumhanyisa wachi frequency inotsamira pane inotarisirwa TMDS wachi frequency, oversampling factor, zviratidzo pawachi, uye TMDS bit clock ratio.

		TMDS Bit Clock Ratio	Batanidza Speed ​​​​Clock Frequency
		0	TMDS wachi frequency/ Chiratidzo pawachi
		1	TMDS wachi frequency * 4 / Symbol pawachi
TX/RX Vhidhiyo Clock	vid_clk	Vhidhiyo data wachi. Vhidhiyo data wachi frequency inotorwa kubva kuTX link yekumhanyisa wachi zvichienderana nekudzika kweruvara.
		TMDS Bit Clock Ratio	Vhidhiyo Data Clock Frequency
		0	TMDS wachi/ Chiratidzo pawachi/ Rudzi rwakadzika chinhu
		1	TMDS wachi * 4 / Chiratidzo pawachi / Rudzi rwakadzika chinhu
		Bits per Color	Rudzi Rwakadzika Factor
		8	1
		10	1.25
		12	1.5
		16	2.0
RX TMDS Clock	tmds_clk_in	TMDS wachi chiteshi kubva kuHDMI RX uye inobatanidza nereferensi wachi kuIOPLL.
RX CDR Reference Clock 0 /TX PLL Reference Clock 0	fr_clk	Yemahara inomhanya yekunongedzera wachi kuRX CDR uye TX PLL. Wachi iyi inodiwa pakugadzirisa simba-up.
RX CDR Reference Clock 1	iopll_outclk0	Reference wachi kuRX CDR yeRX transceiver.
		Data Rate	RX Reference Clock Frequency
		Nhamba yedata <1 Gbps	5 × TMDS wachi frequency
		1 Gbps< Data rate <3.4 Gbps	TMDS wachi frequency
		Nhamba yedata> 3.4 Gbps	4 × TMDS wachi frequency
		• Data Rate <1 Gbps: For oversampling kuti isangane netransceiver shoma data rate inodiwa. • Data Rate > 3.4 Gbps: Kubhadhara TMDS bit rate kusvika ku clock ratio ye 1/40 kuchengetedza transceiver data rate kusvika ku clock ratio pa 1/10. Cherechedza: Usashandise transceiver RX pin seCDR referensi wachi. Dhizaini yako inotadza kukwana kana ukaisa iyo HDMI RX refclk paRX pini.
RX Transceiver Clock Out	rx_clk	Wachi yekubuda yakadzoserwa kubva kune transceiver, uye frequency inosiyana zvichienderana nehuwandu hwe data uye zviratidzo pawachi. RX transceiver wachi kunze frequency = Transceiver data rate/ (Chiratidzo pawachi*10)
Management Clock	mgmt_clk	Yemahara inomhanya 100 MHz wachi yezvikamu izvi:

		• Avalon-MM interfaces yekugadzirisa zvakare - Iyo frequency renji inodiwa iri pakati pe100-125 MHz. •, PHY reset controller ye transceiver reset sequence - Iyo frequency renji inodiwa iri pakati pe1-500 MHz. • IOPLL Reconfiguration - Iyo yakanyanya wachi frequency ndeye 100 MHz. • RX Reconfiguration yehutungamiri • CPU • I2C Master
I2C Clock	i2c_clk	A 100 MHz wachi yekuisa iyo inovhara I2C muranda, SCDC inonyoresa muHDMI RX musimboti, uye EDID RAM.

Related Information

• Kushandisa Transceiver RX Pin seCDR Reference Clock
• Kushandisa Transceiver RX Pin seTX PLL Reference Clock

3.7. Interface Signals
Matafura anonyora zvikwangwani zveHDMI Intel FPGA IP dhizaini example.
Tafura 41. Pamusoro-Chiratidzo chepamusoro

Signal	Direction	Upamhi	Tsanangudzo
Pa-bhodhi Oscillator Chiratidzo
clk_fpga_b3_p	Input	1	100 MHz yemahara inomhanya wachi yepakati referensi wachi
REFCLK_FMCB_P (Intel Quartus Prime Pro Edition)	Input	1	625 MHz yemahara inomhanya wachi ye transceiver referensi wachi; wachi iyi inogona kuva chero frequency

Mushandisi Push Mabhatani uye LEDs
mushandisi_pb	Input	1	Batanidza bhatani kudzora iyo HDMI Intel FPGA IP dhizaini mashandiro
cpu_resetn	Input	1	Global reset
user_led_g	Output	4	Green LED kuratidza Tarisa kune Hardware Setup iri papeji 89 kuti uwane rumwe ruzivo nezve ma LED mabasa.
user_led_r	Output	4	Red LED kuratidza Tarisa kune Hardware Setup iri papeji 89 kuti uwane rumwe ruzivo nezve ma LED mabasa.

HDMI FMC Mwanasikana Kadhi Pini paFMC Port B
fmcb_gbtclk_m2c_p_0	Input	1	HDMI RX TMDS wachi
fmcb_dp_m2c_p	Input	3	HDMI RX tsvuku, girini, uye bhuruu data chiteshi • Bitec mwanasikana kudzokorora kadhi 11 — [0]: RX TMDS Channel 1 (Green) — [1]: RX TMDS Chiteshi chechipiri (Tsvuku) — [2]: RX TMDS Channel 0 (Blue) • Bitec mwanasikana kadhi revision 4 kana 6 — [0]: RX TMDS Chiteshi 1 (Green)— polarity inverted — [1]: RX TMDS Channel 0 (Blue)— polarity inverted — [2]: RX TMDS Channel 2 (Tsvuku)— polarity inverted
fmcb_dp_c2m_p	Output	4	HDMI TX wachi, tsvuku, girini, uye bhuruu data chiteshi • Bitec mwanasikana kudzokorora kadhi 11 — [0]: TX TMDS Channel 2 (Tsvuku) — [1]: TX TMDS Channel 1 (Green) — [2]: TX TMDS Channel 0 (Blue) — [3]: TX TMDS Clock Channel • Bitec mwanasikana kadhi revision 4 kana 6 — [0]: TX TMDS Clock Channel — [1]: TX TMDS Channel 0 (Blue) — [2]: TX TMDS Channel 1 (Green) — [3]: TX TMDS Channel 2 (Tsvuku)
fmcb_la_rx_p_9	Input	1	HDMI RX +5V simba rekuona
fmcb_la_rx_p_8	Inout	1	HDMI RX inopisa plug inoona
fmcb_la_rx_n_8	Inout	1	HDMI RX I2C SDA yeDDC uye SCDC
fmcb_la_tx_p_10	Input	1	HDMI RX I2C SCL yeDDC uye SCDC
fmcb_la_tx_p_12	Input	1	HDMI TX inopisa plug inoona
fmcb_la_tx_n_12	Inout	1	HDMI I2C SDA yeDDC uye SCDC
fmcb_la_rx_p_10	Inout	1	HDMI I2C SCL yeDDC uye SCDC
fmcb_la_tx_p_11	Inout	1	HDMI I2C SDA yekudzora dhiraivha
fmcb_la_rx_n_9	Inout	1	HDMI I2C SCL yekudzora dhiraivha

Tafura 42. HDMI RX Top-Level Zviratidzo

Signal	Direction	Upamhi	Tsanangudzo
Clock uye Reset Signals
mgmt_clk	Input	1	Sisitimu wachi yekupinda (100 MHz)
fr_clk (Intel Quartus Prime Pro Edition)	Input	1	Wachi yemahara inomhanya (625 MHz) yekutanga transceiver referensi wachi. Iyi wachi inodiwa kuti transceiver calibration panguva yekusimba-up state. wachi iyi inogona kuva chero frequency.
reset	Input	1	Kuisazve sisitimu

Signal	Direction	Upamhi	Tsanangudzo
Clock uye Reset Signals
reset_xcvr_powerup (Intel Quartus Prime Pro Edition)	Input	1	Transceiver reset input. Ichi chiratidzo chinotemerwa panguva yereferensi wachi yekuchinjisa wachi (kubva mahara ichimhanya wachi kuenda kuTMDS wachi) mune simba-kumusoro mamiriro.
tmds_clk_in	Input	1	HDMI RX TMDS wachi
i2c_clk	Input	1	Kuisa wachi yeDDC uye SCDC interface
vid_clk_out	Output	1	Vhidhiyo wachi inobuda
ls_clk_out	Output	1	Link yekumhanyisa wachi kubuda
sys_init	Output	1	Sisitimu yekutanga kugadzirisa zvakare sisitimu pane simba-kumusoro

RX Transceiver uye IOPLL Zviratidzo
rx_serial_data	Input	3	HDMI serial data kune iyo RX Native PHY
gxb_rx_ready	Output	1	Inoratidza RX Native PHY yakagadzirira
gxb_rx_cal_busy_out	Output	3	RX Native PHY calibration yakabatikana kune transceiver arbiter
gxb_rx_cal_busy_in	Input	3	Calibration yakabatikana chiratidzo kubva kune transceiver arbiter kuenda kuRX Native PHY
iopll_locked	Output	1	Ratidza IOPLL yakakiiwa
gxb_reconfig_write	Input	3	Transceiver reconfiguration Avalon-MM interface kubva kuRX Native PHY kuenda kune transceiver arbiter.
gxb_reconfig_read	Input	3
gxb_reconfig_address	Input	30
gxb_reconfig_writedata	Input	96
gxb_reconfig_readdata	Output	96
gxb_reconfig_waitrequest	Output	3

RX Reconfiguration Management
rx_reconfig_en	Output	1	RX Reconfiguration inogonesa chiratidzo
chiyero	Output	24	HDMI RX TMDS wachi frequency kuyerwa (mu 10 ms)
measure_valid	Output	1	Inoratidza chiratidzo chechiyero chiri kushanda
os	Output	1	Oversampling factor: • 0: Hapana oversampling • 1: 5× pamusoroampling
reconfig_mgmt_write	Output	1	RX reconfiguration manejimendi Avalon memory-mapped interface kune transceiver arbiter
reconfig_mgmt_read	Output	1
reconfig_mgmt_address	Output	12

reconfig_mgmt_writedata	Output	32
reconfig_mgmt_readdata	Input	32
reconfig_mgmt_waitrequest	Input	1

HDMI RX Core Zviratidzo
TMDS_Bit_clock_Ratio	Output	1	SCDC rejista interfaces
audio_de	Output	1	HDMI RX musimboti audio interfaces Tarisa kune Sink Interfaces chikamu muHDMI Intel FPGA IP Mushandisi Guide kuti uwane rumwe ruzivo.
audio_data	Output	256
audio_info_ai	Output	48
audio_N	Output	20
audio_CTS	Output	20
audio_metadata	Output	165
audio_format	Output	5
aux_pkt_data	Output	72	HDMI RX musimboti wekubatsira interfaces Tarisa kune Sink Interfaces chikamu muHDMI Intel FPGA IP Mushandisi Guide kuti uwane rumwe ruzivo.
aux_pkt_addr	Output	6
aux_pkt_wr	Output	1
aux_data	Output	72
aux_sop	Output	1
aux_eop	Output	1
aux_valid	Output	1
aux_error	Output	1
gcp	Output	6	HDMI RX musimboti webhendi masaini Tarisa kune Sink Interfaces chikamu muHDMI Intel FPGA IP Mushandisi Guide kuti uwane rumwe ruzivo.
info_avi	Output	112
info_vsi	Output	61
colordepth_mgmt_sync	Output	2
vid_data	Output	N*48	HDMI RX yakakosha vhidhiyo ports Cherechedza: N = zviratidzo pawachi Tarisa kune Sink Interfaces chikamu mu HDMI Intel FPGA IP User Guide kuti uwane rumwe ruzivo.
vid_vsync	Output	N
vid_hsync	Output	N
vid_de	Output	N
mode	Output	1	HDMI RX musimboti kudzora uye mamiriro ports Cherechedza: N = zviratidzo pawachi Tarisa kune Sink Interfaces chikamu mu HDMI Intel FPGA IP User Guide kuti uwane rumwe ruzivo.
ctrl	Output	N*6
rakakiyiwa	Output	3
vid_lock	Output	1
mu_5v_simba	Input	1	HDMI RX 5V inoona uye hotplug yekuona Tarisa kune Sink Interfaces chikamu mu HDMI Intel FPGA IP User Guide kuti uwane rumwe ruzivo.
hdmi_rx_hpd_n	Inout	1

hdmi_rx_i2c_sda	Inout	1	HDMI RX DDC uye SCDC interface
hdmi_rx_i2c_scl	Inout	1

RX EDID RAM Zviratidzo
edid_ram_access	Input	1	HDMI RX EDID RAM yekuwana interface. Bvunza edid_ram_access kana uchida kunyora kana kuverenga kubva paEDID RAM, ukasadaro chiratidzo ichi chinofanira kugara chakaderera.
edid_ram_address	Input	8
edid_ram_write	Input	1
edid_ram_read	Input	1
edid_ram_readdata	Output	8
edid_ram_writedata	Input	8
edid_ram_waitrequest	Output	1

Tafura 43. HDMI TX Top-Level Zviratidzo

Signal	Direction	Upamhi	Tsanangudzo
Clock uye Reset Signals
mgmt_clk	Input	1	Sisitimu wachi yekupinda (100 MHz)
fr_clk (Intel Quartus Prime Pro Edition)	Input	1	Wachi yemahara inomhanya (625 MHz) yekutanga transceiver referensi wachi. Iyi wachi inodiwa kuti transceiver calibration panguva yekusimba-up state. wachi iyi inogona kuva chero frequency.
reset	Input	1	Kuisazve sisitimu
hdmi_clk_in	Input	1	Reference wachi kuTX IOPLL uye TX PLL. Kuwanda kwewachi kwakafanana neiyo TMDS wachi frequency.
vid_clk_out	Output	1	Vhidhiyo wachi inobuda
ls_clk_out	Output	1	Link yekumhanyisa wachi kubuda
sys_init	Output	1	Sisitimu yekutanga kugadzirisa zvakare sisitimu pane simba-kumusoro
reset_xcvr	Input	1	Dzorera kuTX transceiver
reset_pll	Input	1	Reset kuIOPLL uye TX PLL
reset_pll_reconfig	Output	1	Reset kune PLL reconfiguration

TX Transceiver uye IOPLL Zviratidzo
tx_serial_data	Output	4	HDMI serial data kubva kuTX Native PHY
gxb_tx_ready	Output	1	Inoratidza TX Native PHY yagadzirira
gxb_tx_cal_busy_out	Output	4	TX Native PHY calibration yakabatikana chiratidzo kune transceiver arbiter
gxb_tx_cal_busy_in	Input	4	Calibration yakabatikana chiratidzo kubva kune transceiver arbiter kuenda kuTX Native PHY

TX Transceiver uye IOPLL Zviratidzo
iopll_locked	Output	1	Ratidza IOPLL yakakiiwa
txpll_locked	Output	1	Ratidza kuti TX PLL yakakiyiwa
gxb_reconfig_write	Input	4	Transceiver reconfiguration Avalon memory-mapped interface kubva kuTX Native PHY kuenda kune transceiver arbiter.
gxb_reconfig_read	Input	4
gxb_reconfig_address	Input	40
gxb_reconfig_writedata	Input	128
gxb_reconfig_readdata	Output	128
gxb_reconfig_waitrequest	Output	4

TX IOPLL uye TX PLL Reconfiguration Signals
pll_reconfig_write/ tx_pll_reconfig_write	Input	1	TX IOPLL/TX PLL kugadzirisazve Avalon memory-mapped interfaces
pll_reconfig_read/ tx_pll_reconfig_read	Input	1
pll_reconfig_address/ tx_pll_reconfig_address	Input	10
pll_reconfig_writedata/ tx_pll_reconfig_writedata	Input	32
pll_reconfig_readdata/ tx_pll_reconfig_readdata	Output	32
pll_reconfig_waitrequest/tx_pll_reconfig_waitrequest	Output	1
os	Input	2	Oversampling factor: • 0: Hapana oversampling • 1: 3× pamusoroampling • 2: 4× pamusoroampling • 3: 5× pamusoroampling
chiyero	Input	24	Inoratidza iyo TMDS wachi frequency yekutapurirana kwevhidhiyo resolution.

HDMI TX Core Signals
ctrl	Input	6*N	HDMI TX core control interfaces Cherechedza: N = Zviratidzo pawachi Tarisa kune iyo Source Interfaces chikamu mu HDMI Intel FPGA IP User Guide kune rumwe ruzivo.
mode	Input	1
TMDS_Bit_clock_Ratio	Input	1	SCDC rejista interfaces Tarisa kune Source Interfaces chikamu muHDMI Intel FPGA IP User Guide kuti uwane rumwe ruzivo.
Scrambler_Enable	Input	1
audio_de	Input	1	HDMI TX musimboti audio interfaces Tarisa kune Source Interfaces chikamu mu HDMI Intel FPGA IP User Guide kuti uwane rumwe ruzivo.
audio_mute	Input	1
audio_data	Input	256
akaenderera…

HDMI TX Core Signals
audio_info_ai	Input	49
audio_N	Input	22
audio_CTS	Input	22
audio_metadata	Input	166
audio_format	Input	5
i2c_master_write	Input	1	TX I2C tenzi Avalon memory-mapped interface kune I2C tenzi mukati meTX musimboti. Cherechedza: Aya masaini anowanikwa chete kana iwe ukabatidza Kusanganisira I2C parameter.
i2c_master_read	Input	1
i2c_master_address	Input	4
i2c_master_writedata	Input	32
i2c_master_readdata	Output	32
aux_ready	Output	1	HDMI TX musimboti wekubatsira nzvimbo Tarisa kune Source Interfaces chikamu muHDMI Intel FPGA IP User Guide kuti uwane rumwe ruzivo.
aux_data	Input	72
aux_sop	Input	1
aux_eop	Input	1
aux_valid	Input	1
gcp	Input	6	HDMI TX musimboti webhendi masaini Tarisa kune Source Interfaces chikamu muHDMI Intel FPGA IP User Guide kuti uwane rumwe ruzivo.
info_avi	Input	113
info_vsi	Input	62
vid_data	Input	N*48	HDMI TX yakakosha vhidhiyo ports Cherechedza: N = zviratidzo pawachi Tarisa kune Source Interfaces chikamu muHDMI Intel FPGA IP User Guide kuti uwane rumwe ruzivo.
vid_vsync	Input	N
vid_hsync	Input	N
vid_de	Input	N

I2C uye Hot Plug Detect Signals
nios_tx_i2c_sda_in (Intel Quartus Prime Pro Edition) Cherechedza: Paunobatidza iyo Kusanganisira I2C parameter, chiratidzo ichi chakaiswa muTX core uye hachizoonekwe padanho iri.	Output	1	I2C Master Avalon memory-mapped interfaces
nios_tx_i2c_scl_in (Intel Quartus Prime Pro Edition) Cherechedza: Paunobatidza iyo Kusanganisira I2C parameter, chiratidzo ichi chakaiswa muTX core uye hachizoonekwe padanho iri.	Output	1
nios_tx_i2c_sda_oe (Intel Quartus Prime Pro Edition) Cherechedza: Paunobatidza iyo Kusanganisira I2C parameter, chiratidzo ichi chakaiswa muTX core uye hachizoonekwe padanho iri.	Input	1
akaenderera…

I2C uye Hot Plug Detect Signals
nios_tx_i2c_scl_oe (Intel Quartus Prime Pro Edition) Cherechedza: Paunobatidza iyo Kusanganisira I2C parameter, chiratidzo ichi chakaiswa muTX core uye hachizoonekwe padanho iri.	Input	1
nios_ti_i2c_sda_in (Intel Quartus Prime Pro Edition)	Output	1
nios_ti_i2c_scl_in (Intel Quartus Prime Pro Edition)	Output	1
nios_ti_i2c_sda_oe (Intel Quartus Prime Pro Edition)	Input	1
nios_ti_i2c_scl_oe (Intel Quartus Prime Pro Edition)	Input	1
hdmi_tx_i2c_sda	Inout	1	HDMI TX DDC uye SCDC interfaces
hdmi_tx_i2c_scl	Inout	1
hdmi_ti_i2c_sda (Intel Quartus Prime Pro Edition)	Inout	1	I2C interface yeBitec Mwanasikana Kadhi Revision 11 TI181 Kudzora
hdmi_tx_ti_i2c_sda (Intel Quartus Prime Standard Edition)	Inout	1
hdmi_ti_i2c_scl (Intel Quartus Prime Pro Edition)	Inout	1
hdmi_tx_ti_i2c_scl (Intel Quartus Prime Standard Edition)	Inout	1
tx_i2c_avalon_waitrequest	Output	1	Avalon memory-mapped interfaces yeI2C master
tx_i2c_avalon_address (Intel Quartus Prime Standard Edition)	Input	3
tx_i2c_avalon_writedata (Intel Quartus Prime Standard Edition)	Input	8
tx_i2c_avalon_readdata (Intel Quartus Prime Standard Edition)	Output	8
tx_i2c_avalon_chipselect (Intel Quartus Prime Standard Edition)	Input	1
tx_i2c_avalon_write (Intel Quartus Prime Standard Edition)	Input	1
tx_i2c_irq (Intel Quartus Prime Standard Edition)	Output	1
tx_ti_i2c_avalon_waitrequest (Intel Quartus Prime Standard Edition)	Output	1
tx_ti_i2c_avalon_address (Intel Quartus Prime Standard Edition)	Input	3
tx_ti_i2c_avalon_writedata (Intel Quartus Prime Standard Edition)	Input	8
tx_ti_i2c_avalon_readdata (Intel Quartus Prime Standard Edition)	Output	8
akaenderera…

I2C uye Hot Plug Detect Signals
tx_ti_i2c_avalon_chipselect (Intel Quartus Prime Standard Edition)	Input	1
tx_ti_i2c_avalon_write (Intel Quartus Prime Standard Edition)	Input	1
tx_ti_i2c_irq (Intel Quartus Prime Standard Edition)	Output	1
hdmi_tx_hpd_n	Input	1	HDMI TX hotplug inoona nzvimbo dzekupindirana
tx_hpd_ack	Input	1
tx_hpd_req	Output	1

Tafura 44. Transceiver Arbiter Signals

Signal	Direction	Upamhi	Tsanangudzo
clk	Input	1	Reconfiguration wachi. Wachi iyi inofanirwa kugovera wachi imwe chete nemabhuroki ekugadzirisa zvakare.
reset	Input	1	Reset chiratidzo. Iyi reset inofanirwa kugovera iyo yakafanana kuseta nemabhuroko ekugadzirisa manejimendi.
rx_rcfg_en	Input	1	RX reconfiguration inogonesa chiratidzo
tx_rcfg_en	Input	1	TX reconfiguration inogonesa chiratidzo
rx_rcfg_ch	Input	2	Inoratidza kuti ndeipi chiteshi chinogadziriswa paRX musimboti. Ichi chiratidzo chinofanira kugara chakasimbiswa.
tx_rcfg_ch	Input	2	Inoratidza kuti ndeipi chiteshi chinogadziriswa paTX core. Ichi chiratidzo chinofanira kugara chakasimbiswa.
rx_reconfig_mgmt_write	Input	1	Reconfiguration Avalon-MM inopindirana kubva kuRX reconfiguration manejimendi
rx_reconfig_mgmt_read	Input	1
rx_reconfig_mgmt_address	Input	10
rx_reconfig_mgmt_writedata	Input	32
rx_reconfig_mgmt_readdata	Output	32
rx_reconfig_mgmt_waitrequest	Output	1
tx_reconfig_mgmt_write	Input	1	Reconfiguration Avalon-MM interfaces kubva kuTX reconfiguration manejimendi
tx_reconfig_mgmt_read	Input	1
tx_reconfig_mgmt_address	Input	10
tx_reconfig_mgmt_writedata	Input	32
tx_reconfig_mgmt_readdata	Output	32
tx_reconfig_mgmt_waitrequest	Output	1
reconfig_write	Output	1	Reconfiguration Avalon-MM inopindirana kune transceiver
reconfig_read	Output	1
akaenderera…

Signal	Direction	Upamhi	Tsanangudzo
reconfig_address	Output	10
reconfig_writedata	Output	32
rx_reconfig_readdata	Input	32
rx_reconfig_waitrequest	Input	1
tx_reconfig_readdata	Input	1
tx_reconfig_waitrequest	Input	1
rx_cal_busy	Input	1	Calibration chimiro chiratidzo kubva kuRX transceiver
tx_cal_busy	Input	1	Calibration chimiro chiratidzo kubva kuTX transceiver
rx_reconfig_cal_busy	Output	1	Calibration chimiro chiratidzo kune RX transceiver PHY reset control
tx_reconfig_cal_busy	Output	1	Calibration chimiro chiratidzo kubva kuTX transceiver PHY reset control

Tafura 45. RX-TX Link Signals

Signal	Direction	Upamhi	Tsanangudzo
reset	Input	1	Reset kune vhidhiyo/odhiyo/mubatsiri/mabhendi FIFO buffer.
hdmi_tx_ls_clk	Input	1	HDMI TX yekubatanidza kumhanya wachi
hdmi_rx_ls_clk	Input	1	HDMI RX yekubatanidza yekumhanyisa wachi
hdmi_tx_vid_clk	Input	1	HDMI TX vhidhiyo wachi
hdmi_rx_vid_clk	Input	1	HDMI RX vhidhiyo wachi
hdmi_rx_locked	Input	3	Inoratidza HDMI RX yakavharwa mamiriro
hdmi_rx_de	Input	N	HDMI RX vhidhiyo interfaces Cherechedza: N = zviratidzo pawachi
hdmi_rx_hsync	Input	N
hdmi_rx_vsync	Input	N
hdmi_rx_data	Input	N*48
rx_audio_format	Input	5	HDMI RX audio interfaces
rx_audio_metadata	Input	165
rx_audio_info_ai	Input	48
rx_audio_CTS	Input	20
rx_audio_N	Input	20
rx_audio_de	Input	1
rx_audio_data	Input	256
rx_gcp	Input	6	HDMI RX sideband interfaces
rx_info_avi	Input	112
rx_info_vsi	Input	61
akaenderera…

Signal	Direction	Upamhi	Tsanangudzo
rx_aux_eop	Input	1	HDMI RX yekubatsira interfaces
rx_aux_sop	Input	1
rx_aux_valid	Input	1
rx_aux_data	Input	72
hdmi_tx_de	Output	N	HDMI TX vhidhiyo interfaces Cherechedza: N = zviratidzo pawachi
hdmi_tx_hsync	Output	N
hdmi_tx_vsync	Output	N
HDmi_tx_data	Output	N*48
tx_audio_format	Output	5	HDMI TX audio interfaces
tx_audio_metadata	Output	165
tx_audio_info_ai	Output	48
tx_audio_CTS	Output	20
tx_audio_N	Output	20
tx_audio_de	Output	1
tx_audio_data	Output	256
tx_gcp	Output	6	HDMI TX sideband interfaces
tx_info_avi	Output	112
tx_info_vsi	Output	61
tx_aux_eop	Output	1	HDMI TX yekubatsira interfaces
tx_aux_sop	Output	1
tx_aux_valid	Output	1
tx_aux_data	Output	72
tx_aux_ready	Output	1

Tafura 46. Platform Designer System Signals

Signal	Direction	Upamhi	Tsanangudzo
cpu_clk (Intel Quartus Prime Standard Edition)	Input	1	CPU wachi
clock_bridge_0_in_clk_clk (Intel Quartus Prime Pro Edition)
cpu_clk_reset_n (Intel Quartus Prime Standard Edition)	Input	1	CPU itangezve
reset_bridge_0_reset_reset_n (Intel Quartus Prime Pro Edition)
tmds_bit_clock_ratio_pio_external_connectio n_export	Input	1	TMDS bit clock ratio
measure_pio_external_connection_export	Input	24	Inotarisirwa TMDS wachi frequency
akaenderera…

Signal	Direction	Upamhi	Tsanangudzo
measure_valid_pio_external_connection_expor t	Input	1	Inoratidza kuyerwa kwePIO inoshanda
i2c_master_i2c_serial_sda_in (Intel Quartus Prime Pro Edition)	Input	1	I2C Master interfaces
i2c_master_i2c_serial_scl_in (Intel Quartus Prime Pro Edition)	Input	1
i2c_master_i2c_serial_sda_oe (Intel Quartus Prime Pro Edition)	Output	1
i2c_master_i2c_serial_scl_oe (Intel Quartus Prime Pro Edition)	Output	1
i2c_master_ti_i2c_serial_sda_in (Intel Quartus Prime Pro Edition)	Input	1
i2c_master_ti_i2c_serial_scl_in (Intel Quartus Prime Pro Edition)	Input	1
i2c_master_ti_i2c_serial_sda_oe (Intel Quartus Prime Pro Edition)	Output	1
i2c_master_ti_i2c_serial_scl_oe (Intel Quartus Prime Pro Edition)	Output	1
oc_i2c_master_av_slave_translator_avalon_an ti_slave_0_address (Intel Quartus Prime Pro Edition)	Output	3	I2C Master Avalon memory-mapped interfaces yeDDC neSCDC
oc_i2c_master_av_slave_translator_avalon_an ti_slave_0_write (Intel Quartus Prime Pro Edition)	Output	1
oc_i2c_master_av_slave_translator_avalon_an ti_slave_0_readdata (Intel Quartus Prime Pro Edition)	Input	32
oc_i2c_master_av_slave_translator_avalon_an ti_slave_0_writedata (Intel Quartus Prime Pro Edition)	Output	32
oc_i2c_master_av_slave_translator_avalon_an ti_slave_0_waitrequest (Intel Quartus Prime Pro Edition)	Input	1
oc_i2c_master_av_slave_translator_avalon_an ti_slave_0_chipselect (Intel Quartus Prime Pro Edition)	Output	1
oc_i2c_master_ti_avalon_anti_slave_address (Intel Quartus Prime Standard Edition)	Output	3	I2C Master Avalon memory-mapped interfaces yeBitec mwanasikana kadhi revision 11, T1181 control.
oc_i2c_master_ti_avalon_anti_slave_write (Intel Quartus Prime Standard Edition)	Output	1
oc_i2c_master_ti_avalon_anti_slave_readdata (Intel Quartus Prime Standard Edition)	Input	32
oc_i2c_master_ti_avalon_anti_slave_writedat a (Intel Quartus Prime Standard Edition)	Output	32
oc_i2c_master_ti_avalon_anti_slave_waitrequ est (Intel Quartus Prime Standard Edition)	Input	1
oc_i2c_master_ti_avalon_anti_slave_chipsele ct (Intel Quartus Prime Standard Edition)	Output	1
akaenderera…

Signal	Direction	Upamhi	Tsanangudzo
edid_ram_access_pio_external_connection_exp ort	Output	1	EDID RAM yekuwana interfaces. Assert edid_ram_access_pio_ external_connection_ export kana uchida kunyora kana kuverenga kubva paEDID RAM pamusoro peRX. Batanidza EDID RAM kuwana Avalon-MM muranda muPlatform Designer kune EDID RAM interface pane yepamusoro-level RX module.
edid_ram_slave_translator_address	Output	8
edid_ram_slave_translator_write	Output	1
edid_ram_slave_translator_read	Output	1
edid_ram_slave_translator_readdata	Input	8
edid_ram_slave_translator_writedata	Output	8
edid_ram_slave_translator_waitrequest	Input	1
powerup_cal_done_export (Intel Quartus Prime Pro Edition)	Input	1	RX PMA Reconfiguration Avalon memory-mapped interfaces
rx_pma_cal_busy_export (Intel Quartus Prime Pro Edition)	Input	1
rx_pma_ch_export (Intel Quartus Prime Pro Edition)	Output	2
rx_pma_rcfg_mgmt_address (Intel Quartus Prime Pro Edition)	Output	12
rx_pma_rcfg_mgmt_write (Intel Quartus Prime Pro Edition)	Output	1
rx_pma_rcfg_mgmt_read (Intel Quartus Prime Pro Edition)	Output	1
rx_pma_rcfg_mgmt_readdata (Intel Quartus Prime Pro Edition)	Input	32
rx_pma_rcfg_mgmt_writedata (Intel Quartus Prime Pro Edition)	Output	32
rx_pma_rcfg_mgmt_waitrequest (Intel Quartus Prime Pro Edition)	Input	1
rx_pma_waitrequest_export (Intel Quartus Prime Pro Edition)	Input	1
rx_rcfg_en_export (Intel Quartus Prime Pro Edition)	Output	1
rx_rst_xcvr_export (Intel Quartus Prime Pro Edition)	Output	1
tx_pll_rcfg_mgmt_translator_avalon_anti_sla ve_waitrequest	Input	1	TX PLL Reconfiguration Avalon memory-mapped interfaces
tx_pll_rcfg_mgmt_translator_avalon_anti_sla ve_writedata	Output	32
tx_pll_rcfg_mgmt_translator_avalon_anti_sla ve_address	Output	10
tx_pll_rcfg_mgmt_translator_avalon_anti_sla ve_write	Output	1
tx_pll_rcfg_mgmt_translator_avalon_anti_sla ve_read	Output	1
tx_pll_rcfg_mgmt_translator_avalon_anti_sla ve_readdata	Input	32
akaenderera…

Signal	Direction	Upamhi	Tsanangudzo
tx_pll_waitrequest_pio_external_connection_ kunze	Input	1	TX PLL waitrequest
tx_pma_rcfg_mgmt_translator_avalon_anti_sla ve_address	Output	12	TX PMA Reconfiguration Avalon memory-mapped interfaces
tx_pma_rcfg_mgmt_translator_avalon_anti_sla ve_write	Output	1
tx_pma_rcfg_mgmt_translator_avalon_anti_sla ve_read	Output	1
tx_pma_rcfg_mgmt_translator_avalon_anti_sla ve_readdata	Input	32
tx_pma_rcfg_mgmt_translator_avalon_anti_sla ve_writedata	Output	32
tx_pma_rcfg_mgmt_translator_avalon_anti_sla ve_waitrequest	Input	1
tx_pma_waitrequest_pio_external_connection_ kunze	Input	1	TX PMA waitrequest
tx_pma_cal_busy_pio_external_connection_exp ort	Input	1	TX PMA Recalibration Yakabatikana
tx_pma_ch_export	Output	2	TX PMA Channels
tx_rcfg_en_pio_external_connection_export	Output	1	TX PMA Reconfiguration Gonesa
tx_iopll_rcfg_mgmt_translator_avalon_anti_s lave_writedata	Output	32	TX IOPLL Reconfiguration Avalon memory-mapped interfaces
tx_iopll_rcfg_mgmt_translator_avalon_anti_s lave_readdata	Input	32
tx_iopll_rcfg_mgmt_translator_avalon_anti_s lave_waitrequest	Input	1
tx_iopll_rcfg_mgmt_translator_avalon_anti_s lave_address	Output	9
tx_iopll_rcfg_mgmt_translator_avalon_anti_s lave_write	Output	1
tx_iopll_rcfg_mgmt_translator_avalon_anti_s lave_read	Output	1
tx_os_pio_external_connection_export	Output	2	Oversampling factor: • 0: Hapana oversampling • 1: 3× pamusoroampling • 2: 4× pamusoroampling • 3: 5× pamusoroampling
tx_rst_pll_pio_external_connection_export	Output	1	Reset kuIOPLL uye TX PLL
tx_rst_xcvr_pio_external_connection_export	Output	1	Reset kuTX Native PHY
wd_timer_resetrequest_reset	Output	1	Nguva yekutarisa inogadziriswazve
color_depth_pio_external_connection_export	Input	2	Kudzika kwemavara
tx_hpd_ack_pio_external_connection_export	Output	1	YeTX hotplug tarisa kubata maoko
tx_hpd_req_pio_external_connection_export	Input	1

3.8. Dhizaini RTL Parameters
Shandisa HDMI TX uye RX Pamusoro RTL paramita kugadzirisa dhizaini example.
Mazhinji emagetsi ekugadzira anowanikwa muDesign Exampuye tebhu yeHDMI Intel FPGA IP parameter mupepeti. Iwe unogona zvakare kushandura dhizaini example settings iwe
yakagadzirwa muparameter mupepeti kuburikidza neRTL paramita.

Tafura 47. HDMI RX Top Parameters

Parameter	Value	Tsanangudzo
SUPPORT_DEEP_COLOR	• 0: Hapana ruvara rwakadzika • 1: Ruvara rwakadzama	Inosarudza kana iyo yakakosha inogona encode yakadzika mavara mafomati.
SUPPORT_AUXILIARY	• 0: Hapana AUX • 1: AUX	Inotarisa kana iyo yekubatsira chiteshi encoding inosanganisirwa.
SYMBOLS_PER_CLOCK	8	Inotsigira 8 zviratidzo pawachi yeIntel Arria 10 zvishandiso.
SUPPORT_AUDIO	• 0: Hapana audio • 1: Audio	Inoona kana musimboti uchikwanisa kukodha odhiyo.
EDID_RAM_ADDR_WIDTH (Intel Quartus Prime Standard Edition)	8 (Default kukosha)	Log base 2 yeEDID RAM saizi.
BITEC_DAUGHTER_CARD_REV	• 0: Kwete kunanga chero Bitec HDMI mwanasikana kadhi • 4: Inotsigira Bitec HDMI mwanasikana kadhi kudzokorora 4 • 6: Targeting Bitec HDMI mwanasikana kadhi revision 6 •11: Targeting Bitec HDMI mwanasikana kadhi revision 11 (default)	Inotsanangura kudzokororwa kweBitec HDMI mwanasikana kadhi rakashandiswa. Paunoshandura gadziriso, dhizaini inogona kuchinjanisa ma transceiver chiteshi uye kushandura polarity zvinoenderana neBitec HDMI mwanasikana kadhi zvinodiwa. Kana ukaisa BITEC_DAUGHTER_CARD_REV parameter kusvika 0, magadzirirwo acho haaiti chero shanduko kumatanho etransceiver uye polarity.
POLARITY_INVERSION	• 0: Invert polarity 1: Usapindure polarity	Gadzirisa iyi parameter kune 1 kuti inverted kukosha kwechimwe nechimwe che data yekupinza. Kuseta iyi parameter kune 1 inopa 4'b1111 kune rx_polinv chiteshi cheiyo RX transceiver.

Tafura 48. HDMI TX Top Parameters

Parameter	Value	Tsanangudzo
USE_FPLL	1	Inotsigira fPLL seTX PLL chete yeIntel Cyclone® 10 GX zvishandiso. Gara uchiisa iyi parameter ku1.
SUPPORT_DEEP_COLOR	• 0: Hapana ruvara rwakadzika • 1: Ruvara rwakadzama	Inosarudza kana iyo yakakosha inogona encode yakadzika mavara mafomati.
SUPPORT_AUXILIARY	• 0: Hapana AUX • 1: AUX	Inotarisa kana iyo yekubatsira chiteshi encoding inosanganisirwa.
SYMBOLS_PER_CLOCK	8	Inotsigira 8 zviratidzo pawachi yeIntel Arria 10 zvishandiso.
akaenderera…

Parameter	Value	Tsanangudzo
SUPPORT_AUDIO	• 0: Hapana audio • 1: Audio	Inoona kana musimboti uchikwanisa kukodha odhiyo.
BITEC_DAUGHTER_CARD_REV	• 0: Kwete kunanga chero Bitec HDMI mwanasikana kadhi • 4: Inotsigira Bitec HDMI mwanasikana kadhi kudzokorora 4 • 6: Targeting Bitec HDMI mwanasikana kadhi revision 6 • 11: Targeting Bitec HDMI mwanasikana kadhi revision 11 (default)	Inotsanangura kudzokororwa kweBitec HDMI mwanasikana kadhi rakashandiswa. Paunoshandura gadziriso, dhizaini inogona kuchinjanisa ma transceiver chiteshi uye kushandura polarity zvinoenderana neBitec HDMI mwanasikana kadhi zvinodiwa. Kana ukaisa BITEC_DAUGHTER_CARD_REV parameter kusvika 0, magadzirirwo acho haaiti chero shanduko kumatanho etransceiver uye polarity.
POLARITY_INVERSION	• 0: Invert polarity 1: Usapindure polarity	Gadzirisa iyi parameter kune 1 kuti inverted kukosha kwechimwe nechimwe che data yekupinza. Kuseta iyi parameter kune 1 inopa 4'b1111 kune tx_polinv chiteshi cheTX transceiver.

3.9. Hardware Setup
Iyo HDMI Intel FPGA IP dhizaini example iHDMI 2.0b inokwanisa uye inoita loopthrough kuratidzira kune yakajairwa HDMI vhidhiyo rwizi.
Kumhanyisa bvunzo dzehardware, batanidza mudziyo unogoneswa neHDMI-senge kadhi remifananidzo rine HDMI interface-kuTransceiver Native PHY RX block, uye HDMI sink.
input.

1. Iyo HDMI sink inodhidha chiteshi kuita yakajairwa vhidhiyo rwizi uye inotumira kune wachi yekudzoreredza musimboti.
2. Iyo HDMI RX musimboti inosarudza vhidhiyo, yebetsero, uye odhiyo data kuti idzoserwe kumashure inoenderana neiyo HDMI TX musimboti kuburikidza neDCFIFO.
3. Iyo HDMI sosi chiteshi cheFMC mwanasikana kadhi inoendesa chifananidzo kune chekutarisa.

Cherechedza:
Kana iwe uchida kushandisa imwe Intel FPGA yekuvandudza bhodhi, iwe unofanirwa kushandura iyo migove yemuchina uye pini yekupihwa. Iyo transceiver analog kuseta inoedzwa iyo Intel Arria 10 FPGA yekuvandudza kit uye Bitec HDMI 2.0 mwanasikana kadhi. Iwe unogona kugadzirisa zvirongwa zvebhodhi rako pachako.

Tafura 49. Pa-bhodhi Push Button uye User LED Mabasa

Push Bhatani / LED	Function
cpu_resetn	Dzvanya kamwe kuti uite system reset.
mushandisi_pb[0]	Dzvanya kamwe chete kushandura chiratidzo cheHPD kune yakajairwa HDMI sosi.
mushandisi_pb[1]	• Dzvanya uye bata kuti uraire TX core kutumira DVI encoded siginecha. • Sunungura kutumira HDMI encoded chiratidzo.
mushandisi_pb[2]	• Dzvanya uye ubate kuti uraire TX musimboti kuti urege kutumira InfoFrames kubva kumasaini ebhendi. • Sunungura kuti utangezve kutumira iyo InfoFrames kubva kumasaini epadivi.
USER_LED[0]	RX HDMI PLL kukiya mamiriro. • 0 = Yakakiyiwa • 1 = Yakakiyiwa
USER_LED[1]	RX transceiver yakagadzirira chimiro.
akaenderera…

Push Bhatani / LED	Function
	• 0 = Haina kugadzirira • 1 = Yakagadzirira
USER_LED[2]	RX HDMI musimboti wekukiya mamiriro. • 0 = Kanenge 1 chiteshi chakavhurwa • 1 = All 3 migero yakakiyiwa
USER_LED[3]	RX pamusoroampling status. • 0 = Zvisiri-pamusoroampled (data rate> 1,000 Mbps muIntel Arria 10 mudziyo) • 1 = Oversampled (data rate <100 Mbps muIntel Arria 10 mudziyo)
USER_LED[4]	TX HDMI PLL kukiya mamiriro. • 0 = Yakakiyiwa • 1 = Yakakiyiwa
USER_LED[5]	TX transceiver yakagadzirira chimiro. • 0 = Haina kugadzirira • 1 = Yakagadzirira
USER_LED[6]	TX transceiver PLL kukiya mamiriro. • 0 = Yakakiyiwa • 1 = Yakakiyiwa
USER_LED[7]	TX pamusoroampling status. • 0 = Zvisiri-pamusoroampled (data rate> 1,000 Mbps muIntel Arria 10 mudziyo) • 1 = Oversampled (data rate <1,000 Mbps muIntel Arria 10 mudziyo)

3.10. Simulation Testbench
Iyo simulation testbench inoteedzera iyo HDMI TX serial loopback kune iyo RX musimboti.
Cherechedza:
Iyi yekunyepedzera testbench haitsigirwe magadzirirwo ane Include I2C parameter yakagoneswa.

3. HDMI 2.0 Dhizaini Example (Kutsigira FRL = 0)
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Mufananidzo 28. HDMI Intel FPGA IP Simulation Testbench Block Diagram

Tafura 50. Testbench Zvikamu

Chikamu	Tsanangudzo
Vhidhiyo TPG	Iyo vhidhiyo bvunzo pateni jenareta (TPG) inopa vhidhiyo inosimudzira.
Audio Sample Gen	Iyo audio sample jenareta inopa odhiyo sample stimulus. Iyo jenareta inogadzira iyo inowedzera bvunzo data pateni kuti ifambiswe kuburikidza neodhiyo chiteshi.
Aux Sample Gen	The aux sample jenareta inopa ebetsero sample stimulus. Iyo jenareta inogadzira data rakagadziriswa kuti rifambiswe kubva kune transmitter.
CRC Tarisa	Iyi yekutarisa inoongorora kana iyo TX transceiver yakadzoreredza wachi frequency ichienderana neinodiwa data data.
Audio Data Check	Iyo yekuteerera dhata cheki inofananidza kana iyo inowedzera bvunzo data patani inogamuchirwa uye yakadhindwa nemazvo.
Aux Data Check	Iyo aux data cheki inofananidza kana iyo inotarisirwa aux data inogamuchirwa uye yakatemwa nemazvo padivi rekugamuchira.

Iyo HDMI simulation testbench inoita zvinotevera bvunzo bvunzo:

HDMI Feature	Verification
Vhidhiyo data	• Testbench inoshandisa CRC ichitarisa pakupinda nekubuda kwevhidhiyo. • Inotarisa kukosha kweCRC ye data yakatumirwa kuCRC yakaverengerwa muvhidhiyo yakagamuchirwa data. • Testbench inobva yaita cheki mushure mekuona 4 yakagadzikana V-SYNC zviratidzo kubva kune anogamuchira.
Auxiliary data	• Nyaya sample jenareta inogadzira data rakagadziriswa kuti rifambiswe kubva kune transmitter. • Padivi rekugamuchira, jenareta inoenzanisa kana data inotarisirwa yebetsero inogamuchirwa uye yakadhindwa nemazvo.
Audio data	• The audio sample jenareta inogadzira iyo inowedzera bvunzo data pateni kuti ifambiswe kuburikidza neodhiyo chiteshi. • Kudivi rekugamuchira, redhiyo data cheki inotarisa uye inoenzanisa kana iyo incrementing test data pateni inogamuchirwa uye yakatemwa nemazvo.

Simulation yakabudirira inopera neshoko rinotevera:
# SYMBOLS_PER_CLOCK = 2
#VIC = 4
# FRL_RATE = 0
# BPP = 0
# AUDIO_FREQUENCY (kHz) = 48
# AUDIO_CHANNEL = 8
# Simulation pass

Tafura 51. HDMI Intel FPGA IP Dhizaini Example Inotsigirwa Simulators

Simulator	Verilog HDL	VHDL
ModelSim - Intel FPGA Edition / ModelSim - Intel FPGA Starter Edition	Ehe	Ehe
VCS/VCS MX	Ehe	Ehe
Riviera-PRO	Ehe	Ehe
Xcelium Parallel	Ehe	Aihwa

3.11. Kuvandudza Dhizaini Yako
Tafura 52. HDMI Dhizaini Example Kuenderana neYapfuura Intel Quartus Prime Pro Edition Software Version

Design Example Variant	Kugona Kukwidziridza kuIntel Quartus Prime Pro Edition 20.3
HDMI 2.0 Dhizaini Example (Kutsigira FRL = 0)	Aihwa

Kune chero isingaenderane dhizaini exampkana, iwe unofanirwa kuita zvinotevera:

1. Gadzira imwe dhizaini example mune yazvino Intel Quartus Prime Pro Edition software vhezheni uchishandisa magadzirirwo akafanana edhizaini yako iripo.
2. Enzanisa yose dhizaini example directory ine dhizaini exampinogadzirwa uchishandisa yakapfuura Intel Quartus Prime Pro Edition software vhezheni. Port pamusoro pekuchinja kwawanikwa.

HDCP Pamusoro peHDMI 2.0/2.1 Dhizaini Example

Iyo HDCP pamusoro peHDMI hardware dhizaini example inokubatsira kuti uongorore mashandiro eiyo HDCP chimiro uye inoita kuti iwe ushandise iyo ficha mune yako Intel Arria gumi madhizaini.
Cherechedza:
Iyo HDCP ficha haina kubatanidzwa muIntel Quartus Prime Pro Edition software. Kuti uwane iyo HDCP chimiro, bata Intel pa https://www.intel.com/content/www/us/en/broadcast/products/programmable/applications/connectivity-solutions.html.

4.1. Yakakwira-bandwidth Digital Content Dziviriro (HDCP)
Yakakwira-bandwidth Dhijitari Yemukati Dziviriro (HDCP) imhando yedziviriro yekodzero dzedhijitari kugadzira hukama hwakachengeteka pakati pekwakabva kuchiratidziro.
Intel yakagadzira tekinoroji yekutanga, inopihwa rezinesi neDigital Content Protection LLC boka. HDCP inzira yekudzivirira kopi uko odhiyo/vhidhiyo rukova rwakavharirwa pakati pemutakuri neanogamuchira, achidzivirira kubva pakukopa zvisiri pamutemo.
Iyo HDCP maficha anoomerera kune HDCP Tsanangudzo vhezheni 1.4 uye HDCP Specification vhezheni 2.3.
Iyo HDCP 1.4 uye HDCP 2.3 IPs inoita zvese computation mukati meiyo hardware musimboti logic isina zvakavanzika kukosha (seyakavanzika kiyi uye chikamu kiyi) ichiwanikwa kubva kunze kweiyo IP yakavharidzirwa.

Tafura 53. HDCP IP Mabasa

HDCP IP	Mabasa
HDCP 1.4 IP	• Kutsinhana kwechokwadi -Kuverengera master kiyi (Km) - Chizvarwa chekungoerekana An -Kuverengera kwesesheni kiyi (Ks), M0 uye R0. • Huchokwadi neanodzokorora -Kuverengera uye kusimbiswa kweV uye V' • Batanidza kuvimbika kwechokwadi -Kuverengera kwekiyi kiyi (Ki), Mi uye Ri.
akaenderera…

Intel Corporation. Kodzero dzese dzakachengetwa. Intel, iyo Intel logo, uye mamwe maIntel mamaki zviratidzo zveIntel Corporation kana vatsigiri vayo. Intel inobvumidza kuita kwayo FPGA uye semiconductor zvigadzirwa kune zvazvino zvirevo zvinoenderana neIntel's standard waranti, asi inochengetera kodzero yekuita shanduko kune chero zvigadzirwa nemasevhisi chero nguva pasina chiziviso. Intel haitore mutoro kana mutoro unobva mukushandisa kana kushandiswa kwechero ruzivo, chigadzirwa, kana sevhisi inotsanangurwa pano kunze kwekunge yakabvumiranwa nekunyora neIntel. Vatengi veIntel vanorairwa kuti vawane yazvino vhezheni yezvakatemwa zvemudziyo vasati vavimba nechero ruzivo rwakaburitswa uye vasati vaisa maodha ezvigadzirwa kana masevhisi.
*Mamwe mazita nemhando zvinogona kunzi ndezvevamwe.

ISO
9001:2015
Registered

HDCP IP	Mabasa
	• Mhando dzese dzecipher dzinosanganisira hdcpBlockCipher, hdcpStreamCipher, hdcpRekeyCipher, uye hdcpRngCipher • Yekutanga encryption status signing (DVI) uye encryption status signing (HDMI) • Chokwadi zvisina tsarukano jenareta (TRNG) - Hardware yakavakirwa, yakazara dhijitari kuita uye isiri-deterministic random nhamba jenareta
HDCP 2.3 IP	• Master Key (km), Session Key (ks) uye nonce (rn, riv) chizvarwa - Inopindirana neNIST.SP800-90A random nhamba chizvarwa • Kutendesa uye kuchinjana kwakakosha -Kugadzirwa kwenhamba dzisina kurongeka dze rtx uye rrx inoenderana neNIST.SP800-90A isina kurongeka nhamba chizvarwa -Siginecha yekusimbisa chitupa chekugamuchira (certrx) uchishandisa DCP yeruzhinji kiyi (kpubdcp) - 3072 bits RSASSA-PKCS#1 v1.5 -RSAES-OAEP (PKCS#1 v2.1) encryption uye decryption yeMaster Key (km) -Kutorwa kwe kd (dkey0, dkey1) uchishandisa AES-CTR modhi -Kuverenga uye kusimbiswa kweH uye H' -Kuverengera kweEkh (km) uye km (pairing) • Huchokwadi neanodzokorora -Kuverengera uye kusimbiswa kweV uye V' -Kuverenga uye kusimbiswa kweM uye M' • Kuvandudza sisitimu (SRM) - SRM siginecha verification uchishandisa kpubdcp - 3072 bits RSASSA-PKCS#1 v1.5 • Session Key exchange • Chizvarwa uye computation yeEdkey(ks) uye riv. • Kubviswa kwe dkey2 uchishandisa AES-CTR mode • Kuongorora Kwenzvimbo -Kuverenga uye kuisirwa kweL uye L' - Chizvarwa chekusaziva (rn) • Data stream management -AES-CTR modhi yakavakirwa kiyi yekuyerera chizvarwa • Asymmetric crypto algorithms -RSA ine modulus kureba kwe1024 (kpubrx) uye 3072 (kpubdcp) bits -RSA-CRT (Chinese Remainder Theorem) ine modulus kureba kwe512 (kprivrx) bits uye exponent kureba kwe512 (kprivrx) bits. • Low-level cryptographic function - Symmetric crypto algorithms • AES-CTR mode ine kiyi yakareba ye128 bits -Hash, MGF uye HMAC algorithms • SHA256 • HMAC-SHA256 • MGF1-SHA256 - Yechokwadi random nhamba jenareta (TRNG) • NIST.SP800-90A inoenderana • Hardware yakavakirwa, yakazara digitaalinen kushandiswa uye non-deterministic random nhamba jenareta

4.1.1. HDCP Pamusoro peHDMI Dhizaini Example Architecture
Iyo HDCP ficha inochengetedza data sezvo data richifambiswa pakati pemidziyo yakabatana kuburikidza neHDMI kana imwe HDCP-yakachengetedzwa dijitari madhijitari.
Iwo HDCP-akachengetedzwa masisitimu anosanganisira matatu marudzi emidziyo:

4. HDCP Pamusoro peHDMI 2.0/2.1 Dhizaini Example
683156 | 2022.12.27
• Nzvimbo (TX)
• Singi (RX)
• Vanodzokorora
Iyi dhizaini example inoratidza iyo HDCP sisitimu mune inodzokorora mudziyo kwainogamuchira data, decrypts, yobva yanyora zvakare data, uye pakupedzisira inotumirazve data. Vanodzokorora vane zvese zveHDMI zvemukati uye zvinobuda. Iyo inosimudzira iyo FIFO buffers kuita yakananga HDMI vhidhiyo rukova kupfuura-pakati peiyo HDMI kunyura uye sosi. Inogona kuita mamwe masaini kugadzirisa, sekushandura mavhidhiyo kuita yepamusoro resolution fomati nekutsiva iyo FIFO buffers neVhidhiyo uye Image Processing (VIP) Suite IP cores.

Mufananidzo 29. HDCP Pamusoro peHDMI Dhizaini Exampuye Block Diagram

Tsanangudzo dzinotevera nezve mavakirwo eiyo dhizaini exampinoenderana neHDCP pamusoro peHDMI dhizaini example block diagram. Kana SUPPORT FRL = 1 kana
SUPPORT HDCP KEY MANAGEMENT = 1, iyo dhizaini exampLe hierarchy yakati siyanei neFigure 29 iri papeji 95 asi aripasi HDCP mabasa anoramba ari iwo.
zvakafanana.

1. Iyo HDCP1x uye HDCP2x iIPs inowanikwa kuburikidza neHDMI Intel FPGA IP parameter mupepeti. Paunenge uchigadzirisa iyo HDMI IP muparameter mupepeti, unogona kugonesa uye kusanganisira ingave HDCP1x kana HDCP2x kana ese maIP sechikamu cheiyo subsystem. Iine ese ari maviri HDCP IPs akagoneswa, iyo HDMI IP inozvigadzirisa pachayo mucascade topology uko HDCP2x uye HDCP1x IPs dzakabatana kumashure-kumashure.
   • Iyo HDCP egress interface yeHDMI TX inotumira ine encrypted audio video data.
   • Iyo data isina kuvharidzirwa inovharwa neiyo inoshanda HDCP block uye inodzoserwa muHDMI TX pamusoro peHDCP Ingress interface yekutapurirana pamusoro peiyo link.
   • Iyo CPU subsystem seyeyechokwadi master controller inova nechokwadi chekuti imwe chete yeHDCP TX IPs inoshanda chero nguva uye imwe yacho isingaiti.
   • Saizvozvowo, HDCP RX inobvisawo data yakagamuchirwa pamusoro pekubatanidza kubva kune kunze HDCP TX.
2. Iwe unofanirwa kuronga iyo HDCP IPs ine Digital Content Dziviriro (DCP) yakapihwa makiyi ekugadzira. Isa makiyi anotevera:
   Tafura 54. DCP-yakabudiswa Makiyi ekugadzira
   

   HDCP	TX / RX	Keys
   HDCP2x	TX	16 bytes: Global Constant (lc128)
   	RX	• 16 bytes (zvakafanana neTX): Global Constant (lc128) • 320 bytes: RSA Private Key (kprivrx) • 522 bytes: RSA Public Key Certificate (certrx)
   HDCP1x	TX	• 5 bytes: TX Key Selection Vector (Aksv) • 280 bytes: TX Private Device Keys (Akeys)
   	RX	• 5 bytes: RX Key Selection Vector (Bksv) • 280 bytes: RX Private Device Keys (Bkeys)

   Iyo yakagadzirwa example inoshandisa ndangariro dzakakosha seyakapusa mbiri-chiteshi, mbiri-wachi synchronous RAM. Kune diki kiyi saizi senge HDCP2x TX, iyo IP inoshandisa kiyi yekuyeuka ichishandisa marejista mune yenguva dzose logic.
   Ongorora: Intel haipe makiyi ekugadzira HDCP ane dhizaini example kana Intel FPGA IPs chero mamiriro ezvinhu. Kushandisa HDCP IPs kana dhizaini exampuye, iwe unofanirwa kuve muchengeti weHDCP uye uwane makiyi ekugadzira zvakananga kubva kuDigital Content Protection LLC (DCP).
   Kumhanyisa dhizaini example, iwe unogona kugadzirisa kiyi yekuyeuka files panguva yekubatanidza kusanganisa makiyi ekugadzira kana kushandisa logic blocks kuti uverenge zvakachengeteka makiyi ekugadzira kubva kune yekunze chengetedzo mudziyo uye woanyora mumakiyi ndangariro panguva yekumhanya.

3. Unogona kuvharisa mabasa ekriptographic anoitwa muHDCP2x IP chero frequency anosvika 200 MHz. Kuwanda kwewachi iyi kunoratidza kuti inokurumidza sei
   HDCP2x yechokwadi inoshanda. Iwe unogona kusarudza kugovera iyo 100 MHz wachi inoshandiswa kuNios II processor asi iyo authentication latency yaizopetwa kaviri kana ichienzaniswa nekushandisa 200 MHz wachi.
4. Hukoshi hunofanirwa kuchinjana pakati peHDCP TX neHDCP RX dzinotaurirwa pamusoro peHDMI DDC interface (I2 C serial interface) yeHDCP-
   yakachengetedzwa interface. Iyo HDCP RX inofanirwa kuratidza mudziyo une musoro paI2C bhazi kune yega yega link yainotsigira. Iyo I2C muranda inodzokororwa kune HDCP port ine mudziyo kero ye0x74. Iyo inotyaira iyo HDCP rejista port (Avalon-MM) yeese ari maviri HDCP2x uye HDCP1x RX IPs.
5. Iyo HDMI TX inoshandisa iyo IC master kuverenga iyo EDID kubva kuRX uye kuendesa iyo SCDC data inodiwa kuHDMI 2.0 kushanda kuRX. Iyo imwechete I2C tenzi inofambiswa neNios II processor inoshandiswawo kuendesa iyo HDCP mameseji pakati peTX neRX. Iyo I2C tenzi yakanyudzwa muCPU subsystem.
6. Iyo Nios II processor inoita satenzi mune yechokwadi protocol uye inotyaira kutonga uye mamiriro marejista (Avalon-MM) eese ari maviri HDCP2x uye HDCP1x TX.
   IPs. Iwo madhiraivha esoftware anoshandisa iyo yechokwadi protocol mamiriro muchina unosanganisira chitupa siginecha verification, master kiyi yekutsinhana, cheki yenzvimbo, sesheni kiyi kuchinjanisa, pairing, yekubatanidza kutendeseka cheki (HDCP1x), uye humbowo nevanodzokorora, senge topology ruzivo kuparadzira uye rwizi manejimendi kuparadzira ruzivo. Iwo madhiraivha esoftware haaite chero ye cryptographic mabasa anodiwa neiyo protocol yekusimbisa. Pane kudaro, iyo HDCP IP hardware inoshandisa ese cryptographic mabasa ekuona kuti hapana zvakavanzika zvakakosha zvinogona kuwanikwa.
   7. Muchiratidziro chechokwadi chekudzokorora apo kuparadzira ruzivo rwetopology kumusoro kwemvura kunodiwa, Nios II processor inotyaira Repeater Message Port (Avalon-MM) yezvose zviri zviviri HDCP2x uye HDCP1x RX IPs. Iyo Nios II processor inobvisa iyo RX REPEATER bit kusvika 0 kana yaona yakabatana pasi pasi haina HDCPinokwanisa kana kana pasina kudzika kwakabatana. Pasina kubatana kwakadzika, iyo RX system ikozvino yave yekupedzisira-yekugashira, pane inodzokorora. Sezvineiwo, iyo Nios II processor inoisa iyo RX REPEATER bit kusvika 1 pakuona iyo yakadzika iri HDCP-inokwanisa.

4.2. Nios II processor Kuyerera kweSoftware
Iyo Nios II software inoyerera inosanganisira iyo HDCP yechokwadi yekutonga pamusoro peHDMI application.
Mufananidzo 30. Nios II Processor Software Flowchart

1. Iyo Nios II software inotanga nekugadzirisa zvakare HDMI TX PLL, TX transceiver PHY, I2C tenzi uye yekunze TI retimer.
2. Iyo Nios II software polls periodic rate yekuona chiratidzo chakasimba kubva kuRX rate yekuona dunhu kuona kana vhidhiyo kugadziriswa kwachinja uye kana TX reconfiguration ichidikanwa. Iyo software zvakare inovhota iyo TX inopisa-plug yekuona siginecha kuona kana TX inopisa-plug chiitiko chakaitika.
3. Kana chiratidzo chakakodzera chakagamuchirwa kubva kuRX chiyero chekuona dunhu, iyo Nios II software inoverenga SCDC uye wachi kudzika kukosha kubva kuHDMI RX uye inotora wachi frequency bhendi zvichibva pachiyero chaonekwa kuti uone kana HDMI TX PLL uye transceiver PHY reconfiguration inodiwa. Kana TX reconfiguration ichidikanwa, iyo Nios II software inoraira I2C tenzi kutumira iyo SCDC kukosha kune yekunze RX. Inobva yaraira kugadzirisa zvakare HDMI TX PLL uye TX transceiver
   PHY, inoteverwa nekugadzirisa zvakare mudziyo, uye kuseta zvakare kutevedzana. Kana chiyero chikasachinja, kana TX reconfiguration kana HDCP re-athentication inodiwa.
4. Kana chiitiko cheTX chinopisa-plug chakaitika, software yeNios II inoraira tenzi weI2C kutumira kukosha kweSCDC kune yekunze RX, wobva waverenga EDID kubva kuRX.
   uye gadziridza yemukati EDID RAM. Iyo software inozoparadzira iyo EDID ruzivo kusvika kumusoro.
5. Iyo Nios II software inotanga iyo HDCP chiitiko nekuraira iyo I2C tenzi kuti averenge offset 0x50 kubva kunze RX kuti aone kana iyo yakadzika iri HDCP-inokwanisa, kana
   zvimwe:
   • Kana kukosha kweHDCP2Version kuri 1, kudzika kuri HDCP2xcaable.
   • Kana kukosha kwadzoserwa kwese 0x50 kuverenga kuri 0's, zasi kuri kugona HDCP1x.
   • Kana kukosha kwadzoserwa kwese 0x50 kuverenga kuri 1, kudzika kwakadzika hakugone HDCP kana kusashanda.
   • Kana iyo yakadzika isati yambove HDCP-inokwanisa kana isingashande asi parizvino inokwanisa HDCP, software inoseta iyo REPEATER bit yeinodzokorora kumusoro (RX) kuenda ku1 kuratidza kuti RX yava kudzokorora.
   • Kana kudzika kwacho kwaimbove neHDCP-inokwanisa asi parizvino isiri HDCPcatable kana kusashanda, software inoisa REPEATER bit ye0 kuratidza kuti RX yava magumo ekugamuchira.
6. Iyo software inotanga HDCP2x yekusimbisa protocol iyo inosanganisira RX chitupa siginecha verification, master kiyi yekutsinhana, cheki yenzvimbo, chikamu chekiyi kuchinjanisa, kubatanidza, kuvimbiswa nevanozvidzokorora senge topology ruzivo rwekuparadzira.
7. Kana iri mumamiriro echokwadi, iyo Nios II software inoraira I2C tenzi kuti avhote iyo RxStatus rejista kubva kunze kweRX, uye kana software ikaona iyo REAUTH_REQ bit yaiswa, inotanga kusimbiswa zvakare uye inodzima TX encryption.
8. Kana iyo yakadzika ichidzokorodza uye iyo READY bit yeRxStatus register yakaiswa kune 1, izvi zvinowanzoratidza iyo yakadzika topology yachinja. Saka, iyo Nios II software inoraira iyo I2C tenzi kuti iverenge ReceiverID_List kubva pasi pasi uye simbisa iyo rondedzero. Kana iyo rondedzero iriko uye pasina chikanganiso chetopology chinoonekwa, software inoenda kune Content Stream Management module. Zvikasadaro, inotangazve kusimbiswa uye inodzima TX encryption.
9. Iyo Nios II software inogadzirira iyo ReceiverID_List uye RxInfo kukosha uye yobva yanyora kuAvalon-MM Repeater Mharidzo chiteshi cheanodzokorora kumusoro (RX). Iyo RX inobva yaparadzira rondedzero kune yekunze TX (kumusoro).
10. Kusimbisa kwapera panguva ino. Iyo software inogonesa TX encryption.
11. Iyo software inotanga HDCP1x yekusimbisa protocol inosanganisira kiyi kuchinjanisa uye kutendeseka nevadzokorodza.
12. Iyo Nios II software inoita yekubatanidza kutendeseka cheki nekuverenga uye kuenzanisa Ri' uye Ri kubva kunze RX (yakadzika) uye HDCP1x TX zvichiteerana. Kana hunhu
    hazvienderane, izvi zvinoratidza kurasikirwa kwekuyananisa uye software inotanga kusimbiswa zvakare uye inodzima TX encryption.
13. Kana iyo yakadzika iri inodzokorora uye iyo READY bit yeBcaps register yakaiswa ku1, izvi zvinowanzoratidza kuti iyo yakadzika topology yachinja. Saka, iyo Nios II software inoraira iyo I2C tenzi kuti iverenge iyo KSV runyorwa kukosha kubva pasi pemvura uye simbisa iyo rondedzero. Kana iyo rondedzero iriko uye pasina topology kukanganisa kwaonekwa, software inogadzirira iyo KSV runyorwa uye Bstatus kukosha uye inonyorera kuAvalon-MM Repeater Mharidzo chiteshi cheanodzokorora kumusoro (RX). Iyo RX inobva yaparadzira rondedzero kune yekunze TX (kumusoro). Zvikasadaro, inotanga kusimbiswa zvakare uye inodzima TX encryption.

4.3. Design Walkthrough
Kumisikidza uye kumhanya iyo HDCP pamusoro peHDMI dhizaini example rine zvishanu stages.

1. Gadzirisa hardware.
2. Gadzira dhizaini.
3. Rongedza iyo HDCP kiyi ndangariro files kuisa makiyi ako ekugadzira HDCP.
   a. Chengetedza akajeka HDCP makiyi ekugadzira muFPGA (Support HDCP Key Management = 0)
   b. Chengetedza makiyi ekugadzira akavharidzirwa eHDCP mune yekunze flash memory kana EEPROM (Support HDCP Key Management = 1)
4. Gadzira dhizaini.
5. View zvabuda.

4.3.1. Gadzirisa Hardware
Wokutanga stage yekuratidzira ndeyekumisikidza hardware.
Kana SUPPORT FRL = 0, tevera matanho aya kumisikidza Hardware yekuratidzira:

1. Batanidza Bitec HDMI 2.0 FMC mwanasikana kadhi (revision 11) kune Arria 10 GX yekuvandudza kit paFMC port B.
2. Batanidza iyo Arria 10 GX yekuvandudza kit kuPC yako uchishandisa USB tambo.
3. Batanidza tambo yeHDMI kubva paHDMI RX yekubatanidza paBitec HDMI 2.0 FMC kadhi remwanasikana kune HDCP-inogonesa HDMI mudziyo, senge graphic kadhi ine HDMI inobuda.
4. Batanidza imwe tambo yeHDMI kubva paHDMI TX yekubatanidza paBitec HDMI 2.0 FMC kadhi remwanasikana kune HDCP-inogonesa HDMI mudziyo, seterevhizheni ine HDMI yekupinda.

Kana SUPPORT FRL = 1, tevera matanho aya kumisikidza Hardware ye kuratidzira:

1. Batanidza Bitec HDMI 2.1 FMC mwanasikana kadhi (Revision 9) kune Arria 10 GX yekuvandudza kit paFMC port B.
2. Batanidza iyo Arria 10 GX yekuvandudza kit kuPC yako uchishandisa USB tambo.
3. Batanidza HDMI 2.1 Chikamu 3 tambo kubva kuHDMI RX yekubatanidza paBitec HDMI 2.1 FMC kadhi remwanasikana kune HDCP-inogonesa HDMI 2.1 sosi, senge Quantum Data 980 48G Jenareta.
4. Batanidza imwe HDMI 2.1 Chikamu 3 tambo kubva kuHDMI TX yekubatanidza paBitec HDMI 2.1 FMC kadhi remwanasikana kune HDCP-inogonesa HDMI 2.1 sink, senge.
   Quantum Data 980 48G Analyzer.

4.3.2. Gadzira Dhizaini
Mushure mekugadzira iyo hardware, iwe unofanirwa kugadzira iyo dhizaini.
Usati watanga, ita shuwa kuisa HDCP chimiro muIntel Quartus Prime Pro Edition software.

1. Dzvanya Zvishandiso ➤ IP Catalog, uye sarudza Intel Arria 10 semhuri yakanangwa mudziyo.
   Cherechedza: Iyo HDCP dhizaini example inotsigira chete Intel Arria 10 uye Intel Stratix® 10 zvishandiso.
2. Mune IP Catalog, tsvaga uye tinya kaviri HDMI Intel FPGA IP. Iyo Itsva IP yekusiyana hwindo inooneka.
3. Rondedzera zita repamusoro-soro kune yako tsika IP musiyano. Iyo parameter mupepeti inochengetedza iyo IP kusiyanisa marongero mune a file zita .qsys kana .ip.
4. Dzvanya OK. Iyo parameter editor inooneka.
5. PaI IP tab, gadzira maparamita anodiwa ezvose zviri zviviri TX uye RX.
6. Batidza Tsigiro HDCP 1.4 kana Tsigira HDCP 2.3 paramende kuti igadzire iyo HDCP dhizaini example.
7. Batidza Rutsigiro HDCP Key Management parameter kana iwe uchida kuchengeta HDCP kiyi yekugadzira mune yakavharidzirwa fomati mune yekunze flash memory kana EEPROM. Zvikasadaro, dzima Rutsigiro HDCP Kiyi Management paramende kuchengetedza kiyi yekugadzira HDCP mune yakajeka fomati muFPGA.
8. Pamusoro peDesign Exampuye tab, sarudza Arria 10 HDMI RX-TX Retransmit.
9. Sarudza Synthesis kugadzira iyo hardware dhizaini example.
10. For Gadzira File Fomati, sarudza Verilog kana VHDL.
11. YeTarget Development Kit, sarudza Arria 10 GX FPGA Development Kit. Kana ukasarudza kit yekuvandudza, ipapo iyo yakanangwa mudziyo (yakasarudzwa mudanho 4) inochinja kuti ienderane nemudziyo uri pakiti yekuvandudza. YeArria 10 GX FPGA Development Kit, iyo default mudziyo ndeye 10AX115S2F45I1SG.
12. Dzvanya Gadzira Example Dhizaini kugadzira iyo purojekiti files uye software Inogoneka uye Inobatanidza Format (ELF) hurongwa file.

4.3.3. Sanganisira HDCP Kugadzira Makiyi
4.3.3.1. Chengetedza akajeka HDCP makiyi ekugadzira muFPGA (Support HDCP Key Management = 0)
Mushure mekugadzira dhizaini, gadzirisa iyo HDCP kiyi yekuyeuka files kuisa makiyi ako ekugadzira.
Kuti ubatanidze makiyi ekugadzira, tevera matanho aya.

1. Tsvaga iyo inotevera kiyi memory files muri /rtl/hdcp/dhairekitori:
   • hdcp2x_tx_kmem.v
   • hdcp2x_rx_kmem.v
   • hdcp1x_tx_kmem.v
   • hdcp1x_rx_kmem.v
2. Vhura iyo hdcp2x_rx_kmem.v file uye tsvaga yakafanotsanangurwa facsimile kiyi R1 yeReceiver Public Certificate uye RX Private Key uye Global Constant sezvakaratidzwa mune yekareampzvishoma pazasi.
   Mufananidzo 31. Wire Array yeFacsimile Key R1 yeReceiver Public Certificate
   Mufananidzo 32. Wire Array yeFacsimile Key R1 yeRX Private Key uye Global Constant
   
3. Tsvaga chinobatirira makiyi ekugadzira uye wotsiva neyako makiyi ekugadzira mune yavo akateedzana waya array muhombe endian fomati.
   Mufananidzo 33. Wire Array yeHDCP Production Keys (Placeholder)
   
4. Dzokorora Nhanho 3 kune mamwe ese makiyi ndangariro files. Kana wapedza kusanganisira makiyi ako ekugadzira mundangariro dzese kiyi files, ita shuwa kuti USE_FACSIMILE paramende yakaiswa kune 0 pane dhizaini example top level file (a10_hdmi2_demo.v)

4.3.3.1.1. HDCP Kiyi Mepu kubva kuDCP Kiyi Files
Zvikamu zvinotevera zvinotsanangura mepu yemakiyi ekugadzira eHDCP akachengetwa mukiyi yeDCP files muwaya array yeHDCP kmem files.
4.3.3.1.2. hdcp1x_tx_kmem.v uye hdcp1x_rx_kmem.v files
Yehdcp1x_tx_kmem.v uye hdcp1x_rx_kmem.v files

• Vaviri ava files vari kugovera maitiro akafanana.
• Kuti uone kiyi chaiyo yeHDCP1 TX DCP file yehdcp1x_tx_kmem.v, ita shuwa kuti mabhayithi mana ekutanga e file "0x01, 0x00, 0x00, 0x00".
• Kuti uone chaiyo HDCP1 RX DCP kiyi file yehdcp1x_rx_kmem.v, ita shuwa kuti mabhayithi mana ekutanga e file "0x02, 0x00, 0x00, 0x00".
• Makiyi ari mukiyi yeDCP files ari mudiki-endian fomati. Kushandisa mu kmem files, iwe unofanirwa kuvashandura kuita hombe-endian.

Mufananidzo 34. Byte mapping kubva kuHDCP1 TX DCP kiyi file kupinda hdcp1x_tx_kmem.v

Cherechedza:
Iyo byte nhamba inoratidzwa mune pazasi fomati:

• Saizi yekiyi mumabhaiti * kiyi nhamba + byte nhamba mumutsara wazvino + inogara ichibvisa + mutsara saizi mumabhayithi * mutsara nhamba.
• 308*n inoratidza kuti kiyi yega yega seti ine 308 bytes.
• 7*y inoratidza kuti mutsara wega wega une 7 bytes.

Mufananidzo 35. HDCP1 TX DCP kiyi file kuzadza nejunk values

Mufananidzo 36. Wire Arrays of hdcp1x_tx_kmem.v
Example ye hdcp1x_tx_kmem.v uye kuti waya wayo anoronga sei mepu kune yekareampye HDCP1 TX DCP kiyi file muMufananidzo 35 uri papeji 105.

4.3.3.1.3. hdcp2x_rx_kmem.v file
Zvehdcp2x_rx_kmem.v file

• Kuti uone chaiyo HDCP2 RX DCP kiyi file yehdcp2x_rx_kmem.v, ita shuwa kuti mabhayithi mana ekutanga e file "0x00, 0x00, 0x00, 0x02".
• Makiyi ari mukiyi yeDCP files ari mudiki-endian fomati.

Mufananidzo 37. Byte mapping kubva HDCP2 RX DCP kiyi file kupinda hdcp2x_rx_kmem.v
Mufananidzo uri pazasi unoratidza iyo chaiyo byte mepu kubva HDCP2 RX DCP kiyi file kupinda hdcp2x_rx_kmem.v.

Cherechedza:
Iyo byte nhamba inoratidzwa mune pazasi fomati:

• Saizi yekiyi mumabhaiti * kiyi nhamba + byte nhamba mumutsara wazvino + inogara ichibvisa + mutsara saizi mumabhayithi * mutsara nhamba.
• 862*n inoratidza kuti kiyi yega yega seti ine 862 bytes.
• 16*y inoratidza kuti mutsara wega wega une 16 bytes. Pane musiyano mu cert_rx_prod apo ROW 32 ine gumi chete.

Mufananidzo 38. HDCP2 RX DCP kiyi file kuzadza nejunk values

Mufananidzo 39. Wire Arrays of hdcp2x_rx_kmem.v
Iyi nhamba inoratidza waya arrays ehdcp2x_rx_kmem.v (cert_rx_prod, kprivrx_qinv_prod, uye lc128_prod) mepu kune yekareampye HDCP2 RX DCP kiyi file in
Mufananidzo 38 papeji 108.

4.3.3.1.4. hdcp2x_tx_kmem.v file
Zvehdcp2x_tx_kmem.v file:

• Kuti uone kiyi chaiyo yeHDCP2 TX DCP file yehdcp2x_tx_kmem.v, ita shuwa kuti mabhayithi mana ekutanga e file "0x00, 0x00, 0x00, 0x01".
• Makiyi ari mukiyi yeDCP files ari mudiki-endian fomati.
• Neimwe nzira, unogona kuisa lc128_prod kubva kuhdcp2x_rx_kmem.v zvakananga muhdcp2x_tx_kmem.v. Makiyi anogovera maitiro akafanana.

Mufananidzo 40. Wire array of hdcp2x_tx_kmem.v
Iyi nhamba inoratidza chaiyo byte mepu kubva HDCP2 TX DCP kiyi file kupinda hdcp2x_tx_kmem.v.

4.3.3.2. Chengetedza encrypted HDCP makiyi ekugadzira mune yekunze flash memory kana EEPROM (Support HDCP Key Management = 1)
Mufananidzo 41. High Level Overview yeHDCP Key Management

Kana Tsigiro HDCP Kiyi Management paramende ikavhurwa, iwe unobata kutonga kweHDCP yekugadzira kiyi encryption uchishandisa kiyi encryption software utility (KEYENC) uye kiyi programmer dhizaini inopihwa neIntel. Iwe unofanirwa kupa HDCP makiyi ekugadzira uye 128 bits HDCP kuchengetedza kiyi. Iyo HDCP yekudzivirira kiyi
encrypts kiyi yekugadzira HDCP uye chengetedza kiyi mune yekunze flash memory (yeexample, EEPROM) paHDMI mwanasikana kadhi.
Batidza Rutsigiro HDCP Kiyi Management paramende uye kiyi yedecryption ficha (KEYDEC) inowanikwa muHDCP IP cores. Iyo yakafanana HDCP kudzivirira
kiyi inofanirwa kushandiswa muKEYDEC kutora makiyi ekugadzira HDCP panguva yekumhanya yekugadzira injini. KEYENC uye KEYDEC inotsigira Atmel AT24CS32 32-Kbit serial EEPROM, Atmel AT24C16A 16-Kbit serial EEPROM uye inowirirana I2C EEPROM zvishandiso zvine kanenge 16-Kbit rom saizi.

Cherechedza:

1. YeHDMI 2.0 FMC mwanasikana kadhi Revision 11, ita shuwa kuti EEPROM pamwanasikana kadhi iri Atmel AT24CS32. Kune maviri akasiyana saizi eEEPROM anoshandiswa paBitec HDMI 2.0 FMC mwanasikana kadhi Revision 11.
2. Dai wakamboshandisa KEYENC encrypt makiyi ekugadzira HDCP uye wakabatidza Tsigiro HDCP Key Management muvhezheni 21.2 kana yapfuura, unofanirwa kunyora zvakare makiyi ekugadzira HDCP uchishandisa KEYENC software yekushandisa uye gadzirazve HDCP IPs kubva muvhezheni 21.3.
   zvichienda mberi.

4.3.3.2.1. Intel KEYENC
KEYENC ndeye command line software utility iyo Intel inoshandisa encrypt iyo HDCP makiyi ekugadzira ane 128 bits HDCP yekudzivirira kiyi yaunopa. KEYENC inoburitsa yakavharidzirwa HDCP makiyi ekugadzira muhex kana bhini kana musoro file format. KEYENC zvakare inogadzira mif file ine yako yakapihwa 128 bits HDCP kiyi yekudzivirira. KEYDEC
inoda mf file.

System Chinodiwa:

1. x86 64-bit muchina une Windows 10 OS
2. Visual C++ Redistributable package yeVisual Studio 2019(x64)

Cherechedza:
Unofanira kuisa Microsoft Visual C++ yeVS 2019. Unogona kutarisa kana Visual C++ inogona kugoverwa zvakare yakaiswa kubva kuWindows ➤ Control Panel ➤ Zvirongwa uye Zvimiro. Kana Microsoft Visual C++ yakaiswa, unogona kuona Visual C++ xxxx
Redistributable (x64). Zvikasadaro, unogona kudhawunirodha uye kuisa Visual C ++
Redistributable kubva kuMicrosoft website. Tarisa kune inoenderana ruzivo rweiyo download link.

Tafura 55. KEYENC Command Line Options

Command Line Options	Nharo/ Tsananguro
-k	<HDCP protection key file> Text file ine chete 128 bits HDCP yekudzivirira kiyi muhexadecimal. Example: f0f1f2f3f4f5f6f7f8f9fafbfcfdfeff
-hdcp1tx	<HDCP 1.4 TX production keys file> HDCP 1.4 transmitter kugadzira makiyi file kubva kuDCP (.bin file)
-hdcp1rx	<HDCP 1.4 RX production keys file> HDCP 1.4 inogamuchira makiyi ekugadzira file kubva kuDCP (.bin file)
-hdcp2tx	<HDCP 2.3 TX production keys file> HDCP 2.3 transmitter kugadzira makiyi file kubva kuDCP (.bin file)
-hdcp2rx	<HDCP 2.3 RX production keys file> HDCP 2.3 inogamuchira makiyi ekugadzira file kubva kuDCP (.bin file)
-hdcp1txkeys	Taura kiyi yemhando yezvakasarudzwa (.bin) files -hdcp1txkeys|hdcp1rxkeys|hdcp2rxkeys nm kupi n = kiyi yekutanga (1 kana > 1) m = kiyi yekupedzisira (n kana > n) Example: Sarudza 1 kusvika ku1000 makiyi kubva kune yega yega HDCP 1.4 TX, HDCP 1.4 RX uye HCDP 2.3 RX makiyi ekugadzira file. "-hdcp1txkeys 1-1000 -hdcp1rxkeys 1-1000 -hdcp2rxkeys 1-1000"
-hdcp1rxkeys
-hdcp2rxkeys
akaenderera…

Command Line Options	Nharo/ Tsananguro
	Cherechedza: 1. Kana usiri kushandisa chero makiyi ekugadzira HDCP file, hauzodi HDCP kiyi renji. Kana usiri kushandisa nharo mumutsara wekuraira, iyo default kiyi renji ndeye 0. 2. Unogonawo kusarudza indekisi yakasiyana yemakiyi eHDCP makiyi ekugadzira file. Zvisinei, nhamba yemakiyi inofanira kufanana nesarudzo dzakasarudzwa. Example: Sarudza akasiyana 100 makiyi Sarudza makiyi zana ekutanga kubva kuHDCP 100 TX makiyi ekugadzira file "-hdcp1txkeys 1-100" Sarudza makiyi mazana matatu kusvika mazana mana eHDCP 300 RX makiyi ekugadzira file "-hdcp1rxkeys 300-400" Sarudza makiyi mazana matatu kusvika mazana mana eHDCP 600 RX makiyi ekugadzira file "-hdcp2rxkeys 600-700"
-o	Output file format . Default ndeye hex file. Gadzira yakavharidzirwa HDCP makiyi ekugadzira mubinary file fomati: -o bin Gadzira yakavharidzirwa HDCP makiyi ekugadzira muhex file fomati: -o hex Gadzira yakavharidzirwa HDCP makiyi ekugadzira mumusoro file fomati: -o
– cheki-makiyi	Dhinda nhamba yemakiyi anowanikwa mukuisa files. Example:
	keync.exe -hdcp1tx file> -hdcp1rx <HDCP 1.4 RX production keys file> -hdcp2tx file> -hdcp2rx file> -check-makiyi
	Cherechedza: shandisa parameter -cheki-makiyi pamagumo emutsara wekuraira sezvataurwa pamusoro apaample.
-shanduro	Dhinda KEYENC vhezheni nhamba

Unogona kusarudza HDCP 1.4 uye/kana HDCP 2.3 makiyi ekugadzira encrypt. For example, kushandisa chete HDCP 2.3 RX makiyi ekugadzira encrypt, shandisa chete -hdcp2rx
<HDCP 2.3 RX production keys file> -hdcp2rxkeys mu command line parameters.
Tafura 56. KEYENC Common Error Message Guideline

Error Message	Guideline
ERROR: HDCP kuchengetedza kiyi file vasipo	Kushaikwa mutsara wemirairo parameter -k file>
ERROR: kiyi inofanira kuva 32 hex manhamba (eg f0f1f2f3f4f5f6f7f8f9fafbfcfdfeff)	HDCP kuchengetedza kiyi file inofanira kunge iine chete HDCP kiyi yekudzivirira mumakumi matatu nemaviri hexadecimal manhamba.
ERROR: Ndokumbirawo utsanangure makiyi aya	Kiyi renji haina kutaurwa kune yakapihwa makiyi ekugadzira HDCP makiyi file.
ERROR: Kiyi yakasiyana-siyana	Kiyi yakasiyana-siyana yakatsanangurwa -hdcp1txkeys kana -hdcp1rxkeys kana -hdcp2rxkeys haina kururama.
ERROR: haigone kugadziraFilezita>	Tarisa mvumo yefolda kubva ku keyenc.exe iri kuitwa.
ERROR: -hdcp1txkeys kuisa handiyo	Kupinza kiyi yemhando yemhando yeHDCP 1.4 TX makiyi ekugadzira haashande. Fomati chaiyo ndeye "-hdcp1txkeys nm" apo n > = 1, m >= n.
ERROR: -hdcp1rxkeys mapindiro haashande	Kupinza kiyi yemhando yemhando yeHDCP 1.4 RX makiyi ekugadzira haashande. Fomati chaiyo ndeye "-hdcp1rxkeys nm" apo n > = 1, m >= n.
ERROR: -hdcp2rxkeys mapindiro haashande	Kupinza kiyi yemhando yemhando yeHDCP 2.3 RX makiyi ekugadzira haashande. Fomati chaiyo ndeye "-hdcp2rxkeys nm" apo n > = 1, m >= n.
akaenderera…

Error Message	Guideline
ERROR: Haikodzeri file <filezita>	Makiyi ekugadzira HDCP haashandi file.
ERROR: file type inoshaikwa ye -o sarudzo	Command line parameter isipo ye -o .
ERROR: haisiriyo filezita -filezita>	<filezita> harina basa, ndapota shandisa iro rinoshanda filezita risina mavara anokosha.

Encrypt Ingle Key yeIngle EEPROM
Mhanya unotevera mutsara wekuraira kubva kuWindows command kukurumidza kunyora kiyi imwechete yeHDCP 1.4 TX, HDCP 1.4 RX, HDCP 2.3 TX uye HDCP 2.3 RX ine zvinobuda file chimiro chemusoro file yeEEPROM imwe chete:
keync.exe -k file> -hdcp1tx file> -hdcp1rx file> -hdcp2tx file> -hdcp2rx file> -hdcp1txkeys 1-1 -hdcp1rxkeys 1-1 -hdcp2rxkeys 1-1 -oh

Encrypt N Keys dzeN EEPROMs
Mhanya unotevera mutsara wekuraira kubva kuWindows command kukurumidza kunyora N makiyi (kutanga kubva kiyi 1) yeHDCP 1.4 TX, HDCP 1.4 RX, HDCP 2.3 TX uye HDCP 2.3 RX ine zvinobuda file chimiro che hex file zveN EEPROMs:
keync.exe -k file> -hdcp1tx file> -hdcp1rx file> -hdcp2tx file> -hdcp2rx file> -hdcp1txkeys 1 -hdcp1rxkeys 1- -hdcp2rxkeys 1- -o hex apo N iri > = 1 uye inofanira kufanana nezvose zvingasarudzwa.

Related Information
Microsoft Visual C++ yeVisual Studio 2019
Inopa Microsoft Visual C++ x86 redistributable package (vc_redist.x86.exe) yekudhawunirodha. Kana chinongedzo ichichinja, Intel inokurudzira kuti utsvage "Visual C++ redistributable" kubva kuMicrosoft yekutsvaga injini.

4.3.3.2.2. Key Programmer
Kuronga makiyi ekugadzira akavharidzirwa eHDCP paEEPROM, tevera matanho aya:

1. Kopa kiyi programmer dhizaini files kubva munzira inotevera kuenda kune yako dhairekitori rekushanda: /hdcp2x/hw_demo/key_programmer/
2. Kopira musoro wesoftware file (hdcp_kiyi .h) yakagadzirwa kubva kuKEYENC software utility (chikamu Encrypt Single Key for Single EEPROM papeji 113 ) kune software/key_programmer_src/ dhairekitori uye uipe zita rekuti hdcp_key.h.
3. Mhanya ./runall.tcl. Ichi chinyorwa chinoita mirairo inotevera:
   • Gadzira IP catalog files
   • Gadzira Platform Designer system
   • Gadzira chirongwa cheIntel Quartus Prime
   • Gadzira software workspace uye kuvaka software
   • Itai kuunganidza kwakazara
4. Dhawunirodha iyo Software Object File (.sof) kuFPGA kuronga makiyi ekugadzira akavharidzirwa eHDCP paEEPROM.

Gadzira iyo Stratix 10 HDMI RX-TX Retransmit dhizaini example neRutsigiro HDCP 2.3 uye Tsigira HDCP 1.4 paramita yakabatidzwa, wobva watevera danho rinotevera kuti ubatanidze kiyi yekudzivirira yeHDCP.

• Kopa iyo mif file (hdcp_kmem.mif) inogadzirwa kubva kuKEYENC software utility (chikamu Encrypt Single Key for Single EEPROM papeji 113) kune iyo /quartus/hdcp/dhairekitori.

4.3.4. Gadzira Dhizaini
Mushure mekuisa makiyi ako ega ega HDCP ekugadzira muFPGA kana kuronga akavharidzirwa HDCP makiyi ekugadzira kuEEPROM, iwe unogona ikozvino kuunganidza dhizaini.

1. Tangisa iyo Intel Quartus Prime Pro Edition software uye vhura /quartus/a10_hdmi2_demo.qpf.
2. Tinya Kugadzirisa ➤ Tanga Kuunganidza.

4.3.5. View the Results
Pakupera kwekuratidzira, uchakwanisa view mhinduro paHDCPenabled HDMI yekunze singi.
To view mhedzisiro yekuratidzira, tevera matanho aya:

1. Simbisa iyo Intel FPGA bhodhi.
2. Chinja dhairekitori kuti /quartus/.
3. Nyora murairo unotevera paNios II Raira Shell kurodha iyo Software Object File (.sof) kuFPGA. nios2-configure-sof output_files/ .sof
4. Simba kumusoro HDCP-inogonesa HDMI yekunze sosi uye sink (kana usati wadaro). Iyo HDMI yekunze singi inoratidza kubuda kweHDMI yako yekunze sosi.

4.3.5.1. Push Mabhatani uye LED Mabasa
Shandisa mabhatani ekusundidzira uye mabasa eLED pabhodhi kudzora kuratidzira kwako.

Tafura 57. Push Button uye LED Indicators (SUPPORT FRL = 0)

Push Bhatani / LED	Mabasa
cpu_resetn	Dzvanya kamwe kuti uite system reset.
mushandisi_pb[0]	Dzvanya kamwe chete kushandura chiratidzo cheHPD kune yakajairwa HDMI sosi.
mushandisi_pb[1]	• Dzvanya uye bata kuti uraire TX core kutumira DVI encoded siginecha. • Sunungura kutumira HDMI encoded chiratidzo. • Ita shuwa kuti vhidhiyo inouya iri mu8 bpc RGB nzvimbo yemavara.
mushandisi_pb[2]	• Dzvanya uye ubate kuti uraire TX musimboti kuti urege kutumira InfoFrames kubva kumasaini epadivi. • Sunungura kuti utangezve kutumira iyo InfoFrames kubva kumasaini epadivi.
user_led[0]	RX HDMI PLL kukiya mamiriro. • 0: Yakakiyiwa • 1: Yakakiiwa
user_led[1]	RX HDMI musimboti wekukiya mamiriro • 0: Kanenge chiteshi 1 chakavhurwa • 1: All 3 migero kukiyiwa
user_led[2]	RX HDCP1x IP decryption mamiriro. • 0: Kusashanda • 1: Kushanda
user_led[3]	RX HDCP2x IP decryption mamiriro. • 0: Kusashanda • 1: Kushanda
user_led[4]	TX HDMI PLL kukiya mamiriro. • 0: Yakakiyiwa • 1: Yakakiiwa
user_led[5]	TX transceiver PLL kukiya mamiriro. • 0: Yakakiyiwa • 1: Yakakiiwa
user_led[6]	TX HDCP1x IP encryption mamiriro. • 0: Kusashanda • 1: Kushanda
user_led[7]	TX HDCP2x IP encryption mamiriro. • 0: Kusashanda • 1: Kushanda

Tafura 58. Push Button uye LED Indicators (SUPPORT FRL = 1)

Push Bhatani / LED	Mabasa
cpu_resetn	Dzvanya kamwe kuti uite system reset.
user_dipsw	Mushandisi-inotsanangurwa DIP switch yekushandura iyo passthrough modhi. • KUDZIMA (default position) = Passthrough HDMI RX paFPGA inowana iyo EDID kubva kunyura yekunze uye inoiisa kune yekunze sosi iyo yakabatana nayo. • ON = Unogona kudzora RX yepamusoro FRL chiyero kubva kuNios II terminal. Iwo murairo unogadzirisa iyo RX EDID nekushandisa iyo yakanyanya FRL chiyero kukosha. Tarisa kune Kumhanyisa Dhizaini mune Yakasiyana FRL Matengo papeji 33 kuti uwane rumwe ruzivo nezve kuseta akasiyana FRL mareti.
akaenderera…

Push Bhatani / LED	Mabasa
mushandisi_pb[0]	Dzvanya kamwe chete kushandura chiratidzo cheHPD kune yakajairwa HDMI sosi.
mushandisi_pb[1]	Reserved.
mushandisi_pb[2]	Dzvanya kamwe kuti uverenge SCDC marejista kubva padhishi yakabatana neTX yeBitec HDMI 2.1 FMC mwanasikana kadhi. Cherechedza: Kuti ugone kuverenga, unofanirwa kuseta DEBUG_MODE kune 1 musoftware.
user_led_g[0]	RX FRL wachi PLL kukiya mamiriro. • 0: Yakakiyiwa • 1: Yakakiiwa
user_led_g[1]	RX HDMI vhidhiyo kukiya mamiriro. • 0: Yakakiyiwa • 1: Yakakiiwa
user_led_g[2]	RX HDCP1x IP decryption mamiriro. • 0: Kusashanda • 1: Kushanda
user_led_g[3]	RX HDCP2x IP decryption mamiriro. • 0: Kusashanda • 1: Kushanda
user_led_g[4]	TX FRL wachi PLL kukiya mamiriro. • 0: Yakakiyiwa • 1: Yakakiiwa
user_led_g[5]	TX HDMI vhidhiyo kukiya mamiriro. • 0 = Yakakiyiwa • 1 = Yakakiyiwa
user_led_g[6]	TX HDCP1x IP encryption mamiriro. • 0: Kusashanda • 1: Kushanda
user_led_g[7]	TX HDCP2x IP encryption mamiriro. • 0: Kusashanda • 1: Kushanda

4.4. Dziviriro yeEncryption Key Yakamisikidzwa muFPGA Dhizaini
Mazhinji maFPGA magadzirirwo anoita encryption, uye kazhinji pane kudikanwa kwekumisikidza zvakavanzika makiyi muFPGA bitstream. Mumhuri nyowani dzemidziyo, senge Intel Stratix 10 uye Intel Agilex, kune Yakachengeteka Chishandiso Maneja block iyo inogona kupa zvakachengeteka uye kubata aya makiyi akavanzika. Iko kune aya maficha asipo, unogona kuchengetedza zvirimo muFPGA bitstream, kusanganisira chero akamisikidzwa zvakavanzika mushandisi makiyi, ane encryption.
Makiyi emushandisi anofanirwa kuchengetedzwa mukati medhizaini yako nharaunda, uye zvakanaka wedzera kune dhizaini uchishandisa otomatiki yakachengeteka maitiro. Matanho anotevera anoratidza maitiro aungaita maitiro akadaro neIntel Quartus Prime zvishandiso.

1. Gadzira uye shongedza iyo HDL muIntel Quartus Prime munzvimbo isina kuchengetedzeka.
2. Chinja dhizaini kunzvimbo yakachengeteka uye ita otomatiki maitiro ekugadzirisa kiyi yakavanzika. Iyo pa-chip memory yakadzamisa kukosha kwakakosha. Kana kiyi ichivandudzwa, ndangariro yekutanga file (.mif) inogona kuchinja uye "quartus_cdb -update_mif" assembler flow inogona kuchinja HDCP kuchengetedza kiyi pasina kuunganidza zvakare. Iyi nhanho inokurumidza kumhanya uye inochengetedza nguva yekutanga.
3. Iyo Intel Quartus Prime bitstream yobva yanyora nekiyi yeFPGA isati yaendesa iyo yakavharidzirwa bitstream kudzokera kune isina-yakachengeteka nharaunda yekuyedzwa kwekupedzisira uye kutumirwa.

Zvinokurudzirwa kudzima kwese kwekugadzirisa kuwana iyo inogona kudzoreredza kiyi yakavanzika kubva kuFPGA. Iwe unogona kudzima maitiro ekugadzirisa zvachose nekudzima iyo JTAG port, kana kusarudza kudzima uye review kuti hapana debug maficha akadai se-in-system memory edhita kana Signal Tap inogona kudzoreredza kiyi. Tarisa kune AN 556: Kushandisa iyo Dhizaini Chengetedzo Zvimiro muIntel FPGAs kuti uwane rumwe ruzivo nezve kushandisa FPGA kuchengetedza maficha anosanganisira chaiwo matanho ekuti encrypt iyo FPGA bitstream uye gadzirisa sarudzo dzekuchengetedza sekudzima J.TAG access.

Cherechedza:
Iwe unogona kufunga nezveyekuwedzera nhanho yekubfuscation kana encryption neimwe kiyi yekiyi yakavanzika muMIF yekuchengetedza.
Related Information
AN 556: Kushandisa Dhizaini Yekuchengetedza Zvimiro muIntel FPGAs

4.5. Chengetedzo Kufunga
Paunenge uchishandisa chimiro cheHDCP, rangarira zvinotevera kuchengetedzwa.

• Paunenge uchigadzira inodzokorora system, unofanirwa kuvharira vhidhiyo yakagamuchirwa kubva pakupinda muTX IP mumamiriro anotevera:
  - Kana vhidhiyo yakagamuchirwa iri HDCP-yakavharidzirwa (kureva kuti encryption status hdcp1_enabled kana hdcp2_enabled kubva kuRX IP ichinzi) uye vhidhiyo yakatumirwa haina HDCP-yakavharidzirwa (kureva kuti encryption status hdcp1_enabled kana hdcp2_enabled kubva kuTX IP haina kusimbiswa).
  - Kana vhidhiyo yakagamuchirwa iri HDCP TYPE 1 (kureva streamid_type kubva kuRX IP ichinzi) uye vhidhiyo yakafambiswa iri HDCP 1.4 yakavharidzirwa (kureva encryption chimiro hdcp1_enabled kubva kuTX IP inosimbiswa)
• Iwe unofanirwa kuchengetedza kuvanzika uye kutendeseka kweHDCP makiyi ekugadzira, uye chero mushandisi encryption kiyi.
• Intel inokurudzira zvakasimba kuti ugadzire chero Intel Quartus Prime mapurojekiti uye dhizaini sosi files ine encryption kiyi munzvimbo yakachengeteka yekombuta kuchengetedza makiyi.
• Intel inokurudzira zvakasimba kuti ushandise dhizaini yekuchengetedza maficha muFPGAs kuchengetedza dhizaini, kusanganisira chero akaiswa encryption kiyi, kubva kusingatenderwe kukopa, reverse engineering, uye t.ampering.

Related Information
AN 556: Kushandisa Dhizaini Yekuchengetedza Zvimiro muIntel FPGAs

4.6. Debug Guidelines
Ichi chikamu chinotsanangura inobatsira HDCP chimiro chiratidzo uye software paramita inogona kushandiswa kugadzirisa. Iyo ine zvakare mibvunzo inowanzo bvunzwa (FAQ) nezve kumhanyisa dhizaini example.

4.6.1. HDCP Status Signals
Kune akati wandei masaini anobatsira kuona mamiriro ekushanda eiyo HDCP IP cores. Aya masaini anowanikwa pane dhizaini example yepamusoro-level uye yakasungirirwa kune onboard LEDs:

Zita rechiratidzo	Function
hdcp1_enabled_rx	RX HDCP1x IP Decryption Status 0: Isingashande 1: Kushanda
hdcp2_enabled_rx	RX HDCP2x IP Decryption Status 0: Isingashande 1: Kushanda
hdcp1_enabled_tx	TX HDCP1x IP Encryption Status 0: Isingashande 1: Kushanda
hdcp2_enabled_tx	TX HDCP2x IP Encryption Status 0: Isingashande 1: Kushanda

Tarisa kuTafura 57 papeji 115 uye Tafura 58 papeji 115 pakuiswa kwavo kweLED.
Iyo inoshanda mamiriro ezviratidzo izvi inoratidza kuti HDCP IP ndeyechokwadi uye kugamuchira / kutumira yakavharidzirwa vhidhiyo rukova. Kune imwe neimwe nzira, HDCP1x chete kana HDCP2x
encryption/decryption mamiriro masaini ari kushanda. For example, kana hdcp1_enabled_rx kana hdcp2_enabled_rx ichishanda, HDCP iri paRX inogoneswa uye kubvisa iyo encrypted vhidhiyo rwizi kubva kunze kwevhidhiyo sosi.

4.6.2. Kugadzirisa HDCP Software Parameters
Kufambisa maitiro eHDCP debugging, unogona kushandura maparamita muhdcp.c.
Tafura iri pazasi inopfupikisa rondedzero yezvinogadziriswa paramita uye mabasa awo.

Parameter	Function
SUPPORT_HDCP1X	Gonesa HDCP 1.4 parutivi rweTX
SUPPORT_HDCP2X	Gonesa HDCP 2.3 parutivi rweTX
DEBUG_MODE_HDCP	Vhura mameseji ekugadzirisa TX HDCP
REPEATER_MODE	Gonesa inodzokorora modhi yeHDCP dhizaini example

Kuti ugadzirise maparameter, shandura hunhu kune hunodiwa hutsika muhdcp.c. Usati watanga kuunganidza, ita shanduko inotevera mune build_sw_hdcp.sh:

1. Tsvaga mutsara unotevera uye uutaure kunze kudzivirira iyo yakagadziridzwa software file ichitsiviwa neyokutanga files kubva kuIntel Quartus Prime Software yekuisa nzira.
   
2.  Mhanya “./build_sw_hdcp.sh” kuti ugadzire software yakagadziridzwa.
3. The generated .elf file inogona kuiswa mukugadzira nenzira mbiri:
   a. Mhanya "nios2-download -g file zita>”. Reset iyo sisitimu mushure mekurodha pasi kwapera kuti ive nechokwadi chekushanda kwakanaka.
   b. Mhanya "quartus_cdb --update_mif" kugadzirisa ndangariro yekutanga files. Mhanyai assembler kugadzira itsva .sof file iyo inosanganisira yakagadziridzwa software.

4.6.3. Mibvunzo Inowanzo bvunzwa (FAQ)
Tafura 59. Kukundikana Zviratidzo uye Nhungamiro

Number	Kukundikana Chiratidzo	Guideline
1.	Iyo RX iri kugamuchira vhidhiyo yakavharidzirwa, asi iyo TX iri kutumira static vhidhiyo yebhuruu kana dema ruvara.	Izvi zvinokonzerwa nekusabudirira kweTX kusimbiswa nekunyura kwekunze. A HDCP-anokwanisa anodzokorora haafanire kufambisa vhidhiyo mufomati isina kunyorwa kana vhidhiyo iri kuuya kubva kumusoro yakavharirwa. Kuti uite izvi, vhidhiyo yakamira yebhuruu kana nhema yeruvara inotsiva vhidhiyo inobuda kana iyo TX HDCP encryption chimiro chiratidzo chisisashande uku iyo RX HDCP decryption chimiro chiratidzo chiri kushanda. Kuti uwane nhungamiro chaiyo, tarisa kune Chengetedzo Kufunga papeji 117. Zvisineyi, hunhu uhwu hunogona kudzikisira maitiro ekugadzirisa kana uchigonesa HDCP dhizaini. Pazasi pane nzira yekudzima vhidhiyo ichivharira mudhizaini example: 1. Tsvaga iyo inotevera chiteshi chekubatanidza padanho repamusoro redhizaini example. Chiteshi ichi ndeche hdmi_tx_top module. 2. Shandura chinongedzo chechiteshi mumutsara unotevera:
2.	TX HDCP encryption chimiro chiratidzo chiri kushanda asi chando pikicha inoratidzwa pazasi pemvura.	Izvi zvinokonzerwa nekuti kunyura kuzasi hakugadzirise vhidhiyo inobuda yakavharidzirwa nemazvo. Ita shuwa kuti iwe unopa iyo yepasi rose (LC128) kuTX HDCP IP. Iko kukosha kunofanirwa kuve kukosha kwekugadzira uye kwakaringana.
3.	TX HDCP encryption chimiro chiratidzo haina kugadzikana kana inogara isingaite.	Izvi zvinokonzerwa nekusabudirira kweTX kusimbiswa nekudzika kwakadzika. Kufambisa iyo debugging process, unogona kugonesa iyo DEBUG_MODE_HDCP parameter in hdcp.c. Tarisa kune Kugadzirisa HDCP Software Parameters papeji 118 panhungamiro. Inotevera 3a-3c inogona kunge iri zvikonzero zvekusabudirira kweTX kusimbiswa.
3a.	Iyo software debug log inoramba ichidhinda iyi meseji "HDCP 1.4 haitsigirwe nekudzika (Rx)".	Iyo meseji inoratidza kunyura kwepasi haitsigire zvese HDCP 2.3 uye HDCP 1.4. Ita shuwa kuti sink yepasi inotsigira HDCP 2.3 kana HDCP 1.4.
3b.	TX kuvimbiswa kunokundikana pakati.	Izvi zvinokonzerwa nechero chikamu che TX chechokwadi senge siginecha verification, nharaunda cheki nezvimwe zvinogona kutadza. Ita shuwa kuti sink yepasi iri kushandisa kiyi yekugadzira asi kwete facsimile kiyi.
3c.	Iyo software debug log inoramba ichidhinda "Re- authentication	Iyi meseji inoratidza singi yepasi yakumbira kuti isimbiswe zvakare nekuti vhidhiyo yagamuchirwa haina kuvharwa nemazvo. Ita shuwa kuti iwe unopa iyo yepasi rose (LC128) kuTX HDCP IP. Iko kukosha kunofanirwa kunge kuri kukosha kwekugadzira uye kukosha kwacho.
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Number	Kukundikana Chiratidzo	Guideline
	inodiwa” mushure mekunge humbowo hweHDCP hwapera.
4.	RX HDCP decryption status siginecha haishande kunyangwe iyo yekumusoro sosi yakagonesa HDCP.	Izvi zvinoratidza kuti iyo RX HDCP IP haina kuwana iyo yakatenderwa nyika. By default, the REPEATER_MODE parameter inogoneswa mune dhizaini example. Kana iyo REPEATER_MODE inogoneswa, ita shuwa kuti TX HDCP IP ndeyechokwadi. Apo iyo REPEATER_MODE parameter inogoneswa, iyo RX HDCP IP inoedza kuvimbiswa seinodzokorora kana TX yakabatana kune HDCP-inokwanisa sink. Huchokwadi hunomira pakati uchimirira iyo TX HDCP IP kuti ipedze humbowo nekudzika kwakadzika uye kupfuudza iyo RECEIVERID_LIST kuRX HDCP IP. Nguva yekupedza sekutsanangurwa kwayo muHDCP Specification ndeye 2 masekondi. Kana iyo TX HDCP IP isingakwanise kupedzisa huchokwadi munguva ino, iyo yekumusoro sosi inobata iyo yechokwadi sekutadza uye inotangazve kusimbisa sezvakatsanangurwa muHDCP Specification.
		Cherechedza: • Tarisa kune Kugadzirisa HDCP Software Parameters papeji 118 yenzira yekudzima REPEATER_MODE parameter yechinangwa chekugadzirisa. Mushure mekudzima iyo REPEATER_MODE parameter, iyo RX HDCP IP inogara ichiedza kusimbiswa seyekupedzisira inogamuchira. Iyo TX HDCP IP haina gedhi maitiro echokwadi.
		• Kana iyo REPEATER_MODE parameter haina kugoneswa, ita shuwa kuti HDCP kiyi yakapihwa HDCP IP kukosha kwekugadzira uye kukosha kwacho.
5.	RX HDCP decryption chimiro chiratidzo haina kugadzikana.	Izvi zvinoreva kuti RX HDCP IP yakumbira kuvimbiswazve mushure mekunge nyika yakavimbiswa yawanikwa. Izvi zvinogona kunge zviri nekuda kweiyo iri kuuya yakavharidzirwa vhidhiyo haina kunyorwa nenzira kwayo neRX HDCP IP. Ita shuwa kuti iyo yepasirese inogara (LC128) yakapihwa kuRX HDCP IP yakakosha kukosha kwekugadzira uye kukosha kwacho.

HDMI Intel Arria 10 FPGA IP Dhizaini Example User Guide Archives

Kune ichangoburwa uye yapfuura shanduro yegwaro remushandisi, tarisa HDMI Intel® Arria 10 FPGA IP Dhizaini Ex.ample User Guide. Kana IP kana software vhezheni isina kunyorwa, gwaro remushandisi rekare IP kana software shanduro inoshanda.
IP shanduro dzakafanana neIntel Quartus Prime Design Suite software shanduro kusvika v19.1. Kubva kuIntel Quartus Prime Design Suite software vhezheni 19.2 kana gare gare, IP
cores ane itsva IP shanduro chirongwa.

Yekudzokorora Nhoroondo yeHDMI Intel Arria 10 FPGA IP Dhizaini Example User Guide

Document Version	Intel Quartus Prime Version	IP Version	Kuchinja
2022.12.27	22.4	19.7.1	Yakawedzera parameter nyowani yekusarudza HDMI mwanasikana kadhi kudzokorora kune Hardware uye Software Zvinodiwa chikamu cheiyo dhizaini ex.ample yeHDMI 2.0 (isina-FRL modhi).
2022.07.29	22.2	19.7.0	• Chiziviso chekubviswa kwechikamu cheCygwin kubva muWindows* vhezheni yeNios II EDS uye zvinodiwa kuisa WSL yevashandisi veWindows*. • Kadhi remwanasikana rakagadziridzwa kubva kuRevision 4 kusvika ku9 pazvinoshanda mugwaro rose.
2021.11.12	21.3	19.6.1	• Yakagadziridza chikamu cheChitoro chakavharidzirwa makiyi ekugadzira HDCP mundangariro yekunze yeflash kana EEPROM (Support HDCP Key Management = 1) kutsanangura kiyi itsva encryption software utility (KEYENC). • Akabvisa nhamba dzinotevera: - Dhata dhata reFacsimile Kiyi R1 yeRX Yakavanzika Kiyi -Data arrays eHDCP Production Keys (Placeholder) -Data dhata yeHDCP Dziviriro kiyi (yakafanotsanangurwa kiyi) - HDCP kiyi yekudzivirira yakatangwa muhdcp2x_tx_kmem.mif - HDCP kiyi yekudzivirira yakatangwa muhdcp1x_rx_kmem.mif - HDCP kiyi yekudzivirira yakatangwa muhdcp1x_tx_kmem.mif • Yakafambiswa chikamu cheHDCP Key Mapping kubva kuDCP Key Files kubva kuDebug Guidelines Kuchengeta akajeka HDCP makiyi ekugadzira muFPGA (Support HDCP Key Management = 0).
2021.09.15	21.1	19.6.0	Yakabviswa chirevo chencsim
2021.05.12	21.1	19.6.0	• Yakawedzerwa Kana SUPPORT FRL = 1 kana SUPPORT HDCP KEY MANAGEMENT = 1 kune tsananguro yeFigure 29 HDCP Pamusoro peHDMI Dhizaini Ex.ampuye Block Diagram. • Yakawedzera matanho muHDCP key memory files in Dhizaini Walkthrough. • Yakawedzerwa Kana SUPPORT FRL = 0 kune chikamu Seta iyo ardware. • Yakawedzera danho rekubatidza Tsigira HDCP Key Management parameter muGadzira Dhizaini. • Yakawedzera chikamu chitsva Chitoro chakavharidzirwa makiyi ekugadzira eHDCP mundangariro dzekunze kana EEPROM (Support HDCP Key Management = 1).
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Document Version	Intel Quartus Prime Version	IP Version	Kuchinja
			• Yakatumidzwazve Tafura Push Button uye LED Indicators kuPush Button uye LED Indicators (SUPPORT FRL = 0). • Yakawedzerwa Tafura Push Button uye LED Indicators (SUPPORT FRL = 1). • Yakawedzera chitsauko chitsva Dziviriro yeEncryption Key Yakamisikidzwa muFPGA Dhizaini. • Yakawedzera chitsauko chitsva Debug Guidelines uye zvikamu zviduku zveHDCP Status Signals, Kugadzirisa HDCP Software Parameter uye Mibvunzo Inowanzo bvunzwa.
2021.04.01	21.1	19.6.0	• Yakagadziridzwa Figure Zvikamu Zvinodiwa paRX-Chete kana TX-Chete Dhizaini. • Tafura Yakagadziridzwa Yakagadzirwa RTL Files. • Yakagadziridzwa Mufananidzo HDMI RX Pamusoro Zvikamu. • Yakabviswa Chikamu HDMI RX Top Link Training Process. • Yakagadziridza nhanho muKumhanyisa Dhizaini mune Yakasiyana FRL Rates. • Yakagadziridzwa Mufananidzo HDMI 2.1 Dhizaini Example Clock Scheme. • Yakagadziridzwa Tafura Yekuvhara Scheme Signals. • Mufananidzo wakagadziridzwa HDMI RX-TX Block Diagram kuti uwedzere chinongedzo kubva kuTransceiver Arbiter kuenda kuTX kumusoro.
2020.09.28	20.3	19.5.0	• Yakabvisa chinyorwa chekuti HDMI 2.1 dhizaini example muFRL modhi inotsigira chete kumhanya giredhi -1 zvishandiso muHDMI Intel FPGA IP Dhizaini Example Quick Start Guide yeIntel Arria 10 Devices uye HDMI 2.1 Dhizaini Example (Support FRL = 1) zvikamu. Iyo dhizaini inotsigira ese kumhanya mamakisi. • Yakabviswa ls_clk ruzivo kubva kune ese HDMI 2.1 design exampnezvikamu zvinoenderana. Iyo ls_clk domain haichashandiswe mudhizaini example. • Yakagadziridza dhizaini yebhuroko yeHDMI 2.1 dhizaini example muFRL modhi muHDMI 2.1 Dhizaini Example (Support FRL = 1), Kugadzira RX- Chete kana TX-Chete Dhizaini Dhizaini Zvikamu, uye Kuvhara Scheme zvikamu. • Akagadziridza madhairekitori uye akagadzirwa files runyorwa muzvikamu zveDirectory Structure. • Yakabvisa zviratidzo zvisina basa, uye yakawedzera kana kugadzirisa tsananguro yeinotevera HDMI 2.1 design ex.ample masaini muchikamu cheInterface Signals: — sys_init — txpll_frl_locked — tx_os - txphy_rcfg* zviratidzo — tx_reconfig_done — txcore_tbcr — pio_in0_external_connection_export • Yakawedzera zvinotevera muchikamu cheDesign RTL Parameters: — EDID_RAM_ADDR_WIDTH — BITEC_DAUGHTER_CARD_REV -SHANDISA FPLL - POLARITY_INVERSION
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Document Version	Intel Quartus Prime Version	IP Version	Kuchinja
			• Yakagadziridza dhizaini yebhuroko yeHDMI 2.0 dhizaini example yeIntel Quartus Prime Pro Edition software muHDMI 2.0 Dhizaini Example (Support FRL = 0), Kugadzira RX-Chete kana TX-Chete Dhizaini Dhizaini Zvikamu, uye Kuvhara Scheme zvikamu. • Kugadziridza wachi uye kuseta patsva mazita ezviratidzo muchikamu cheDynamic Range uye Mastering (HDR) InfoFrame Insertion and Filtering. • Yakabvisa zviratidzo zvisina basa, uye yakawedzera kana kugadzirisa tsananguro yeinotevera HDMI 2.0 design ex.ample masaini muchikamu cheInterface Signals: — clk_fpga_b3_p — REFCLK_FMCB_P — fmcb_la_tx_p_11 — fmcb_la_rx_n_9e -fr_clck — reset_xcvr_powerup - nios_tx_i2c* zviratidzo — hdmi_ti_i2c* zviratidzo - tx_i2c_avalon* zviratidzo — clock_bridge_0_in_clk_clk — reset_bridge_0_reset_reset_n - i2c_master* zviratidzo - nios_tx_i2c* zviratidzo — measure_valid_pio_external_connectio n_export — oc_i2c_av_slave_translator_avalon_an ti_slave_0* zviratidzo — powerup_cal_done_export — rx_pma_cal_busy_export — rx_pma_ch_export — rx_pma_rcfg_mgmt* zviratidzo • Yakawedzera chiziviso chekuti simulation testbench haitsigirwe magadzirirwo ane Kusanganisira I2C parameter yakagoneswa uye yakagadziridza meseji yekufananidza muchikamu cheSimulation Testbench. • Yakagadziridza chikamu cheKuvandudza Dhizaini Yako.
2020.04.13	20.1	19.4.0	• Yakawedzera chinyorwa kuti HDMI 2.1 dhizaini example muFRL modhi inotsigira chete kumhanya giredhi -1 zvishandiso muHDMI Intel FPGA IP Dhizaini Example Quick Start Guide yeIntel Arria 10 Zvishandiso uye Tsanangudzo Yakadzama yeHDMI 2.1 Dhizaini Example (Support FRL = 1) zvikamu. • Yakafambisa HDCP Pamusoro peHDMI Dhizaini Example yeIntel Arria 10 Devices chikamu kubva kuHDMI Intel FPGA IP User Guide. • Yakagadzirisa chikamu cheKutevedzera Dhizaini kuti ubatanidze iyo odhiyo sample jenareta, sideband data jenareta, uye yekubatsira data jenareta uye yakagadziridza yakabudirira meseji yekunyepedzera. • Yakabviswa chinyorwa kuti yakataurwa simulation inowanikwa chete Tsigira FRL akaremara magadzirirwo note. Simulation yave kuwanikwa Tsigira FRL akagonesa madhizaini zvakare. • Yakagadziridza tsananguro yechinhu muDetailed Description yeHDMI 2.1 Dhizaini Example (Support FRL Inogoneswa) chikamu.
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Document Version	Intel Quartus Prime Version	IP Version	Kuchinja
			• Yakagadzirisa dhizaini yebhuroko muHDMI 2.1 RX-TX Dhizaini Yekuvhara Dhizaini, Dhizaini Zvikamu, uye Kugadzira RX-Chete kana TX-Chete Dhizaini zvikamu zveHDMI 2.1 dhizaini ex.ample. Yakawedzera zvikamu zvitsva uye zvakabviswa zvikamu izvo zvisisashande. • Akapepeta main.c script rairo muchikamu cheKugadzira RX-Chete kana TX-Chete Dhizaini. • Yakagadziridza zvikamu zveDirectory Structure kuwedzera maforodha matsva uye files yezvose zviri zviviri HDMI 2.0 uye HDMI 2.1 dhizaini examples. • Yakagadziridza chikamu cheHardware neSoftware Inodiwa cheHDMI 2.1 dhizaini example. • Yakagadziridza dhayagiramu yebhuroko uye tsananguro yezviratidzo muDynamic Range uye Mastering (HDR) InfoFrame Insertion uye Sefa chikamu cheHDMI 2.1 design ex.ample. • Yakawedzera chikamu chitsva, Running the Design in Different FRL Rates, yeHDMI 2.1 design ex.amples. • Yakagadziridza dhayagiramu yebhuroko uye tsananguro yechiratidzo muchikamu cheClocking Scheme yeHDMI 2.1 dhizaini ex.ample. • Yakawedzerwa tsananguro pamusoro pemushandisi DIP chinja muHardware Setup chikamu cheHDMI 2.1 dhizaini example. • Yakagadziridza chikamu cheDesign Limitations yeHDMI 2.1 design example. • Yakagadziridza chikamu cheKuvandudza Dhizaini Yako. • Yakagadziridza zvikamu zveSimulation Testbench zvose HDMI 2.0 uye HDMI 2.1 design examples.
2020.01.16	19.4	19.3.0	• Yakagadziridza HDMI Intel FPGA IP Dhizaini Example Quick Start Guide yeIntel Arria 10 Devices chikamu chine ruzivo nezve ichangobva kuwedzerwa HDMI 2.1 dhizaini ex.ample ne FRL mode. • Yakawedzera chitsauko chitsva, Tsanangudzo Yakadzama yeHDMI 2.1 Dhizaini Example (Support FRL Inogoneswa) iyo ine ruzivo rwese rwakakodzera nezve ichangobva kuwedzerwa dhizaini example. • Yakanzizve HDMI Intel FPGA IP Dhizaini Example Tsanangudzo Yakadzama kune Tsananguro Yakadzama yeHDMI 2.0 Dhizaini Example kuitira kujeka kuri nani.
2019.10.31	18.1	18.1	• Yakawedzerwa yakagadzirwa files mu tx_control_src folda: ti_i2c.c uye ti_i2c.h. • Yakawedzera tsigiro yeFMC mwanasikana kadhi revision 11 muHardware uye Software Zvinodiwa uye Kuunganidza uye Kuedza Zvikamu Zvikamu. • Yakabvisa chikamu cheDesign Limitation. Muganho maererano nekutyorwa kwenguva pane yakanyanya skew constraints yakagadziriswa mushanduro 18.1 yeHDMI Intel FPGA IP. • Tawedzera RTL parameter itsva, BITEC_DAUGHTER_CARD_REV, kuti ukwanise kusarudza kudzokororwa kwekadhi remwanasikana reBitec HDMI.
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Document Version	Intel Quartus Prime Version	IP Version	Kuchinja
			• Vakagadziridza tsananguro ye fmcb_dp_m2c_p ne fmcb_dp_c2m_p masiginecha kuti ibatanidze ruzivo nezve FMC kudzokorora kadhi remwanasikana 11, 6, uye 4. • Yakawedzera zviratidzo zvitsva zvinotevera zvekudzokorora kadhi remwanasikana weBitec 11: — hdmi_tx_ti_i2c_sda — hdmi_tx_ti_i2c_scl — oc_i2c_master_ti_avalon_anti_slave_a kero — oc_i2c_master_ti_avalon_anti_slave_w rite — oc_i2c_master_ti_avalon_anti_slave_r eaddata — oc_i2c_master_ti_avalon_anti_slave_w ritedata — oc_i2c_master_ti_avalon_anti_slave_w aitrequest • Yakawedzera chikamu pamusoro peKukwidziridza Dhizaini Yako.
2017.11.06	17.1	17.1	• Yakanzizve HDMI IP musimboti kuita HDMI Intel FPGA IP maererano neIntel rebranding. • Yakashandura izwi rekuti Qsys kuita Platform Designer. • Mashoko akawedzerwa pamusoro peDynamic Range uye Mastering InfoFrame (HDR) kuisa uye kusefa. • Yakagadziridza dhairekitori chimiro: - Yakawedzera script uye software maforodha uye files. - Yakagadziridzwa zvakajairika uye HDr files. - Yakabviswa atx files. - Yakasiyana files yeIntel Quartus Prime Standard Edition uye Intel Quartus Prime Pro Edition. • Yakagadziridza Chikamu Chekugadzira Dhizaini kuti uwedzere mudziyo unoshandiswa se 10AX115S2F4I1SG. • Yakagadziridzwa transceiver data rate ye 50-100 MHz TMDS wachi frequency kusvika 2550-5000 Mbps. • Yakagadziridza RX-TX ruzivo rwelink rwaunokwanisa kuburitsa user_pb[2] bhatani kuti udzime kusefa kwekunze. • Yakagadziridza Nios II software flow diagram inosanganisira zvidzoro zveI2C master uye HDMI source. • Yakawedzera ruzivo nezve Design Example GUI parameters. • Yakawedzera HDMI RX uye TX Top design parameters. • Yakawedzera aya masaini eHDMI RX neTX epamusoro-soro: — mgmt_clk - reset — i2c_clk — hdmi_clk_in - Yakabvisa aya HDMI RX uye TX masaini epamusoro-level: • shanduro • i2c_clk
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Document Version	Intel Quartus Prime Version	IP Version	Kuchinja
			• Yakawedzera chinyorwa chokuti transceiver analogi setting yakaedzwa Intel Arria 10 FPGA Development Kit uye Bitec HDMI 2.0 Daughter card. Iwe unogona kugadzirisa analog marongero ebhodhi rako. • Yakawedzera chinongedzo chekushanda kudzivirira jitter yePLL cascading kana isina-yakatsaurirwa wachi nzira dzeIntel Arria 10 PLL referensi wachi. • Yakawedzera chinyorwa chekuti haugone kushandisa transceiver RX pin seCDR refclk yeHDMI RX kana seTX PLL refclk yeHDMI TX. • Yakawedzera chinyorwa pamusoro pekuti ungawedzera sei set_max_skew constraint kune madhizaini anoshandisa TX PMA nePCS bonding.
2017.05.08	17.0	17.0	• Yakadzorerwa zvakare seIntel. • Yakachinjwa chikamu nhamba. • Yakagadziridza dhairekitori chimiro: - Yakawedzerwa hdr files. - Yakashandurwa qsys_vip_passthrough.qsys kuita nios.qsys. - Yakawedzerwa files yakagadzirirwa Intel Quartus Prime Pro Edition. • Ruzivo rwakavandudzwa rwekuti RX-TX Link block inoitawo kusefa kwekunze paHigh Dynamic Range (HDR) Infoframe kubva kuHDMI RX data yekubatsira uye inoisa ex.ample HDR Infoframe kune iyo yekubatsira data yeHDMI TX kuburikidza neAvalon ST multiplexer. • Yakawedzera chinyorwa cheTransceiver Native PHY tsananguro kuti kusangana neHDMI TX inter-channel skew zvinodiwa, unofanira kuseta sarudzo yeTX channel bonding mode muArria 10 Transceiver Native PHY parameter editor kuti PMA uye PCS kubatana. • Updated tsananguro nokuti os uye kuyerwa zviratidzo. • Akagadziridza oversampling factor yeakasiyana transceiver data rate pane yega yega TMDS wachi frequency renji kutsigira TX FPLL yakananga wachi chirongwa. • Yakachinjwa TX IOPLL kuita TX FPLL cascade clocking scheme kuita TX FPLL direct scheme. • Yakawedzerwa TX PMA reconfiguration zviratidzo. • Yakagadziriswa USER_LED[7] ovhaampling status. 1 inoratidza oversampled (data rate <1,000 Mbps muArria 10 mudziyo). • Yakagadziridzwa HDMI Dhizaini Example Inotsigirwa Simulators tafura. VHDL haina kutsigirwa yeNCSim. • Yakawedzera chinongedzo kushanduro yakachengetwa yeArria 10 HDMI IP Core Dhizaini Example User Guide.
2016.10.31	16.1	16.1	Kusunungurwa kwekutanga.

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References

• User Manual