HDMI Arria 10 FPGA IP Design Eksample
Itọsọna olumuloHDMI Intel® Arria 10 FPGA IP
Apẹrẹ Example User Itọsọna
Imudojuiwọn fun Intel®Quartus®
NOMBA Design Suite: 22.4
Ẹya IP: 19.7.1

HDMI Intel® FPGA IP Design Example Quick Bẹrẹ Itọsọna fun Intel® Arria® 10 awọn ẹrọ

Awọn ohun elo HDMI Intel® 10 ṣe ẹya simulating testbench ati apẹrẹ ohun elo ti o ṣe atilẹyin iṣakojọpọ ati idanwo ohun elo.
FPGA IP apẹrẹ example fun Intel Arria®
HDMI Intel FPGA IP nfunni ni apẹrẹ atẹle yiiample:

• HDMI 2.1 RX-TX retransmit oniru pẹlu ti o wa titi oṣuwọn ọna asopọ (FRL) mode sise
• HDMI 2.0 RX-TX retransmit oniru pẹlu FRL mode alaabo
• HDCP lori HDMI 2.0 design

Akiyesi: Ẹya HDCP ko si ninu sọfitiwia Intel® Quartus Prime Pro Edition.
Lati wọle si ẹya HDCP, kan si Intel ni https://www.intel.com/content/www/us/en/broadcast/products/programmable/applications/connectivity-solutions.html.
Nigba ti o ba se ina kan oniru example, paramita olootu laifọwọyi ṣẹda awọn files pataki lati ṣe simulate, ṣajọ, ati idanwo apẹrẹ ni hardware.
Nọmba 1. Awọn Igbesẹ IdagbasokeAlaye ti o jọmọ
HDMI Intel FPGA IP Itọsọna olumulo
1.1. Ti o npese awọn Design
Lo olootu paramita IP HDMI Intel FPGA ninu sọfitiwia Intel Quartus Prime lati ṣe ipilẹṣẹ apẹrẹ tẹlẹamples. Intel Corporation. Gbogbo awọn ẹtọ wa ni ipamọ. Intel, aami Intel, ati awọn aami Intel miiran jẹ aami-išowo ti Intel Corporation tabi awọn oniranlọwọ rẹ. Intel ṣe atilẹyin iṣẹ ṣiṣe ti FPGA rẹ ati awọn ọja semikondokito si awọn pato lọwọlọwọ ni ibamu pẹlu atilẹyin ọja boṣewa Intel, ṣugbọn ni ẹtọ lati ṣe awọn ayipada si eyikeyi awọn ọja ati iṣẹ nigbakugba laisi akiyesi. Intel ko gba ojuse tabi layabiliti ti o dide lati inu ohun elo tabi lilo eyikeyi alaye, ọja, tabi iṣẹ ti a ṣalaye ninu rẹ ayafi bi a ti gba ni kikun si kikọ nipasẹ Intel. A gba awọn alabara Intel nimọran lati gba ẹya tuntun ti awọn pato ẹrọ ṣaaju gbigbekele eyikeyi alaye ti a tẹjade ati ṣaaju gbigbe awọn aṣẹ fun awọn ọja tabi awọn iṣẹ. * Awọn orukọ miiran ati awọn ami iyasọtọ le jẹ ẹtọ bi ohun-ini ti awọn miiran.
Bibẹrẹ pẹlu Nios® II EDS ninu ẹya sọfitiwia Intel Quartus Prime Pro Edition 19.2 ati ẹya sọfitiwia Intel Quartus Prime Standard Edition 19.1, Intel ti yọ paati Cygwin kuro ninu ẹya Windows * ti Nios II EDS, rọpo pẹlu Windows * Subsytem fun Linux (WSL). Ti o ba jẹ olumulo Windows * kan, o nilo lati fi sori ẹrọ WSL ṣaaju ṣiṣe ipilẹṣẹ apẹrẹ rẹ tẹlẹample.
olusin 2. Ti o npese awọn Design sisan

1. Ṣẹda ise agbese kan ìfọkànsí Intel Arria 10 ẹrọ ebi ati ki o yan awọn ti o fẹ ẹrọ.
2. Ninu Katalogi IP, wa ati tẹ Awọn Ilana Atọka Ilọpo meji ➤ Audio & Fidio ➤ HDMI Intel FPGA IP. Iyatọ IP Tuntun tabi Ferese Iyipada IP Tuntun yoo han.
3. Pato orukọ ipele-oke fun iyatọ IP aṣa rẹ. Olootu paramita n fipamọ awọn eto iyatọ IP ni a file ti a npè ni .ip tabi .qsys.
4. Tẹ O DARA. Olootu paramita yoo han.
5. Lori IP taabu, tunto awọn paramita ti o fẹ fun mejeeji TX ati RX.
6. Tan paramita FRL Atilẹyin lati ṣe ipilẹṣẹ HDMI 2.1 apẹrẹ example ni FRL mode. Pa a lati ṣe ina HDMI 2.0 oniru example lai FRL.
7. Lori apẹrẹ Example taabu, yan Arria 10 HDMI RX-TX Retransmit.
8. Yan Simulation lati se ina testbench, ki o si yan Synthesis lati se ina awọn hardware oniru example.You gbọdọ yan ni o kere ọkan ninu awọn aṣayan lati se ina awọn oniru Mofiample files. Ti o ba yan awọn mejeeji, akoko iran naa gun.
9. Fun ipilẹṣẹ File Ọna kika, yan Verilog tabi VHDL.
10. Fun Apo Idagbasoke Àkọlé, yan Apo Idagbasoke Intel Arria 10 GX FPGA. Ti o ba yan a idagbasoke kit, ki o si awọn afojusun ẹrọ (ti a ti yan ni igbese 4) ayipada lati baramu awọn ẹrọ lori afojusun ọkọ. Fun Apo Idagbasoke Intel Arria 10 GX FPGA, ẹrọ aifọwọyi jẹ 10AX115S2F4I1SG.
11. Tẹ ina Example Design.

Alaye ti o jọmọ
Bawo ni lati fi sori ẹrọ Windows * Subsystem fun Lainos* (WSL) lori Windows* OS?
1.2. Simulating awọn Design
HDMI testbench ṣe afọwọṣe apẹrẹ loopback ni tẹlentẹle lati apẹẹrẹ TX kan si apẹẹrẹ RX kan. Olupilẹṣẹ apẹẹrẹ fidio inu, ohun sampmonomono, olupilẹṣẹ data sideband, ati awọn modulu olupilẹṣẹ data iranlọwọ n ṣe apẹẹrẹ HDMI TX ati abajade ni tẹlentẹle lati apẹẹrẹ TX sopọ si apẹẹrẹ RX ni testbench.
olusin 3. Ṣiṣan Simulation Design

1. Lọ si folda kikopa ti o fẹ.
2. Ṣiṣe awọn iwe afọwọkọ kikopa fun atilẹyin iṣeṣiro ti o fẹ. Awọn akosile akopọ ati ki o nṣiṣẹ testbench ni labeabo.
3. Ṣe itupalẹ awọn abajade.

Tabili 1. Igbesẹ lati Ṣiṣe Simulation

Simulator	Ṣiṣẹ Directory	Awọn ilana
Riviera-PRO*	/ kikopa/aldec	Ninu laini aṣẹ, tẹ
		vsim -c -ṣe aldec.do
AwoṣeSim*	/ kikopa / olutojueni	Ninu laini aṣẹ, tẹ
		vsim -c -ṣe mentor.do
VCS*	/ kikopa/synopsys/vcs	Ninu laini aṣẹ, tẹ
		orisun vcs_sim.sh
VCS MX	/ kikopa/synopsys/ vcsmx	Ninu laini aṣẹ, tẹ
		orisun vcsmx_sim.sh
Xcelium * Ni afiwe	/ kikopa/xcelium	Ninu laini aṣẹ, tẹ
		orisun xcelium_sim.sh

Simulation aṣeyọri pari pẹlu ifiranṣẹ atẹle:
# SYMBOLS_PER_CLOCK = 2
# VIC = 4
# FRL_RATE = 0
BPP = 0
# AUDIO_FREQUENCY (kHz) = 48
# AUDIO_CHANNEL = 8
# Simulation kọja
1.3. Iṣakojọpọ ati Idanwo Oniru naa

Lati ṣajọ ati ṣiṣe idanwo ifihan lori hardware exampFun apẹrẹ, tẹle awọn igbesẹ wọnyi:

1. Rii daju hardware example oniru iran jẹ pari.
2. Lọlẹ Intel Quartus Prime software ati ṣi .qpf file.
   • HDMI 2.1 oniru example pẹlu Atilẹyin FRL ṣiṣẹ: itọsọna ise agbese/quartus/a10_hdmi21_frl_demo.qpf
   • HDMI 2.0 oniru example pẹlu Atilẹyin FRL alaabo: ise agbese irectory/quartus/a10_hdmi2_demo.qpf
3. Tẹ Ṣiṣeto ➤ Bẹrẹ Iṣakojọpọ.
4. Lẹhin akojọpọ aṣeyọri, a .sof file yoo jẹ ipilẹṣẹ ni kuotisi/jade_files liana.
5. Sopọ si ibudo FMC lori-ọkọ B (J2):
   • HDMI 2.1 oniru example pẹlu Support FRL ṣiṣẹ: Bitec HDMI 2.1 FMC Ọmọbinrin Kaadi Rev 9
   Akiyesi: O le yan awọn àtúnyẹwò ti rẹ Biec HDMI ọmọbinrin kaadi. Labẹ apẹrẹ Example taabu, ṣeto HDMI Ọmọbinrin Card Àtúnyẹwò si boya Àtúnyẹwò 9, Àtúnyẹwò tabi ko si ọmọbinrin kaadi. Iye aiyipada jẹ Atunyẹwo 9.
   • HDMI 2.0 oniru example pẹlu Atilẹyin FRL alaabo: Biec HDMI 2.0 FMC Kaadi Ọmọbinrin Rev 11
6. So TX (P1) ti kaadi ọmọbinrin Bitec FMC si orisun fidio ita.
7. So RX (P2) ti kaadi ọmọbinrin Bitec FMC si ifọwọ fidio ita tabi oluyẹwo fidio.
8. Rii daju pe gbogbo awọn iyipada lori igbimọ idagbasoke wa ni ipo aiyipada.
9. Tunto awọn ti a ti yan Intel Arria 10 ẹrọ lori idagbasoke ọkọ lilo awọn ti ipilẹṣẹ .sof file (Awọn irinṣẹ ➤ Oluṣeto).
10. Oluyanju yẹ ki o ṣafihan fidio ti ipilẹṣẹ lati orisun.

Alaye ti o jọmọ
Intel Arria 10 FPGA Development Apo olumulo Itọsọna
1.4. HDMI Intel FPGA IP Design Example Parameters
Tabili 2.
HDMI Intel FPGA IP Design Example Awọn paramita fun Intel Arria 10 Awọn ẹrọ Awọn aṣayan wọnyi wa fun awọn ẹrọ Intel Arria 10 nikan.

Paramita	Iye	Apejuwe
Apẹrẹ ti o wa Example
Yan Oniru	Arria 10 HDMI RX-TX Retransmit	Yan apẹrẹ example lati wa ni ipilẹṣẹ.

Apẹrẹ Example Files
Afọwọṣe	Tan, paa	Tan aṣayan yii lati ṣe ina pataki files fun testbench kikopa.
Akopọ	Tan, paa	Tan aṣayan yii lati ṣe ina pataki files fun Intel Quartus Prime akopo ati hardware ifihan.

Ti ipilẹṣẹ HDL kika
Ṣẹda File Ọna kika	Verilog, VHDL	Yan ọna kika HDL ti o fẹ fun apẹrẹ ti ipilẹṣẹ example fileṣeto. Akiyesi: Aṣayan yii nikan pinnu ọna kika fun ipilẹṣẹ IP ipele oke files. Gbogbo miiran files (fun apẹẹrẹample testbenches ati oke ipele files fun ifihan ohun elo) wa ni ọna kika Verilog HDL

Àkọlé Development Kit
Yan Board	Ko si Apo Idagbasoke,	Yan igbimọ fun apẹrẹ ìfọkànsí example.
	Arria 10 GX Apo Idagbasoke FPGA, Aṣa Development Apo	Ko si Apo Idagbasoke: Aṣayan yii yọkuro gbogbo awọn aaye ohun elo fun apẹrẹ apẹẹrẹample. Ipilẹ ipilẹ IP ṣeto gbogbo awọn iṣẹ iyansilẹ pin si awọn pinni foju. Apo Idagbasoke Arria 10 GX FPGA: Aṣayan yii laifọwọyi yan ẹrọ ibi-afẹde iṣẹ akanṣe lati baamu ẹrọ naa lori ohun elo idagbasoke yii. O le yi awọn afojusun ẹrọ nipa lilo awọn Yi Àkọlé Device paramita ti atunyẹwo igbimọ rẹ ba ni iyatọ ẹrọ ti o yatọ. Ipilẹ IP ṣeto gbogbo awọn iṣẹ iyansilẹ pin ni ibamu si ohun elo idagbasoke.
		• Aṣa Development Apo: Eleyi aṣayan faye gba awọn oniru example ṣe idanwo lori ohun elo idagbasoke ẹnikẹta pẹlu Intel FPGA kan. O le nilo lati ṣeto awọn iṣẹ iyansilẹ pin lori tirẹ.

Àkọlé Device
Yi Àkọlé Device	Tan, paa	Tan aṣayan yii ki o yan iyatọ ẹrọ ti o fẹ fun ohun elo idagbasoke.

HDMI 2.1 Apẹrẹ Example (Atilẹyin FRL = 1)

HDMI 2.1 apẹrẹ example ni ipo FRL ṣe afihan ọkan HDMI apẹẹrẹ parallel loopback ti o ni awọn ikanni RX mẹrin ati awọn ikanni TX mẹrin.
Table 3. HDMI 2.1 Design Eksample fun Intel Arria 10 Awọn ẹrọ

Apẹrẹ Example	Data Oṣuwọn	Ipo Ikanni	Loopback Iru
Arria 10 HDMI RX-TX Retransmit	• 12 Gbps (FRL) • 10 Gbps (FRL) • 8Gbps (FRL) • 6 Gbps (FRL) • 3 Gbps (FRL) <6 Gbps (TMDS)	Simplex	Ni afiwe pẹlu ifipamọ FIFO

Awọn ẹya ara ẹrọ

• Apẹrẹ naa ṣe afiṣe awọn buffers FIFO lati ṣe ipasẹ ṣiṣan fidio taara HDMI kan laarin ifọwọ HDMI 2.1 ati orisun.
• Apẹrẹ naa ni agbara lati yipada laarin ipo FRL ati ipo TMDS lakoko akoko ṣiṣe.
• Apẹrẹ naa nlo ipo LED fun n ṣatunṣe aṣiṣe ni kutukutu stage.
• Apẹrẹ wa pẹlu HDMI RX ati awọn iṣẹlẹ TX.
• Apẹrẹ ṣe afihan fifi sii ati sisẹ ti Ibiti Yiyiyi ati Mastering (HDR) InfoFrame ni module ọna asopọ RX-TX.
• Apẹrẹ naa ṣe idunadura oṣuwọn FRL laarin iho ti a ti sopọ si TX ati orisun ti a ti sopọ si RX. Apẹrẹ naa kọja nipasẹ EDID lati inu ifọwọ ita si RX lori-ọkọ ni iṣeto aiyipada. Nios II ero isise duna awọn ọna asopọ mimọ lori awọn agbara ti awọn rii ti sopọ si TX. O tun le yi olumulo_dipsw lori-board yipada lati ṣakoso pẹlu ọwọ awọn agbara TX ati RX FRL.
• Apẹrẹ pẹlu ọpọlọpọ awọn ẹya n ṣatunṣe aṣiṣe.
  Apeere RX gba orisun fidio kan lati olupilẹṣẹ fidio ita, ati data lẹhinna lọ nipasẹ loopback FIFO ṣaaju ki o to tan si apẹẹrẹ TX. O nilo lati so olutupalẹ fidio ita, atẹle, tabi tẹlifisiọnu kan pẹlu asopọ HDMI si mojuto TX lati jẹrisi iṣẹ ṣiṣe naa.

2.1. HDMI 2.1 RX-TX Retransmit Design Block aworan atọka
The HDMI RX-TX retransmit oniru example ṣe afihan loopback ti o jọra lori ipo ikanni simplex fun HDMI 2.1 pẹlu atilẹyin FRL ṣiṣẹ.
olusin 4. HDMI 2.1 RX-TX Retransmit Block Diagram2.2. Ṣiṣẹda RX-Nikan tabi TX-Nikan Apẹrẹns
Fun awọn olumulo to ti ni ilọsiwaju, o le lo apẹrẹ HDMI 2.1 lati ṣẹda apẹrẹ TX- tabi RX-nikan.
Ṣe nọmba 5. Awọn ohun elo ti a beere fun RX-Nikan tabi Apẹrẹ TX-NikanLati lo awọn paati RX tabi TX nikan, yọ awọn bulọọki ti ko ṣe pataki kuro ninu apẹrẹ.
Table 4. RX-Nikan ati TX-Nikan Design awọn ibeere

Awọn ibeere olumulo	Fipamọ	Yọ kuro	Fi kun
HDMI RX nikan	Iye ti o ga julọ ti RX	TX Top • RX-TX Ọna asopọ • Sipiyu Subsystem • Arbiter Transceiver	–
HDMI TX nikan	• TX Oke •CPU-System	• RX Oke • RX-TX Ọna asopọ •Transceiver Arbiter	Olupilẹṣẹ Àpẹẹrẹ Fidio (Module aṣa tabi ti ipilẹṣẹ lati Fidio ati Sisẹ Aworan (VIP) Suite)

Yato si awọn ayipada RTL, o nilo lati tun satunkọ main.c script.
• Fun HDMI TX-nikan awọn aṣa, decouple awọn idaduro fun HDMI RX ipo titiipa nipa yiyọ awọn ila wọnyi ki o rọpo pẹlu
tx_xcvr_reconfig (tx_frl_rate);
rx_hdmi_lock = READ_PIO(PIO_IN0_BASE, PIO_RX_LOCKED_OFFSET,
PIO_RX_LOCKED_WIDTH);
nigba (rx_hdmi_lock == 0) {
ti (check_hpd_isr ()) { ṣẹ; }
// rx_vid_lock = READ_PIO(PIO_IN0_BASE, PIO_VID_LOCKED_OFFSET,
PIO_VID_LOCKED_WIDTH);
rx_hdmi_lock = READ_PIO(PIO_IN0_BASE, PIO_RX_LOCKED_OFFSET,
PIO_RX_LOCKED_WIDTH);
// Tunto Tx lẹhin rx ti wa ni titiipa
ti (rx_hdmi_lock == 1) {
ti (READ_PIO(PIO_IN0_BASE, PIO_LOOPBACK_MODE_OFFSET,
PIO_LOOPBACK_MODE_WIDTH) == 1) {
rx_frl_rate = READ_PIO(PIO_IN0_BASE, PIO_RX_FRL_RATE_OFFSET,
PIO_RX_FRL_RATE_WIDTH );
tx_xcvr_reconfig (rx_frl_rate);
} miran {
tx_xcvr_reconfig (tx_frl_rate);
} }
Fun HDMI RX-nikan awọn aṣa, tọju awọn ila wọnyi nikan ni iwe afọwọkọ main.c:
REDRIVER_INIT ();
hdmi_rx_init ();
2.3. Hardware ati Software Awọn ibeere
Intel nlo awọn wọnyi hardware ati software lati se idanwo awọn oniru example.
Hardware

• Intel Arria 10 GX FPGA Development Apo
• HDMI 2.1 Orisun (Kuatomu Data 980 48G monomono)
• HDMI 2.1 rì (kuatomu Data 980 48G Oluyanju)
• Bitec HDMI kaadi ọmọbinrin FMC 2.1 (Atunyẹwo 9)
• HDMI 2.1 Awọn kebulu Ẹka 3 (idanwo pẹlu Belkin 48Gbps HDMI 2.1 Cable)

Software

• Ẹya sọfitiwia Intel Quartus Prime Pro Edition 20.1

2.4. Ilana Ilana
Awọn ilana ni awọn ti ipilẹṣẹ files fun HDMI Intel FPGA IP oniru example.
olusin 6. Ilana Itọsọna fun Oniru ExampleTable 5. Ti ipilẹṣẹ RTL Files

Awọn folda	Files/ Awọn folda inu
wọpọ	clock_control.ip
	clock_crosser.v
	dcfifo_inst.v
	Edge_detector.sv
	fifo.ip
	iṣẹjade_buf_i2c.ip

	test_pattern_gen.v
	tpg.v
	tpg_data.v
gxb	gxb_rx.ip
	gxb_rx_reset.ip
	gxb_tx.ip
	gxb_tx_fpll.ip
	gxb_tx_reset.ip
hdmi_rx	hdmi_rx.ip
	hdmi_rx_top.v
	Panasonic.hex
hdmi_tx	hdmi_tx.ip
	hdmi_tx_top.v
i2c_ẹrú	i2c_avl_mst_intf_gen.v
	i2c_clk_cnt.v
	i2c_condt_det.v
	i2c_databuffer.v
	i2c_rxshifter.v
	i2c_slvfsm.v
	i2c_spksup.v
	i2c_txout.v
	i2c_txshifter.v
	i2cslave_to_avlmm_bridge.v
pll	pll_hdmi_reconfig.ip
	pll_frl.ip
	pl_reconfig_ctrl.v
	pll_tmds.ip
	pll_vidclk.ip
	kuotisi.ini
rxtx_link	altera_hdmi_hdr_infoframe.v
	aux_mux.qsys
	aux_retransmit.v
	aux_src_gen.v
	ext_aux_filter.v

	rxtx_link.v
	scfifo_vid.ip
atunto	mr_rx_iopll_tmds/
	mr_rxphy/
	mr_tx_fpll/
	altera_xcvr_functions.sv
	mr_compare.sv
	mr_rate_detect.v
	mr_rx_rate_detect_top.v
	mr_rx_rcfg_ctrl.v
	mr_rx_reconfig.v
	mr_tx_rate_detect_top.v
	mr_tx_rcfg_ctrl.v
	mr_tx_reconfig.v
	rcfg_array_streamer_iopll.sv
	rcfg_array_streamer_rxphy.sv
	rcfg_array_streamer_rxphy_xn.sv
	rcfg_array_streamer_txphy.sv
	rcfg_array_streamer_txphy_xn.sv
	rcfg_array_streamer_txpll.sv
sdc	a10_hdmi2.sdc
	jtag.sdc

Table 6. ti ipilẹṣẹ Simulation Files
Tọkasi awọn Testbench kikopa apakan fun alaye siwaju sii

Awọn folda	Files
aldec	/aldec.do
	/rivierapro_setup.tcl
oye	/cds.lib
	/hdl.var
olutojueni	/ mentor.do
	/msim_setup.tcl
synopsys	/vcs/fileakojọ.f
	/vcs/vcs_setup.sh

	/vcs/vcs_sim.sh
	/vcsmx/synopsys_sim_setup
	/vcsmx/vcsmx_setup.sh
	/vcsmx/vcsmx_sim.sh
xcelium	/cds.lib
	/hdl.var
	/xcelium_setup.sh
	/xcelium_sim.sh
wọpọ	/ modeli_files.tcl
	/ riviera_files.tcl
	/vcs_files.tcl
	/vcsmx_files.tcl
	/xcelium_files.tcl
hdmi_rx	/hdmi_rx.ip
	/Panasonic.hex
hdmi_tx	/hdmi_tx.ip

Table 7. ti ipilẹṣẹ Software Files

Awọn folda	Files
tx_control_src Akiyesi: Tx_control folda tun ni awọn ẹda-ẹda ti iwọnyi files.	agbaye.h
	hdmi_rx.c
	hdmi_rx.h
	hdmi_tx.c
	hdmi_tx.h
	hdmi_tx_read_edid.c
	hdmi_tx_read_edid.h
	intel_fpga_i2c.c
	intel_fpga_i2c.h
	akọkọ.c
	pio_read_write.c
	pio_read_write.h

2.5. Awọn irinše apẹrẹ
HDMI Intel FPGA IP apẹrẹ example oriširiši awọn wọpọ oke-ipele irinše ati HDMI TX ati RX oke irinše.
2.5.1. HDMI TX irinše
Awọn paati oke HDMI TX pẹlu awọn paati ipele oke TX mojuto, ati IOPLL, oluṣakoso atunto PHY transceiver, transceiver abinibi PHY, TX PLL, iṣakoso atunto TX, ati awọn buffer saarin jade.
olusin 7. HDMI TX Top irinšeTable 8. HDMI TX Top irinše

Modulu	Apejuwe
HDMI TX mojuto	IP naa gba data fidio lati ipele oke ati ṣe ifidipo data iranlọwọ, fifi data ohun ohun, fifi koodu data fidio, scrambling, TMDS koodu tabi packetization.
IOPLL	IOPLL (iopll_frl) ṣe ipilẹṣẹ aago FRL fun mojuto TX. Aago itọkasi yii gba aago iṣejade TX FPL. Igbohunsafẹfẹ aago FRL = Iwọn data fun awọn ọna x 4 / (awọn ohun kikọ FRL fun aago x 18)
Transceiver PHY Tunto Adarí	Oluṣakoso atunto Transceiver PHY ṣe idaniloju ipilẹṣẹ igbẹkẹle ti awọn transceivers TX. Iṣagbewọle atunto ti oludari yii jẹ okunfa lati ipele oke, ati pe o ṣe agbejade afọwọṣe ti o baamu ati ifihan agbara atunto oni-nọmba si bulọki Native PHY Transceiver ni ibamu si ilana atunto inu bulọki naa. Ifihan agbara tx_ready lati bulọki yii tun ṣiṣẹ bi ifihan atunto si HDMI Intel FPGA IP lati tọka transceiver ti wa ni oke ati nṣiṣẹ, ati pe o ti ṣetan lati gba data lati mojuto.
Transceiver abinibi PHY	Lile transceiver Àkọsílẹ ti o gba awọn afiwe data lati HDMI TX mojuto ati serializes awọn data lati atagba o. Akiyesi: Lati pade ibeere skew inter-ikanni HDMI TX, ṣeto aṣayan ipo isọmọ ikanni TX ni Intel Arria 10 Transceiver Native PHY olootu paramita si PMA ati PCS imora. O tun nilo lati ṣafikun ibeere idiwọ ti o pọju skew (set_max_skew) si ifihan agbara atunto oni-nọmba lati ọdọ oluṣakoso atunto transceiver (tx_digitalreset) bi a ṣe iṣeduro ninu Intel Arria 10 Transceiver PHY olumulo Itọsọna.
TX PLL	Awọn Atagba PLL Àkọsílẹ pese ni tẹlentẹle sare aago si Transceiver Native PHY Àkọsílẹ. Fun eyi HDMI Intel FPGA IP apẹrẹ example, fPLL ti lo bi TX PLL. TX PLL ni awọn aago itọkasi meji. Aago itọkasi 0 ti sopọ si oscillator ti siseto (pẹlu igbohunsafẹfẹ aago TMDS) fun ipo TMDS. Ninu apẹrẹ yii example, Aago RX TMDS ni a lo lati sopọ si aago itọkasi 0 fun ipo TMDS. Intel ṣeduro ọ lati lo oscillator ti eto pẹlu igbohunsafẹfẹ aago TMDS fun aago itọkasi 0. • Aago itọkasi 1 ti sopọ si aago 100 MHz ti o wa titi fun ipo FRL.
TX Reconfiguration Management	• Ni ipo TMDS, bulọki iṣakoso atunto TX ṣe atunto TX PLL fun awọn igbohunsafẹfẹ aago ti o yatọ ni ibamu si igbohunsafẹfẹ aago TMDS ti fidio kan pato. • Ni ipo FRL, bulọki iṣakoso atunto TX ṣe atunto TX PLL lati pese aago iyara ni tẹlentẹle fun 3 Gbps, 6 Gbps, 8 Gbps, 10 Gbps ati 12 Gbps ni ibamu si aaye FRL_Rate ninu iforukọsilẹ 0x31 SCDC. • Àkọsílẹ iṣakoso atunto TX yipada aago itọkasi TX PLL laarin aago itọkasi 0 fun ipo TMDS ati aago itọkasi 1 fun ipo FRL.
Idaduro ti o wu jade	Ifipamọ yii n ṣiṣẹ bi wiwo lati ṣe ajọṣepọ wiwo I2C ti HDMI DDC ati awọn paati atunṣe.

Table 9.Transceiver Data Rate ati Oversampling ifosiwewe Kọọkan Aago Igbohunsafẹfẹ Range

Ipo	Data Oṣuwọn	oversampler 1 (2x oversample)	oversampler 2 (4x oversample)	oversample Okunfa	oversampOṣuwọn data idari (Mbps)
TMDS	250–1000	On	On	8	2000–8000
TMDS	1000–6000	On	Paa	2	2000–12000
FRL	3000	Paa	Paa	1	3000
FRL	6000	Paa	Paa	1	6000

FRL	8000	Paa	Paa	1	8000
FRL	10000	Paa	Paa	1	10000
FRL	12000	Paa	Paa	1	12000

olusin 8. TX Reconfiguration Ọkọọkan Sisan2.5.2. HDMI RX irinše
Awọn paati oke HDMI RX pẹlu awọn paati ipele oke RX mojuto, ẹru I²C iyan ati EDID Ramu, IOPLL, oluṣakoso atunto PHY transceiver, PHY abinibi RX, ati awọn bulọọki iṣakoso atunto RX.
olusin 9. HDMI RX Top irinšeTable 10. HDMI RX Top irinše

Modulu	Apejuwe
HDMI RX mojuto	IP naa gba data ni tẹlentẹle lati ọdọ Transceiver Native PHY ati ṣe titete data, deskew ikanni, iyipada TMDS, iyipada data iranlọwọ, iyipada data fidio, iyipada data ohun, ati sisọnu.
I2C Ẹrú	I2C ni wiwo ti a lo fun Ikanni Ifihan Data Ibẹrẹ (DDC) ati Ipo ati ikanni Data (SCDC). Orisun HDMI nlo DDC lati pinnu awọn agbara ati awọn abuda ti ifọwọ nipa kika Imudara Imudara Ifihan Identification Data (E-EDID). Awọn adirẹsi 8-bit I2C ẹrú fun E-EDID jẹ 0xA0 ati 0xA1. LSB tọkasi iru wiwọle: 1 fun kika ati 0 fun kikọ. Nigbati iṣẹlẹ HPD kan ba waye, ẹrú I2C ṣe idahun si data E-EDID nipa kika lati ori-chip Adarí ẹrú-nikan I2C tun ṣe atilẹyin SCDC fun HDMI 2.0 ati 2.1 Adirẹsi ẹrú I9C 2-bit fun SCDC jẹ 0xA8 ati 0xA9. Nigbati iṣẹlẹ HPD kan ba waye, ẹru I2C ṣe kikọ tabi ka idunadura si tabi lati wiwo SCDC ti HDMI RX mojuto. Ilana ikẹkọ ọna asopọ fun Ọna asopọ Oṣuwọn Ti o wa titi (FRL) tun ṣẹlẹ nipasẹ I2C Lakoko iṣẹlẹ HPD kan tabi nigbati orisun ba kọ oṣuwọn FRL ti o yatọ si iforukọsilẹ Oṣuwọn FRL (SCDC forukọsilẹ 0x31 bit[3: 0]), ilana ikẹkọ ọna asopọ bẹrẹ. Akiyesi: Adarí ẹrú-nikan I2C fun SCDC ko nilo ti HDMI 2.0 tabi HDMI 2.1 ko ba pinnu

EDID Ramu

Apẹrẹ naa tọju alaye EDID nipa lilo Ramu 1-Port IP. A boṣewa meji- waya (aago ati data) tẹlentẹle akero bèèrè (I2C ẹrú-nikan oludari) gbigbe CEA-861-D ni ifaramọ E-EDID data be. RAM EDID yii tọju alaye E-EDID naa. • Nigbati o wa ni ipo TMDS, apẹrẹ ṣe atilẹyin EDID passthrough lati TX si RX. Nigba EDID passthrough, nigbati TX ti wa ni ti sopọ si ita ifọwọ, Nios II isise kika EDID lati ita ifọwọ ati ki o kọwe si EDID Ramu. • Nigbati o ba wa ni ipo FRL, ero isise Nios II kọ EDID ti a ti ṣeto tẹlẹ fun oṣuwọn ọna asopọ kọọkan ti o da lori paramita HDMI_RX_MAX_FRL_RATE ninu iwe afọwọkọ global.h. Lo awọn igbewọle HDMI_RX_MAX_FRL_RATE wọnyi fun oṣuwọn FRL ti o ni atilẹyin: • 1: 3G 3 Awọn ọna • 2: 6G 3 Awọn ọna •3: 6G 4 Awọn ọna • 4: 8G 4 Awọn ọna •5: Awọn ọna 10G 4 (aiyipada) •6: 12G 4 Awọn ọna

IOPLL

HDMI RX nlo awọn IOPLL meji. • IOPLL akọkọ (pll_tmds) ṣe ipilẹṣẹ aago itọkasi RX CDR. IOPLL yii jẹ lilo nikan ni ipo TMDS. Aago itọkasi ti IOPLL yii gba aago TMDS. Ipo TMDS nlo IOPLL yii nitori CDR ko le gba awọn aago itọkasi ni isalẹ 50 MHz ati awọn sakani igbohunsafẹfẹ aago TMDS lati 25 MHz si 340 MHz. IOPLL yii n pese igbohunsafẹfẹ aago ti o jẹ awọn akoko 5 ti aago itọkasi titẹ sii fun iwọn igbohunsafẹfẹ laarin 25 MHz si 50 MHz ati pese igbohunsafẹfẹ aago kanna gẹgẹbi aago itọkasi titẹ sii fun iwọn igbohunsafẹfẹ laarin 50 MHz si 340 MHz. • IOPLL keji (iopll_frl) n ṣe agbejade aago FRL fun mojuto RX. Aago itọkasi yii gba aago CDR ti o gba pada. Igbohunsafẹfẹ aago FRL = Iwọn data fun awọn ọna x 4 / (awọn ohun kikọ FRL fun aago x 18)

Transceiver PHY Tunto Adarí	Oluṣakoso atunto Transceiver PHY ṣe idaniloju ipilẹṣẹ igbẹkẹle ti awọn transceivers RX. Iṣagbewọle atunto ti oludari yii jẹ okunfa nipasẹ atunto RX, ati pe o ṣe agbekalẹ afọwọṣe ti o baamu ati ifihan agbara atunto oni-nọmba si bulọki Native PHY Transceiver ni ibamu si ilana atunto inu bulọọki naa.
PHY abinibi RX	Dina transceiver lile ti o gba data ni tẹlentẹle lati orisun fidio ita. O deserializes data ni tẹlentẹle si data afiwera ṣaaju gbigbe data naa si mojuto HDMI RX. Àkọsílẹ yii nṣiṣẹ lori PCS Imudara fun ipo FRL. RX CDR ni awọn aago itọkasi meji. • Aago itọkasi 0 ti sopọ si aago iṣejade ti IOPLL TMDS (pll_tmds), eyiti o jẹyọ lati aago TMDS. • Aago itọkasi 1 ti sopọ si aago 100 MHz ti o wa titi. Ni ipo TMDS, RX CDR jẹ atunto lati yan aago itọkasi 0, ati ni ipo FRL, RX CDR ti tunto lati yan aago itọkasi 1.
RX Reconfiguration Management	Ni ipo TMDS, bulọki iṣakoso atunto RX n ṣe adaṣe wiwa oṣuwọn pẹlu HDMI PLL lati wakọ transceiver RX lati ṣiṣẹ ni awọn oṣuwọn ọna asopọ lainidii eyikeyi ti o wa lati 250 Mbps si 6,000 Mbps. Ni ipo FRL, bulọki iṣakoso atunto RX ṣe atunto transceiver RX lati ṣiṣẹ ni 3 Gbps, 6 Gbps, 8 Gbps, 10 Gbps, tabi 12 Gbps da lori iwọn FRL ni aaye iforukọsilẹ SCDC_FRL_RATE (0x31[3:0]). Awọn iyipada iṣakoso atunto RX laarin PCS/RX Standard fun ipo TMDS ati PCS Imudara fun ipo FRL. Tọkasi si Olusin 10 loju iwe 22.

olusin 10. RX Reconfiguration Ọkọọkan Sisan
Nọmba naa ṣe afihan ṣiṣan isọdọtun iwọn-ọpọlọpọ ti oluṣakoso nigbati o gba ṣiṣan data titẹ sii ati igbohunsafẹfẹ aago itọkasi, tabi nigbati transceiver ti wa ni ṣiṣi silẹ.2.5.3. Top-Level wọpọ ohun amorindun
Awọn bulọọki ti o wọpọ ni ipele oke pẹlu arbiter transceiver, awọn paati ọna asopọ RX-TX, ati eto inu Sipiyu.
Table 11. Top-Level wọpọ ohun amorindun

Modulu

Apejuwe

Arbiter Transceiver

Àkọsílẹ iṣẹ-ṣiṣe jeneriki yii ṣe idilọwọ awọn transceivers lati tun ṣe atunṣe nigbakanna nigbati boya RX tabi TX transceivers laarin ikanni ti ara kanna nilo atunto. Atunṣe atunṣe nigbakanna ni ipa awọn ohun elo nibiti RX ati TX transceivers laarin ikanni kanna ni a yàn si awọn imuse IP ominira. Arbiter transceiver yii jẹ itẹsiwaju si ipinnu ti a ṣeduro fun didapọ simplex TX ati simplex RX sinu ikanni ti ara kanna. Arbiter transceiver yii tun ṣe iranlọwọ ni sisọpọ ati ṣiṣe idajọ iranti Avalon® ti o ya aworan RX ati awọn ibeere atunto TX ti o fojusi simplex RX ati awọn transceivers TX laarin ikanni kan bi ibudo wiwo atunto atunto ti awọn transceivers le wọle nikan ni atẹlera. Asopọ ni wiwo laarin transceiver arbiter ati TX/RX Native PHY/PHY Awọn ohun amorindun Oluṣeto atunto ninu apẹrẹ apẹrẹ yiiample ṣe afihan ipo jeneriki kan ti o kan fun eyikeyi apapo IP nipa lilo arbiter transceiver. Oluranlọwọ transceiver ko nilo nigbati boya RX tabi transceiver TX nikan lo ni ikanni kan. Arbiter transceiver n ṣe idanimọ olubẹwẹ ti atunto nipasẹ awọn atọkun atunto atunto Avalon iranti rẹ ati rii daju pe tx_reconfig_cal_busy ti o baamu tabi rx_reconfig_cal_busy ti wa ni ibamu. Fun awọn ohun elo HDMI, RX nikan bẹrẹ atunto. Nipa a ikanni Avalon iranti-mapped atunto ìbéèrè nipasẹ awọn arbiter, arbiter man wipe atunto ìbéèrè wa lati RX, eyi ti lẹhinna ibode tx_reconfig_cal_busy lati asserting ati ki o gba rx_reconfig_cal_busy lati so. Gating ṣe idiwọ transceiver TX lati gbe lọ si ipo isọdi laimọ-imọ. Akiyesi: Nitori HDMI nikan nilo atunto RX, awọn ifihan agbara tx_reconfig_mgmt_* ti so ni pipa. Paapaa, wiwo Avalon ti o ya aworan ko nilo laarin arbiter ati TX Native PHY Àkọsílẹ. Awọn ohun amorindun ti wa ni sọtọ si wiwo ni awọn oniru example ṣe afihan asopọ arbiter transceiver jeneriki si TX/RX Abinibi PHY/Aṣakoso Tunto PHY

RX-TX ọna asopọ

• Ijade data fidio ati awọn ifihan agbara amuṣiṣẹpọ lati HDMI RX core loop nipasẹ DCFIFO kọja awọn agbegbe aago fidio RX ati TX. • Ibudo data iranlọwọ ti HDMI TX mojuto n ṣakoso awọn alaye iranlọwọ ti o nṣàn nipasẹ DCFIFO nipasẹ ẹhin ẹhin. Igbẹhin ẹhin ṣe idaniloju pe ko si apo-iranlọwọ ti ko pe lori ibudo data iranlọwọ. • Àkọsílẹ yii tun ṣe sisẹ ita: - Ajọ data ohun ati apo isọdọtun aago ohun lati ṣiṣan data iranlọwọ ṣaaju gbigbe si ibudo data iranlọwọ mojuto HDMI TX. - Ajọ Ibiti Yiyi to gaju (HDR) Alaye lati inu data iranlọwọ HDMI RX ati fi sii tẹlẹample HDR InfoFrame si data iranlọwọ ti HDMI TX nipasẹ Avalon streaming multiplexer.

Sipiyu Subsystem

Eto inu Sipiyu n ṣiṣẹ bi SCDC ati awọn oludari DDC, ati oludari atunto orisun. • Oluṣakoso SCDC orisun ni oludari I2C titunto si. Adarí titunto si I2C n gbe igbekalẹ data SCDC lati orisun FPGA si ifọwọ ita fun iṣẹ HDMI 2.0. Fun example, ti o ba ti njade data san ni 6,000 Mbps, Nios II isise paṣẹ fun awọn I2C titunto si oludari lati mu awọn TMDS_BIT_CLOCK_RATIO ati SCRAMBLER_ENABLE die-die ti awọn rii TMDS iṣeto ni forukọsilẹ to 1. • Titunto si I2C kanna tun n gbe ilana data DDC (E-EDID) laarin orisun HDMI ati ifọwọ ita. • Nios II Sipiyu n ṣiṣẹ bi oluṣakoso atunto fun orisun HDMI. Sipiyu da lori wiwa oṣuwọn igbakọọkan lati inu module Iṣakoso Atunto RX lati pinnu boya TX nilo atunto. Olutumọ ẹrú ti a ṣe aworan iranti Avalon n pese wiwo laarin ero isise Nios II Avalon ni wiwo titunto si iranti-mapped ati awọn atọkun ẹru Avalon iranti-maapu ti ita HDMI orisun IOPLL ati TX Native PHY. • Ṣe ikẹkọ ọna asopọ nipasẹ wiwo oluwa I2C pẹlu ifọwọ ita

2.6. Yiyi to Range ati Mastering (HDR) InfoFrame Fi sii ati Sisẹ
HDMI Intel FPGA IP apẹrẹ example pẹlu ifihan ti fifi sii HDR InfoFrame sinu eto loopback RX-TX kan.
Ẹya Sipesifikesonu HDMI 2.0b ngbanilaaye Range Yiyi ati Mastering InfoFrame lati tan kaakiri nipasẹ ṣiṣan iranlọwọ HDMI. Ninu ifihan, idinamọ Packet Oluranlọwọ ṣe atilẹyin ifibọ HDR. O nilo nikan lati ṣe ọna kika apo-iwe InfoFrame HDR ti a pinnu gẹgẹbi pato ninu tabili atokọ ifihan module ati fifi sii HDR InfoFrame waye lẹẹkan ni gbogbo fireemu fidio.
Ninu example iṣeto ni, ni awọn igba ibi ti awọn ti nwọle san oluranlowo tẹlẹ pẹlu HDR InfoFrame, awọn san HDR akoonu ti wa ni filtered. Sisẹ naa yago fun ilodisi HDR InfoFrames lati tan kaakiri ati rii daju pe awọn iye ti o pato ninu HDR Sample Data module ti wa ni lilo.
Nọmba 11. Ọna asopọ RX-TX pẹlu Ibiti Yiyiyi ati Titẹ sii InfoFrame Mastering
Nọmba naa ṣe afihan aworan atọka ti ọna asopọ RX-TX pẹlu Ibiti Yiyiyi ati fifi sii InfoFrame Mastering sinu ṣiṣan iranlọwọ mojuto HDMI TX.Table 12. Iranlọwọ Data ifibọ Block (aux_retransmit) awọn ifihan agbara

Ifihan agbara	Itọsọna	Ìbú	Apejuwe
Aago ati Tunto
clk	Iṣawọle	1	Iṣagbewọle aago. Aago yii yẹ ki o sopọ mọ aago fidio.
tunto	Iṣawọle	1	Tun igbewọle to.

Awọn ifihan agbara Packet Iranlọwọ
tx_aux_data	Abajade	72	Iṣjade apo-iranlọwọ TX lati multiplexer.
tx_aux_valid	Abajade	1
tx_aux_ṣetan	Abajade	1
tx_aux_sop	Abajade	1
tx_aux_eop	Abajade	1
rx_aux_data	Iṣawọle	72	Awọn data Iranlọwọ RX kọja si module àlẹmọ apo-iwe ṣaaju titẹ sii multiplexer.
rx_aux_valid	Iṣawọle	1
rx_aux_sop	Iṣawọle	1
rx_aux_eop	Iṣawọle	1

Iṣakoso Signal
hdmi_tx_vsync	Iṣawọle	1	HDMI TX Video Vsync. Ifihan agbara yii yẹ ki o muuṣiṣẹpọ si agbegbe aago iyara ọna asopọ. Ipilẹ ti nfi HDR InfoFrame si ṣiṣan iranlọwọ ni eti ti o dide ti ifihan agbara yii.

Tabili 13. HDR Data Module (altera_hdmi_hdr_infoframe) Awọn ifihan agbara

Ifihan agbara	Itọsọna	Ìbú	Apejuwe
hb0	Abajade	8	Baiti akọsori 0 ti Ibiti Yiyiyi ati Mastering InfoFrame: InfoFrame iru koodu.
hb1	Abajade	8	Baiti akọsori 1 ti Ibiti Yiyiyi ati Mastering InfoFrame: Nọmba ẹya InfoFrame.
hb2	Abajade	8	Baiti akọsori 2 ti Ibiti Yiyiyi ati Mastering InfoFrame: Gigun InfoFrame.
pb	Iṣawọle	224	Data baiti ti Yiyi to Range ati Mastering InfoFrame.

Tabili 14. Yiyipo Ibiti ati Mastering InfoFrame Data Baiti Bundle Bit-Fields

Bit-Field	Itumọ	Metadata Aimi Iru 1
7:0	Data Baiti 1: {5'h0, EOTF[2:0]}
15:8	Data Baiti 2: {5'h0, Static_Metadata_Descriptor_ID[2:0]}
23:16	Data Baiti 3: Static_Metadata_Descriptor	display_primaries_x [0], LSB
31:24	Data Baiti 4: Static_Metadata_Descriptor	display_primaries_x [0], MSB
39:32	Data Baiti 5: Static_Metadata_Descriptor	display_primaries_y [0], LSB
47:40	Data Baiti 6: Static_Metadata_Descriptor	display_primaries_y [0], MSB
55:48	Data Baiti 7: Static_Metadata_Descriptor	display_primaries_x [1], LSB
63:56	Data Baiti 8: Static_Metadata_Descriptor	display_primaries_x [1], MSB
71:64	Data Baiti 9: Static_Metadata_Descriptor	display_primaries_y [1], LSB
79:72	Data Baiti 10: Static_Metadata_Descriptor	display_primaries_y [1], MSB
87:80	Data Baiti 11: Static_Metadata_Descriptor	display_primaries_x [2], LSB
95:88	Data Baiti 12: Static_Metadata_Descriptor	display_primaries_x [2], MSB
103:96	Data Baiti 13: Static_Metadata_Descriptor	display_primaries_y [2], LSB
111:104	Data Baiti 14: Static_Metadata_Descriptor	display_primaries_y [2], MSB
119:112	Data Baiti 15: Static_Metadata_Descriptor	white_point_x, LSB
127:120	Data Baiti 16: Static_Metadata_Descriptor	white_point_x, MSB
135:128	Data Baiti 17: Static_Metadata_Descriptor	funfun_point_y, LSB
143:136	Data Baiti 18: Static_Metadata_Descriptor	funfun_point_y, MSB
151:144	Data Baiti 19: Static_Metadata_Descriptor	max_display_mastering_luminance, LSB

159:152	Data Baiti 20: Static_Metadata_Descriptor	max_display_mastering_luminance, MSB
167:160	Data Baiti 21: Static_Metadata_Descriptor	min_display_mastering_luminance, LSB
175:168	Data Baiti 22: Static_Metadata_Descriptor	min_display_mastering_luminance, MSB
183:176	Data Baiti 23: Static_Metadata_Descriptor	Ipele Imọlẹ Akoonu ti o pọju, LSB
191:184	Data Baiti 24: Static_Metadata_Descriptor	Ipele Imọlẹ Akoonu ti o pọju, MSB
199:192	Data Baiti 25: Static_Metadata_Descriptor	Ipele Imọlẹ Apapọ fireemu ti o pọju, LSB
207:200	Data Baiti 26: Static_Metadata_Descriptor	Ipele Imọlẹ Apapọ Iwọn fireemu, MSB
215:208	Ni ipamọ
223:216	Ni ipamọ

Pa HDR Fi sii ati Sisẹ
Pa ifibọ HDR ati àlẹmọ jẹ ki o rii daju gbigbejade ti akoonu HDR ti o wa tẹlẹ ninu ṣiṣan iranlọwọ orisun laisi iyipada eyikeyi ninu apẹrẹ Retransmit RX-TX example.
Lati mu ifibọ InfoFrame HDR ṣiṣẹ ati sisẹ:

1. Ṣeto block_ext_hdr_infoframe si 1'b0 ninu rxtx_link.v file lati ṣe idiwọ sisẹ ti HDR InfoFrame lati ṣiṣan Iranlọwọ.
2. Ṣeto multiplexer_in0_valid ti apẹẹrẹ avalon_st_multiplexer ni altera_hdmi_aux_hdr.v file si 1'b0 lati ṣe idiwọ Olupilẹṣẹ Packet Oluranlọwọ lati dida ati fifi sii HDR InfoFrame ni afikun sinu ṣiṣan Auxiliary TX.

2.7. Ṣiṣan Software oniru
Ninu ṣiṣan sọfitiwia akọkọ apẹrẹ, ero isise Nios II tunto eto atunṣe TI ati ṣe ipilẹṣẹ awọn ọna TX ati RX lori agbara-soke.
olusin 12. Software Sisan ni main.c Script
Sọfitiwia naa ṣiṣẹ lupu igba diẹ lati ṣe atẹle ifọwọ ati awọn ayipada orisun, ati lati fesi si awọn ayipada. Sọfitiwia naa le fa atunto TX, ikẹkọ ọna asopọ TX ati bẹrẹ gbigbe fidio.
olusin 13. TX Path Initialization Flowchart Initialize TX Patholusin 14. RX Path Initialization FlowchartṢe nọmba 15. TX Reconfiguration ati Link Training FlowchartṢe nọmba 16. Ikẹkọ Ọna asopọ LTS: Ilana 3 ni Specific Rate Flowchart FRLolusin 17. HDMI TX Video Gbigbe Flowchart2.8. Ṣiṣe Apẹrẹ ni Awọn Oṣuwọn FRL oriṣiriṣi
O le ṣe apẹrẹ rẹ ni oriṣiriṣi awọn oṣuwọn FRL, miiran ju iwọn FRL aiyipada rii ita.
Lati ṣiṣẹ apẹrẹ ni oriṣiriṣi awọn oṣuwọn FRL:

1. Yipada on-board user_dipsw0 yipada si ON ipo.
2. Ṣi ikarahun aṣẹ Nios II, lẹhinna tẹ nios2-terminal
3. Bọtini ninu awọn aṣẹ atẹle ki o tẹ Tẹ lati ṣiṣẹ.

Òfin	Apejuwe
h	Ṣe afihan akojọ iranlọwọ.
r0	Ṣe imudojuiwọn agbara FRL ti o pọju RX si oṣuwọn FRL (TMDS nikan).
r1	Ṣe imudojuiwọn agbara FRL ti o pọju RX si oṣuwọn FRL 1 (3 Gbps).
r2	Ṣe imudojuiwọn agbara FRL ti o pọju RX si oṣuwọn FRL 2 (6 Gbps, awọn ọna 3).
r3	Ṣe imudojuiwọn agbara FRL ti o pọju RX si oṣuwọn FRL 3 (6 Gbps, awọn ọna 4).
r4	Ṣe imudojuiwọn agbara FRL ti o pọju RX si oṣuwọn FRL 4 (8 Gbps).
r5	Ṣe imudojuiwọn agbara FRL ti o pọju RX si oṣuwọn FRL 5 (10 Gbps).
r6	Ṣe imudojuiwọn agbara FRL ti o pọju RX si oṣuwọn FRL 6 (12 Gbps).
t1	TX ṣe atunto oṣuwọn ọna asopọ si oṣuwọn FRL 1 (3 Gbps).
t2	TX ṣe atunto oṣuwọn ọna asopọ si oṣuwọn FRL 2 (6 Gbps, awọn ọna 3).
t3	TX ṣe atunto oṣuwọn ọna asopọ si oṣuwọn FRL 3 (6 Gbps, awọn ọna 4).
t4	TX ṣe atunto oṣuwọn ọna asopọ si oṣuwọn FRL 4 (8 Gbps).
t5	TX ṣe atunto oṣuwọn ọna asopọ si oṣuwọn FRL 5 (10 Gbps).
t6	TX ṣe atunto oṣuwọn ọna asopọ si oṣuwọn FRL 6 (12 Gbps).

2.9. Eto aago
Eto clocking ṣe apejuwe awọn ibugbe aago ni HDMI Intel FPGA IP apẹrẹ example.
olusin 18. HDMI 2.1 Design Example clocking EroTable 15. clocking Ero awọn ifihan agbara

Aago	Orukọ ifihan agbara ni Apẹrẹ	Apejuwe
Aago isakoso	mgmt_clk	Aago 100 MHz nṣiṣẹ ọfẹ fun awọn paati wọnyi: • Avalon-MM atọkun fun atunto - Ibeere iwọn igbohunsafẹfẹ wa laarin 100-125 MHz. • Adarí atunto PHY fun ọna atunto transceiver - Ibeere iwọn igbohunsafẹfẹ wa laarin 1-500 MHz. • IOPLL atunto - Awọn ti o pọju aago igbohunsafẹfẹ jẹ 100 MHz. • RX Reconfiguration Management • TX Reconfiguration Management • Sipiyu • I2C Titunto
I2C aago	i2c_clk	Iṣawọle aago 100 MHz kan ti o ṣe aago ẹrú I2C, awọn buffers jade, awọn iforukọsilẹ SCDC, ati ilana ikẹkọ ọna asopọ ni HDMI RX mojuto, ati EDID Ramu.
Aago Itọkasi TX PLL 0	tx_tmds_clk	Aago itọkasi 0 si TX PLL. Igbohunsafẹfẹ aago jẹ kanna bi igbohunsafẹfẹ aago TMDS ti a reti lati ikanni aago HDMI TX TMDS. Aago itọkasi yii jẹ lilo ni ipo TMDS. Fun apẹrẹ HDMI yii example, yi aago ti wa ni ti sopọ si RX TMDS aago fun ifihan idi. Ninu ohun elo rẹ, o nilo lati pese aago iyasọtọ pẹlu igbohunsafẹfẹ aago TMDS lati oscillator ti siseto fun iṣẹ jitter to dara julọ.

		Akiyesi: Maṣe lo pin RX transceiver bi aago itọkasi TX PLL. Apẹrẹ rẹ yoo kuna lati baamu ti o ba gbe HDMI TX refclk sori pin RX kan.
Aago Itọkasi TX PLL 1	txfpll_refclk1 / rxphy_cdr_refclk1	Aago itọkasi si TX PLL ati RX CDR, bakanna bi IOPLL fun vid_clk. Igbohunsafẹfẹ aago jẹ 100 MHz.
TX PLL Aago Serial	tx_bonding_clocks	Serial fast aago ti ipilẹṣẹ nipasẹ TX PLL. Igbohunsafẹfẹ aago ti ṣeto da lori data oṣuwọn.
TX Transceiver Aago Jade	tx_clk	Aago jade ti o gba pada lati transceiver, ati igbohunsafẹfẹ yatọ da lori data oṣuwọn ati awọn aami fun aago. Aago transceiver TX jade igbohunsafẹfẹ = Oṣuwọn data oluyipada/Iwọn olugba Fun apẹrẹ HDMI yii example, TX transceiver aago jade lati ikanni 0 titobi TX transceiver mojuto input (tx_coreclkin), ọna asopọ iyara IOPLL (pll_hdmi) itọkasi aago, ati fidio ati FRL IOPLL (pll_vid_frl) itọkasi aago.
Aago fidio	tx_vid_clk/rx_vid_clk	Aago fidio si TX ati RX mojuto. Aago naa nṣiṣẹ ni igbohunsafẹfẹ ti o wa titi ti 225 MHz.
TX/RX FRL Aago	tx_frl_clk/rx_frl_clk	Aago FRL si fun TX ati RX mojuto.
Aago RX TMDS	rx_tmds_clk	TMDS aago ikanni lati HDMI RX asopo ohun ati ki o sopọ si ohun IOPLL lati se ina awọn itọkasi aago fun CDR itọkasi aago 0. Awọn mojuto nlo yi aago nigbati o wa ni TMDS mode.
Aago Itọkasi RX CDR 0	rxphy_cdr_refclk0	Aago itọkasi 0 si RX CDR. Aago yii wa lati aago RX TMDS. Awọn ipo igbohunsafẹfẹ aago RX TMDS lati 25 MHz si 340 MHz lakoko ti igbohunsafẹfẹ aago itọkasi RX CDR ti o kere ju jẹ 50 MHz. A lo IOPLL lati ṣe ina igbohunsafẹfẹ aago marun fun aago TMDS laarin 5 MHz si 25 MHz ati ṣe ina igbohunsafẹfẹ aago kanna fun aago TMDS laarin 50 MHz – 50 MHz.
Aago Transceiver RX Jade	rx_clk	Aago jade ti o gba pada lati transceiver, ati awọn igbohunsafẹfẹ yatọ da lori awọn data oṣuwọn ati transceiver iwọn. Aago transceiver RX jade igbohunsafẹfẹ = Oṣuwọn data oluyipada/Iwọn olugba Fun apẹrẹ HDMI yii example, RX transceiver aago jade lati ikanni 1 aago RX transceiver mojuto input (rx_coreclkin) ati FRL IOPLL (pll_frl) itọkasi aago.

2.10. Awọn ifihan agbara wiwo
Awọn tabili ṣe atokọ awọn ifihan agbara fun apẹrẹ HDMI example pẹlu FRL ṣiṣẹ.
Table 16. Top-Level awọn ifihan agbara

Ifihan agbara	Itọsọna	Ìbú	Apejuwe
Lori-ọkọ Oscillator Signal
clk_fpga_b3_p	Iṣawọle	1	100 MHz free nṣiṣẹ aago fun mojuto itọkasi aago.
refclk4_p	Iṣawọle	1	100 MHz free nṣiṣẹ aago fun transceiver itọkasi aago.

Awọn bọtini Titari olumulo ati Awọn LED
olumulo_pb	Iṣawọle	3	Bọtini Titari lati ṣakoso iṣẹ apẹrẹ IP HDMI Intel FPGA.
cpu_resetn	Iṣawọle	1	Atunto agbaye.
olumulo_led_g	Abajade	8	Green LED àpapọ. Tọkasi si Hardware Oṣo loju iwe 48 fun alaye siwaju sii nipa awọn LED awọn iṣẹ.
olumulo_dipsw	Iṣawọle	1	Olumulo-telẹ DIP yipada. Tọkasi si Hardware Oṣo loju iwe 48 fun alaye siwaju sii nipa awọn iṣẹ yipada DIP.

Awọn pinni Kaadi Ọmọbinrin HDMI FMC lori Port B
fmcb_gbtclk_m2c_p_0	Iṣawọle	1	HDMI RX TMDS aago.
fmcb_dp_m2c_p	Iṣawọle	4	Aago HDMI RX, pupa, alawọ ewe, ati awọn ikanni data bulu.
fmcb_dp_c2m_p	Abajade	4	Aago HDMI TX, pupa, alawọ ewe, ati awọn ikanni data bulu.
fmcb_la_rx_p_9	Iṣawọle	1	HDMI RX + 5V agbara iwari.
fmcb_la_rx_p_8	Abajade	1	HDMI RX gbona plug iwari.
fmcb_la_rx_n_8	Iṣawọle	1	HDMI RX I2C SDA fun DDC ati SCDC.
fmcb_la_tx_p_10	Iṣawọle	1	HDMI RX I2C SCL fun DDC ati SCDC.
fmcb_la_tx_p_12	Iṣawọle	1	HDMI TX gbona plug iwari.
fmcb_la_tx_n_12	Iṣawọle	1	HDMI I2C SDA fun DDC ati SCDC.
fmcb_la_rx_p_10	Iṣawọle	1	HDMI I2C SCL fun DDC ati SCDC.
fmcb_la_tx_n_9	Iṣawọle	1	HDMI I2C SDA fun iṣakoso atunṣe.
fmcb_la_rx_p_11	Iṣawọle	1	HDMI I2C SCL fun iṣakoso atunṣe.
fmcb_la_tx_n_13	Abajade	1	HDMI TX +5V Akiyesi: Nikan wa nigbati Biec HDMI Atunyẹwo Kaadi Ọmọbinrin 9 ti yan.

Table 17. HDMI RX Top-Level awọn ifihan agbara

Ifihan agbara	Itọsọna	Ìbú	Apejuwe
Aago ati Tun awọn ifihan agbara
mgmt_clk	Iṣawọle	1	Iṣagbewọle aago eto (100 MHz).
tunto	Iṣawọle	1	Iṣagbewọle atunto eto.
rx_tmds_clk	Iṣawọle	1	HDMI RX TMDS aago.
i2c_clk	Iṣawọle	1	Iṣagbewọle aago fun DDC ati wiwo SCDC.

Aago ati Tun awọn ifihan agbara
rxphy_cdr_refclk1	Iṣawọle	1	Iṣagbewọle aago fun aago itọkasi RX CDR 1. Igbohunsafẹfẹ aago jẹ 100 MHz.
rx_vid_clk	Abajade	1	Ijade aago fidio.
sys_init	Abajade	1	Ipilẹṣẹ eto lati tun eto naa sori agbara-soke.

Transceiver RX ati awọn ifihan agbara IOPLL
rxpll_tmds_locked	Abajade	1	Tọkasi aago TMDS IOPLL ti wa ni titiipa.
rxpll_frl_locked	Abajade	1	Tọkasi aago FRL IOPLL ti wa ni titiipa.
rxphy_serial_data	Iṣawọle	4	HDMI ni tẹlentẹle data si awọn RX Native PHY.
rxphy_ṣetan	Abajade	1	Tọkasi RX Abinibi PHY ti ṣetan.
rxphy_cal_busy_raw	Abajade	4	RX Native PHY odiwọn nšišẹ si transceiver arbiter.
rxphy_cal_busy_gated	Iṣawọle	4	Iṣatunṣe iwọntunwọnsi nšišẹ lati ọdọ olutọpa transceiver si RX Native PHY.
rxphy_rcfg_slave_write	Iṣawọle	4	Transceiver atunto Avalon iranti-mapped ni wiwo lati RX Native PHY si transceiver arbiter.
rxphy_rcfg_slave_read	Iṣawọle	4
rxphy_rcfg_slave_adirẹsi	Iṣawọle	40
rxphy_rcfg_slave_writedata	Iṣawọle	128
rxphy_rcfg_slave_readata	Abajade	128
ibeere rxphy_rcfg_slave_waitrequest	Abajade	4

RX Reconfiguration Management
rxphy_rcfg_busy	Abajade	1	RX Reconfiguration nšišẹ ifihan agbara.
rx_tmds_freq	Abajade	24	HDMI RX TMDS aago igbohunsafẹfẹ wiwọn (ni 10 ms).
rx_tmds_freq_valid	Abajade	1	Tọkasi wiwọn igbohunsafẹfẹ aago RX TMDS wulo.
rxphy_os	Abajade	1	oversampifosiwewe ling: •0: 1x juampling • 1:5× oversampling
rxphy_rcfg_master_write	Abajade	1	RX reconfiguration isakoso Avalon iranti-mapped ni wiwo to transceiver arbiter.
rxphy_rcfg_master_read	Abajade	1
rxphy_rcfg_master_adirẹsi	Abajade	12
rxphy_rcfg_master_writedata	Abajade	32
rxphy_rcfg_master_readdata	Iṣawọle	32
rxphy_rcfg_master_waitrequest	Iṣawọle	1

HDMI RX mojuto awọn ifihan agbara
rx_vid_clk_locked	Iṣawọle	1	Tọkasi vid_clk jẹ iduroṣinṣin.
rxcore_frl_oṣuwọn	Abajade	4	Tọkasi oṣuwọn FRL ti RX mojuto nṣiṣẹ. • 0: Ipo Legacy (TMDS) • 1: 3 Gbps 3 ona • 2: 6 Gbps 4 ona • 3: 6 Gbps 4 ona • 4: 8 Gbps 4 ona • 5: 10 Gbps 4 ona • 6: 12 Gbps 4 ona • 7-15: Ni ipamọ
rxcore_frl_locked	Abajade	4	Kọọkan bit tọkasi ọna kan pato ti o ti ṣaṣeyọri titiipa FRL. FRL ti wa ni titiipa nigbati RX mojuto ni aṣeyọri ṣe titete, deskew, ati ṣaṣeyọri titiipa ọna. • Fun ipo ọna 3, titiipa ọna ti waye nigbati RX mojuto gba Scrambler Reset (SR) tabi Start-Super-Block (SSB) fun gbogbo awọn akoko kikọ 680 FRL fun o kere ju awọn akoko 3. • Fun ipo ọna 4, titiipa ọna ti waye nigbati RX mojuto gba Scrambler Reset (SR) tabi Start-Super-Block (SSB) fun gbogbo awọn akoko kikọ 510 FRL fun o kere ju awọn akoko 3.
rxcore_frl_ffe_levels	Abajade	4	Ni ibamu si FFE_level bit ni SCDC 0x31 Forukọsilẹ bit [7:4] ni RX mojuto.
rxcore_frl_flt_ṣetan	Iṣawọle	1	Awọn ifisilẹ lati tọkasi RX ti ṣetan fun ilana ikẹkọ ọna asopọ lati bẹrẹ. Nigbati a ba fi idi rẹ mulẹ, FLT_ready bit ninu iforukọsilẹ SCDC 0x40 bit 6 tun jẹ itọkasi.
rxcore_frl_src_test_config	Iṣawọle	8	Ṣeto awọn atunto idanwo orisun. Iye naa ni a kọ sinu iforukọsilẹ Iṣeto Igbeyewo SCDC ni iforukọsilẹ SCDC 0x35.
rxcore_tbcr	Abajade	1	Tọkasi TMDS bit to aago ratio; ni ibamu si iforukọsilẹ TMDS_Bit_Clock_Ratio ninu iforukọsilẹ SCDC 0x20 bit 1. • Nigbati o nṣiṣẹ ni HDMI 2.0 mode, yi bit ti wa ni idaniloju. Tọkasi ipin TMDS bit si aago ti 40:1. • Nigbati o ba nṣiṣẹ ni HDMI 1.4b, bit yii ko ni idaniloju. Tọkasi TMDS bit to aago ipin ti 10:1. • Yi bit jẹ ajeku fun FRL mode.
rxcore_scrambler_enable	Abajade	1	Tọkasi ti o ba ti gba data ti wa ni scrambled; ni ibamu si aaye Scrambling_Enable ninu iforukọsilẹ SCDC 0x20 bit 0.
rxcore_audio_de	Abajade	1	HDMI RX mojuto iwe atọkun Tọkasi awọn Rí Awọn atọkun apakan ninu awọn HDMI Intel FPGA IP Itọsọna olumulo fun alaye siwaju sii.
rxcore_audio_data	Abajade	256
rxcore_audio_info_ai	Abajade	48

rxcore_audio_N	Abajade	20
rxcore_audio_CTS	Abajade	20
rxcore_audio_metadata	Abajade	165
rxcore_audio_kika	Abajade	5
rxcore_aux_pkt_data	Abajade	72	HDMI RX mojuto iranlowo atọkun Tọkasi awọn Rí Awọn atọkun apakan ninu awọn HDMI Intel FPGA IP Itọsọna olumulo fun alaye siwaju sii.
rxcore_aux_pkt_addr	Abajade	6
rxcore_aux_pkt_wr	Abajade	1
rxcore_aux_data	Abajade	72
rxcore_aux_sop	Abajade	1
rxcore_aux_eop	Abajade	1
rxcore_aux_valid	Abajade	1
rxcore_aux_error	Abajade	1
rxcore_gcp	Abajade	6	HDMI RX mojuto sideband awọn ifihan agbara Tọkasi awọn Rí Awọn atọkun apakan ninu awọn HDMI Intel FPGA IP Itọsọna olumulo fun alaye siwaju sii.
rxcore_info_avi	Abajade	123
rxcore_info_vsi	Abajade	61
rxcore_locked	Abajade	1	HDMI RX mojuto fidio ibudo Akiyesi: N = awọn piksẹli fun aago Tọkasi awọn Rí Awọn atọkun apakan ninu awọn HDMI Intel FPGA IP Itọsọna olumulo fun alaye siwaju sii.
rxcore_vid_data	Abajade	N* 48
rxcore_vid_vsync	Abajade	N
rxcore_vid_hsync	Abajade	N
rxcore_vid_de	Abajade	N
rxcore_vid_valid	Abajade	1
rxcore_vid_lock	Abajade	1
rxcore_mode	Abajade	1	HDMI RX mojuto Iṣakoso ati ipo ibudo. Akiyesi: N = aami fun aago Tọkasi awọn Rí Awọn atọkun apakan ninu awọn HDMI Intel FPGA IP Itọsọna olumulo fun alaye siwaju sii.
rxcore_ctrl	Abajade	N*6
rxcore_color_depth_sync	Abajade	2
hdmi_5v_ri	Iṣawọle	1	HDMI RX 5V iwari ati hotplug iwari. Tọkasi awọn Rí Awọn atọkun apakan ninu awọn HDMI Intel FPGA IP Itọsọna olumulo fun alaye siwaju sii.
hdmi_rx_hpd	Abajade	1
rx_hpd_trigger	Iṣawọle	1

I2C Awọn ifihan agbara
hdmi_rx_i2c_sda	Iṣawọle	1	HDMI RX DDC ati SCDC ni wiwo.
hdmi_rx_i2c_scl	Iṣawọle	1

Awọn ifihan agbara RX EDID Ramu
edit_ram_access	Iṣawọle	1	HDMI RX EDID Ramu wiwọle ni wiwo.

edit_ram_adirẹsi	Iṣawọle	8	Sọ edid_ram_access nigba ti o ba fẹ kọ tabi ka lati Ramu EDID, bibẹẹkọ o yẹ ki ifihan agbara jẹ kekere. Nigbati o ba sọ edid_ram_access, hotplug ifihan agbara deasserts lati gba kikọ tabi ka si EDID Ramu. Nigbati EDID Ramu wiwọle ba ti pari, o yẹ ki o deassert edid_ram_assess ati hotplug ifihan agbara. Orisun naa yoo ka EDID tuntun nitori iyipada ifihan hotplug.
edid_ram_write	Iṣawọle	1
edit_ram_read	Iṣawọle	1
edit_ram_readata	Abajade	8
edid_ram_writedata	Iṣawọle	8
edid_ram_waitrequest	Abajade	1

Table 18.HDMI TX Top-Level awọn ifihan agbara

Ifihan agbara	Itọsọna	Ìbú	Apejuwe
Aago ati Tun awọn ifihan agbara
mgmt_clk	Iṣawọle	1	Iṣagbewọle aago eto (100 MHz).
tunto	Iṣawọle	1	Iṣagbewọle atunto eto.
tx_tmds_clk	Iṣawọle	1	HDMI RX TMDS aago.
txfpll_refclk1	Iṣawọle	1	Iṣagbewọle aago fun aago itọkasi TX PLL 1. Igbohunsafẹfẹ aago jẹ 100 MHz.
tx_vid_clk	Abajade	1	Ijade aago fidio.
tx_frl_clk	Abajade	1	FRL aago jade.
sys_init	Iṣawọle	1	Ipilẹṣẹ eto lati tun eto naa sori agbara-soke.
tx_init_ti ṣe	Iṣawọle	1	Ibẹrẹ TX lati tunto bulọọki iṣakoso atunto atunto TX ati wiwo atunto transceiver.

TX Transceiver ati IOPLL Awọn ifihan agbara
txpll_frl_locked	Abajade	1	Tọkasi aago iyara ọna asopọ ati aago FRL IOPLL ti wa ni titiipa.
txfpll_locked	Abajade	1	Tọkasi TX PLL ti wa ni titiipa.
txphy_serial_data	Abajade	4	HDMI ni tẹlentẹle data lati TX Native PHY.
txphy_ṣetan	Abajade	1	Tọkasi TX Abinibi PHY ti ṣetan.
txphy_cal_busy	Abajade	1	TX Native PHY ifihan agbara odiwọn nšišẹ.
txphy_cal_busy_raw	Abajade	4	Odiwọn nšišẹ ifihan agbara si transceiver arbiter.
txphy_cal_busy_gated	Iṣawọle	4	Iṣatunṣe iwọntunwọnsi nšišẹ lati ọdọ olutọpa transceiver si TX Native PHY.
txphy_rcfg_busy	Abajade	1	Tọkasi atunto TX PHY ti nlọ lọwọ.
txphy_rcfg_slave_write	Iṣawọle	4	Transceiver atunto Avalon iranti-mapped ni wiwo lati TX Native PHY si transceiver arbiter.
txphy_rcfg_slave_read	Iṣawọle	4
txphy_rcfg_slave_adirẹsi	Iṣawọle	40
txphy_rcfg_slave_writedata Iṣawọle 128 txphy_rcfg_slave_readata Abajade 128 txphy_rcfg_slave_waitrequest Abajade 4

TX Reconfiguration Management
tx_tmds_freq	Iṣawọle	24	HDMI TX TMDS iye igbohunsafẹfẹ aago (ni 10 ms).
tx_os	Abajade	2	oversampifosiwewe ling: • 0: 1x oversampling •1: 2× oversampling •2: 8x juampling
txphy_rcfg_master_write	Abajade	1	TX reconfiguration isakoso Avalon iranti-mapped ni wiwo to transceiver arbiter.
txphy_rcfg_master_read	Abajade	1
txphy_rcfg_master_adirẹsi	Abajade	12
txphy_rcfg_master_writedata	Abajade	32
txphy_rcfg_master_readdata	Iṣawọle	32
txphy_rcfg_master_waitrequest	Iṣawọle	1
tx_reconfig_ti ṣe	Abajade	1	Tọkasi pe ilana atunto TX ti pari.

HDMI TX mojuto awọn ifihan agbara
tx_vid_clk_locked	Iṣawọle	1	Tọkasi vid_clk jẹ iduroṣinṣin.
txcore_ctrl	Iṣawọle	N*6	HDMI TX mojuto Iṣakoso atọkun. Akiyesi: N = awọn piksẹli fun aago Tọkasi awọn Awọn atọkun Orisun apakan ninu awọn HDMI Intel FPGA IP Itọsọna olumulo fun alaye siwaju sii.
txcore_mode	Iṣawọle	1
txcore_audio_de	Iṣawọle	1	HDMI TX mojuto iwe atọkun. Tọkasi awọn Awọn atọkun Orisun apakan ninu awọn HDMI Intel FPGA IP Itọsọna olumulo fun alaye siwaju sii.
txcore_audio_mute	Iṣawọle	1
txcore_audio_data	Iṣawọle	256
txcore_audio_info_ai	Iṣawọle	49
txcore_audio_N	Iṣawọle	20
txcore_audio_CTS	Iṣawọle	20
txcore_audio_metadata	Iṣawọle	166
txcore_audio_kika	Iṣawọle	5
txcore_aux_ready	Abajade	1	HDMI TX mojuto iranlowo atọkun. Tọkasi awọn Awọn atọkun Orisun apakan ninu awọn HDMI Intel FPGA IP Itọsọna olumulo fun alaye siwaju sii.
txcore_aux_data	Iṣawọle	72
txcore_aux_sop	Iṣawọle	1
txcore_aux_eop	Iṣawọle	1

txcore_aux_valid	Iṣawọle	1
txcore_gcp	Iṣawọle	6	HDMI TX mojuto sideband awọn ifihan agbara. Tọkasi awọn Awọn atọkun Orisun apakan ninu awọn HDMI Intel FPGA IP Itọsọna olumulo fun alaye siwaju sii.
txcore_info_avi	Iṣawọle	123
txcore_info_vsi	Iṣawọle	62
txcore_i2c_master_write	Iṣawọle	1	TX I2C titunto si Avalon iranti-mapped ni wiwo to I2C titunto si inu awọn TX mojuto. Akiyesi: Awọn ifihan agbara wọnyi wa nigbati o ba tan-an Pẹlu I2C paramita.
txcore_i2c_master_read	Iṣawọle	1
txcore_i2c_master_adirẹsi	Iṣawọle	4
txcore_i2c_master_writedata	Iṣawọle	32
txcore_i2c_master_readdata	Abajade	32
txcore_vid_data	Iṣawọle	N* 48	HDMI TX mojuto fidio ibudo. Akiyesi: N = awọn piksẹli fun clockRef er si awọn Awọn atọkun Orisun apakan ninu awọn HDMI Intel FPGA IP Itọsọna olumulo fun alaye siwaju sii.
txcore_vid_vsync	Iṣawọle	N
txcore_vid_hsync	Iṣawọle	N
txcore_vid_de	Iṣawọle	N
txcore_vid_ṣetan	Abajade	1
txcore_vid_overflow	Abajade	1
txcore_vid_valid	Iṣawọle	1
oṣuwọn txcore_frl	Iṣawọle	4	SCDC Forukọsilẹ atọkun.
txcore_frl_pattern	Iṣawọle	16
txcore_frl_ibẹrẹ	Iṣawọle	1
txcore_scrambler_enable	Iṣawọle	1
txcore_tbcr	Iṣawọle	1

I2C Awọn ifihan agbara
nios_tx_i2c_sda_in	Abajade	1	TX I2C Titunto ni wiwo fun SCDC ati DDC lati awọn Nios II ero isise si awọn ti o wu saarin. Akiyesi: Ti o ba tan-an Pẹlu I2C paramita, awọn ifihan agbara wọnyi yoo gbe inu TX mojuto ati pe kii yoo han ni ipele yii.
nios_tx_i2c_scl_in	Abajade	1
nios_tx_i2c_sda_oe	Iṣawọle	1
nios_tx_i2c_scl_oe	Iṣawọle	1
nios_ti_i2c_sda_in	Abajade	1	TX I2C Titunto ni wiwo lati Nios II ero isise si awọn saarin o wu lati sakoso TI redriver lori Bitec HDMI 2.1 FMC ọmọbinrin kaadi.
nios_ti_i2c_scl_in	Abajade	1
nios_ti_i2c_sda_oe	Iṣawọle	1
nios_ti_i2c_scl_oe	Iṣawọle	1
hdmi_tx_i2c_sda	Iṣawọle	1	Awọn atọkun TX I2C fun awọn atọkun SCDC ati DDC lati inu ifipamọ iṣelọpọ si asopo HDMI TX.
hdmi_tx_i2c_scl	Iṣawọle	1
hdmi_tx_ti_i2c_sda	Iṣawọle	1	TX I2C atọkun lati ifi saarin o wu si TI redriver lori Bitec HDMI 2.1 FMC ọmọbinrin kaadi.
hdmi_tx_ti_i2c_scl	Iṣawọle	1

tx_hpd_req	Abajade	1	HDMI TX hotplug iwari awọn atọkun.
hdmi_tx_hpd_n	Iṣawọle	1

Table 19. Transceiver Arbiter awọn ifihan agbara

Ifihan agbara	Itọsọna	Ìbú	Apejuwe
clk	Iṣawọle	1	Aago atunto. Aago yii gbọdọ pin aago kanna pẹlu awọn bulọọki iṣakoso atunto.
tunto	Iṣawọle	1	Tun ifihan agbara. Atunto yii gbọdọ pin atunto kanna pẹlu awọn bulọọki iṣakoso atunto.
rx_rcfg_en	Iṣawọle	1	RX atunto jeki ifihan agbara.
tx_rcfg_en	Iṣawọle	1	TX atunto sise ifihan agbara.
rx_rcfg_ch	Iṣawọle	2	Tọkasi iru ikanni lati tunto lori mojuto RX. Ifihan agbara yii gbọdọ wa ni idaniloju nigbagbogbo.
tx_rcfg_ch	Iṣawọle	2	Tọkasi eyi ti ikanni lati wa ni tunto lori TX mojuto. Ifihan agbara yii gbọdọ wa ni idaniloju nigbagbogbo.
rx_reconfig_mgmt_write	Iṣawọle	1	Atunto Avalon iranti-mapped atọkun lati RX reconfiguration isakoso.
rx_reconfig_mgmt_read	Iṣawọle	1
rx_reconfig_mgmt_address	Iṣawọle	10
rx_reconfig_mgmt_writedata	Iṣawọle	32
rx_reconfig_mgmt_readdata	Abajade	32
rx_reconfig_mgmt_waitrequest	Abajade	1
tx_reconfig_mgmt_write	Iṣawọle	1	Atunto Avalon iranti-mapped atọkun lati TX reconfiguration isakoso.
tx_reconfig_mgmt_read	Iṣawọle	1
tx_reconfig_mgmt_address	Iṣawọle	10
tx_reconfig_mgmt_writedata	Iṣawọle	32
tx_reconfig_mgmt_readdata	Abajade	32
tx_reconfig_mgmt_waitrequest	Abajade	1
reconfig_write	Abajade	1	Reconfiguration Avalon iranti-mapped atọkun to transceiver.
reconfig_read	Abajade	1
reconfig_address	Abajade	10
reconfig_writedata	Abajade	32
rx_reconfig_readdata	Iṣawọle	32
rx_reconfig_waitrequest	Iṣawọle	1
tx_reconfig_readdata	Iṣawọle	1
tx_reconfig_waitrequest	Iṣawọle	1

rx_cal_busy	Iṣawọle	1	Ifihan ipo iwọntunwọnsi lati transceiver RX.
tx_cal_busy	Iṣawọle	1	Ifihan ipo iwọnwọn lati TX transceiver.
rx_reconfig_cal_busy	Abajade	1	Ifihan ipo iwọnwọn si iṣakoso atunto RX transceiver PHY.
tx_reconfig_cal_busy	Abajade	1	Ifihan ipo iwọnwọn lati TX transceiver PHY iṣakoso atunto.

Table 20. RX-TX Link awọn ifihan agbara

Ifihan agbara	Itọsọna	Ìbú	Apejuwe
vid_clk	Iṣawọle	1	HDMI aago fidio.
rx_vid_lock	Iṣawọle	3	Ṣe afihan ipo titiipa fidio HDMI RX.
rx_vid_wulo	Iṣawọle	1	HDMI RX fidio atọkun.
rx_vid_de	Iṣawọle	N
rx_vid_hsync	Iṣawọle	N
rx_vid_vsync	Iṣawọle	N
rx_vid_data	Iṣawọle	N* 48
rx_aux_eop	Iṣawọle	1	HDMI RX awọn atọkun iranlọwọ.
rx_aux_sop	Iṣawọle	1
rx_aux_valid	Iṣawọle	1
rx_aux_data	Iṣawọle	72
tx_vid_de	Abajade	N	HDMI TX fidio atọkun. Akiyesi: N = awọn piksẹli fun aago
tx_vid_hsync	Abajade	N
tx_vid_vsync	Abajade	N
tx_vid_data	Abajade	N*48
tx_vid_wulo	Abajade	1
tx_vid_ṣetan	Iṣawọle	1
tx_aux_eop	Abajade	1	HDMI TX awọn atọkun iranlọwọ.
tx_aux_sop	Abajade	1
tx_aux_valid	Abajade	1
tx_aux_data	Abajade	72
tx_aux_ṣetan	Iṣawọle	1

Table 21. Platform onise System awọn ifihan agbara

Ifihan agbara	Itọsọna	Ìbú	Apejuwe
cpu_clk_in_clk_clk	Iṣawọle	1	Sipiyu aago.
cpu_rst_in_reset_reset	Iṣawọle	1	Sipiyu tunto.

edid_ram_slave_translator_avalon_anti_slave_0_adirẹsi	Abajade	8	EDID Ramu wiwọle atọkun.
edid_ram_slave_translator_avalon_anti_slave_0_write	Abajade	1
edid_ram_slave_translator_avalon_anti_slave_0_read	Abajade	1
edid_ram_slave_translator_avalon_anti_slave_0_readdata	Iṣawọle	8
edid_ram_slave_translator_avalon_anti_slave_0_writedata	Abajade	8
edid_ram_slave_translator_avalon_anti_slave_0_waitrequest	Iṣawọle	1
hdmi_i2c_master_i2c_serial_sda_in	Iṣawọle	1	Awọn atọkun Titunto I2C lati ero isise Nios II si ifipamọ iṣelọpọ fun DDC ati iṣakoso SCDC.
hdmi_i2c_master_i2c_serial_scl_in	Iṣawọle	1
hdmi_i2c_master_i2c_serial_sda_oe	Abajade	1
hdmi_i2c_master_i2c_serial_scl_oe	Abajade	1
redriver_i2c_master_i2c_serial_sda_in	Iṣawọle	1	I2C Titunto atọkun lati Nios II ero isise si awọn saarin o wu fun TI redriver eto iṣeto ni.
redriver_i2c_master_i2c_serial_scl_in	Iṣawọle	1
redriver_i2c_master_i2c_serial_sda_oe	Abajade	1
redriver_i2c_master_i2c_serial_scl_oe	Abajade	1
pio_in0_external_connection_export	Iṣawọle	32	Ni afiwe igbewọle o wu atọkun. • Bit 0: Sopọ si ami olumulo_dipsw lati ṣakoso ipo iwọle EDID. • Bit 1: TX HPD ìbéèrè • Bit 2: TX transceiver setan • Bits 3: TX atunto ti ṣe •Bits 4–7: Ni ipamọ • Bits 8–11: Oṣuwọn RX FRL • Bit 12: RX TMDS bit aago ratio • Bits 13–16: RX FRL titiipa • Bits 17-20: Awọn ipele RX FFE • Bit 21: Titiipa titete RX

Ifihan agbara	Itọsọna	Ìbú	Apejuwe
			•Bit 22: Titiipa fidio RX • Bit 23: Bọtini titari olumulo 2 lati ka awọn iforukọsilẹ SCDC lati inu iwẹ ita •Bits 24–31: Ni ipamọ
pio_out0_external_connection_export	Abajade	32	Ni afiwe igbewọle o wu atọkun. • Bit 0: TX HPD afọwọsi •Bit 1: Bibẹrẹ TX ti ṣe • Bits 2–7: Ni ipamọ • Bits 8-11: Oṣuwọn TX FRL • Bits 12–27: Ilana ikẹkọ ọna asopọ TX FRL • Bit 28: TX FRL ibere • Bits 29–31: Ni ipamọ
pio_out1_external_connection_export	Abajade	32	Ni afiwe igbewọle o wu atọkun. • Bit 0: RX EDID Ramu wiwọle • Bit 1: RX FLT setan • Bits 2–7: Ni ipamọ • Bits 8-15: RX FRL iṣeto igbeyewo orisun •Bits 16–31: Ni ipamọ

2.1. 1. Apẹrẹ RTL paramita
Lo HDMI TX ati RX Top RTL paramita lati ṣe akanṣe apẹrẹ example.
Ọpọlọpọ awọn paramita oniru wa ninu awọn Apẹrẹ Example taabu ti HDMI Intel FPGA IP paramita olootu. O tun le yi awọn oniru example eto ti o ṣe ni paramita olootu nipasẹ awọn RTL sile.
Table 22. HDMI RX Top paramita

Paramita	Iye	Apejuwe
SUPPORT_DEEP_COLOR	• 0: Ko si jin awọ • : Jin awọ	Ṣe ipinnu boya mojuto le ṣe koodu awọn ọna kika awọ ti o jinlẹ.
SUPPORT_AUXILIARY	• 0: Ko si AUX •1: AUX	Ṣe ipinnu boya fifi koodu ikanni oluranlowo wa pẹlu.
SYMBOLS_PER_CLOCK	8	Ṣe atilẹyin awọn aami 8 fun aago kan fun awọn ẹrọ Intel Arria 10.
SUPPORT_AUDIO	• 0: Ko si ohun • 1: Ohun	Ṣe ipinnu boya mojuto le ṣe koodu ohun ohun.

EDID_RAM_ADDR_WIDTH	8 (Iye aiyipada)	Wọle mimọ 2 ti EDID Ramu iwọn.
BITEC_DAUGHTER_CARD_REV	•0: Ko ìfọkànsí eyikeyi Bitec HDMI ọmọbinrin kaadi •4: Atilẹyin Bitec HDMI ọmọbinrin àtúnyẹwò kaadi 4 • 6: Àwákirí Bitec HDMI ọmọbinrin àtúnyẹwò kaadi 6 • 11: Ifojusi Bitec HDMI kaadi atunyẹwo kaadi ọmọbinrin 11 (aiyipada)	So awọn àtúnyẹwò ti Bitec HDMI ọmọbinrin kaadi lo. Nigba ti o ba yi awọn àtúnyẹwò, awọn oniru le siwopu transceiver awọn ikanni ati invert awọn polarity ni ibamu si awọn Bitec HDMI ọmọbinrin kaadi awọn ibeere. Ti o ba ṣeto paramita BITEC_DAUGHTER_CARD_REV si 0, apẹrẹ ko ṣe awọn ayipada eyikeyi si awọn ikanni transceiver ati polarity.
POLARITY_INVERSION	• 0: Iyipada polarity • 1: Ma ko invert polarity	Ṣeto paramita yii si 1 lati yi iye ti data titẹ sii kọọkan pada. Ṣiṣeto paramita yii si 1 ṣe ipinnu 4'b1111 si ibudo rx_polinv ti transceiver RX.

Table 23. HDMI TX Top paramita

Paramita	Iye	Apejuwe
LO_FPLL	1	Ṣe atilẹyin fPLL bi TX PLL nikan fun awọn ẹrọ Intel Arria 10. Nigbagbogbo ṣeto paramita yii si 1.
SUPPORT_DEEP_COLOR	•0: Ko si jin awọ • 1: jin awọ	Ṣe ipinnu boya mojuto le ṣe koodu awọn ọna kika awọ ti o jinlẹ.
SUPPORT_AUXILIARY	• 0: Ko si AUX • 1: AUX	Ṣe ipinnu boya fifi koodu ikanni oluranlowo wa pẹlu.
SYMBOLS_PER_CLOCK	8	Ṣe atilẹyin awọn aami 8 fun aago kan fun awọn ẹrọ Intel Arria 10.
SUPPORT_AUDIO	• 0: Ko si ohun • 1: Ohun	Ṣe ipinnu boya mojuto le ṣe koodu ohun ohun.
BITEC_DAUGHTER_CARD_REV	• 0: Ko fojusi eyikeyi kaadi ọmọbinrin Bitec HDMI • 4: Atilẹyin Bitec HDMI ọmọbinrin àtúnyẹwò kaadi 4 • 6: Ìfọkànsí Bitec HDMI ọmọbinrin àtúnyẹwò kaadi 6 • 11: Ifojusi Bitec HDMI kaadi atunyẹwo kaadi ọmọbinrin 11 (aiyipada)	So awọn àtúnyẹwò ti Bitec HDMI ọmọbinrin kaadi lo. Nigba ti o ba yi awọn àtúnyẹwò, awọn oniru le siwopu transceiver awọn ikanni ati invert awọn polarity ni ibamu si awọn Bitec HDMI ọmọbinrin kaadi awọn ibeere. Ti o ba ṣeto paramita BITEC_DAUGHTER_CARD_REV si 0, apẹrẹ ko ṣe awọn ayipada eyikeyi si awọn ikanni transceiver ati polarity.
POLARITY_INVERSION	• 0: Iyipada polarity • 1: Ma ko invert polarity	Ṣeto paramita yii si 1 lati yi iye ti data titẹ sii kọọkan pada. Ṣiṣeto paramita yii si 1 ṣe ipinnu 4'b1111 si ibudo tx_polinv ti transceiver TX.

2.12. Hardware Oṣo
Awọn HDMI FRL-sise oniru example jẹ HDMI 2.1 ti o lagbara ati pe o ṣe ifihan loopthrough fun ṣiṣan fidio HDMI boṣewa kan.
Lati ṣiṣẹ idanwo ohun elo, so ohun elo HDMI-ṣiṣẹ pọ-gẹgẹbi kaadi eya aworan kan pẹlu wiwo HDMI — si titẹ sii inu HDMI. Apẹrẹ ṣe atilẹyin mejeeji HDMI 2.1 tabi HDMI 2.0/1.4b orisun ati rii.

1. Awọn ifọwọ HDMI ṣe ipinnu ibudo naa sinu ṣiṣan fidio boṣewa ati firanṣẹ si mojuto imularada aago.
2. HDMI RX mojuto ṣe ipinnu fidio, iranlọwọ, ati data ohun ohun lati wa ni yipo pada ni afiwe si HDMI TX mojuto nipasẹ DCFIFO.
3. Ibudo orisun HDMI ti kaadi ọmọbinrin FMC n gbe aworan naa si atẹle kan.

Akiyesi:
Ti o ba fẹ lo igbimọ idagbasoke Intel FPGA miiran, o gbọdọ yi awọn iṣẹ iyansilẹ ẹrọ ati awọn iṣẹ iyansilẹ pin. Eto afọwọṣe transceiver ti ni idanwo fun ohun elo idagbasoke Intel Arria 10 FPGA ati kaadi ọmọbinrin Bitec HDMI 2.1. O le ṣe atunṣe awọn eto fun igbimọ tirẹ.
Table 24. Lori-ọkọ Titari Button ati User LED Awọn iṣẹ

Titari Bọtini / LED	Išẹ
cpu_resetn	Tẹ lẹẹkan lati ṣe atunto eto.
olumulo_dipsw	Olumulo-telẹ DIP yipada lati yi ipo irekọja lọ. •PA (ipo aipe) = Ikọja HDMI RX lori FPGA gba EDID lati inu ifọwọ ita ati ṣafihan si orisun ita ti o sopọ si. • ON = O le ṣakoso iwọn FRL ti o pọju RX lati ebute Nios II. Aṣẹ ṣe atunṣe RX EDID nipa ifọwọyi iye oṣuwọn FRL ti o pọju. Tọkasi Ṣiṣe Apẹrẹ ni Oriṣiriṣi Awọn Oṣuwọn FRL loju iwe 33 fun alaye diẹ sii nipa tito awọn oṣuwọn FRL oriṣiriṣi.
olumulo_pb[0]	Tẹ lẹẹkan lati yi ifihan agbara HPD pada si orisun HDMI boṣewa.
olumulo_pb[1]	Ni ipamọ.
olumulo_pb[2]	Tẹ lẹẹkan lati ka awọn iforukọsilẹ SCDC lati ibi ifọwọ ti a ti sopọ si TX ti kaadi ọmọbinrin Bitec HDMI 2.1 FMC. Akiyesi: Lati mu kika ṣiṣẹ, o gbọdọ ṣeto DEBUG_MODE si 1 ninu sọfitiwia naa.
USER_LED[0]	RX TMDS aago PLL ipo titiipa. •0 = Ṣii silẹ • 1 = Titiipa
USER_LED[1]	RX transceiver setan ipo. •0 = Ko setan • 1 = Ṣetan
USER_LED[2]	Aago iyara ọna asopọ RX PLL, ati fidio RX ati ipo titiipa aago FRL PLL. • 0 = Boya ọkan ninu aago RX PLL ti wa ni ṣiṣi silẹ • 1 = Mejeeji PLL aago RX ti wa ni titiipa
USER_LED[3]	Titete mojuto RX HDMI ati ipo titiipa deskew. • 0 = O kere ju ikanni 1 ti wa ni ṣiṣi silẹ • 1 = Gbogbo awọn ikanni ti wa ni titiipa
USER_LED[4]	RX HDMI ipo titiipa fidio. • 0 = Ṣii silẹ • 1 = Titiipa
USER_LED[5]	Aago iyara ọna asopọ TX PLL, ati fidio TX ati ipo titiipa aago FRL PLL. •0 = Boya ọkan ninu aago TX PLL ti wa ni ṣiṣi silẹ • 1 = Mejeeji PLL aago TX ti wa ni titiipa
USER_LED[6] USER_LED[7]	TX transceiver setan ipo. • 0 = Ko setan • 1 = Ṣetan TX ọna asopọ ikẹkọ ipo. • 0 = O kuna • 1 = O ti kọja

2.13. Testbench kikopa
Testbench kikopa simulates HDMI TX ni tẹlentẹle loopback si RX mojuto.
Akiyesi:
Ijẹẹri kikopa yii ko ṣe atilẹyin fun awọn apẹrẹ pẹlu paramita I2C ti o ṣiṣẹ.
Olusin 19. HDMI Intel FPGA IP Simulation Testbench Block aworan atọkaTable 25. Testbench irinše

Ẹya ara ẹrọ	Apejuwe
TPG fidio	Olupilẹṣẹ apẹẹrẹ idanwo fidio (TPG) n pese ayun fidio naa.
Ohun Sample Gen	Olohun sample monomono pese iwe sample iwuri. Olupilẹṣẹ n ṣe agbekalẹ ilana data idanwo ti o pọ si lati tan kaakiri nipasẹ ikanni ohun.
Aux Sample Gen	Awọn aux sample monomono pese awọn oluranlowo sample iwuri. Olupilẹṣẹ ṣe ipilẹṣẹ data ti o wa titi lati gbejade lati atagba.

Ṣayẹwo CRC	Oluyẹwo yii jẹri boya transceiver TX ti o gba igbohunsafẹfẹ aago ibaamu oṣuwọn data ti o fẹ.
Ṣayẹwo Data Audio	Ṣiṣayẹwo data ohun afetigbọ ṣe afiwe boya ilana data idanwo ti n pọ si ti gba ati yipada ni deede.
Aux Data Ṣayẹwo	Ayẹwo data aux ṣe afiwe boya data aux ti a reti ti gba ati ṣe iyipada ni deede ni ẹgbẹ olugba.

Idanwo kikopa HDMI ṣe awọn idanwo ijerisi wọnyi:

HDMI Ẹya	Ijerisi
Awọn data fidio	• Awọn testbench awọn imuse CRC yiyewo lori awọn input ki o si wu fidio. • O ṣayẹwo iye CRC ti data ti a tan kaakiri lodi si CRC ti a ṣe iṣiro ninu data fidio ti o gba. • Testbench lẹhinna ṣe ayẹwo lẹhin wiwa awọn ifihan agbara V-SYNC iduroṣinṣin 4 lati ọdọ olugba.
Awọn alaye iranlọwọ	• Awọn aux sample monomono gbogbo a ti o wa titi data lati wa ni zqwq lati awọn Atagba. • Ni ẹgbẹ olugba, monomono ṣe afiwe boya o ti gba data iranlọwọ ti o nireti ti gba ati yipada ni deede.
Data ohun	• Ohun sampmonomono le ṣe agbekalẹ ilana data idanwo ti o pọ si lati tan kaakiri nipasẹ ikanni ohun. • Ni ẹgbẹ olugba, oluṣayẹwo data ohun ohun n ṣayẹwo ati ṣe afiwe boya ilana data idanwo ti o pọ si ti gba ati yipada ni deede.

Simulation aṣeyọri pari pẹlu ifiranṣẹ atẹle:
# SYMBOLS_PER_CLOCK = 2
# VIC = 4
# FRL_RATE = 0
BPP = 0
# AUDIO_FREQUENCY (kHz) = 48
# AUDIO_CHANNEL = 8
# Simulation kọja
Table 26. HDMI Intel FPGA IP Design Eksample Atilẹyin Simulators

Simulator	Verilog HDL	VHDL
ModelSim – Intel FPGA Edition/ ModelSim – Intel FPGA Starter Edition	Bẹẹni	Bẹẹni
VCS/VCS MX	Bẹẹni	Bẹẹni
Riviera-PRO	Bẹẹni	Bẹẹni
Xcelium Parallel	Bẹẹni	Rara

2.14. Awọn idiwọn apẹrẹ
O nilo lati ronu diẹ ninu awọn idiwọn nigbati o ba nfi HDMI 2.1 apẹrẹ example.

• TX ko le ṣiṣẹ ni ipo TMDS nigbati o wa ni ipo ti kii ṣe irekọja. Lati ṣe idanwo ni ipo TMDS, yi olumulo_dipsw pada si ipo irekọja.
• Awọn ero isise Nios II gbọdọ sin ikẹkọ ọna asopọ TX si ipari laisi eyikeyi idalọwọduro lati awọn ilana miiran.

2.15. Awọn ẹya ara ẹrọ ti n ṣatunṣe aṣiṣe
Apẹrẹ yii example pese awọn ẹya ti n ṣatunṣe aṣiṣe kan lati ṣe iranlọwọ fun ọ.
2.15.1. Ifiranṣẹ N ṣatunṣe aṣiṣe Software
O le tan-an ifiranṣẹ n ṣatunṣe aṣiṣe ninu sọfitiwia lati pese iranlọwọ akoko-ṣiṣe fun ọ.
Lati tan ifiranṣẹ ti n ṣatunṣe aṣiṣe ninu sọfitiwia, tẹle awọn igbesẹ wọnyi:

1. Yi DEBUG_MODE pada si 1 ninu iwe afọwọkọ global.h.
2. Ṣiṣe iwe afọwọkọ/build_sw.sh lori Ikarahun aṣẹ Nios II.
3. Ṣe atunto sọfitiwia ti ipilẹṣẹ / tx_control/tx_control.elf file nipa ṣiṣe aṣẹ lori Ikarahun aṣẹ Nios II:
   nios2-download -r -g software/tx_control/tx_control.elf
4. Ṣiṣe aṣẹ ebute Nios II lori Ikarahun Aṣẹ Nios II:
   nios2-ebute

Nigbati o ba tan ifiranṣẹ ti n ṣatunṣe aṣiṣe, alaye atẹle naa tẹjade:

• Awọn eto atunṣe TI lori TX ati RX mejeeji ni a ka ati ṣafihan lẹẹkan lẹhin siseto ELF file.
• Ifiranṣẹ ipo fun iṣeto RX EDID ati ilana hotplug
• Ipinnu pẹlu tabi laisi alaye atilẹyin FRL ti a fa jade lati EDID lori rii ti a ti sopọ si TX. Alaye yi ti han fun gbogbo TX hotplug.
• Ifiranṣẹ ipo fun ilana ikẹkọ ọna asopọ TX lakoko ikẹkọ ọna asopọ TX.

2.15.2. Alaye SCDC lati Ifọwọ ti a ti sopọ si TX
O le lo ẹya yii lati gba alaye SCDC.

1. Ṣiṣe aṣẹ ebute Nios II lori Ikarahun aṣẹ Nios II: nios2-terminal
2. Tẹ user_pb[2] lori ohun elo idagbasoke Intel Arria 10 FPGA.

Sọfitiwia naa ka ati ṣafihan alaye SCDC lori ifọwọ ti a ti sopọ si TX lori ebute Nios II.
2.15.3. Wiwọn Igbohunsafẹfẹ Aago
Lo ẹya ara ẹrọ yii lati ṣayẹwo ipo igbohunsafẹfẹ fun awọn aago oriṣiriṣi.

1. Ninu hdmi_rx_oke ati hdmi_tx_oke files, uncomment "//`setumo DEBUG_EN 1".
2. Ṣafikun ifihan agbara refclock_measure lati apẹẹrẹ mr_rate_detect kọọkan si Oluyanju Logic Tap Signal lati gba igbohunsafẹfẹ aago ti aago kọọkan (ni iye akoko 10 ms).
3. Ṣe akopọ apẹrẹ pẹlu Oluyanju Logic Tap Signal.
4. Eto SOF file ati ṣiṣe Oluyanju Logic Tap Signal.

Table 27. Agogo

Modulu	mr_rate_detect Apeere	Aago lati wa ni Idiwon
hdmi_rx_oke	rx_pll_tmds	Aago itọkasi RX CDR 0
	rx_clk0_freq	Aago transceiver RX jade lati ikanni 0
	rx_vid_clk_freq	RX fidio aago
	rx_frl_clk_freq	RX FRL aago
	rx_hsync_freq	Igbohunsafẹfẹ Hsync ti fireemu fidio ti o gba
hdmi_tx_oke	tx_clk0_freq	Aago transceiver TX jade lati ikanni 0
	vid_clk_freq	aago fidio TX
	frl_clk_freq	TX FRL aago
	tx_hsync_freq	Igbohunsafẹfẹ Hsync ti fireemu fidio lati tan kaakiri

2.16. Igbegasoke rẹ Design
Table 28. HDMI Design Eksample Ibamu pẹlu išaaju Intel kuotisi NOMBA Pro Edition Software Version

Apẹrẹ Example Iyatọ	Agbara lati ṣe igbesoke si Intel Quartus Prime Pro Edition 20.3
HDMI 2.1 Apẹrẹ Example (Atilẹyin FRL = 1)	Rara

Fun eyikeyi ti kii-ibaramu oniru exampBibẹẹkọ, o nilo lati ṣe atẹle naa:

1. Ṣe ina apẹrẹ tuntun example ni lọwọlọwọ Intel Quartus Prime Pro Edition software version lilo awọn atunto kanna ti rẹ tẹlẹ oniru.
2. Afiwera gbogbo oniru example liana pẹlu oniru example ṣe ipilẹṣẹ nipa lilo ẹya sọfitiwia Intel Quartus Prime Pro ti tẹlẹ. Port lori awọn ayipada ri.

HDMI 2.0 Apẹrẹ Example (Atilẹyin FRL = 0)

HDMI Intel FPGA IP apẹrẹ example ṣe afihan ọkan HDMI apẹẹrẹ parallel loopback ti o ni awọn ikanni RX mẹta ati awọn ikanni TX mẹrin.
Table 29. HDMI Intel FPGA IP Design Eksample fun Intel Arria 10 Awọn ẹrọ

Apẹrẹ Example	Data Oṣuwọn	Ipo Ikanni	Loopback Iru
Arria 10 HDMI RX-TX Retransmit	<6,000 Mbps	Simplex	Ni afiwe pẹlu ifipamọ FIFO

Awọn ẹya ara ẹrọ

• Apẹrẹ naa ṣe afiṣe awọn buffers FIFO lati ṣe ṣiṣanwọle ṣiṣan fidio taara HDMI kan laarin ifọwọ HDMI ati orisun.
  
• Apẹrẹ naa nlo ipo LED fun n ṣatunṣe aṣiṣe ni kutukutu stage.
• Apẹrẹ wa pẹlu awọn aṣayan RX ati TX nikan.
• Apẹrẹ ṣe afihan fifi sii ati sisẹ ti Ibiti Yiyiyi ati Mastering (HDR) InfoFrame ni module ọna asopọ RX-TX.
• Apẹrẹ ṣe afihan iṣakoso ti EDID passthrough lati ita HDMI ifọwọ si orisun HDMI ita nigbati o fa nipasẹ iṣẹlẹ TX gbona-plug.
• Apẹrẹ naa ngbanilaaye iṣakoso akoko ṣiṣe nipasẹ yipada DIP ati bọtini-titari lati ṣakoso awọn ifihan agbara mojuto HDMI TX:
  - ifihan ipo lati yan DVI tabi HDMI fireemu fidio ti a fi koodu pa
  - info_avi[47], info_vsi[61], ati audio_info_ai[48] awọn ifihan agbara lati yan gbigbe apo-iwe iranlọwọ nipasẹ awọn ẹgbẹ ẹgbẹ tabi awọn ibudo data iranlọwọ

Apeere RX gba orisun fidio kan lati olupilẹṣẹ fidio ita, ati data lẹhinna lọ nipasẹ loopback FIFO ṣaaju ki o to tan si apẹẹrẹ TX.
O nilo lati so olutupalẹ fidio ita, atẹle, tabi tẹlifisiọnu kan pẹlu asopọ HDMI si mojuto TX lati jẹrisi iṣẹ ṣiṣe naa.
3.1. HDMI 2.0 RX-TX Retransmit Design Block aworan atọka
The HDMI 2.0 RX-TX retransmit oniru example ṣe afihan loopback afiwe lori ipo ikanni rọrun fun HDMI Intel FPGA IP.
Ṣe nọmba 20. HDMI RX-TX Retransmit Block Diagram (Intel Quartus Prime Pro Edition)Ṣe nọmba 21. HDMI RX-TX Retransmit Block Diagram (Intel Quartus Prime Standard Edition)Alaye ti o jọmọ
Jitter ti PLL Cascading tabi Ọna aago ti kii ṣe igbẹhin fun Aago Itọkasi Arria 10 PLL Tọkasi ojutu yii fun ibi iṣẹ ti awọn aago apẹrẹ rẹ ba ni iriri afikun
jitter.
3.2. Hardware ati Software Awọn ibeere
Intel nlo awọn wọnyi hardware ati software lati se idanwo awọn oniru example.
Hardware

• Intel Arria 10 GX FPGA Development Apo
• Orisun HDMI (Ẹka Processor Eya aworan (GPU))
• HDMI rì (Atẹle)
• Bitec HDMI kaadi ọmọbinrin FMC 2.0 (Atunyẹwo 11)
• HDMI kebulu

Akiyesi:
O le yan awọn àtúnyẹwò ti rẹ Biec HDMI ọmọbinrin kaadi. Ṣeto paramita agbegbe BITEC_DAUGHTER_CARD_REV si 4, 6, tabi 11 ni ipele oke file (a10_hdmi2_demo.v). Nigbati o ba yi atunyẹwo naa pada, apẹrẹ le yi awọn ikanni transceiver pada ki o yipada polarity ni ibamu si awọn ibeere kaadi ọmọbinrin Bitec HDMI. Ti o ba ṣeto paramita BITEC_DAUGHTER_CARD_REV si 0, apẹrẹ ko ṣe awọn ayipada eyikeyi si awọn ikanni transceiver ati polarity. Fun HDMI 2.1 oniru examples, labẹ awọn Design Example taabu, ṣeto HDMI Ọmọbinrin Kaadi Àtúnyẹwò si boya Àtúnyẹwò 9, Àtúnyẹwò 4, tabi ko si ọmọbinrin kaadi. Iye aiyipada jẹ Atunyẹwo 9.
Software

• Ẹya Intel Quartus Prime 18.1 ati nigbamii (fun idanwo ohun elo)
• ModelSim – Intel FPGA Edition, ModelSim – Intel FPGA Starter Edition, , RivieraPRO, VCS (Verilog HDL nikan)/VCS MX, tabi Xcelium Parallel simulator

3.3. Ilana Ilana
Awọn ilana ni awọn ti ipilẹṣẹ files fun HDMI Intel FPGA IP oniru example.
olusin 22. Ilana Itọsọna fun Oniru ExampleTable 30. Ti ipilẹṣẹ RTL Files

Awọn folda	Files
gxb	• /gxb_rx.qsys (Intel Quartus Prime Standard Edition) • /gxb_rx.ip (Intel Quartus Prime Pro Edition)
	• /gxb_rx_reset.qsys (Intel Quartus Prime Standard Edition) • /gxb_rx_reset.ip (Intel Quartus Prime Pro Edition)
	• /gxb_tx.qsys (Intel Quartus Prime Standard Edition) • /gxb_tx.ip (Intel Quartus Prime Pro Edition)
	• /gxb_tx_fpll.qsys (Intel Quartus Prime Standard Edition) • /gxb_tx_fpll.ip (Intel Quartus Prime Pro Edition)
	• /gxb_tx_reset.qsys (Intel Quartus Prime Standard Edition) • /gxb_tx_reset.ip (Intel Quartus Prime Pro Edition)
hdmi_rx	•/hdmi_rx.qsys (Intel Quartus Prime Standard Edition) •/hdmi_rx.ip (Intel Quartus Prime Pro Edition)
	/hdmi_rx_top.v
	/mr_clock_sync.v (Intel Quartus Prime Standard Edition)
	/mr_hdmi_rx_core_top.v (Intel Quartus Prime Standard Edition)
	/mr_rx_oversample.v (Intel Quartus Prime Standard Edition)
	/symbol_aligner.v
	Panasonic.hex (Intel Quartus Prime Pro Edition)
hdmi_tx	• /hdmi_tx.qsys (Intel Quartus Prime Standard Edition) •/hdmi_tx.ip (Intel Quartus Prime Pro Edition)

	/hdmi_tx_top.v
	/mr_ce.v (Intel Quartus Prime Standard Edition)
	/mr_hdmi_tx_core_top.v (Intel Quartus Prime Standard Edition)
	/mr_tx_oversample.v (Intel Quartus Prime Standard Edition)
i2c_oga (Intel Quartus Prime Standard Edition)	/i2c_master_bit_ctrl.v
	/i2c_master_byte_ctrl.v
	/i2c_master_defines.v
	/i2c_master_top.v
	/oc_i2c_master.v
	/oc_i2c_master_hw.tcl
	/timescale.v
i2c_ẹrú	/edid_ram.qsys (Intel Quartus Prime Standard Edition)
	/Panasonic.hex (Intel Quartus Prime Standard Edition)
	/i2c_avl_mst_intf_gen.v
	/i2c_clk_cnt.v
	/i2c_condt_det.v
	/i2c_databuffer.v
	/i2c_rxshifter.v
	/i2c_slvfsm.v
	/i2c_spksup.v
	/i2c_txout.v
	/i2c_txshifter.v
	/i2cslave_to_avlmm_bridge.v
pll	• /pll_hdmi.qsys (Intel Quartus Prime Standard Edition) • /pll_hdmi.ip (Intel Quartus Prime Pro Edition)
	• /pll_hdmi_reconfig.qsys (Intel Quartus Prime Standard Edition) • /pll_hdmi_reconfig.ip (Intel Quartus Prime Pro Edition)
	kuotisi.ini
wọpọ	• /clock_control.qsys (Intel Quartus Prime Standard Edition) • /clock_control.ip (Intel Quartus Prime Pro Edition)
	• /fifo.qsys (Intel Quartus Prime Standard Edition) • /fifo.ip (Intel Quartus Prime Pro Edition)
	• /output_buf_i2c.qsys (Intel Quartus Prime Standard Edition) •/output_buf_i2c.ip (Intel Quartus Prime Pro Edition)
	/reset_controller.qsys (Intel Quartus Prime Standard Edition)
	/clock_crosser.v

	dcfifo_inst.v
	debouncer.sv (Intel Quartus Prime Pro Edition)
hdr	/altera_hdmi_aux_hdr.v
	/altera_hdmi_aux_snk.v
	/altera_hdmi_aux_src.v
	/altera_hdmi_hdr_infoframe.v
	/avalon_st_mutiplexer.qsys
reconfig_mgmt	/mr_compare_pll.v
	/mr_compare_rx.v
	/mr_rate_detect.v
	/mr_reconfig_master_pll.v
	/mr_reconfig_master_rx.v
	/mr_reconfig_mgmt.v
	/mr_rom_pll_dprioaddr.v
	/mr_rom_pll_valuemask_8bpc.v
	/mr_rom_pll_valuemask_10bpc.v
	/mr_rom_pll_valuemask_12bpc.v
	/mr_rom_pll_valuemask_16bpc.v
	/mr_rom_rx_dprioaddr_bitmask.v
	/mr_rom_rx_valuemask.v
	/mr_state_machine.v
sdc	/a10_hdmi2.sdc
	/mr_reconfig_mgmt.sdc
	/jtag.sdc
	/rxtx_link.sdc
	/mr_clock_sync.sdc (Intel Quartus Prime Standard Edition)

Table 31. ti ipilẹṣẹ Simulation Files
Tọkasi apakan Testbench Simulation fun alaye diẹ sii.

Awọn folda	Files
aldec	/aldec.do
	/rivierapro_setup.tcl
oye	/cds.lib
	/hdl.var
	<cds_libs folda>

olutojueni	/ mentor.do
	/msim_setup.tcl
synopsys	/vcs/fileakojọ.f
	/vcs/vcs_setup.sh
	/vcs/vcs_sim.sh
	/vcsmx/vcsmx_setup.sh
	/vcsmx/vcsmx_sim.sh
	/vcsmx/synopsys_sim_setup
xcelium (Intel Quartus Prime Pro Edition)	/cds.lib
	/hdl.var
	/xcelium_setup.sh
	/xcelium_sim.sh
wọpọ (Intel Quartus Prime Pro Edition)	/ modeli_files.tcl
	/ riviera_files.tcl
	/vcs_files.tcl
	/vcsmx_files.tcl
	/xcelium_files.tcl
hdmi_rx	• /hdmi_rx.qsys (Intel Quartus Prime Standard Edition) • /hdmi_rx.ip (Intel Quartus Prime Pro Edition)
	/hdmi_rx.sopcinfo (Intel Quartus Prime Standard Edition)
	/Panasonic.hex (Intel Quartus Prime Pro Edition)
	/symbol_aligner.v (Intel Quartus Prime Pro Edition)
hdmi_tx	• /hdmi_tx.qsys (Intel Quartus Prime Standard Edition) • /hdmi_tx.ip (Intel Quartus Prime Pro Edition)
	/hdmi_tx.sopcinfo (Intel Quartus Prime Standard Edition)

Table 32.Ti ipilẹṣẹ Software Files

Awọn folda	Files
tx_control_src Akiyesi: Tx_control folda tun ni awọn ẹda-ẹda ti iwọnyi files.	/intel_fpga_i2c.c (Intel Quartus Prime Pro Edition)
	/intel_fpga_i2c.h (Intel Quartus Prime Pro Edition)
	/i2c.c (Intel Quartus Prime Standard Edition)
	/i2c.h (Intel Quartus Prime Standard Edition)
	/main.c
	/xcvr_gpll_rcfg.c /xcvr_gpll_rcfg.h /ti_i2c.c (Intel Quartus Prime Standard Edition) /ti_i2c.h (Intel Quartus Prime Standard Edition)

3.4. Awọn irinše apẹrẹ
HDMI Intel FPGA IP apẹrẹ example nilo awọn wọnyi irinše.
Table 33. HDMI RX Top irinše

Modulu	Apejuwe
HDMI RX mojuto	IP naa gba data ni tẹlentẹle lati ọdọ Transceiver Native PHY ati ṣe titete data, deskew ikanni, iyipada TMDS, iyipada data iranlọwọ, iyipada data fidio, iyipada data ohun, ati sisọnu.
I2	I2C ni wiwo ti a lo fun Ikanni Ifihan Data Ibẹrẹ (DDC) ati Ipo ati ikanni Data (SCDC). Orisun HDMI nlo DDC lati pinnu awọn agbara ati awọn abuda ti ifọwọ nipa kika Imudara Imudara Ifihan Identification Data (E-EDID). • Awọn adirẹsi 8-bit I2C ẹrú fun E-EDID jẹ 0xA0 ati 0xA1. LSB tọkasi iru wiwọle: 1 fun kika ati 0 fun kikọ. Nigbati iṣẹlẹ HPD kan ba waye, ẹru I2C ṣe idahun si data E-EDID nipa kika lati inu Ramu lori-chip. • Adarí ẹrú-nikan I2C tun ṣe atilẹyin SCDC fun awọn iṣẹ HDMI 2.0. Adirẹsi ẹrú I8C 2-bit fun SCDC jẹ 0xA8 ati 0xA9. Nigbati iṣẹlẹ HPD kan ba waye, ẹrú I2C ṣe kikọ tabi ka idunadura si tabi lati wiwo SCDC ti HDMI RX mojuto. Akiyesi: Adarí ẹrú-nikan I2C yii fun SCDC ko nilo ti HDMI 2.0b ko ba pinnu. Ti o ba tan-an Pẹlu I2C paramita, bulọọki yii yoo wa ninu mojuto ati pe kii yoo han ni ipele yii.
EDID Ramu	Apẹrẹ naa tọju alaye EDID ni lilo mojuto IP 1-ibudo Ramu. A boṣewa meji-waya (aago ati data) tẹlentẹle akero bèèrè (I2C ẹrú-nikan oludari) gbigbe CEA-861-D ni ifaramọ E-EDID data be. Ramu EDID yii tọju alaye E-EDID. Akiyesi: Ti o ba tan-an Pẹlu EDID Ramu paramita, bulọọki yii yoo wa ninu mojuto ati pe kii yoo han ni ipele yii.
IOPLL	IOPLL n ṣe agbejade aago itọkasi RX CDR, aago iyara ọna asopọ, ati aago fidio fun aago TMDS ti nwọle. • Aago igbejade 0 (Aago itọkasi CDR) • Aago ijade 1 (Aago iyara ọna asopọ) • Aago ijade 2 (Aago fidio) Akiyesi: Iṣeto IOPLL aiyipada ko wulo fun eyikeyi ipinnu HDMI. A tunto IOPLL si awọn eto ti o yẹ lori agbara.
Transceiver PHY Tunto Adarí	Oluṣakoso atunto Transceiver PHY ṣe idaniloju ipilẹṣẹ igbẹkẹle ti awọn transceivers RX. Iṣagbewọle atunto ti oludari yii jẹ okunfa nipasẹ atunto RX, ati pe o ṣe agbekalẹ afọwọṣe ti o baamu ati ifihan agbara atunto oni-nọmba si bulọki Native PHY Transceiver ni ibamu si ilana atunto inu bulọọki naa.
PHY abinibi RX	Dina transceiver lile ti o gba data ni tẹlentẹle lati orisun fidio ita. O deserializes data ni tẹlentẹle si data afiwera ṣaaju gbigbe data naa si mojuto HDMI RX.
RX Reconfiguration Management	Abojuto atunto RX ti o ṣe adaṣe wiwadi oṣuwọn pẹlu HDMI PLL lati wakọ transceiver RX lati ṣiṣẹ ni eyikeyi awọn oṣuwọn ọna asopọ lainidii ti o wa lati 250 Mbps si 6,000 Mbps. Tọkasi Nọmba 23 ni oju-iwe 63 ni isalẹ.

IOPLL atunto

IOPLL bulọọki atunto n ṣe irọrun atunto akoko gidi ti o ni agbara ti awọn PLL ni awọn FPGA Intel. Bulọọki yii ṣe imudojuiwọn igbohunsafẹfẹ aago iṣejade ati bandiwidi PLL ni akoko gidi, laisi atunto gbogbo FPGA. Yi Àkọsílẹ nṣiṣẹ ni 100 MHz ni Intel Arria 10 awọn ẹrọ. Nitori aropin atunto IOPLL, lo Quartus INI permit_nf_pll_reconfig_out_of_lock=lori lakoko iran IP atunto IOPLL. Lati lo Quartus INI, pẹlu “permit_nf_pll_reconfig_out_of_lock=on” ninu quartus.ini file ati ibi ninu awọn file Intel Quartus Prime ise agbese liana. O yẹ ki o wo ifiranṣẹ ikilọ nigbati o ṣatunkọ bulọki atunto IOPLL (pll_hdmi_reconfig) ninu sọfitiwia Quartus Prime pẹlu INI. Akiyesi: Laisi Quartus INI yii, atunto IOPLL ko le pari ti IOPLL ba padanu titiipa lakoko atunto.

PIO

Titẹwọle/ijade ti o jọra (PIO) awọn iṣẹ dina bi iṣakoso, ipo ati awọn atọkun tunto si tabi lati inu eto iha Sipiyu.

olusin 23. Olona-Rate Reconfiguration Ọkọọkan Sisan
Nọmba naa ṣe afihan ṣiṣan isọdọtun iwọn-ọpọlọpọ ti oluṣakoso nigbati o gba ṣiṣan data titẹ sii ati igbohunsafẹfẹ aago itọkasi, tabi nigbati transceiver ti wa ni ṣiṣi silẹ.Table 34. HDMI TX Top irinše

Modulu	Apejuwe
HDMI TX mojuto	Ipilẹ IP n gba data fidio lati ipele oke ati ṣiṣe fifi koodu TMDS, fifi koodu iranlọwọ iranlọwọ, fifi koodu data ohun ohun, fifi koodu data fidio, ati scrambling ṣe.
I2C Titunto	I2C ni wiwo ti a lo fun Ikanni Ifihan Data Ibẹrẹ (DDC) ati Ipo ati ikanni Data (SCDC). Orisun HDMI nlo DDC lati pinnu awọn agbara ati awọn abuda ti ifọwọ nipa kika Imudara Imudara Ifihan Identification Data (E-EDID). • Gẹgẹbi DDC, I2C Titunto si ka EDID lati inu iṣiwe ita lati tunto alaye EDID EDID Ramu ni HDMI RX Top tabi fun ṣiṣe fidio. • Gẹgẹbi SCDC, oluwa I2C n gbe ilana data SCDC lati orisun FPGA si ifọwọ ita fun iṣẹ HDMI 2.0b. Fun example, ti o ba ti njade data san jẹ loke 3,400 Mbps, aṣẹ Nios II isise I2C titunto si lati mu TMDS_BIT_CLOCK_RATIO ati SCRAMBLER_ENABLE die-die ti awọn rii SCDC iṣeto ni Forukọsilẹ to 1.
IOPLL	IOPLL n pese aago iyara ọna asopọ ati aago fidio lati aago TMDS ti nwọle. • Aago ijade 1 (Aago iyara ọna asopọ) • Aago ijade 2 (Aago fidio) Akiyesi: Iṣeto IOPLL aiyipada ko wulo fun eyikeyi ipinnu HDMI. A tunto IOPLL si awọn eto ti o yẹ lori agbara.
Transceiver PHY Tunto Adarí	Oluṣakoso atunto Transceiver PHY ṣe idaniloju ipilẹṣẹ igbẹkẹle ti awọn transceivers TX. Iṣagbewọle atunto ti oludari yii jẹ okunfa lati ipele oke, ati pe o ṣe agbejade afọwọṣe ti o baamu ati ifihan agbara atunto oni-nọmba si bulọki Native PHY Transceiver ni ibamu si ilana atunto inu bulọki naa. Ifihan agbara tx_ready lati bulọki yii tun ṣiṣẹ bi ifihan atunto si HDMI Intel FPGA IP lati tọka transceiver ti wa ni oke ati nṣiṣẹ, ati pe o ti ṣetan lati gba data lati mojuto.
Transceiver abinibi PHY	Lile transceiver Àkọsílẹ ti o gba awọn afiwe data lati HDMI TX mojuto ati serializes awọn data lati atagba o. Ni wiwo atunto ti ṣiṣẹ ni TX Native PHY Àkọsílẹ lati ṣe afihan asopọ laarin TX Native PHY ati transceiver arbiter. Ko si atunto ti a ṣe fun TX Native PHY. Akiyesi: Lati pade ibeere skew inter-ikanni HDMI TX, ṣeto aṣayan ipo isọmọ ikanni TX ni Intel Arria 10 Transceiver Native PHY olootu paramita si PMA ati PCS imora. O tun nilo lati ṣafikun ibeere idiwọ ti o pọju skew (set_max_skew) si ifihan agbara atunto oni-nọmba lati ọdọ oluṣakoso atunto transceiver (tx_digitalreset) bi a ṣe iṣeduro ninu Intel Arria 10 Transceiver PHY olumulo Itọsọna.
TX PLL	Awọn Atagba PLL Àkọsílẹ pese ni tẹlentẹle sare aago si Transceiver Native PHY Àkọsílẹ. Fun eyi HDMI Intel FPGA IP apẹrẹ example, fPLL ti lo bi TX PLL.
IOPLL atunto	IOPLL bulọọki atunto n ṣe irọrun atunto akoko gidi ti o ni agbara ti awọn PLL ni awọn FPGA Intel. Bulọọki yii ṣe imudojuiwọn igbohunsafẹfẹ aago iṣejade ati bandiwidi PLL ni akoko gidi, laisi atunto gbogbo FPGA. Yi Àkọsílẹ nṣiṣẹ ni 100 MHz ni Intel Arria 10 awọn ẹrọ. Nitori aropin atunto IOPLL, lo Quartus INI permit_nf_pll_reconfig_out_of_lock=lori lakoko iran IP atunto IOPLL. Lati lo Quartus INI, pẹlu “permit_nf_pll_reconfig_out_of_lock=on” ninu quartus.ini file ati ibi ninu awọn file Intel Quartus Prime ise agbese liana. O yẹ ki o rii ifiranṣẹ ikilọ nigbati o ṣatunkọ bulọki atunto IOPLL (pll_hdmi_reconfig) ninu sọfitiwia Intel Quartus Prime pẹlu INI. Akiyesi: Laisi Quartus INI yii, atunto IOPLL ko le pari ti IOPLL ba padanu titiipa lakoko atunto.
PIO	Titẹwọle/ijade ti o jọra (PIO) awọn iṣẹ dina bi iṣakoso, ipo ati awọn atọkun tunto si tabi lati inu eto iha Sipiyu.

Table 35. Transceiver Data Rate ati Oversampling ifosiwewe fun kọọkan TMDS Aago Igbohunsafẹfẹ Range

Igbohunsafẹfẹ Aago TMDS (MHz)	TMDS Bit aago Ratio	oversampling ifosiwewe	Oṣuwọn Data Transceiver (Mbps)
85–150	1	Ko ṣiṣẹ fun	3400–6000
100–340	0	Ko ṣiṣẹ fun	1000–3400
50–100	0	5	2500–5000
35–50	0	3	1050–1500
30–35	0	4	1200–1400
25–30	0	5	1250–1500

Table 36. Top-Level wọpọ ohun amorindun

Modulu

Apejuwe

Arbiter Transceiver

Àkọsílẹ iṣẹ-ṣiṣe jeneriki yii ṣe idilọwọ awọn transceivers lati tun ṣe atunṣe nigbakanna nigbati boya RX tabi TX transceivers laarin ikanni ti ara kanna nilo atunto. Atunṣe atunṣe nigbakanna ni ipa awọn ohun elo nibiti RX ati TX transceivers laarin ikanni kanna ni a yàn si awọn imuse IP ominira. Arbiter transceiver yii jẹ itẹsiwaju si ipinnu ti a ṣeduro fun didapọ simplex TX ati simplex RX sinu ikanni ti ara kanna. Arbiter transceiver yii tun ṣe iranlọwọ ni sisopọ ati ṣiṣe idajọ Avalon-MM RX ati awọn ibeere atunto TX ti o fojusi simplex RX ati awọn transceivers TX laarin ikanni kan bi ibudo wiwo atunto ti awọn transceivers le wọle nikan ni atẹlera. Asopọ ni wiwo laarin transceiver arbiter ati TX/RX Native PHY/PHY Awọn ohun amorindun Oluṣeto atunto ninu apẹrẹ apẹrẹ yiiample ṣe afihan ipo jeneriki kan ti o kan fun eyikeyi apapo IP nipa lilo arbiter transceiver. Oluranlọwọ transceiver ko nilo nigbati boya RX tabi transceiver TX nikan lo ni ikanni kan. Arbiter transceiver ṣe idanimọ olubẹwẹ ti atunto nipasẹ awọn atọkun atunto Avalon-MM rẹ ati rii daju pe tx_reconfig_cal_busy ti o baamu tabi rx_reconfig_cal_busy ti wa ni gated ni ibamu. Fun ohun elo HDMI, RX nikan bẹrẹ atunto. Nipa sisọ ibeere atunto Avalon-MM nipasẹ apaniyan, adari naa ṣe idanimọ pe ibeere atunto wa lati RX, eyiti lẹhinna ẹnu-ọna tx_reconfig_cal_busy lati sọ ati gba rx_reconfig_cal_busy laaye lati sọ. Gating ṣe idiwọ transceiver TX lati gbe lọ si ipo isọdi laimọ-imọ.

	Akiyesi: Nitori HDMI nikan nilo atunto RX, awọn ifihan agbara tx_reconfig_mgmt_* ti so ni pipa. Paapaa, wiwo Avalon-MM ko nilo laarin arbiter ati TX Native PHY Àkọsílẹ. Awọn ohun amorindun ti wa ni sọtọ si wiwo ni awọn oniru example ṣe afihan asopọ arbiter transceiver jeneriki si TX/RX Native PHY/ PHY Tunto Adarí.
RX-TX ọna asopọ	• Ijade data fidio ati awọn ifihan agbara amuṣiṣẹpọ lati HDMI RX core loop nipasẹ DCFIFO kọja awọn agbegbe aago fidio RX ati TX. • Apapọ Iṣakoso Gbogbogbo (GCP), InfoFrames (AVI, VSI ati AI), data iranlọwọ, ati loop data ohun nipasẹ DCFIFOs kọja awọn agbegbe aago iyara ọna asopọ RX ati TX. • Ibudo data iranlọwọ ti HDMI TX mojuto n ṣakoso awọn alaye iranlọwọ ti o nṣàn nipasẹ DCFIFO nipasẹ ẹhin ẹhin. Igbẹhin ẹhin ṣe idaniloju pe ko si apo-iranlọwọ ti ko pe lori ibudo data iranlọwọ. • Àkọsílẹ yii tun ṣe sisẹ ita: - Ajọ data ohun ati apo isọdọtun aago ohun lati ṣiṣan data iranlọwọ ṣaaju gbigbe si ibudo data iranlọwọ mojuto HDMI TX. Akiyesi: Lati mu sisẹ yii jẹ, tẹ user_pb[2]. Mu sisẹ yii ṣiṣẹ lati rii daju pe ko si išẹpo ti data ohun ati apo isọdọtun aago ohun ninu ṣiṣan data iranlọwọ ti a tun gbejade. - Ajọ Ibiti Yiyi to gaju (HDR) Alaye lati inu data iranlọwọ HDMI RX ati fi sii tẹlẹample HDR InfoFrame si data iranlọwọ ti HDMI TX nipasẹ Avalon ST multiplexer.
Sipiyu iha-System	Awọn eto iha Sipiyu n ṣiṣẹ bi SCDC ati awọn oludari DDC, ati oludari atunto orisun. • Oludari orisun SCDC ni oluṣakoso I2C titunto si. Oludari titunto si I2C n gbe igbekalẹ data SCDC lati orisun FPGA si ifọwọ ita fun iṣẹ HDMI 2.0b. Fun example, ti o ba ti njade data san ni 6,000 Mbps, Nios II isise paṣẹ fun awọn I2C titunto si oludari lati mu awọn TMDS_BIT_CLOCK_RATIO ati SCRAMBLER_ENABLE die-die ti awọn rii TMDS iṣeto ni forukọsilẹ to 1. • Titunto si I2C kanna tun n gbe ilana data DDC (E-EDID) laarin orisun HDMI ati ifọwọ ita. • Nios II Sipiyu n ṣiṣẹ bi oluṣakoso atunto fun orisun HDMI. Sipiyu da lori wiwa oṣuwọn igbakọọkan lati inu module Iṣakoso Atunto RX lati pinnu boya TX nilo atunto. Olutumọ ẹrú Avalon-MM n pese ni wiwo laarin ero isise Nios II Avalon-MM titunto si ati awọn atọkun ẹrú Avalon-MM ti ita HDMI orisun IOPLL ati TX Native PHY. • Sisan ọna atunto atunto fun TX jẹ kanna bi RX, ayafi ti PLL ati atunto transceiver ati ilana atunto ti wa ni ṣiṣe lẹsẹsẹ. Tọkasi Nọmba 24 ni oju-iwe 67.

olusin 24. Reconfiguration Ọkọọkan Sisan
Nọmba naa ṣe apejuwe ṣiṣan sọfitiwia Nios II ti o kan awọn idari fun oluwa I2C ati orisun HDMI.3.5. Yiyi to Range ati Mastering (HDR) InfoFrame Fi sii ati Sisẹ
HDMI Intel FPGA IP apẹrẹ example pẹlu ifihan ti fifi sii HDR InfoFrame sinu eto loopback RX-TX kan.
Ẹya Sipesifikesonu HDMI 2.0b ngbanilaaye Range Yiyi ati Mastering InfoFrame lati tan kaakiri nipasẹ ṣiṣan iranlọwọ HDMI. Ninu iṣafihan naa, Àkọsílẹ ifibọ Data Iranlọwọ ṣe atilẹyin ifibọ HDR. O nilo nikan lati ṣe ọna kika apo-iwe HDR InfoFrame ti a pinnu gẹgẹbi pato ninu tabili atokọ ifihan agbara module ki o lo module Iṣakoso ifibọ AUX ti a pese lati ṣeto ifibọ ti HDR InfoFrame lẹẹkan ni gbogbo fireemu fidio.
Ninu example iṣeto ni, ni awọn igba ibi ti awọn ti nwọle san oluranlowo tẹlẹ pẹlu HDR InfoFrame, awọn san HDR akoonu ti wa ni filtered. Sisẹ naa yago fun ilodisi HDR InfoFrames lati tan kaakiri ati rii daju pe awọn iye ti o pato ninu HDR Sample Data module ti wa ni lilo.
Nọmba 25. Ọna asopọ RX-TX pẹlu Ibiti Yiyiyi ati Titẹ sii InfoFrame Mastering
Nọmba naa ṣe afihan aworan atọka ti ọna asopọ RX-TX pẹlu Ibiti Yiyiyi ati fifi sii InfoFrame Mastering sinu ṣiṣan iranlọwọ mojuto HDMI TX.
Tabili 37. Idina ifibọ Data Iranlọwọ (altera_hdmi_aux_hdr) Awọn ifihan agbara

Ifihan agbara	Itọsọna	Ìbú	Apejuwe
Aago ati Tunto
clk	Iṣawọle	1	Iṣagbewọle aago. Aago yii yẹ ki o sopọ si aago iyara ọna asopọ.
tunto	Iṣawọle	1	Tun igbewọle to.

Oluranlọwọ Packet monomono ati Multiplexer awọn ifihan agbara
multiplexer_out_data	Abajade	72	Avalon śiśanwọle o wu lati multiplexer.
multiplexer_out_valid	Abajade	1
multiplexer_out_ready	Abajade	1
multiplexer_out_startofpacket	Abajade	1
multiplexer_out_endofpacket	Abajade	1
multiplexer_out_channel	Abajade	11
multiplexer_in_data	Iṣawọle	72	Iṣagbewọle ṣiṣanwọle Avalon si ibudo In1 ti multiplexer. HDMI TX Video Vsync. Ifihan agbara yii yẹ ki o muuṣiṣẹpọ si agbegbe aago iyara ọna asopọ. Ifilelẹ fi HDR InfoFrame si ṣiṣan iranlọwọ ni eti ti o ga ti ifihan agbara yii.
multiplexer_in_valid	Iṣawọle	1
multiplexer_in_ready	Iṣawọle	1
multiplexer_in_startofpacket	Iṣawọle	1
multiplexer_in_endofpacket hdmi_tx_vsync	Iṣawọle Iṣawọle	1 1

Tabili 38. HDR Data Module (altera_hdmi_hdr_infoframe) Awọn ifihan agbara

Ifihan agbara	Itọsọna	Ìbú	Apejuwe
hb0	Abajade	8	Baiti akọsori 0 ti Ibiti Yiyiyi ati Mastering InfoFrame: InfoFrame iru koodu.
hb1	Abajade	8	Baiti akọsori 1 ti Ibiti Yiyiyi ati Mastering InfoFrame: Nọmba ẹya InfoFrame.
hb2	Abajade	8	Baiti akọsori 2 ti Ibiti Yiyiyi ati Mastering InfoFrame: Gigun InfoFrame.
pb	Iṣawọle	224	Data baiti ti Yiyi to Range ati Mastering InfoFrame.

Tabili 39. Yiyipo Ibiti ati Mastering InfoFrame Data Baiti Bundle Bit-Fields

Bit-Field	Itumọ	Metadata Aimi Iru 1
7:0	Data Baiti 1: {5'h0, EOTF[2:0]}
15:8	Data Baiti 2: {5'h0, Static_Metadata_Descriptor_ID[2:0]}
23:16	Data Baiti 3: Static_Metadata_Descriptor	display_primaries_x [0], LSB
31:24	Data Baiti 4: Static_Metadata_Descriptor	display_primaries_x [0], MSB
39:32	Data Baiti 5: Static_Metadata_Descriptor	display_primaries_y [0], LSB
47:40	Data Baiti 6: Static_Metadata_Descriptor	display_primaries_y [0], MSB
55:48	Data Baiti 7: Static_Metadata_Descriptor	display_primaries_x [1], LSB
63:56	Data Baiti 8: Static_Metadata_Descriptor	display_primaries_x [1], MSB
71:64	Data Baiti 9: Static_Metadata_Descriptor	display_primaries_y [1], LSB
79:72	Data Baiti 10: Static_Metadata_Descriptor	display_primaries_y [1], MSB
87:80	Data Baiti 11: Static_Metadata_Descriptor	display_primaries_x [2], LSB
95:88	Data Baiti 12: Static_Metadata_Descriptor	display_primaries_x [2], MSB
103:96	Data Baiti 13: Static_Metadata_Descriptor	display_primaries_y [2], LSB
111:104	Data Baiti 14: Static_Metadata_Descriptor	display_primaries_y [2], MSB
119:112	Data Baiti 15: Static_Metadata_Descriptor	white_point_x, LSB
127:120	Data Baiti 16: Static_Metadata_Descriptor	white_point_x, MSB
135:128	Data Baiti 17: Static_Metadata_Descriptor	funfun_point_y, LSB

143:136	Data Baiti 18: Static_Metadata_Descriptor	funfun_point_y, MSB
151:144	Data Baiti 19: Static_Metadata_Descriptor	max_display_mastering_luminance, LSB
159:152	Data Baiti 20: Static_Metadata_Descriptor	max_display_mastering_luminance, MSB
167:160	Data Baiti 21: Static_Metadata_Descriptor	min_display_mastering_luminance, LSB
175:168	Data Baiti 22: Static_Metadata_Descriptor	min_display_mastering_luminance, MSB
183:176	Data Baiti 23: Static_Metadata_Descriptor	Ipele Imọlẹ Akoonu ti o pọju, LSB
191:184	Data Baiti 24: Static_Metadata_Descriptor	Ipele Imọlẹ Akoonu ti o pọju, MSB
199:192	Data Baiti 25: Static_Metadata_Descriptor	Ipele Imọlẹ Apapọ fireemu ti o pọju, LSB
207:200	Data Baiti 26: Static_Metadata_Descriptor	Ipele Imọlẹ Apapọ Iwọn fireemu, MSB
215:208	Ni ipamọ
223:216	Ni ipamọ

Pa HDR Fi sii ati Sisẹ
Pa ifibọ HDR ati àlẹmọ jẹ ki o rii daju gbigbejade ti akoonu HDR ti o wa tẹlẹ ninu ṣiṣan iranlọwọ orisun laisi iyipada eyikeyi ninu apẹrẹ Retransmit RX-TX example.
Lati mu ifibọ InfoFrame HDR ṣiṣẹ ati sisẹ:

1. Ṣeto block_ext_hdr_infoframe si 1'b0 ninu rxtx_link.v file lati ṣe idiwọ sisẹ ti HDR InfoFrame lati ṣiṣan Iranlọwọ.
2. Ṣeto multiplexer_in0_valid ti apẹẹrẹ avalon_st_multiplexer ni altera_hdmi_aux_hdr.v file si 1'b0 lati ṣe idiwọ Olupilẹṣẹ Packet Oluranlọwọ lati dida ati fifi sii HDR InfoFrame ni afikun sinu ṣiṣan Auxiliary TX.
   

3.6. Eto aago
Eto clocking ṣe apejuwe awọn ibugbe aago ni HDMI Intel FPGA IP apẹrẹ example.
olusin 26. HDMI Intel FPGA IP Design EksampEto clocking (Intel Quartus Prime Pro Edition)olusin 27. HDMI Intel FPGA IP Design EksampÈtò Clocking (Intel Quartus Prime Standard Edition)Table 40. clocking Ero awọn ifihan agbara

Aago	Orukọ ifihan agbara ni Apẹrẹ	Apejuwe
Aago Itọkasi TX IOPLL/TX PLL 1	hdmi_clk_in	Aago itọkasi si TX IOPLL ati TX PLL. Igbohunsafẹfẹ aago jẹ kanna bi igbohunsafẹfẹ aago TMDS ti a reti lati ikanni aago HDMI TX TMDS. Fun eyi HDMI Intel FPGA IP apẹrẹ example, yi aago ti wa ni ti sopọ si RX TMDS aago fun ifihan idi. Ninu ohun elo rẹ, o nilo lati pese aago iyasọtọ pẹlu igbohunsafẹfẹ aago TMDS lati oscillator ti siseto fun iṣẹ jitter to dara julọ. Akiyesi: Maṣe lo pin RX transceiver bi aago itọkasi TX PLL. Apẹrẹ rẹ yoo kuna lati baamu ti o ba gbe HDMI TX refclk sori pin RX kan.
TX Transceiver Aago Jade	tx_clk	Aago jade ti o gba pada lati transceiver, ati igbohunsafẹfẹ yatọ da lori data oṣuwọn ati awọn aami fun aago. Aago transceiver TX jade igbohunsafẹfẹ = Oṣuwọn data transceiver/ (Aami fun aago kan*10)
TX PLL Aago Serial	tx_bonding_clocks	Serial fast aago ti ipilẹṣẹ nipasẹ TX PLL. Igbohunsafẹfẹ aago ti ṣeto da lori data oṣuwọn.
TX/RX Link Speed ​​Aago	ls_clk	Aago iyara ọna asopọ. Igbohunsafẹfẹ aago iyara ọna asopọ da lori ipo igbohunsafẹfẹ aago TMDS ti a nireti, juampling ifosiwewe, aami fun aago, ati TMDS bit aago ratio.

		TMDS Bit Aago ratio	Aago Iyara Igbohunsafẹfẹ
		0	TMDS aago igbohunsafẹfẹ/ Aami fun aago
		1	TMDS aago igbohunsafẹfẹ * 4 / Aami fun aago
Aago fidio TX/RX	vid_clk	Aago data fidio. Igbohunsafẹfẹ aago data fidio ti wa lati aago iyara ọna asopọ TX ti o da lori ijinle awọ.
		TMDS Bit Aago ratio	Video Data Igbohunsafẹfẹ
		0	Aago TMDS / Aami fun aago / Awọ ijinle ifosiwewe
		1	TMDS aago * 4 / Aami fun aago / Awọ ijinle ifosiwewe
		Bits fun Awọ	Awọ Ijinle ifosiwewe
		8	1
		10	1.25
		12	1.5
		16	2.0
Aago RX TMDS	tmds_clk_in	ikanni aago TMDS lati HDMI RX ati sopọ si aago itọkasi si IOPLL.
Aago Itọkasi RX CDR 0 /TX PLL Aago Itọkasi 0	fr_clk	Aago itọkasi ṣiṣiṣẹ ọfẹ si RX CDR ati TX PLL. Aago yii nilo fun isọdọtun-agbara.
Aago Itọkasi RX CDR 1	iopll_outclk0	Aago itọkasi si RX CDR ti transceiver RX.
		Data Oṣuwọn	Igbohunsafẹfẹ Aago Itọkasi RX
		Iwọn data <1 Gbps	5× TMDS aago igbohunsafẹfẹ
		1 Gbps< Oṣuwọn data <3.4 Gbps	TMDS aago igbohunsafẹfẹ
		Oṣuwọn data> 3.4 Gbps	4× TMDS aago igbohunsafẹfẹ
		Oṣuwọn data <1 Gbps: Fun awọn aṣejuampling lati pade transceiver kere data oṣuwọn ibeere. • Oṣuwọn Data>3.4 Gbps: Lati sanpada fun oṣuwọn bit TMDS si ipin aago ti 1/40 lati ṣetọju oṣuwọn data transceiver si ipin aago ni 1/10. Akiyesi: Maṣe lo pin RX transceiver bi aago itọkasi CDR. Apẹrẹ rẹ yoo kuna lati baamu ti o ba gbe HDMI RX refclk sori pin RX kan.
Aago Transceiver RX Jade	rx_clk	Aago jade ti o gba pada lati transceiver, ati igbohunsafẹfẹ yatọ da lori data oṣuwọn ati awọn aami fun aago. Aago transceiver RX jade igbohunsafẹfẹ = Oṣuwọn data transceiver/ (Aami fun aago kan*10)
Aago isakoso	mgmt_clk	Aago 100 MHz nṣiṣẹ ọfẹ fun awọn paati wọnyi:

		• Avalon-MM atọkun fun atunto - Ibeere iwọn igbohunsafẹfẹ wa laarin 100-125 MHz. •, oludari atunto PHY fun ọna atunto transceiver - Ibeere iwọn igbohunsafẹfẹ wa laarin 1-500 MHz. • IOPLL atunto - Awọn ti o pọju aago igbohunsafẹfẹ jẹ 100 MHz. • Atunto RX fun isakoso • Sipiyu • I2C Titunto
I2C aago	i2c_clk	Iṣawọle aago 100 MHz ti o ṣe aago I2C ẹrú, SCDC forukọsilẹ ni HDMI RX mojuto, ati EDID Ramu.

Alaye ti o jọmọ

• Lilo Transceiver RX Pin bi aago Itọkasi CDR
• Lilo Transceiver RX Pin bi aago Itọkasi TX PLL

3.7. Awọn ifihan agbara wiwo
Awọn tabili ṣe atokọ awọn ifihan agbara fun HDMI Intel FPGA IP apẹrẹ example.
Table 41. Top-Level awọn ifihan agbara

Ifihan agbara	Itọsọna	Ìbú	Apejuwe
Lori-ọkọ Oscillator Signal
clk_fpga_b3_p	Iṣawọle	1	100 MHz free nṣiṣẹ aago fun mojuto itọkasi aago
REFCLK_FMCB_P (Intel Quartus Prime Pro Edition)	Iṣawọle	1	625 MHz aago nṣiṣẹ ọfẹ fun aago itọkasi transceiver; aago yi le jẹ ti eyikeyi igbohunsafẹfẹ

Awọn bọtini Titari olumulo ati Awọn LED
olumulo_pb	Iṣawọle	1	Bọtini Titari lati ṣakoso iṣẹ apẹrẹ IP HDMI Intel FPGA
cpu_resetn	Iṣawọle	1	Atunto agbaye
olumulo_led_g	Abajade	4	Green LED àpapọ Tọkasi Eto Hardware loju iwe 89 fun alaye diẹ ẹ sii nipa awọn iṣẹ LED.
olumulo_led_r	Abajade	4	Red LED àpapọ Tọkasi Eto Hardware loju iwe 89 fun alaye diẹ ẹ sii nipa awọn iṣẹ LED.

Awọn pinni Kaadi Ọmọbinrin HDMI FMC lori Port B
fmcb_gbtclk_m2c_p_0	Iṣawọle	1	HDMI RX TMDS aago
fmcb_dp_m2c_p	Iṣawọle	3	HDMI RX pupa, alawọ ewe, ati awọn ikanni data bulu • Bitec ọmọbinrin kaadi àtúnyẹwò 11 - [0]: ikanni RX TMDS 1 (Awọ ewe) - [1]: ikanni RX TMDS 2 (pupa) - [2]: RX TMDS ikanni 0 (bulu) • Bitec ọmọbinrin kaadi àtúnyẹwò 4 tabi 6 - [0]: RX TMDS ikanni 1 (Awọ ewe) - polarity inverted - [1]: RX TMDS ikanni 0 (Blue) - polarity inverted - [2]: RX TMDS ikanni 2 (Pupa) - polarity inverted
fmcb_dp_c2m_p	Abajade	4	Aago HDMI TX, pupa, alawọ ewe, ati awọn ikanni data bulu • Bitec ọmọbinrin kaadi àtúnyẹwò 11 - [0]: ikanni TX TMDS 2 (pupa) - [1]: TX TMDS ikanni 1 (Awọ ewe) - [2]: TX TMDS ikanni 0 (bulu) - [3]: TX TMDS aago ikanni • Bitec ọmọbinrin kaadi àtúnyẹwò 4 tabi 6 - [0]: TX TMDS aago ikanni - [1]: TX TMDS ikanni 0 (bulu) - [2]: TX TMDS ikanni 1 (Awọ ewe) - [3]: ikanni TX TMDS 2 (pupa)
fmcb_la_rx_p_9	Iṣawọle	1	HDMI RX + 5V agbara iwari
fmcb_la_rx_p_8	Wọle	1	HDMI RX gbona plug iwari
fmcb_la_rx_n_8	Wọle	1	HDMI RX I2C SDA fun DDC ati SCDC
fmcb_la_tx_p_10	Iṣawọle	1	HDMI RX I2C SCL fun DDC ati SCDC
fmcb_la_tx_p_12	Iṣawọle	1	HDMI TX gbona plug iwari
fmcb_la_tx_n_12	Wọle	1	HDMI I2C SDA fun DDC ati SCDC
fmcb_la_rx_p_10	Wọle	1	HDMI I2C SCL fun DDC ati SCDC
fmcb_la_tx_p_11	Wọle	1	HDMI I2C SDA fun iṣakoso atunṣe
fmcb_la_rx_n_9	Wọle	1	HDMI I2C SCL fun iṣakoso atunṣe

Table 42. HDMI RX Top-Level awọn ifihan agbara

Ifihan agbara	Itọsọna	Ìbú	Apejuwe
Aago ati Tun awọn ifihan agbara
mgmt_clk	Iṣawọle	1	Iṣagbewọle aago eto (100 MHz)
fr_clk (Intel Quartus Prime Pro Edition)	Iṣawọle	1	Aago ṣiṣiṣẹ ọfẹ (625 MHz) fun aago itọkasi transceiver akọkọ. Aago yii nilo fun isọdiwọn transceiver lakoko ipo agbara. Aago yii le jẹ ti eyikeyi igbohunsafẹfẹ.
tunto	Iṣawọle	1	Iṣagbewọle atunto eto

Ifihan agbara	Itọsọna	Ìbú	Apejuwe
Aago ati Tun awọn ifihan agbara
reset_xcvr_powerup (Intel Quartus Prime Pro Edition)	Iṣawọle	1	Iṣagbewọle atunto Transceiver. Ifihan agbara yii jẹ afihan lakoko ilana iyipada awọn aago itọkasi (lati aago ṣiṣiṣẹ ọfẹ si aago TMDS) ni ipo agbara.
tmds_clk_in	Iṣawọle	1	HDMI RX TMDS aago
i2c_clk	Iṣawọle	1	Iṣagbewọle aago fun DDC ati wiwo SCDC
vid_clk_jade	Abajade	1	Aago fidio jade
ls_clk_jade	Abajade	1	O wu aago iyara ọna asopọ
sys_init	Abajade	1	Ipilẹṣẹ eto lati tun eto naa sori agbara-soke

Transceiver RX ati awọn ifihan agbara IOPLL
rx_serial_data	Iṣawọle	3	HDMI ni tẹlentẹle data si awọn RX Native PHY
gxb_rx_setan	Abajade	1	Tọkasi RX Abinibi PHY ti ṣetan
gxb_rx_cal_busy_jade	Abajade	3	RX Native PHY odiwọn nšišẹ si transceiver arbiter
gxb_rx_cal_busy_in	Iṣawọle	3	Iṣatunṣe iwọntunwọnsi nšišẹ lati ọdọ olutọpa transceiver si RX Native PHY
iopll_locked	Abajade	1	Tọkasi IOPLL ti wa ni titiipa
gxb_reconfig_write	Iṣawọle	3	Atunṣe atunto Transceiver Avalon-MM ni wiwo lati inu RX Native PHY si adari transceiver
gxb_reconfig_read	Iṣawọle	3
gxb_reconfig_address	Iṣawọle	30
gxb_reconfig_writedata	Iṣawọle	96
gxb_reconfig_readdata	Abajade	96
gxb_reconfig_waitrequest	Abajade	3

RX Reconfiguration Management
rx_reconfig_en	Abajade	1	Atunto RX jeki ifihan agbara
odiwọn	Abajade	24	HDMI RX TMDS wiwọn igbohunsafẹfẹ aago (ni 10 ms)
odiwọn_wulo	Abajade	1	Tọkasi ifihan agbara wiwọn wulo
os	Abajade	1	oversampifosiwewe ling: • 0: Ko si oversampling • 1:5× oversampling
reconfig_mgmt_write	Abajade	1	RX reconfiguration isakoso Avalon iranti-mapped ni wiwo to transceiver arbiter
reconfig_mgmt_read	Abajade	1
reconfig_mgmt_address	Abajade	12

reconfig_mgmt_writedata	Abajade	32
reconfig_mgmt_readdata	Iṣawọle	32
reconfig_mgmt_waitrequest	Iṣawọle	1

HDMI RX mojuto awọn ifihan agbara
TMDS_Bit_clock_Ratio	Abajade	1	SCDC Forukọsilẹ atọkun
audio_de	Abajade	1	HDMI RX mojuto iwe atọkun Tọkasi apakan Awọn atọkun Rin ni HDMI Intel FPGA IP Itọsọna olumulo fun alaye diẹ sii.
olohun_data	Abajade	256
audio_info_ai	Abajade	48
ohun_N	Abajade	20
ohun_CTS	Abajade	20
audio_metadata	Abajade	165
audio_kika	Abajade	5
aux_pkt_data	Abajade	72	HDMI RX mojuto iranlowo atọkun Tọkasi apakan Awọn atọkun Rin ni HDMI Intel FPGA IP Itọsọna olumulo fun alaye diẹ sii.
aux_pkt_addr	Abajade	6
aux_pkt_wr	Abajade	1
aux_data	Abajade	72
aux_sop	Abajade	1
aux_eop	Abajade	1
aux_valid	Abajade	1
aux_error	Abajade	1
gcp	Abajade	6	HDMI RX mojuto sideband awọn ifihan agbara Tọkasi apakan Awọn atọkun Rin ni HDMI Intel FPGA IP Itọsọna olumulo fun alaye diẹ sii.
alaye_avi	Abajade	112
alaye_vsi	Abajade	61
colordepth_mgmt_sync	Abajade	2
vid_data	Abajade	N* 48	HDMI RX mojuto fidio ibudo Akiyesi: N = aami fun aago Tọkasi awọn Rí Awọn atọkun apakan ninu awọn HDMI Intel FPGA IP Itọsọna olumulo fun alaye siwaju sii.
vid_vsync	Abajade	N
vid_hsync	Abajade	N
vid_de	Abajade	N
mode	Abajade	1	HDMI RX mojuto Iṣakoso ati ipo ibudo Akiyesi: N = aami fun aago Tọkasi awọn Rí Awọn atọkun apakan ninu awọn HDMI Intel FPGA IP Itọsọna olumulo fun alaye siwaju sii.
ctrl	Abajade	N*6
titii pa	Abajade	3
vid_lock	Abajade	1
ni_5v_agbara	Iṣawọle	1	HDMI RX 5V iwari ati hotplug iwari Tọkasi awọn Rí Awọn atọkun apakan ninu awọn HDMI Intel FPGA IP Itọsọna olumulo fun alaye siwaju sii.
hdmi_rx_hpd_n	Wọle	1

hdmi_rx_i2c_sda	Wọle	1	HDMI RX DDC ati SCDC ni wiwo
hdmi_rx_i2c_scl	Wọle	1

Awọn ifihan agbara RX EDID Ramu
edit_ram_access	Iṣawọle	1	HDMI RX EDID Ramu wiwọle ni wiwo. Sọ edid_ram_access nigba ti o ba fẹ kọ tabi ka lati Ramu EDID, bibẹẹkọ o yẹ ki ifihan agbara jẹ kekere.
edit_ram_adirẹsi	Iṣawọle	8
edid_ram_write	Iṣawọle	1
edit_ram_read	Iṣawọle	1
edit_ram_readata	Abajade	8
edid_ram_writedata	Iṣawọle	8
edid_ram_waitrequest	Abajade	1

Table 43. HDMI TX Top-Level awọn ifihan agbara

Ifihan agbara	Itọsọna	Ìbú	Apejuwe
Aago ati Tun awọn ifihan agbara
mgmt_clk	Iṣawọle	1	Iṣagbewọle aago eto (100 MHz)
fr_clk (Intel Quartus Prime Pro Edition)	Iṣawọle	1	Aago ṣiṣiṣẹ ọfẹ (625 MHz) fun aago itọkasi transceiver akọkọ. Aago yii nilo fun isọdiwọn transceiver lakoko ipo agbara. Aago yii le jẹ ti eyikeyi igbohunsafẹfẹ.
tunto	Iṣawọle	1	Iṣagbewọle atunto eto
hdmi_clk_in	Iṣawọle	1	Aago itọkasi si TX IOPLL ati TX PLL. Igbohunsafẹfẹ aago jẹ kanna bi igbohunsafẹfẹ aago TMDS.
vid_clk_jade	Abajade	1	Aago fidio jade
ls_clk_jade	Abajade	1	O wu aago iyara ọna asopọ
sys_init	Abajade	1	Ipilẹṣẹ eto lati tun eto naa sori agbara-soke
atunto_xcvr	Iṣawọle	1	Tun to TX transceiver
atunto_pl	Iṣawọle	1	Tunto si IOPLL ati TX PLL
reset_pll_reconfig	Abajade	1	Tunto si atunto PLL

TX Transceiver ati IOPLL Awọn ifihan agbara
tx_serial_data	Abajade	4	HDMI ni tẹlentẹle data lati TX Native PHY
gxb_tx_setan	Abajade	1	Tọkasi TX Abinibi PHY ti šetan
gxb_tx_cal_busy_jade	Abajade	4	TX Native PHY isọdiwọn nšišẹ ifihan agbara si transceiver arbiter
gxb_tx_cal_busy_in	Iṣawọle	4	Iṣatunṣe iwọntunwọnsi nšišẹ lati ọdọ oludajọ transceiver si TX Native PHY

TX Transceiver ati IOPLL Awọn ifihan agbara
iopll_locked	Abajade	1	Tọkasi IOPLL ti wa ni titiipa
txpll_locked	Abajade	1	Tọkasi TX PLL ti wa ni titiipa
gxb_reconfig_write	Iṣawọle	4	Atunṣe atunto Transceiver Avalon ni wiwo ti a ṣe iranti iranti lati TX Native PHY si adari transceiver
gxb_reconfig_read	Iṣawọle	4
gxb_reconfig_address	Iṣawọle	40
gxb_reconfig_writedata	Iṣawọle	128
gxb_reconfig_readdata	Abajade	128
gxb_reconfig_waitrequest	Abajade	4

TX IOPLL ati TX PLL Awọn ifihan agbara atunto
pll_reconfig_write/ tx_pll_reconfig_write	Iṣawọle	1	TX IOPLL/TX PLL atunto Avalon iranti-mapped atọkun
pll_reconfig_read/ tx_pll_reconfig_read	Iṣawọle	1
pll_reconfig_address/ tx_pll_reconfig_address	Iṣawọle	10
pll_reconfig_writedata/ tx_pll_reconfig_writedata	Iṣawọle	32
pll_reconfig_readdata/ tx_pll_reconfig_readdata	Abajade	32
pll_reconfig_waitrequest/ tx_pll_reconfig_waitrequest	Abajade	1
os	Iṣawọle	2	oversampifosiwewe ling: • 0: Ko si oversampling • 1:3× oversampling • 2:4× oversampling • 3:5× oversampling
odiwọn	Iṣawọle	24	Ṣe afihan igbohunsafẹfẹ aago TMDS ti gbigbe fidio ipinnu.

HDMI TX mojuto awọn ifihan agbara
ctrl	Iṣawọle	6*N	HDMI TX mojuto Iṣakoso atọkun Akiyesi: N = Awọn aami fun aago Tọkasi apakan Awọn atọkun Orisun ni apakan HDMI Intel FPGA IP Itọsọna olumulo fun alaye siwaju sii.
mode	Iṣawọle	1
TMDS_Bit_clock_Ratio	Iṣawọle	1	SCDC Forukọsilẹ atọkun Tọkasi apakan Awọn atọkun Orisun ni HDMI Intel FPGA IP Itọsọna olumulo fun alaye diẹ sii.
Scrambler_Jeki	Iṣawọle	1
audio_de	Iṣawọle	1	HDMI TX mojuto iwe atọkun Tọkasi awọn Awọn atọkun Orisun apakan ninu awọn HDMI Intel FPGA IP Itọsọna olumulo fun alaye siwaju sii.
audio_odi	Iṣawọle	1
olohun_data	Iṣawọle	256
tesiwaju…

HDMI TX mojuto awọn ifihan agbara
audio_info_ai	Iṣawọle	49
ohun_N	Iṣawọle	22
ohun_CTS	Iṣawọle	22
audio_metadata	Iṣawọle	166
audio_kika	Iṣawọle	5
i2c_master_write	Iṣawọle	1	TX I2C titunto si Avalon iranti-mapped ni wiwo to I2C titunto si inu awọn TX mojuto. Akiyesi: Awọn ifihan agbara wọnyi wa nigbati o ba tan-an Pẹlu I2C paramita.
i2c_master_read	Iṣawọle	1
i2c_master_adirẹsi	Iṣawọle	4
i2c_master_writedata	Iṣawọle	32
i2c_master_readata	Abajade	32
aux_ṣetan	Abajade	1	HDMI TX mojuto iranlowo atọkun Tọkasi apakan Awọn atọkun Orisun ni HDMI Intel FPGA IP Itọsọna olumulo fun alaye diẹ sii.
aux_data	Iṣawọle	72
aux_sop	Iṣawọle	1
aux_eop	Iṣawọle	1
aux_valid	Iṣawọle	1
gcp	Iṣawọle	6	HDMI TX mojuto sideband awọn ifihan agbara Tọkasi apakan Awọn atọkun Orisun ni HDMI Intel FPGA IP Itọsọna olumulo fun alaye diẹ sii.
alaye_avi	Iṣawọle	113
alaye_vsi	Iṣawọle	62
vid_data	Iṣawọle	N* 48	HDMI TX mojuto fidio ibudo Akiyesi: N = awọn aami fun aago kan Tọkasi apakan Awọn atọkun Orisun ni HDMI Intel FPGA IP Itọsọna olumulo fun alaye diẹ sii.
vid_vsync	Iṣawọle	N
vid_hsync	Iṣawọle	N
vid_de	Iṣawọle	N

I2C ati Gbona Plug Wa Awọn ifihan agbara
nios_tx_i2c_sda_in (Intel Quartus Prime Pro Edition) Akiyesi: Nigbati o ba tan-an Pẹlu I2C paramita, ifihan agbara yii ni a gbe sinu mojuto TX ati pe kii yoo han ni ipele yii.	Abajade	1	I2C Titunto Avalon iranti-mapped atọkun
nios_tx_i2c_scl_in (Intel Quartus Prime Pro Edition) Akiyesi: Nigbati o ba tan-an Pẹlu I2C paramita, ifihan agbara yii ni a gbe sinu mojuto TX ati pe kii yoo han ni ipele yii.	Abajade	1
nios_tx_i2c_sda_oe (Intel Quartus Prime Pro Edition) Akiyesi: Nigbati o ba tan-an Pẹlu I2C paramita, ifihan agbara yii ni a gbe sinu mojuto TX ati pe kii yoo han ni ipele yii.	Iṣawọle	1
tesiwaju…

I2C ati Gbona Plug Wa Awọn ifihan agbara
nios_tx_i2c_scl_oe (Intel Quartus Prime Pro Edition) Akiyesi: Nigbati o ba tan-an Pẹlu I2C paramita, ifihan agbara yii ni a gbe sinu mojuto TX ati pe kii yoo han ni ipele yii.	Iṣawọle	1
nios_ti_i2c_sda_in (Intel Quartus Prime Pro Edition)	Abajade	1
nios_ti_i2c_scl_in (Intel Quartus Prime Pro Edition)	Abajade	1
nios_ti_i2c_sda_oe (Intel Quartus Prime Pro Edition)	Iṣawọle	1
nios_ti_i2c_scl_oe (Intel Quartus Prime Pro Edition)	Iṣawọle	1
hdmi_tx_i2c_sda	Wọle	1	HDMI TX DDC ati SCDC atọkun
hdmi_tx_i2c_scl	Wọle	1
hdmi_ti_i2c_sda (Intel Quartus Prime Pro Edition)	Wọle	1	I2C ni wiwo fun Biec ọmọbinrin Card Àtúnyẹwò 11 TI181 Iṣakoso
hdmi_tx_ti_i2c_sda (Intel Quartus Prime Standard Edition)	Wọle	1
hdmi_ti_i2c_scl (Intel Quartus Prime Pro Edition)	Wọle	1
hdmi_tx_ti_i2c_scl (Intel Quartus Prime Standard Edition)	Wọle	1
tx_i2c_avalon_waitrequest	Abajade	1	Avalon iranti-mapped atọkun ti I2C titunto si
tx_i2c_avalon_address (Intel Quartus Prime Standard Edition)	Iṣawọle	3
tx_i2c_avalon_writedata (Intel Quartus Prime Standard Edition)	Iṣawọle	8
tx_i2c_avalon_readdata (Intel Quartus Prime Standard Edition)	Abajade	8
tx_i2c_avalon_chipselect (Intel Quartus Prime Standard Edition)	Iṣawọle	1
tx_i2c_avalon_write (Intel Quartus Prime Standard Edition)	Iṣawọle	1
tx_i2c_irq (Intel Quartus Prime Standard Edition)	Abajade	1
tx_ti_i2c_avalon_waitrequest (Intel Quartus Prime Standard Edition)	Abajade	1
tx_ti_i2c_avalon_address (Intel Quartus Prime Standard Edition)	Iṣawọle	3
tx_ti_i2c_avalon_writedata (Intel Quartus Prime Standard Edition)	Iṣawọle	8
tx_ti_i2c_avalon_readdata (Intel Quartus Prime Standard Edition)	Abajade	8
tesiwaju…

I2C ati Gbona Plug Wa Awọn ifihan agbara
tx_ti_i2c_avalon_chipselect (Intel Quartus Prime Standard Edition)	Iṣawọle	1
tx_ti_i2c_avalon_write (Intel Quartus Prime Standard Edition)	Iṣawọle	1
tx_ti_i2c_irq (Intel Quartus Prime Standard Edition)	Abajade	1
hdmi_tx_hpd_n	Iṣawọle	1	HDMI TX hotplug iwari awọn atọkun
tx_hpd_ack	Iṣawọle	1
tx_hpd_req	Abajade	1

Table 44. Transceiver Arbiter awọn ifihan agbara

Ifihan agbara	Itọsọna	Ìbú	Apejuwe
clk	Iṣawọle	1	Aago atunto. Aago yii gbọdọ pin aago kanna pẹlu awọn bulọọki iṣakoso atunto.
tunto	Iṣawọle	1	Tun ifihan agbara. Atunto yii gbọdọ pin atunto kanna pẹlu awọn bulọọki iṣakoso atunto.
rx_rcfg_en	Iṣawọle	1	RX atunto jeki ifihan agbara
tx_rcfg_en	Iṣawọle	1	TX atunto sise ifihan agbara
rx_rcfg_ch	Iṣawọle	2	Tọkasi iru ikanni lati tunto lori mojuto RX. Ifihan agbara yii gbọdọ wa ni idaniloju nigbagbogbo.
tx_rcfg_ch	Iṣawọle	2	Tọkasi eyi ti ikanni lati wa ni tunto lori TX mojuto. Ifihan agbara yii gbọdọ wa ni idaniloju nigbagbogbo.
rx_reconfig_mgmt_write	Iṣawọle	1	Awọn atọkun atunto Avalon-MM lati iṣakoso atunto RX
rx_reconfig_mgmt_read	Iṣawọle	1
rx_reconfig_mgmt_address	Iṣawọle	10
rx_reconfig_mgmt_writedata	Iṣawọle	32
rx_reconfig_mgmt_readdata	Abajade	32
rx_reconfig_mgmt_waitrequest	Abajade	1
tx_reconfig_mgmt_write	Iṣawọle	1	Awọn atọkun atunto Avalon-MM lati iṣakoso atunto TX
tx_reconfig_mgmt_read	Iṣawọle	1
tx_reconfig_mgmt_address	Iṣawọle	10
tx_reconfig_mgmt_writedata	Iṣawọle	32
tx_reconfig_mgmt_readdata	Abajade	32
tx_reconfig_mgmt_waitrequest	Abajade	1
reconfig_write	Abajade	1	Atunto Avalon-MM awọn atọkun si transceiver
reconfig_read	Abajade	1
tesiwaju…

Ifihan agbara	Itọsọna	Ìbú	Apejuwe
reconfig_address	Abajade	10
reconfig_writedata	Abajade	32
rx_reconfig_readdata	Iṣawọle	32
rx_reconfig_waitrequest	Iṣawọle	1
tx_reconfig_readdata	Iṣawọle	1
tx_reconfig_waitrequest	Iṣawọle	1
rx_cal_busy	Iṣawọle	1	Ifihan ipo iwọntunwọnsi lati transceiver RX
tx_cal_busy	Iṣawọle	1	Ifihan ipo iwọnwọn lati TX transceiver
rx_reconfig_cal_busy	Abajade	1	Ifihan ipo iwọnwọn si iṣakoso atunto RX transceiver PHY
tx_reconfig_cal_busy	Abajade	1	Ifihan ipo iwọnwọn lati TX transceiver PHY iṣakoso atunto

Table 45. RX-TX Link awọn ifihan agbara

Ifihan agbara	Itọsọna	Ìbú	Apejuwe
tunto	Iṣawọle	1	Tunto fidio/olohun/oluranlọwọ/awọn ẹgbẹ ẹgbẹẹgbẹ FIFO ifipamọ.
hdmi_tx_ls_clk	Iṣawọle	1	HDMI TX ọna asopọ aago iyara
hdmi_rx_ls_clk	Iṣawọle	1	HDMI RX ọna asopọ aago iyara
hdmi_tx_vid_clk	Iṣawọle	1	HDMI TX aago fidio
hdmi_rx_vid_clk	Iṣawọle	1	HDMI RX aago fidio
hdmi_rx_titiipa	Iṣawọle	3	Tọkasi HDMI RX ipo titiipa
hdmi_rx_de	Iṣawọle	N	HDMI RX fidio atọkun Akiyesi: N = aami fun aago
hdmi_rx_hsync	Iṣawọle	N
hdmi_rx_vsync	Iṣawọle	N
hdmi_rx_data	Iṣawọle	N*48
rx_audio_kika	Iṣawọle	5	HDMI RX iwe atọkun
rx_audio_metadata	Iṣawọle	165
rx_audio_info_ai	Iṣawọle	48
rx_audio_CTS	Iṣawọle	20
rx_audio_N	Iṣawọle	20
rx_audio_de	Iṣawọle	1
rx_audio_data	Iṣawọle	256
rx_gcp	Iṣawọle	6	HDMI RX sideband atọkun
rx_info_avi	Iṣawọle	112
rx_info_vsi	Iṣawọle	61
tesiwaju…

Ifihan agbara	Itọsọna	Ìbú	Apejuwe
rx_aux_eop	Iṣawọle	1	HDMI RX awọn atọkun iranlọwọ
rx_aux_sop	Iṣawọle	1
rx_aux_valid	Iṣawọle	1
rx_aux_data	Iṣawọle	72
hdmi_tx_de	Abajade	N	HDMI TX fidio atọkun Akiyesi: N = aami fun aago
hdmi_tx_hsync	Abajade	N
hdmi_tx_vsync	Abajade	N
hdmi_tx_data	Abajade	N*48
tx_audio_kika	Abajade	5	HDMI TX iwe atọkun
tx_audio_metadata	Abajade	165
tx_audio_info_ai	Abajade	48
tx_audio_CTS	Abajade	20
tx_audio_N	Abajade	20
tx_audio_de	Abajade	1
tx_audio_data	Abajade	256
tx_gcp	Abajade	6	HDMI TX sideband atọkun
tx_info_avi	Abajade	112
tx_info_vsi	Abajade	61
tx_aux_eop	Abajade	1	HDMI TX awọn atọkun iranlọwọ
tx_aux_sop	Abajade	1
tx_aux_valid	Abajade	1
tx_aux_data	Abajade	72
tx_aux_ṣetan	Abajade	1

Table 46. Platform onise System awọn ifihan agbara

Ifihan agbara	Itọsọna	Ìbú	Apejuwe
cpu_clk (Intel Quartus Prime Standard Edition)	Iṣawọle	1	Sipiyu aago
clock_bridge_0_in_clk_clk (Intel Quartus Prime Pro Edition)
cpu_clk_reset_n (Intel Quartus Prime Standard Edition)	Iṣawọle	1	Sipiyu tunto
reset_bridge_0_reset_reset_n (Intel Quartus Prime Pro Edition)
tmds_bit_clock_ratio_pio_external_connectio n_export	Iṣawọle	1	TMDS bit aago ratio
odiwọn_pio_external_connection_export	Iṣawọle	24	O ti ṣe yẹ igbohunsafẹfẹ aago TMDS
tesiwaju…

Ifihan agbara	Itọsọna	Ìbú	Apejuwe
odiwọn_valid_pio_external_connection_expor t	Iṣawọle	1	Tọkasi iwọn PIO wulo
i2c_master_i2c_serial_sda_in (Intel Quartus Prime Pro Edition)	Iṣawọle	1	I2C Titunto atọkun
i2c_master_i2c_serial_scl_in (Intel Quartus Prime Pro Edition)	Iṣawọle	1
i2c_master_i2c_serial_sda_oe (Intel Quartus Prime Pro Edition)	Abajade	1
i2c_master_i2c_serial_scl_oe (Intel Quartus Prime Pro Edition)	Abajade	1
i2c_master_ti_i2c_serial_sda_in (Intel Quartus Prime Pro Edition)	Iṣawọle	1
i2c_master_ti_i2c_serial_scl_in (Intel Quartus Prime Pro Edition)	Iṣawọle	1
i2c_master_ti_i2c_serial_sda_oe (Intel Quartus Prime Pro Edition)	Abajade	1
i2c_master_ti_i2c_serial_scl_oe (Intel Quartus Prime Pro Edition)	Abajade	1
oc_i2c_master_av_slave_translator_avalon_an ti_slave_0_address (Intel Quartus Prime Pro Edition)	Abajade	3	I2C Titunto Avalon awọn atọkun-aworan iranti fun DDC ati SCDC
oc_i2c_master_av_slave_translator_avalon_an ti_slave_0_write (Intel Quartus Prime Pro Edition)	Abajade	1
oc_i2c_master_av_slave_translator_avalon_an ti_slave_0_readdata (Intel Quartus Prime Pro Edition)	Iṣawọle	32
oc_i2c_master_av_slave_translator_avalon_an ti_slave_0_writedata (Intel Quartus Prime Pro Edition)	Abajade	32
oc_i2c_master_av_slave_translator_avalon_an ti_slave_0_waitrequest (Intel Quartus Prime Pro Edition)	Iṣawọle	1
oc_i2c_master_av_slave_translator_avalon_an ti_slave_0_chipselect (Intel Quartus Prime Pro Edition)	Abajade	1
oc_i2c_master_ti_avalon_anti_slave_address (Intel Quartus Prime Standard Edition)	Abajade	3	I2C Titunto Avalon awọn atọkun ti a ṣe iranti fun Biec ọmọbinrin kaadi atunyẹwo 11, iṣakoso T1181
oc_i2c_master_ti_avalon_anti_slave_write (Intel Quartus Prime Standard Edition)	Abajade	1
oc_i2c_master_ti_avalon_anti_slave_readdata (Intel Quartus Prime Standard Edition)	Iṣawọle	32
oc_i2c_master_ti_avalon_anti_slave_writedat a (Intel Quartus Prime Standard Edition)	Abajade	32
oc_i2c_master_ti_avalon_anti_slave_waitrequ est (Intel Quartus Prime Standard Edition)	Iṣawọle	1
oc_i2c_master_ti_avalon_anti_slave_chipsele ct (Intel Quartus Prime Standard Edition)	Abajade	1
tesiwaju…

Ifihan agbara	Itọsọna	Ìbú	Apejuwe
edid_ram_access_pio_external_connection_exp ort	Abajade	1	EDID Ramu wiwọle atọkun. Ṣafikun edid_ram_access_pio_ external_connection_ okeere nigba ti o ba fẹ kọ si tabi ka lati EDID Ramu lori oke RX. So EDID Ramu wiwọle Avalon-MM ẹrú ni Platform Designer to EDID Ramu ni wiwo lori oke-ipele RX modulu.
edid_ram_slave_translator_adirẹsi	Abajade	8
edid_ram_slave_translator_write	Abajade	1
edid_ram_slave_translator_ka	Abajade	1
edid_ram_slave_translator_readata	Iṣawọle	8
edid_ram_slave_translator_writedata	Abajade	8
edid_ram_slave_translator_waitrequest	Iṣawọle	1
powerup_cal_done_export (Intel Quartus Prime Pro Edition)	Iṣawọle	1	RX PMA atunto Avalon iranti-maapu atọkun
rx_pma_cal_busy_export (Intel Quartus Prime Pro Edition)	Iṣawọle	1
rx_pma_ch_export (Intel Quartus Prime Pro Edition)	Abajade	2
rx_pma_rcfg_mgmt_address (Intel Quartus Prime Pro Edition)	Abajade	12
rx_pma_rcfg_mgmt_write (Intel Quartus Prime Pro Edition)	Abajade	1
rx_pma_rcfg_mgmt_read (Intel Quartus Prime Pro Edition)	Abajade	1
rx_pma_rcfg_mgmt_readdata (Intel Quartus Prime Pro Edition)	Iṣawọle	32
rx_pma_rcfg_mgmt_writedata (Intel Quartus Prime Pro Edition)	Abajade	32
rx_pma_rcfg_mgmt_waitrequest (Intel Quartus Prime Pro Edition)	Iṣawọle	1
rx_pma_waitrequest_export (Intel Quartus Prime Pro Edition)	Iṣawọle	1
rx_rcfg_en_export (Intel Quartus Prime Pro Edition)	Abajade	1
rx_rst_xcvr_export (Intel Quartus Prime Pro Edition)	Abajade	1
tx_pll_rcfg_mgmt_translator_avalon_anti_sla ve_waitrequest	Iṣawọle	1	TX PLL atunto Avalon iranti-mapped atọkun
tx_pll_rcfg_mgmt_translator_avalon_anti_sla ve_writedata	Abajade	32
tx_pll_rcfg_mgmt_translator_avalon_anti_sla ve_adirẹsi	Abajade	10
tx_pll_rcfg_mgmt_translator_avalon_anti_sla ve_write	Abajade	1
tx_pll_rcfg_mgmt_translator_avalon_anti_sla ve_read	Abajade	1
tx_pll_rcfg_mgmt_translator_avalon_anti_sla ve_readdata	Iṣawọle	32
tesiwaju…

Ifihan agbara	Itọsọna	Ìbú	Apejuwe
tx_pll_waitrequest_pio_external_connection_ okeere	Iṣawọle	1	TX PLL ibeere
tx_pma_rcfg_mgmt_translator_avalon_anti_sla ve_adirẹsi	Abajade	12	TX PMA atunto Avalon iranti-mapped atọkun
tx_pma_rcfg_mgmt_translator_avalon_anti_sla ve_write	Abajade	1
tx_pma_rcfg_mgmt_translator_avalon_anti_sla ve_read	Abajade	1
tx_pma_rcfg_mgmt_translator_avalon_anti_sla ve_readdata	Iṣawọle	32
tx_pma_rcfg_mgmt_translator_avalon_anti_sla ve_writedata	Abajade	32
tx_pma_rcfg_mgmt_translator_avalon_anti_sla ve_waitrequest	Iṣawọle	1
tx_pma_waitrequest_pio_external_connection_ okeere	Iṣawọle	1	TX PMA ibeere
tx_pma_cal_busy_pio_external_connection_exp ort	Iṣawọle	1	TX PMA Recalibration Nšišẹ
tx_pma_ch_export	Abajade	2	TX PMA awọn ikanni
tx_rcfg_en_pio_external_connection_export	Abajade	1	Ṣiṣe atunto TX PMA ṣiṣẹ
tx_iopll_rcfg_mgmt_translator_avalon_anti_s lave_writedata	Abajade	32	TX IOPLL atunto Avalon iranti-mapped atọkun
tx_iopll_rcfg_mgmt_translator_avalon_anti_s lave_readdata	Iṣawọle	32
tx_iopll_rcfg_mgmt_translator_avalon_anti_s lave_waitrequest	Iṣawọle	1
tx_iopll_rcfg_mgmt_translator_avalon_anti_s lave_address	Abajade	9
tx_iopll_rcfg_mgmt_translator_avalon_anti_s lave_write	Abajade	1
tx_iopll_rcfg_mgmt_translator_avalon_anti_s lave_read	Abajade	1
tx_os_pio_external_connection_export	Abajade	2	oversampifosiwewe ling: • 0: Ko si oversampling • 1:3× oversampling • 2:4× oversampling • 3:5× oversampling
tx_rst_pll_pio_external_connection_export	Abajade	1	Tunto si IOPLL ati TX PLL
tx_rst_xcvr_pio_external_connection_export	Abajade	1	Tunto si TX Abinibi PHY
wd_timer_resetrequest_reset	Abajade	1	Atunto aago oluṣọ
color_depth_pio_external_connection_export	Iṣawọle	2	Ijinle awọ
tx_hpd_ack_pio_external_connection_export	Abajade	1	Fun TX hotplug rii mimu mimu
tx_hpd_req_pio_external_connection_export	Iṣawọle	1

3.8. Apẹrẹ RTL paramita
Lo HDMI TX ati RX Top RTL paramita lati ṣe akanṣe apẹrẹ example.
Pupọ julọ awọn ipilẹ apẹrẹ wa ni Apẹrẹ Example taabu ti HDMI Intel FPGA IP paramita olootu. O tun le yi awọn oniru example eto ti o
ṣe ninu awọn paramita olootu nipasẹ awọn RTL sile.

Table 47. HDMI RX Top paramita

Paramita	Iye	Apejuwe
SUPPORT_DEEP_COLOR	• 0: Ko si jin awọ • 1: jin awọ	Ṣe ipinnu boya mojuto le ṣe koodu awọn ọna kika awọ ti o jinlẹ.
SUPPORT_AUXILIARY	• 0: Ko si AUX • 1: AUX	Ṣe ipinnu boya fifi koodu ikanni oluranlowo wa pẹlu.
SYMBOLS_PER_CLOCK	8	Ṣe atilẹyin awọn aami 8 fun aago kan fun awọn ẹrọ Intel Arria 10.
SUPPORT_AUDIO	• 0: Ko si ohun • 1: Ohun	Ṣe ipinnu boya mojuto le ṣe koodu ohun ohun.
EDID_RAM_ADDR_WIDTH (Intel Quartus Prime Standard Edition)	8 (Iye aiyipada)	Wọle mimọ 2 ti EDID Ramu iwọn.
BITEC_DAUGHTER_CARD_REV	• 0: Ko fojusi eyikeyi kaadi ọmọbinrin Bitec HDMI • 4: Atilẹyin Bitec HDMI ọmọbinrin àtúnyẹwò kaadi 4 • 6: Ìfọkànsí Bitec HDMI ọmọbinrin àtúnyẹwò kaadi 6 •11: Ifojusi Bitec HDMI atunyẹwo kaadi ọmọbinrin 11 (aiyipada)	So awọn àtúnyẹwò ti Bitec HDMI ọmọbinrin kaadi lo. Nigba ti o ba yi awọn àtúnyẹwò, awọn oniru le siwopu transceiver awọn ikanni ati invert awọn polarity ni ibamu si awọn Bitec HDMI ọmọbinrin kaadi awọn ibeere. Ti o ba ṣeto paramita BITEC_DAUGHTER_CARD_REV si 0, apẹrẹ ko ṣe awọn ayipada eyikeyi si awọn ikanni transceiver ati polarity.
POLARITY_INVERSION	• 0: Iyipada polarity • 1: Ma ko invert polarity	Ṣeto paramita yii si 1 lati yi iye ti data titẹ sii kọọkan pada. Ṣiṣeto paramita yii si 1 ṣe ipinnu 4'b1111 si ibudo rx_polinv ti transceiver RX.

Table 48. HDMI TX Top paramita

Paramita	Iye	Apejuwe
LO_FPLL	1	Ṣe atilẹyin fPLL bi TX PLL nikan fun awọn ẹrọ Intel Cyclone® 10 GX. Nigbagbogbo ṣeto paramita yii si 1.
SUPPORT_DEEP_COLOR	• 0: Ko si jin awọ • 1: jin awọ	Ṣe ipinnu boya mojuto le ṣe koodu awọn ọna kika awọ ti o jinlẹ.
SUPPORT_AUXILIARY	• 0: Ko si AUX • 1: AUX	Ṣe ipinnu boya fifi koodu ikanni oluranlowo wa pẹlu.
SYMBOLS_PER_CLOCK	8	Ṣe atilẹyin awọn aami 8 fun aago kan fun awọn ẹrọ Intel Arria 10.
tesiwaju…

Paramita	Iye	Apejuwe
SUPPORT_AUDIO	• 0: Ko si ohun • 1: Ohun	Ṣe ipinnu boya mojuto le ṣe koodu ohun ohun.
BITEC_DAUGHTER_CARD_REV	• 0: Ko fojusi eyikeyi kaadi ọmọbinrin Bitec HDMI • 4: Atilẹyin Bitec HDMI ọmọbinrin àtúnyẹwò kaadi 4 • 6: Ìfọkànsí Bitec HDMI ọmọbinrin àtúnyẹwò kaadi 6 • 11: Ifojusi Bitec HDMI kaadi atunyẹwo kaadi ọmọbinrin 11 (aiyipada)	So awọn àtúnyẹwò ti Bitec HDMI ọmọbinrin kaadi lo. Nigba ti o ba yi awọn àtúnyẹwò, awọn oniru le siwopu transceiver awọn ikanni ati invert awọn polarity ni ibamu si awọn Bitec HDMI ọmọbinrin kaadi awọn ibeere. Ti o ba ṣeto paramita BITEC_DAUGHTER_CARD_REV si 0, apẹrẹ ko ṣe awọn ayipada eyikeyi si awọn ikanni transceiver ati polarity.
POLARITY_INVERSION	• 0: Iyipada polarity • 1: Ma ko invert polarity	Ṣeto paramita yii si 1 lati yi iye ti data titẹ sii kọọkan pada. Ṣiṣeto paramita yii si 1 ṣe ipinnu 4'b1111 si ibudo tx_polinv ti transceiver TX.

3.9. Hardware Oṣo
HDMI Intel FPGA IP apẹrẹ example jẹ HDMI 2.0b lagbara ati ki o ṣe ifihan loopthrough fun a boṣewa HDMI fidio san.
Lati ṣiṣẹ idanwo ohun elo, so ohun elo HDMI-ṣiṣẹ pọ-gẹgẹbi kaadi eya aworan kan pẹlu wiwo HDMI—si Transceiver Native PHY RX block, ati HDMI ifọwọ
igbewọle.

1. Awọn ifọwọ HDMI ṣe ipinnu ibudo naa sinu ṣiṣan fidio boṣewa ati firanṣẹ si mojuto imularada aago.
2. HDMI RX mojuto ṣe ipinnu fidio, iranlọwọ, ati data ohun ohun lati wa ni yipo pada ni afiwe si HDMI TX mojuto nipasẹ DCFIFO.
3. Ibudo orisun HDMI ti kaadi ọmọbinrin FMC n gbe aworan naa si atẹle kan.

Akiyesi:
Ti o ba fẹ lo igbimọ idagbasoke Intel FPGA miiran, o gbọdọ yi awọn iṣẹ iyansilẹ ẹrọ ati awọn iṣẹ iyansilẹ pin. Eto afọwọṣe transceiver ti ni idanwo fun ohun elo idagbasoke Intel Arria 10 FPGA ati kaadi ọmọbinrin Bitec HDMI 2.0. O le ṣe atunṣe awọn eto fun igbimọ tirẹ.

Table 49. Lori-ọkọ Titari Button ati User LED Awọn iṣẹ

Titari Bọtini / LED	Išẹ
cpu_resetn	Tẹ lẹẹkan lati ṣe atunto eto.
olumulo_pb[0]	Tẹ lẹẹkan lati yi ifihan agbara HPD pada si orisun HDMI boṣewa.
olumulo_pb[1]	• Tẹ mọlẹ lati kọ TX mojuto lati fi ifihan koodu DVI ranṣẹ. Tu silẹ lati fi ami ami koodu HDMI ranṣẹ.
olumulo_pb[2]	Tẹ mọlẹ lati kọ TX mojuto lati da fifiranṣẹ InfoFrames duro lati awọn ifihan agbara ẹgbẹ ẹgbẹ. Tu silẹ lati bẹrẹ fifiranṣẹ InfoFrames lati awọn ifihan agbara ẹgbẹ ẹgbẹ.
USER_LED[0]	RX HDMI PLL ipo titiipa. • 0 = Ṣii silẹ • 1 = Titiipa
USER_LED[1]	RX transceiver setan ipo.
tesiwaju…

Titari Bọtini / LED	Išẹ
	• 0 = Ko setan • 1 = Ṣetan
USER_LED[2]	RX HDMI ipo titiipa mojuto. • 0 = O kere ju ikanni 1 ṣiṣi silẹ • 1 = Gbogbo awọn ikanni mẹta ti wa ni titiipa
USER_LED[3]	Iye owo ti RXampipo ling. • 0 = ti kii-oversampmu (oṣuwọn data> 1,000 Mbps ni Intel Arria 10 ẹrọ) • 1 = Oversampmu (oṣuwọn data <100 Mbps ni Intel Arria 10 ẹrọ)
USER_LED[4]	TX HDMI PLL ipo titiipa. • 0 = Ṣii silẹ • 1 = Titiipa
USER_LED[5]	TX transceiver setan ipo. • 0 = Ko setan • 1 = Ṣetan
USER_LED[6]	TX transceiver PLL ipo titiipa. • 0 = Ṣii silẹ • 1 = Titiipa
USER_LED[7]	Iye owo ti TXampipo ling. • 0 = ti kii-oversampmu (oṣuwọn data> 1,000 Mbps ni Intel Arria 10 ẹrọ) • 1 = Oversampmu (oṣuwọn data <1,000 Mbps ni Intel Arria 10 ẹrọ)

3.10. Testbench kikopa
Testbench kikopa simulates HDMI TX ni tẹlentẹle loopback si RX mojuto.
Akiyesi:
Ijẹẹri kikopa yii ko ṣe atilẹyin fun awọn apẹrẹ pẹlu paramita I2C ti o ṣiṣẹ.

3. HDMI 2.0 Oniru Example (Atilẹyin FRL = 0)
683156 | 2022.12.27
olusin 28. HDMI Intel FPGA IP Simulation Testbench Block aworan atọka

Table 50. Testbench irinše

Ẹya ara ẹrọ	Apejuwe
TPG fidio	Olupilẹṣẹ apẹẹrẹ idanwo fidio (TPG) n pese ayun fidio naa.
Ohun Sample Gen	Olohun sample monomono pese iwe sample iwuri. Olupilẹṣẹ n ṣe agbekalẹ ilana data idanwo ti o pọ si lati tan kaakiri nipasẹ ikanni ohun.
Aux Sample Gen	Awọn aux sample monomono pese awọn oluranlowo sample iwuri. Olupilẹṣẹ ṣe ipilẹṣẹ data ti o wa titi lati gbejade lati atagba.
Ṣayẹwo CRC	Oluyẹwo yii jẹri boya transceiver TX ti o gba igbohunsafẹfẹ aago ibaamu oṣuwọn data ti o fẹ.
Ṣayẹwo Data Audio	Ṣiṣayẹwo data ohun afetigbọ ṣe afiwe boya ilana data idanwo ti n pọ si ti gba ati yipada ni deede.
Aux Data Ṣayẹwo	Ayẹwo data aux ṣe afiwe boya data aux ti a reti ti gba ati ṣe iyipada ni deede ni ẹgbẹ olugba.

Idanwo kikopa HDMI ṣe awọn idanwo ijerisi wọnyi:

HDMI Ẹya	Ijerisi
Awọn data fidio	• Awọn testbench awọn imuse CRC yiyewo lori awọn input ki o si wu fidio. • O ṣayẹwo iye CRC ti data ti a tan kaakiri lodi si CRC ti a ṣe iṣiro ninu data fidio ti o gba. • Testbench lẹhinna ṣe ayẹwo lẹhin wiwa awọn ifihan agbara V-SYNC iduroṣinṣin 4 lati ọdọ olugba.
Awọn alaye iranlọwọ	• Awọn aux sample monomono gbogbo a ti o wa titi data lati wa ni zqwq lati awọn Atagba. • Ni ẹgbẹ olugba, monomono ṣe afiwe boya o ti gba data iranlọwọ ti o nireti ti gba ati yipada ni deede.
Data ohun	• Ohun sampmonomono le ṣe agbekalẹ ilana data idanwo ti o pọ si lati tan kaakiri nipasẹ ikanni ohun. • Ni ẹgbẹ olugba, oluṣayẹwo data ohun ohun n ṣayẹwo ati ṣe afiwe boya ilana data idanwo ti o pọ si ti gba ati yipada ni deede.

Simulation aṣeyọri pari pẹlu ifiranṣẹ atẹle:
# SYMBOLS_PER_CLOCK = 2
# VIC = 4
# FRL_RATE = 0
BPP = 0
# AUDIO_FREQUENCY (kHz) = 48
# AUDIO_CHANNEL = 8
# Simulation kọja

Table 51. HDMI Intel FPGA IP Design Eksample Atilẹyin Simulators

Simulator	Verilog HDL	VHDL
ModelSim – Intel FPGA Edition/ ModelSim – Intel FPGA Starter Edition	Bẹẹni	Bẹẹni
VCS/VCS MX	Bẹẹni	Bẹẹni
Riviera-PRO	Bẹẹni	Bẹẹni
Xcelium Parallel	Bẹẹni	Rara

3.11. Igbegasoke rẹ Design
Table 52. HDMI Design Eksample Ibamu pẹlu išaaju Intel kuotisi NOMBA Pro Edition Software Version

Apẹrẹ Example Iyatọ	Agbara lati ṣe igbesoke si Intel Quartus Prime Pro Edition 20.3
HDMI 2.0 Apẹrẹ Example (Atilẹyin FRL = 0)	Rara

Fun eyikeyi ti kii-ibaramu oniru exampBibẹẹkọ, o nilo lati ṣe atẹle naa:

1. Ṣe ina apẹrẹ tuntun example ni lọwọlọwọ Intel Quartus Prime Pro Edition software version lilo awọn atunto kanna ti rẹ tẹlẹ oniru.
2. Afiwera gbogbo oniru example liana pẹlu oniru example ṣe ipilẹṣẹ nipa lilo ẹya sọfitiwia Intel Quartus Prime Pro ti tẹlẹ. Port lori awọn ayipada ri.

HDCP Lori HDMI 2.0/2.1 Design Example

HDCP naa lori apẹrẹ ohun elo HDMI example ṣe iranlọwọ fun ọ lati ṣe iṣiro iṣẹ ṣiṣe ti ẹya HDCP ati fun ọ laaye lati lo ẹya naa ninu awọn aṣa Intel Arria 10 rẹ.
Akiyesi:
Ẹya HDCP ko si ninu sọfitiwia Intel Quartus Prime Pro Edition. Lati wọle si ẹya HDCP, kan si Intel ni https://www.intel.com/content/www/us/en/broadcast/products/programmable/applications/connectivity-solutions.html.

4.1. Idaabobo Akoonu oni-nọmba bandiwidi giga (HDCP)
Idaabobo akoonu oni-nọmba bandiwidi giga-giga (HDCP) jẹ ọna aabo awọn ẹtọ oni-nọmba lati ṣẹda asopọ to ni aabo laarin orisun si ifihan.
Intel ṣẹda imọ-ẹrọ atilẹba, eyiti o ni iwe-aṣẹ nipasẹ ẹgbẹ Digital Akoonu Idaabobo LLC. HDCP jẹ ọna aabo ẹda kan nibiti ṣiṣan ohun/fidio ti wa ni fifi ẹnọ kọ nkan laarin atagba ati olugba, aabo fun didakọ arufin.
Awọn ẹya HDCP faramọ ẹya HDCP Specification 1.4 ati HDCP Specification version 2.3.
HDCP 1.4 ati HDCP 2.3 IPs ṣe gbogbo iṣiro laarin ero inu ohun elo hardware laisi awọn iye asiri (gẹgẹbi bọtini ikọkọ ati bọtini igba) ni iraye si lati ita IP ti paroko.

Table 53. HDCP IP Awọn iṣẹ

HDCP IP	Awọn iṣẹ
HDCP 1.4 IP	• Ijeri paṣipaarọ - Iṣiro ti bọtini titunto si (Km) - Iran ti ID An - Iṣiro ti bọtini igba (Ks), M0 ati R0. • Ijeri pẹlu repeater - Iṣiro ati iṣeduro ti V ati V' • Asopọ iyege ijerisi - Iṣiro bọtini fireemu (Ki), Mi ati Ri.
tesiwaju…

Intel Corporation. Gbogbo awọn ẹtọ wa ni ipamọ. Intel, aami Intel, ati awọn aami Intel miiran jẹ aami-išowo ti Intel Corporation tabi awọn oniranlọwọ rẹ. Intel ṣe atilẹyin iṣẹ ṣiṣe ti FPGA rẹ ati awọn ọja semikondokito si awọn pato lọwọlọwọ ni ibamu pẹlu atilẹyin ọja boṣewa Intel, ṣugbọn ni ẹtọ lati ṣe awọn ayipada si eyikeyi awọn ọja ati iṣẹ nigbakugba laisi akiyesi. Intel ko gba ojuse tabi layabiliti ti o dide lati inu ohun elo tabi lilo eyikeyi alaye, ọja, tabi iṣẹ ti a ṣalaye ninu rẹ ayafi bi a ti gba ni kikun si kikọ nipasẹ Intel. A gba awọn alabara Intel nimọran lati gba ẹya tuntun ti awọn pato ẹrọ ṣaaju gbigbekele eyikeyi alaye ti a tẹjade ati ṣaaju gbigbe awọn aṣẹ fun awọn ọja tabi awọn iṣẹ.
* Awọn orukọ miiran ati awọn ami iyasọtọ le jẹ ẹtọ bi ohun-ini ti awọn miiran.

ISO
9001:2015
Iforukọsilẹ

HDCP IP	Awọn iṣẹ
	Gbogbo awọn ipo cipher pẹlu hdcpBlockCipher, hdcpStreamCipher, hdcpRekeyCipher, ati hdcpRngCipher • Ifihan ipo fifi ẹnọ kọ nkan atilẹba (DVI) ati ifihan ipo fifi ẹnọ kọ nkan (HDMI) Olupilẹṣẹ nọmba ID otitọ (TRNG) - orisun ohun elo, imuse oni-nọmba ni kikun ati olupilẹṣẹ nọmba ID ti kii ṣe ipinnu
HDCP 2.3 IP	• Titunto si Key (km), Key Ikoni (ks) ati nonce (rn, riv) iran - Ni ibamu si NIST.SP800-90A ID nọmba iran • Ijeri ati paṣipaarọ bọtini - Iran ti awọn nọmba ID fun rtx ati rrx ni ifaramọ si NIST.SP800-90A nọmba ID nọmba iran - Ijeri ibuwọlu ti ijẹrisi olugba (certrx) nipa lilo bọtini gbangba DCP (kpubdcp) - 3072 die-die RSASSA-PKCS # 1 v1.5 - RSAES-OAEP (PKCS # 1 v2.1) ìsekóòdù ati decryption ti Titunto Key (km) - Ipilẹṣẹ ti kd (dkey0, dkey1) ni lilo ipo AES-CTR - Iṣiro ati iṣeduro ti H ati H' - Iṣiro ti Ekh (km) ati km (sisọpọ) • Ijeri pẹlu repeater - Iṣiro ati iṣeduro ti V ati V' - Iṣiro ati iṣeduro ti M ati M' • Isọdọtun eto (SRM) - Ijẹrisi Ibuwọlu SRM nipa lilo kpubdcp - 3072 die-die RSASSA-PKCS # 1 v1.5 • Ikoni Key paṣipaarọ • Iran ati isiro ti Edkey (ks) ati riv. • Itọsẹ ti dkey2 lilo AES-CTR mode • Ṣayẹwo agbegbe - Iṣiro ati iṣeduro ti L ati L' - Iran ti kii ṣe (rn) • Iṣakoso ṣiṣan data - Ipo AES-CTR ti o da lori iran ṣiṣan bọtini • Asymmetric crypto aligoridimu - RSA pẹlu modulus ipari ti 1024 (kpubrx) ati 3072 (kpubdcp) die-die - RSA-CRT (Theorem Remainder Kannada) pẹlu gigun modulus ti 512 (kprivrx) die-die ati ipari ti 512 (kprivrx) awọn bits • Low-ipele cryptographic iṣẹ - Awọn algoridimu crypto Symmetric • Ipo AES-CTR pẹlu ipari bọtini ti 128 die-die - Hash, MGF ati awọn algoridimu HMAC • SHA256 • HMAC-SHA256 • MGF1-SHA256 - Olupilẹṣẹ nọmba ID otitọ (TRNG) • NIST.SP800-90A ni ifaramọ • orisun Hardware, imuse oni-nọmba ni kikun ati olupilẹṣẹ nọmba ID ti kii ṣe ipinnu

4.1.1. HDCP Lori HDMI Design Example Architecture
Ẹya HDCP ṣe aabo data bi data ṣe tan kaakiri laarin awọn ẹrọ ti a ti sopọ nipasẹ HDMI tabi awọn atọkun oni-nọmba ti o ni aabo HDCP miiran.
Awọn ọna ṣiṣe aabo HDCP pẹlu awọn iru ẹrọ mẹta:

4. HDCP Lori HDMI 2.0 / 2.1 Design Example
683156 | 2022.12.27
• Awọn orisun (TX)
• Awọn rì (RX)
• Awọn atunwi
Apẹrẹ yii example ṣe afihan eto HDCP ninu ẹrọ atunṣe nibiti o ti gba data, decrypts, lẹhinna tun encrypts data naa, ati nikẹhin tun gbe data pada. Awọn atunwi ni awọn igbewọle HDMI mejeeji ati awọn igbejade. O ṣe afiṣe awọn buffers FIFO lati ṣe ṣiṣan ṣiṣan fidio taara taara laarin HDMI ifọwọ ati orisun. O le ṣe diẹ ninu awọn sisẹ ifihan agbara, gẹgẹbi iyipada awọn fidio sinu ọna kika ipinnu ti o ga julọ nipa rirọpo awọn ifipa FIFO pẹlu Fidio ati Ṣiṣe Aworan (VIP) Suite IP awọn ohun kohun.

olusin 29. HDCP Lori HDMI Design Example Àkọsílẹ aworan atọka

Awọn apejuwe wọnyi nipa faaji ti apẹrẹ example badọgba lati HDCP lori HDMI oniru example Àkọsílẹ aworan atọka. Nigba ti support FRL = 1 tabi
Àtìlẹ́yìn HDCP Bọtini isakoso = 1, awọn oniru exampIlana le jẹ iyatọ diẹ si Nọmba 29 ni oju-iwe 95 ṣugbọn awọn iṣẹ HDCP ti o wa ni abẹlẹ wa ni
kanna.

1. HDCP1x ati HDCP2x jẹ IPs ti o wa nipasẹ HDMI Intel FPGA IP olootu paramita. Nigbati o ba tunto IP HDMI ni olootu paramita, o le mu ṣiṣẹ ati pẹlu boya HDCP1x tabi HDCP2x tabi awọn IP mejeeji gẹgẹbi apakan ti eto-ipin. Pẹlu mejeeji HDCP IPs ṣiṣẹ, HDMI IP tunto ararẹ ni kasikedi topology nibiti HDCP2x ati HDCP1x IPs ti sopọ mọ-si-pada.
   • Iwoye HDCP egress ti HDMI TX nfi data fidio ohun afetigbọ ranṣẹ.
   • Awọn data ti a ko paro ni fifi ẹnọ kọ nkan nipasẹ bulọọki HDCP ti nṣiṣe lọwọ ati firanṣẹ pada sinu HDMI TX lori wiwo HDCP Ingress fun gbigbe lori ọna asopọ.
   • Sipiyu subsystem bi awọn ìfàṣẹsí titunto si oludari idaniloju wipe nikan ni ọkan ninu HDCP TX IPs nṣiṣẹ ni eyikeyi akoko ati awọn miiran ọkan jẹ palolo.
   Bakanna, HDCP RX tun sọ data ti o gba lori ọna asopọ lati HDCP TX ita.
2. O nilo lati ṣe eto awọn HDCP IPs pẹlu Idaabobo Akoonu Digital (DCP) awọn bọtini iṣelọpọ ti a pese. Kojọpọ awọn bọtini atẹle:
   Table 54. DCP-ti oniṣowo Production Keys
   

   HDCP	TX/RX	Awọn bọtini
   HDCP2x	TX	16 baiti: Ibakan Agbaye (lc128)
   	RX	• 16 baiti (kanna bi TX): Global Constant (lc128) • 320 awọn baiti: RSA Ikọkọ Aladani (kprivrx) • 522 baiti: Iwe-ẹri Bọtini gbangba RSA (certrx)
   HDCP1x	TX	• 5 baiti: TX Bọtini Yiyan Vector (Aksv) • 280 awọn baiti: Awọn bọtini Ẹrọ Aladani TX (Awọn bọtini)
   	RX	• 5 baiti: RX Bọtini Yiyan Vector (Bksv) • 280 baiti: Awọn bọtini Ẹrọ Aladani RX (Awọn bọtini Bkeys)

   Apẹrẹ example ṣe awọn iranti bọtini bi o rọrun meji-ibudo, meji-aago amuṣiṣẹpọ Ramu. Fun iwọn bọtini kekere bi HDCP2x TX, IP ṣe imuse iranti bọtini nipa lilo awọn iforukọsilẹ ni ọgbọn deede.
   Akiyesi: Intel ko pese awọn bọtini iṣelọpọ HDCP pẹlu apẹrẹ apẹẹrẹample tabi Intel FPGA IPs labẹ eyikeyi ayidayida. Lati lo HDCP IPs tabi apẹrẹ example, o gbọdọ di ohun HDCP olomo ati ki o gba awọn isejade bọtini taara lati Digital akoonu Idaabobo LLC (DCP).
   Lati ṣiṣe awọn oniru example, o boya satunkọ awọn iranti bọtini files ni akoko akopọ lati ni awọn bọtini iṣelọpọ tabi ṣe awọn bulọọki ọgbọn lati ka awọn bọtini iṣelọpọ ni aabo lati ẹrọ ibi ipamọ ita ati kọ wọn sinu awọn iranti bọtini ni akoko ṣiṣe.

3. O le aago awọn iṣẹ cryptographic ti a ṣe ni HDCP2x IP pẹlu igbohunsafẹfẹ eyikeyi to 200 MHz. Awọn igbohunsafẹfẹ ti yi aago ipinnu bi o ni kiakia awọn
   HDCP2x ìfàṣẹsí nṣiṣẹ. O le jade lati pin aago 100 MHz ti a lo fun ero isise Nios II ṣugbọn aiduro ijẹrisi yoo jẹ ilọpo meji ni akawe si lilo aago 200 MHz kan.
4. Awọn iye ti o gbọdọ paarọ laarin HDCP TX ati HDCP RX ti wa ni ibaraẹnisọrọ lori HDMI DDC ni wiwo (I2 C ni wiwo tẹlentẹle) ti HDCP-
   ni idaabobo ni wiwo. HDCP RX gbọdọ ṣafihan ẹrọ ọgbọn kan lori ọkọ akero I2C fun ọna asopọ kọọkan ti o ṣe atilẹyin. Ẹrú I2C jẹ pidánpidán fun ibudo HDCP pẹlu adirẹsi ẹrọ ti 0x74. O wakọ ibudo iforukọsilẹ HDCP (Avalon-MM) ti mejeeji HDCP2x ati HDCP1x RX IPs.
5. HDMI TX nlo oluwa IC lati ka EDID lati RX ati gbe data SCDC ti o nilo fun iṣẹ HDMI 2.0 si RX. Ọga I2C kanna ti o jẹ idari nipasẹ ero isise Nios II tun lo lati gbe awọn ifiranṣẹ HDCP laarin TX ati RX. I2C titunto si ti wa ni ifibọ ni Sipiyu subsystem.
6. Awọn ero isise Nios II n ṣiṣẹ bi oluwa ninu ilana ijẹrisi ati ṣe iṣakoso iṣakoso ati awọn iforukọsilẹ ipo (Avalon-MM) ti mejeeji HDCP2x ati HDCP1x TX
   IPs. Awọn awakọ sọfitiwia naa n ṣe imuse ilana ilana ijẹrisi ipinlẹ ẹrọ pẹlu ijẹrisi Ibuwọlu ijẹrisi, paṣipaarọ bọtini titun, ṣayẹwo agbegbe, paṣipaarọ bọtini igba, sisopọ, iṣayẹwo iduroṣinṣin ọna asopọ (HDCP1x), ati ijẹrisi pẹlu awọn atunwi, gẹgẹbi itankale alaye topology ati itankale alaye iṣakoso ṣiṣan. Awọn awakọ sọfitiwia naa ko ṣe eyikeyi awọn iṣẹ cryptographic ti o nilo nipasẹ ilana ijẹrisi. Dipo, ohun elo HDCP IP ohun elo ṣe gbogbo awọn iṣẹ cryptographic ni idaniloju pe ko si awọn iye asiri ti o le wọle.
   7. Ni a otitọ repeater ifihan ibi ti ikede topology alaye si oke wa ni ti beere, awọn Nios II isise iwakọ Repeater Message Port (Avalon-MM) ti awọn mejeeji HDCP2x ati HDCP1x RX IPs. Nios II ero isise nso RX REPEATER bit to 0 nigba ti o iwari awọn ti sopọ ibosile ni ko HDCPcapable tabi nigbati ko si ibosile ti a ti sopọ. Laisi asopọ isalẹ, eto RX jẹ olugba aaye-ipari, kuku ju olutun-pada. Ni idakeji, ero isise Nios II ṣeto RX REPEATER bit si 1 lori wiwa isalẹ jẹ agbara HDCP.

4.2. Nios II Prosessor Software Sisan
Aworan ṣiṣan sọfitiwia Nios II pẹlu awọn iṣakoso ìfàṣẹsí HDCP lori ohun elo HDMI.
olusin 30. Nios II Prosessor Software Flowchart

1. Sọfitiwia Nios II bẹrẹ ati tunto HDMI TX PLL, transceiver PHY TX, oluwa I2C ati ifẹhinti TI ita.
2. Sọfitiwia Nios II sọfitiwia wiwa oṣuwọn igbakọọkan jẹ ifihan agbara lati Circuit wiwa oṣuwọn RX lati pinnu boya ipinnu fidio ti yipada ati ti atunto TX ba nilo. Sọfitiwia naa tun ṣe ibori ifihan agbara iwari TX gbona-plug lati pinnu boya iṣẹlẹ ohun itanna gbona TX kan ti ṣẹlẹ.
3. Nigbati ifihan to wulo ti o gba lati Circuit wiwa oṣuwọn RX, sọfitiwia Nios II ka SCDC ati awọn iye ijinle aago lati HDMI RX ati gba iye igbohunsafẹfẹ aago ti o da lori oṣuwọn ti a rii lati pinnu boya HDMI TX PLL ati atunto transceiver PHY nilo. Ti o ba nilo atunto TX, sọfitiwia Nios II paṣẹ fun oluwa I2C lati fi iye SCDC ranṣẹ si RX ita. Lẹhinna o paṣẹ lati tunto HDMI TX PLL ati transceiver TX
   PHY, atẹle nipa atunṣe ẹrọ, ati tunto ọkọọkan. Ti oṣuwọn ko ba yipada, ko nilo atunto TX tabi HDCP tun-ifọwọsi.
4. Nigbati iṣẹlẹ TX gbona-plug ti waye, sọfitiwia Nios II paṣẹ fun oluwa I2C lati fi iye SCDC ranṣẹ si RX ita, ati lẹhinna ka EDID lati RX
   ki o si mu awọn ti abẹnu EDID Ramu. Sọfitiwia naa lẹhinna tan kaakiri alaye EDID si oke.
5. Sọfitiwia Nios II bẹrẹ iṣẹ HDCP nipasẹ pipaṣẹ fun oluwa I2C lati ka aiṣedeede 0x50 lati RX ita lati rii boya isalẹ jẹ agbara HDCP, tabi
   bibẹkọ:
   • Ti iye HDCP2Version ti o pada jẹ 1, isalẹ jẹ HDCP2xcapable.
   • Ti iye ti o pada ti gbogbo awọn kika 0x50 jẹ 0's, isalẹ jẹ agbara HDCP1x.
   • Ti iye ti o pada ti gbogbo kika 0x50 jẹ 1's, ibosile jẹ boya ko lagbara HDCP tabi aiṣiṣẹ.
   • Ti isalẹ ko ba ni agbara HDCP tẹlẹ tabi aiṣiṣẹ ṣugbọn o ni agbara HDCP lọwọlọwọ, sọfitiwia naa ṣeto bit REPEATER ti oke atunwi (RX) si 1 lati fihan pe RX ti jẹ atunwi bayi.
   • Ti o ba jẹ agbara HDCP ni isalẹ ṣugbọn lọwọlọwọ ko ṣe HDCPcapable tabi aiṣiṣẹ, sọfitiwia ṣeto iwọn REPEATER ti 0 lati fihan pe RX jẹ olugba opin opin bayi.
6. Sọfitiwia naa bẹrẹ ilana ijẹrisi HDCP2x ti o pẹlu ijẹrisi ibuwọlu ijẹrisi RX, paṣipaarọ bọtini titun, ṣayẹwo agbegbe, paṣipaarọ bọtini igba, sisopọ, ìfàṣẹsí pẹlu awọn atunwi bii itankalẹ alaye topology.
7. Nigbati o ba wa ni ipo ti o ni idaniloju, sọfitiwia Nios II paṣẹ fun oluwa I2C lati ṣe ibo iforukọsilẹ RxStatus lati RX ita, ati pe ti sọfitiwia ba rii pe a ti ṣeto bit REAUTH_REQ, o bẹrẹ tun-ifọwọsi ati mu fifi ẹnọ kọ nkan TX ṣiṣẹ.
8. Nigbati isale isalẹ jẹ atunṣe ati pe o ti ṣeto bit READY ti iforukọsilẹ RxStatus si 1, eyi nigbagbogbo tọkasi topology ibosile ti yipada. Nitorinaa, sọfitiwia Nios II paṣẹ fun oluwa I2C lati ka OlugbaID_List lati isalẹ ki o jẹrisi atokọ naa. Ti atokọ naa ba wulo ati pe ko si aṣiṣe topology ti a rii, sọfitiwia naa tẹsiwaju si module Ṣiṣan ṣiṣan akoonu. Bibẹẹkọ, o bẹrẹ atunjẹ-ẹri ati mu fifi ẹnọ kọ nkan TX ṣiṣẹ.
9. Sọfitiwia Nios II n murasilẹ OlugbaID_List ati awọn iye RxInfo ati lẹhinna kọwe si Avalon-MM Repeater Ifiranṣẹ ibudo ti atunlo oke (RX). RX naa ṣe ikede atokọ naa si TX ita (oke).
10. Ijeri ti pari ni aaye yii. Sọfitiwia naa jẹ ki fifi ẹnọ kọ nkan TX ṣiṣẹ.
11. Sọfitiwia naa bẹrẹ ilana ijẹrisi HDCP1x ti o pẹlu paṣipaarọ bọtini ati ijẹrisi pẹlu awọn atunwi.
12. Sọfitiwia Nios II n ṣe ayẹwo iṣotitọ ọna asopọ nipasẹ kika ati ifiwera Ri' ati Ri lati RX ita (isalẹ) ati HDCP1x TX lẹsẹsẹ. Ti o ba ti awọn iye
    ko baramu, eyi tọkasi isonu amuṣiṣẹpọ ati sọfitiwia naa bẹrẹ ifọwọsi ati mu fifi ẹnọ kọ nkan TX kuro.
13. Ti o ba ti isalẹ ni a repeater ati awọn READY bit ti awọn Bcaps Forukọsilẹ ti ṣeto si 1, yi maa tọkasi wipe awọn ibosile topology ti yi pada. Nitorinaa, sọfitiwia Nios II paṣẹ fun oluwa I2C lati ka iye atokọ KSV lati isalẹ ki o jẹrisi atokọ naa. Ti atokọ naa ba wulo ati pe ko si aṣiṣe topology ti a rii, sọfitiwia naa mura atokọ KSV ati iye Bstatus ati kọwe si ibudo Ifiranṣẹ Avalon-MM Repeater ti oluṣeto oke (RX). RX naa ṣe ikede atokọ naa si TX ita (oke). Bibẹẹkọ, o bẹrẹ isọdọtun ati mu fifi ẹnọ kọ nkan TX ṣiṣẹ.

4.3. Design Ririn
Ṣiṣeto ati ṣiṣe HDCP lori apẹrẹ HDMI example oriširiši marun stages.

1. Ṣeto ohun elo.
2. Ṣẹda apẹrẹ.
3. Ṣatunkọ HDCP iranti bọtini files lati ni awọn bọtini iṣelọpọ HDCP rẹ.
   a. Tọju awọn bọtini iṣelọpọ HDCP pẹtẹlẹ ni FPGA (Atilẹyin Itọju Kokoro HDCP = 0)
   b. Tọju awọn bọtini iṣelọpọ HDCP ti paroko ni iranti filasi ita tabi EEPROM (Atilẹyin Iṣakoso bọtini HDCP = 1)
4. Ṣe akopọ apẹrẹ.
5. View awon Iyori si.

4.3.1. Ṣeto Hardware
Ni igba akọkọ ti stage ti ifihan ni lati ṣeto awọn hardware.
Nigbati SUPPORT FRL = 0, tẹle awọn igbesẹ wọnyi lati ṣeto ohun elo fun ifihan:

1. So Bitec HDMI 2.0 FMC kaadi ọmọbinrin (atunyẹwo 11) si ohun elo idagbasoke Arria 10 GX ni ibudo FMC B.
2. So ohun elo idagbasoke Arria 10 GX pọ mọ PC rẹ nipa lilo okun USB kan.
3. So okun HDMI kan pọ lati HDMI RX asopo lori kaadi ọmọbinrin Bitec HDMI 2.0 FMC si ohun elo HDMI ti o ni HDCP, gẹgẹbi kaadi ayaworan pẹlu iṣelọpọ HDMI.
4. So okun HDMI miiran pọ lati HDMI TX asopo lori kaadi ọmọbinrin Bitec HDMI 2.0 FMC si ohun elo HDMI ti o ni HDCP, gẹgẹbi tẹlifisiọnu pẹlu titẹ sii HDMI.

Nigbati SUPPORT FRL = 1, tẹle awọn igbesẹ wọnyi lati ṣeto ohun elo fun awọn ifihan:

1. So Bitec HDMI 2.1 FMC kaadi ọmọbinrin (Atunyẹwo 9) si ohun elo idagbasoke Arria 10 GX ni ibudo FMC B.
2. So ohun elo idagbasoke Arria 10 GX pọ mọ PC rẹ nipa lilo okun USB kan.
3. So awọn kebulu HDMI 2.1 Ẹka 3 kan lati HDMI RX asopo lori kaadi ọmọbinrin Bitec HDMI 2.1 FMC si orisun HDCP-agbara HDMI 2.1, gẹgẹbi kuatomu Data 980 48G Generator.
4. So miiran HDMI 2.1 Ẹka 3 kebulu lati HDMI TX asopo lori Bitec HDMI 2.1 FMC ọmọbinrin kaadi si HDCP-sise HDMI 2.1 ifọwọ, gẹgẹ bi awọn.
   kuatomu Data 980 48G Oluyanju.

4.3.2. Ṣẹda Apẹrẹ
Lẹhin ti ṣeto ohun elo, o nilo lati ṣe ipilẹṣẹ apẹrẹ.
Ṣaaju ki o to bẹrẹ, rii daju lati fi ẹya HDCP sori ẹrọ ni sọfitiwia Intel Quartus Prime Pro Edition.

1. Tẹ Awọn irinṣẹ ➤ IP Catalog, ki o yan Intel Arria 10 gẹgẹbi ẹbi ẹrọ afojusun.
   Akiyesi: Apẹrẹ HDCP example atilẹyin nikan Intel Arria 10 ati Intel Stratix® 10 awọn ẹrọ.
2. Ninu Katalogi IP, wa ati tẹ-lẹẹmeji HDMI Intel FPGA IP. Ferese iyatọ IP Tuntun yoo han.
3. Pato orukọ ipele-oke fun iyatọ IP aṣa rẹ. Olootu paramita n fipamọ awọn eto iyatọ IP ni a file ti a npè ni .qsys tabi .ip.
4. Tẹ O DARA. Olootu paramita yoo han.
5. Lori IP taabu, tunto awọn paramita ti o fẹ fun mejeeji TX ati RX.
6. Tan-an Atilẹyin HDCP 1.4 tabi Atilẹyin HDCP 2.3 paramita lati ṣe ina apẹrẹ HDCP example.
7. Tan paramita Iṣakoso Bọtini HDCP Atilẹyin ti o ba fẹ tọju bọtini iṣelọpọ HDCP ni ọna kika ti paroko ni iranti filasi ita tabi EEPROM. Bibẹẹkọ, pa a paramita Iṣakoso Bọtini Atilẹyin HDCP lati tọju bọtini iṣelọpọ HDCP ni ọna kika itele ni FPGA.
8. Lori apẹrẹ Example taabu, yan Arria 10 HDMI RX-TX Retransmit.
9. Yan Synthesis lati ṣe ina apẹrẹ hardware example.
10. Fun ipilẹṣẹ File Ọna kika, yan Verilog tabi VHDL.
11. Fun Apo Idagbasoke Àkọlé, yan Arria 10 GX FPGA Apo Idagbasoke. Ti o ba yan ohun elo idagbasoke, lẹhinna ẹrọ ibi-afẹde (ti a yan ni igbese 4) yipada lati baamu ẹrọ naa lori ohun elo idagbasoke. Fun Arria 10 GX FPGA Apo Idagbasoke, ẹrọ aiyipada jẹ 10AX115S2F45I1SG.
12. Tẹ ina Example Design lati se ina ise agbese files ati sọfitiwia Executable ati Ọna asopọ Ọna asopọ (ELF) siseto file.

4.3.3. Pẹlu HDCP Awọn bọtini iṣelọpọ
4.3.3.1. Tọju awọn bọtini iṣelọpọ HDCP pẹtẹlẹ ni FPGA (Atilẹyin Bọtini HDCP Isakoso = 0)
Lẹhin ti ipilẹṣẹ apẹrẹ, ṣatunkọ iranti bọtini HDCP files lati ni awọn bọtini iṣelọpọ rẹ.
Lati pẹlu awọn bọtini iṣelọpọ, tẹle awọn igbesẹ wọnyi.

1. Wa iranti bọtini atẹle files ninu /rtl/hdcp/ ilana:
   • hdcp2x_tx_kmem.v
   • hdcp2x_rx_kmem.v
   • hdcp1x_tx_kmem.v
   • hdcp1x_rx_kmem.v
2. Ṣii hdcp2x_rx_kmem.v file ki o si wa bọtini facsimile ti a ti sọ tẹlẹ R1 fun Iwe-ẹri Gbangba Olugba ati Bọtini Aladani RX ati Ibakan Agbaye gẹgẹbi o han ninu iṣaajuamples ni isalẹ.
   Ṣe nọmba 31. Wire Array of Facsimile Key R1 fun Iwe-ẹri gbangba olugba
   Nọmba 32. Wire Array of Facsimile Key R1 fun RX Private Key Key and Global Constant
   
3. Wa ibi ti o wa fun awọn bọtini iṣelọpọ ki o rọpo pẹlu awọn bọtini iṣelọpọ tirẹ ni titobi waya oniwun wọn ni ọna kika endian nla.
   Ṣe nọmba 33. Wire Array ti HDCP Awọn bọtini iṣelọpọ (olugbepo)
   
4. Tun Igbesẹ 3 ṣe fun gbogbo iranti bọtini miiran files. Nigbati o ba ti pari pẹlu awọn bọtini iṣelọpọ rẹ ni gbogbo iranti bọtini files, rii daju pe USE_FACSIMILE paramita ti ṣeto si 0 ni apẹrẹ example oke ipele file (a10_hdmi2_demo.v)

4.3.3.1.1. HDCP Key Mapping lati DCP Key Files
Awọn apakan atẹle n ṣe apejuwe aworan agbaye ti awọn bọtini iṣelọpọ HDCP ti o fipamọ sinu bọtini DCP files sinu okun waya ti HDCP kmem files.
4.3.3.1.2. hdcp1x_tx_kmem.v ati hdcp1x_rx_kmem.v files
Fun hdcp1x_tx_kmem.v ati hdcp1x_rx_kmem.v files

• Awọn meji wọnyi files ti wa ni pínpín kanna kika.
• Lati ṣe idanimọ bọtini HDCP1 TX DCP to tọ file fun hdcp1x_tx_kmem.v, rii daju akọkọ 4 baiti ti awọn file jẹ "0x01, 0x00, 0x00, 0x00".
• Lati ṣe idanimọ bọtini HDCP1 RX DCP to tọ file fun hdcp1x_rx_kmem.v, rii daju akọkọ 4 baiti ti awọn file jẹ "0x02, 0x00, 0x00, 0x00".
• Awọn bọtini inu bọtini DCP files wa ni kekere-endian kika. Lati lo ni kmem files, o gbọdọ se iyipada wọn sinu ńlá-endian.

olusin 34. Baiti maapu lati HDCP1 TX DCP bọtini file sinu hdcp1x_tx_kmem.v

Akiyesi:
Nọmba baiti ṣe afihan ni ọna kika isalẹ:

• Iwọn bọtini ni awọn baiti * nọmba bọtini + nọmba baiti ni ila lọwọlọwọ + aiṣedeede igbagbogbo + iwọn ila ni awọn baiti * nọmba ila.
• 308 * n tọka si pe ṣeto bọtini kọọkan ni awọn baiti 308.
• 7 * y tọkasi wipe kọọkan kana ni o ni 7 baiti.

olusin 35. HDCP1 TX DCP bọtini file àgbáye pẹlu ijekuje iye

olusin 36. Waya Arrays of hdcp1x_tx_kmem.v
Example of hdcp1x_tx_kmem.v ati bi awọn oniwe-waya orunkun maapu si awọn example ti HDCP1 TX DCP bọtini file ni olusin 35 loju iwe 105.

4.3.3.1.3. hdcp2x_rx_kmem.v file
Fun hdcp2x_rx_kmem.v file

• Lati ṣe idanimọ bọtini HDCP2 RX DCP to tọ file fun hdcp2x_rx_kmem.v, rii daju akọkọ 4 baiti ti awọn file jẹ "0x00, 0x00, 0x00, 0x02".
• Awọn bọtini inu bọtini DCP files wa ni kekere-endian kika.

olusin 37. Baiti maapu lati HDCP2 RX DCP bọtini file sinu hdcp2x_rx_kmem.v
Nọmba ti o wa ni isalẹ fihan aworan agbaye baiti gangan lati HDCP2 RX DCP bọtini file sinu hdcp2x_rx_kmem.v.

Akiyesi:
Nọmba baiti ṣe afihan ni ọna kika isalẹ:

• Iwọn bọtini ni awọn baiti * nọmba bọtini + nọmba baiti ni ila lọwọlọwọ + aiṣedeede igbagbogbo + iwọn ila ni awọn baiti * nọmba ila.
• 862 * n tọka si pe ṣeto bọtini kọọkan ni awọn baiti 862.
• 16 * y tọkasi wipe kọọkan kana ni o ni 16 baiti. Iyatọ wa ni cert_rx_prod nibiti ROW 32 ni awọn baiti 10 nikan.

olusin 38. HDCP2 RX DCP bọtini file àgbáye pẹlu ijekuje iye

olusin 39. Waya Arrays of hdcp2x_rx_kmem.v
Nọmba yii ṣe afihan awọn ọna okun waya fun hdcp2x_rx_kmem.v (cert_rx_prod, kprivrx_qinv_prod, ati lc128_prod) maapu si iṣaaju.ample ti HDCP2 RX DCP bọtini file in
Aworan 38 loju iwe 108.

4.3.3.1.4. hdcp2x_tx_kmem.v file
Fun hdcp2x_tx_kmem.v file:

• Lati ṣe idanimọ bọtini HDCP2 TX DCP to tọ file fun hdcp2x_tx_kmem.v, rii daju akọkọ 4 baiti ti awọn file jẹ "0x00, 0x00, 0x00, 0x01".
• Awọn bọtini inu bọtini DCP files wa ni kekere-endian kika.
• Ni omiiran, o le lo lc128_prod lati hdcp2x_rx_kmem.v taara sinu hdcp2x_tx_kmem.v. Awọn bọtini pin awọn iye kanna.

olusin 40. Wire orun ti hdcp2x_tx_kmem.v
Nọmba yii ṣe afihan aworan agbaye baiti gangan lati HDCP2 TX DCP bọtini file sinu hdcp2x_tx_kmem.v.

4.3.3.2. Tọju awọn bọtini iṣelọpọ HDCP ti paroko ni iranti filasi ita tabi EEPROM (Atilẹyin iṣakoso bọtini HDCP = 1)
olusin 41. High Level Overview ti HDCP Key Management

Nigbati paramita Iṣakoso Bọtini HDCP ti wa ni titan, o di iṣakoso ti fifi ẹnọ kọ nkan iṣelọpọ HDCP mu nipa lilo ohun elo sọfitiwia fifi ẹnọ kọ nkan (KEYENC) ati apẹrẹ pirogirama bọtini ti Intel pese. O gbọdọ pese awọn bọtini iṣelọpọ HDCP ati bọtini aabo HDCP 128 kan. Bọtini aabo HDCP
encrypts bọtini iṣelọpọ HDCP ati fi bọtini pamọ sinu iranti filasi ita (fun example, EEPROM) on HDMI ọmọbinrin kaadi.
Tan paramita Iṣakoso Bọtini Atilẹyin HDCP ati ẹya idinku bọtini (KEYDEC) wa ni awọn ohun kohun HDCP IP. Idaabobo HDCP kanna
bọtini yẹ ki o lo ni KEYDEC lati gba awọn bọtini iṣelọpọ HDCP pada ni akoko ṣiṣe fun awọn ẹrọ iṣelọpọ. KEYENC ati KEYDEC ṣe atilẹyin Atmel AT24CS32 32-Kbit serial EEPROM, Atmel AT24C16A 16-Kbit serial EEPROM ati awọn ẹrọ I2C EEPROM ibaramu pẹlu o kere ju 16-Kbit rom.

Akiyesi:

1. Fun HDMI 2.0 FMC ọmọbinrin kaadi Àtúnyẹwò 11, rii daju awọn EEPROM lori awọn ọmọbinrin kaadi ni Atmel AT24CS32. Awọn titobi oriṣiriṣi meji lo wa ti EEPROM ti a lo lori Biec HDMI 2.0 FMC kaadi ọmọbinrin Atunyẹwo 11.
2. Ti o ba ti lo KEYENC tẹlẹ lati encrypt awọn bọtini iṣelọpọ HDCP ati titan Atilẹyin HDCP Key Management ni ẹya 21.2 tabi tẹlẹ, o nilo lati tun-fi paroko awọn bọtini iṣelọpọ HDCP nipa lilo ohun elo sọfitiwia KEYENC ati tun ṣe awọn HDCP IPs lati ẹya 21.3
   siwaju.

4.3.3.2.1. Intel KEYENC
KEYENC jẹ ohun elo sọfitiwia laini aṣẹ ti Intel nlo lati parọ awọn bọtini iṣelọpọ HDCP pẹlu bọtini aabo HDCP 128 bit ti o pese. Awọn abajade KEYENC ti paroko awọn bọtini iṣelọpọ HDCP ni hex tabi bin tabi akọsori file ọna kika. KEYENC tun ṣe ipilẹṣẹ mif file ti o ni bọtini aabo HDCP 128 ti a pese rẹ ninu. KEYDEC
nbeere mif file.

Ibeere eto:

1. x86 64-bit ẹrọ pẹlu Windows 10 OS
2. Ohun elo C ++ Atunpin fun Visual Studio 2019(x64)

Akiyesi:
O gbọdọ fi Microsoft Visual C++ sori ẹrọ fun VS 2019. O le ṣayẹwo boya Visual C++ ti a tun pin kaakiri ti fi sii lati Windows ➤ Igbimọ Iṣakoso ➤ Awọn eto ati Awọn ẹya ara ẹrọ. Ti Microsoft Visual C ++ ti fi sori ẹrọ, o le wo Visual C ++ xxxx
Atunpin (x64). Bibẹẹkọ, o le ṣe igbasilẹ ati fi Visual C++ sori ẹrọ
Ṣe atunpinpin lati ọdọ Microsoft webojula. Tọkasi alaye ti o jọmọ fun ọna asopọ igbasilẹ naa.

Table 55. KEYENC Òfin Line Aw

Òfin Line Aw	Ariyanjiyan / Apejuwe
-k	<HDCP protection key file> Ọrọ file ti o ni bọtini aabo HDCP 128 nikan ni hexadecimal. Example: f0f1f2f3f4f5f6f7f8f9fafbfcfdfeff
-hdcp1tx	<HDCP 1.4 TX production keys file> HDCP 1.4 awọn bọtini iṣelọpọ atagba file lati DCP (.bin file)
-hdcp1rx	<HDCP 1.4 RX production keys file> HDCP 1.4 awọn bọtini iṣelọpọ olugba file lati DCP (.bin file)
-hdcp2tx	<HDCP 2.3 TX production keys file> HDCP 2.3 awọn bọtini iṣelọpọ atagba file lati DCP (.bin file)
-hdcp2rx	<HDCP 2.3 RX production keys file> HDCP 2.3 awọn bọtini iṣelọpọ olugba file lati DCP (.bin file)
-hdcp1txkeys	Pato ibiti bọtini fun titẹ sii ti a yan (.bin) files -hdcp1txkeys|hdcp1rxkeys|hdcp2rxkeys nm nibiti n = ibere bọtini (1 tabi >1) m = ipari bọtini (n tabi > n) Example: Yan awọn bọtini 1 si 1000 lati HDCP 1.4 TX kọọkan, HDCP 1.4 RX ati HCDP 2.3 RX gbóògì bọtini file. "-hdcp1txkeys 1-1000 -hdcp1rxkeys 1-1000 -hdcp2rxkeys 1-1000"
-hdcp1rxkeys
-hdcp2rxkeys
tesiwaju…

Òfin Line Aw	Ariyanjiyan / Apejuwe
	Akiyesi: 1. Ti o ko ba lo awọn bọtini iṣelọpọ HDCP eyikeyi file, iwọ kii yoo nilo ibiti bọtini HDCP. Ti o ko ba lo ariyanjiyan ni laini aṣẹ, ibiti bọtini aiyipada jẹ 0. 2. O tun le yan itọka oriṣiriṣi ti awọn bọtini fun awọn bọtini iṣelọpọ HDCP file. Sibẹsibẹ, nọmba awọn bọtini yẹ ki o baamu awọn aṣayan ti o yan. Example: Yan o yatọ si 100 awọn bọtini Yan awọn bọtini 100 akọkọ lati awọn bọtini iṣelọpọ HDCP 1.4 TX file "-hdcp1txkeys 1-100" Yan awọn bọtini 300 si 400 fun awọn bọtini iṣelọpọ HDCP 1.4 RX file "-hdcp1rxkeys 300-400" Yan awọn bọtini 600 si 700 fun awọn bọtini iṣelọpọ HDCP 2.3 RX file "-hdcp2rxkeys 600-700"
-o	Abajade file ọna kika . Aiyipada jẹ hex file. Ṣe ipilẹṣẹ awọn bọtini iṣelọpọ HDCP ti paroko ni alakomeji file kika: -o bin Ina ti paroko HDCP gbóògì bọtini ni hex file kika: -o hex Ina ti paroko HDCP gbóògì bọtini ni akọsori file kika: -oh
- awọn bọtini ayẹwo	Nọmba titẹ awọn bọtini ti o wa ni titẹ sii files. Eksample:
	keyenc.exe -hdcp1tx file> -hdcp1rx <HDCP 1.4 RX production keys file> -hdcp2tx file> -hdcp2rx file> -awọn bọtini ayẹwo
	Akiyesi: lo paramita –awọn bọtini ayẹwo ni opin laini aṣẹ bi a ti mẹnuba ninu loke example.
-ẹya	Tẹ nọmba ẹya KEYENC

O le yan HDCP 1.4 ati/tabi HDCP 2.3 awọn bọtini iṣelọpọ lati encrypt. Fun example, lati lo awọn bọtini iṣelọpọ HDCP 2.3 RX nikan lati encrypt, lo nikan -hdcp2rx
<HDCP 2.3 RX production keys file> -hdcp2rxkeys ni pipaṣẹ ila sile.
Table 56. KEYENC Itọnisọna Aṣiṣe Aṣiṣe wọpọ

Ifiranṣẹ aṣiṣe	Itọsọna
Aṣiṣe: HDCP Idaabobo bọtini file sonu	Sonu pipaṣẹ ila paramita -k file>
Aṣiṣe: bọtini yẹ ki o jẹ awọn nọmba hex 32 (fun apẹẹrẹ f0f1f2f3f4f5f6f7f8f9fafbfcfdfeff)	HDCP Idaabobo bọtini file yẹ ki o ni bọtini aabo HDCP nikan ni awọn nọmba hexadecimal 32.
Aṣiṣe: Jọwọ pato ibiti bọtini	Iwọn bọtini ko ṣe pato fun titẹ sii HDCP awọn bọtini iṣelọpọ file.
Aṣiṣe: Iwọn bọtini ti ko tọ	Ibiti bọtini pato fun -hdcp1txkeys tabi -hdcp1rxkeys tabi -hdcp2rxkeys ko pe.
Aṣiṣe: ko le ṣẹdaFileorukọ>	Ṣayẹwo igbanilaaye folda lati keyenc.exe ti n ṣiṣẹ.
Aṣiṣe: -hdcp1txkeys igbewọle ko tọ	Ọna kika ibiti bọtini titẹ sii fun awọn bọtini iṣelọpọ HDCP 1.4 TX ko wulo. Ọna kika to pe ni “-hdcp1txkeys nm” nibiti n>= 1, m>= n
Aṣiṣe: -hdcp1rxkeys igbewọle ko tọ	Ọna kika ibiti bọtini titẹ sii fun awọn bọtini iṣelọpọ HDCP 1.4 RX ko wulo. Ọna kika to pe ni “-hdcp1rxkeys nm” nibiti n>= 1, m>= n
Aṣiṣe: -hdcp2rxkeys igbewọle ko tọ	Ọna kika ibiti bọtini titẹ sii fun awọn bọtini iṣelọpọ HDCP 2.3 RX ko wulo. Ọna kika to pe ni “-hdcp2rxkeys nm” nibiti n>= 1, m>= n
tesiwaju…

Ifiranṣẹ aṣiṣe	Itọsọna
Asise: Ko wulo file <fileorukọ>	Awọn bọtini iṣelọpọ HDCP ti ko tọ file.
Asise: file iru sonu fun -o aṣayan	Pamita laini aṣẹ sonu fun –o .
Aṣiṣe: ko wulo fileoruko –fileorukọ>	<fileorukọ> ko wulo, jọwọ lo wulo filelorukọ lai pataki ohun kikọ.

Encrypt Nikan Key fun Nikan EEPROM
Ṣiṣe laini aṣẹ atẹle lati aṣẹ aṣẹ Windows lati encrypt bọtini ẹyọkan ti HDCP 1.4 TX, HDCP 1.4 RX, HDCP 2.3 TX ati HDCP 2.3 RX pẹlu iṣẹjade file kika akọsori file fun EEPROM ẹyọkan:
keyenc.exe -k file> -hdcp1tx file> -hdcp1rx file> -hdcp2tx file> -hdcp2rx file> -hdcp1txkeys 1-1 -hdcp1rxkeys 1-1 -hdcp2rxkeys 1-1 -oh

Encrypt N Awọn bọtini fun N EEPROMs
Ṣiṣe laini aṣẹ atẹle lati inu aṣẹ aṣẹ Windows lati encrypt awọn bọtini N (ti o bẹrẹ lati bọtini 1) ti HDCP 1.4 TX, HDCP 1.4 RX, HDCP 2.3 TX ati HDCP 2.3 RX pẹlu iṣẹjade file kika hex file fun N EEPROMs:
keyenc.exe -k file> -hdcp1tx file> -hdcp1rx file> -hdcp2tx file> -hdcp2rx file> -hdcp1txkeys 1 -hdcp1rxkeys 1- -hdcp2rxkeys 1- -o hex nibiti N wa>= 1 ati pe o yẹ ki o baamu fun gbogbo awọn aṣayan.

Alaye ti o jọmọ
Microsoft Visual C ++ fun Studio Visual 2019
Pese Microsoft Visual C ++ x86 package redistributable (vc_redist.x86.exe) fun igbasilẹ. Ti ọna asopọ ba yipada, Intel ṣeduro fun ọ lati wa “Visual C++ atunpinpin” lati ẹrọ wiwa Microsoft.

4.3.3.2.2. Olupilẹṣẹ bọtini
Lati ṣe eto awọn bọtini iṣelọpọ HDCP ti paroko sori EEPROM, tẹle awọn igbesẹ wọnyi:

1. Da apẹrẹ pirogirama bọtini files lati ọna atẹle si itọsọna iṣẹ rẹ: /hdcp2x/hw_demo/key_programmer/
2. Daakọ akọsori sọfitiwia file (hdcp_key .h) ti ipilẹṣẹ lati IwUlO sọfitiwia KEYENC (apakan Encrypt Single Key fun Nikan EEPROM ni oju-iwe 113) si sọfitiwia/key_programmer_src/ liana ki o tun lorukọ rẹ bi hdcp_key.h.
3. Ṣiṣe ./runall.tcl. Iwe afọwọkọ yii nṣiṣẹ awọn aṣẹ wọnyi:
   Ṣe ina IP katalogi files
   • Ina awọn Platform onise eto
   • Ṣẹda Intel Quartus Prime ise agbese
   Ṣẹda aaye iṣẹ sọfitiwia ati kọ sọfitiwia naa
   Ṣe akojọpọ kikun
4. Ṣe igbasilẹ Nkan Software File (.sof) si FPGA lati ṣe eto awọn bọtini iṣelọpọ HDCP ti paroko sori EEPROM.

Ṣe ina Stratix 10 HDMI RX-TX Retransmit design example pẹlu Atilẹyin HDCP 2.3 ati Atilẹyin HDCP 1.4 paramita titan, lẹhinna tẹle igbesẹ atẹle lati ṣafikun bọtini aabo HDCP.

• Daakọ mif file (hdcp_kmem.mif) ti ipilẹṣẹ lati inu ohun elo sọfitiwia KEYENC (apakan Encrypt Key Key fun Nikan EEPROM ni oju-iwe 113) si /quartus/hdcp/ liana.

4.3.4. Ṣe akopọ Oniru naa
Lẹhin ti o ṣafikun awọn bọtini iṣelọpọ HDCP pẹtẹlẹ tirẹ ninu FPGA tabi ṣe eto awọn bọtini iṣelọpọ HDCP ti paroko si EEPROM, o le ṣajọ apẹrẹ naa ni bayi.

1. Lọlẹ Intel Quartus Prime Pro Edition sọfitiwia ati ṣii /quartus/a10_hdmi2_demo.qpf.
2. Tẹ Ṣiṣeto ➤ Bẹrẹ Iṣakojọpọ.

4.3.5. View awon Iyori si
Ni ipari ifihan, iwọ yoo ni anfani lati view awọn esi lori HDCPenabled HDMI ifọwọ ita.
Si view Awọn abajade ifihan, tẹle awọn igbesẹ wọnyi:

1. Agbara soke Intel FPGA ọkọ.
2. Yi liana si /quartus/.
3. Tẹ aṣẹ atẹle naa sori Ikarahun Aṣẹ Nios II lati ṣe igbasilẹ Nkan sọfitiwia naa File (.sof) si FPGA. nios2-configure-sof output_files/ .oso
4. Fi agbara mu HDCP-agbara HDMI orisun ita ati rii (ti o ko ba ṣe bẹ). Awọn HDMI ita rii han awọn wu ti rẹ HDMI ita orisun.

4.3.5.1. Awọn bọtini Titari ati Awọn iṣẹ LED
Lo awọn bọtini titari ati awọn iṣẹ LED lori igbimọ lati ṣakoso ifihan rẹ.

Tabili 57. Bọtini Titari ati Awọn Atọka LED (SUPPORT FRL = 0)

Titari Bọtini / LED	Awọn iṣẹ
cpu_resetn	Tẹ lẹẹkan lati ṣe atunto eto.
olumulo_pb[0]	Tẹ lẹẹkan lati yi ifihan agbara HPD pada si orisun HDMI boṣewa.
olumulo_pb[1]	• Tẹ mọlẹ lati kọ TX mojuto lati fi ifihan koodu DVI ranṣẹ. Tu silẹ lati fi ami ami koodu HDMI ranṣẹ. • Rii daju pe fidio ti nwọle wa ni 8 bpc RGB aaye awọ.
olumulo_pb[2]	Tẹ mọlẹ lati kọ TX mojuto lati da fifiranṣẹ InfoFrames duro lati awọn ifihan agbara ẹgbẹ ẹgbẹ. Tu silẹ lati bẹrẹ fifiranṣẹ InfoFrames lati awọn ifihan agbara ẹgbẹ ẹgbẹ.
olumulo_led[0]	RX HDMI PLL ipo titiipa. • 0: Ṣii silẹ • 1: Titiipa
olumulo_led[1]	RX HDMI ipo titiipa mojuto • 0: O kere ju ikanni 1 ṣiṣi silẹ • 1: Gbogbo awọn ikanni 3 wa ni titiipa
olumulo_led[2]	RX HDCP1x IP ipo decryption. • 0: Aiṣiṣẹ • 1: Ti nṣiṣe lọwọ
olumulo_led[3]	RX HDCP2x IP ipo decryption. • 0: Aiṣiṣẹ • 1: Ti nṣiṣe lọwọ
olumulo_led[4]	TX HDMI PLL ipo titiipa. • 0: Ṣii silẹ • 1: Titiipa
olumulo_led[5]	TX transceiver PLL ipo titiipa. • 0: Ṣii silẹ • 1: Titiipa
olumulo_led[6]	TX HDCP1x IP ipo ìsekóòdù. • 0: Aiṣiṣẹ • 1: Ti nṣiṣe lọwọ
olumulo_led[7]	TX HDCP2x IP ipo ìsekóòdù. • 0: Aiṣiṣẹ • 1: Ti nṣiṣe lọwọ

Tabili 58. Bọtini Titari ati Awọn Atọka LED (SUPPORT FRL = 1)

Titari Bọtini / LED	Awọn iṣẹ
cpu_resetn	Tẹ lẹẹkan lati ṣe atunto eto.
olumulo_dipsw	Olumulo-telẹ DIP yipada lati yi ipo irekọja lọ. • PA (aiyipada ipo) = Passthrough HDMI RX lori FPGA gba EDID lati inu ifọwọ ita ati ṣafihan si orisun ita ti o sopọ si. • ON = O le ṣakoso iwọn FRL ti o pọju RX lati ebute Nios II. Aṣẹ ṣe atunṣe RX EDID nipa ifọwọyi iye oṣuwọn FRL ti o pọju. Tọkasi si Ṣiṣe Apẹrẹ ni Awọn Oṣuwọn FRL oriṣiriṣi loju iwe 33 fun alaye siwaju sii nipa tito awọn oriṣiriṣi awọn oṣuwọn FRL.
tesiwaju…

Titari Bọtini / LED	Awọn iṣẹ
olumulo_pb[0]	Tẹ lẹẹkan lati yi ifihan agbara HPD pada si orisun HDMI boṣewa.
olumulo_pb[1]	Ni ipamọ.
olumulo_pb[2]	Tẹ lẹẹkan lati ka awọn iforukọsilẹ SCDC lati ibi ifọwọ ti a ti sopọ si TX ti kaadi ọmọbinrin Bitec HDMI 2.1 FMC. Akiyesi: Lati mu kika ṣiṣẹ, o gbọdọ ṣeto DEBUG_MODE si 1 ninu sọfitiwia naa.
olumulo_led_g[0]	RX FRL aago PLL ipo titiipa. • 0: Ṣii silẹ • 1: Titiipa
olumulo_led_g[1]	RX HDMI ipo titiipa fidio. • 0: Ṣii silẹ • 1: Titiipa
olumulo_led_g[2]	RX HDCP1x IP ipo decryption. • 0: Aiṣiṣẹ • 1: Ti nṣiṣe lọwọ
olumulo_led_g[3]	RX HDCP2x IP ipo decryption. • 0: Aiṣiṣẹ • 1: Ti nṣiṣe lọwọ
olumulo_led_g[4]	TX FRL aago PLL ipo titiipa. • 0: Ṣii silẹ • 1: Titiipa
olumulo_led_g[5]	TX HDMI ipo titiipa fidio. • 0 = Ṣii silẹ • 1 = Titiipa
olumulo_led_g[6]	TX HDCP1x IP ipo ìsekóòdù. • 0: Aiṣiṣẹ • 1: Ti nṣiṣe lọwọ
olumulo_led_g[7]	TX HDCP2x IP ipo ìsekóòdù. • 0: Aiṣiṣẹ • 1: Ti nṣiṣe lọwọ

4.4. Idaabobo ti Bọtini fifi ẹnọ kọ nkan ti a fi sinu Apẹrẹ FPGA
Ọpọlọpọ awọn apẹrẹ FPGA ṣe fifi ẹnọ kọ nkan, ati pe igbagbogbo iwulo wa lati fi sabe awọn bọtini aṣiri ninu ṣiṣan FPGA. Ninu awọn idile ẹrọ tuntun, bii Intel Stratix 10 ati Intel Agilex, bulọọki Oluṣakoso Ẹrọ Aabo kan wa ti o le pese ni aabo ati ṣakoso awọn bọtini aṣiri wọnyi. Nibiti awọn ẹya wọnyi ko si, o le ni aabo akoonu ti FPGA bitstream, pẹlu eyikeyi awọn bọtini olumulo ikoko ti a fi sii, pẹlu fifi ẹnọ kọ nkan.
Awọn bọtini olumulo yẹ ki o wa ni aabo laarin agbegbe apẹrẹ rẹ, ati pe o yẹ ki o ṣafikun si apẹrẹ nipa lilo ilana aabo adaṣe. Awọn igbesẹ wọnyi fihan bi o ṣe le ṣe iru ilana kan pẹlu awọn irinṣẹ Intel Quartus Prime.

1. Dagbasoke ati mu HDL pọ si ni Intel Quartus Prime ni agbegbe ti ko ni aabo.
2. Gbe apẹrẹ lọ si agbegbe to ni aabo ati ṣe ilana adaṣe lati ṣe imudojuiwọn bọtini aṣiri. Iranti on-chip ṣe ifibọ iye bọtini. Nigbati bọtini ti ni imudojuiwọn, ipilẹṣẹ iranti file (.mif) le yipada ati ṣiṣan apejọ “quartus_cdb –update_mif” le yi bọtini aabo HDCP pada laisi iṣakojọpọ. Igbesẹ yii yara pupọ lati ṣiṣẹ ati ṣe itọju akoko atilẹba naa.
3. Intel Quartus Prime bitstream lẹhinna encrypt pẹlu bọtini FPGA ṣaaju ki o to gbe ṣiṣan ṣiṣan ti paroko pada si agbegbe ti ko ni aabo fun idanwo ikẹhin ati imuṣiṣẹ.

A ṣe iṣeduro lati mu gbogbo iraye si atunkọ ti o le gba bọtini aṣiri pada lati FPGA. O le mu awọn agbara yokokoro kuro patapata nipa piparẹ JTAG ibudo, tabi selectively mu ati ki o tunview pe ko si awọn ẹya yokokoro bii olootu iranti eto inu tabi Tẹ ifihan agbara le gba bọtini pada. Tọkasi AN 556: Lilo Awọn ẹya Aabo Apẹrẹ ni Intel FPGAs fun alaye siwaju lori lilo awọn ẹya aabo FPGA pẹlu awọn igbesẹ kan pato lori bii o ṣe le encrypt FPGA bitstream ati tunto awọn aṣayan aabo bii piparẹ JTAG wiwọle.

Akiyesi:
O le ronu igbesẹ afikun ti obfuscation tabi fifi ẹnọ kọ nkan pẹlu bọtini miiran ti bọtini aṣiri ni ibi ipamọ MIF.
Alaye ti o jọmọ
AN 556: Lilo Awọn ẹya Aabo Oniru ni Intel FPGAs

4.5. Aabo riro
Nigbati o ba nlo ẹya HDCP, ṣe akiyesi awọn ero aabo atẹle.

• Nigbati o ba n ṣe apẹrẹ eto atunwi, o gbọdọ dènà fidio ti o gba lati titẹ TX IP ni awọn ipo wọnyi:
  - Ti fidio ti o gba naa ba jẹ HDCP-encrypted (ie ipo fifi ẹnọ kọ nkan hdcp1_enabled tabi hdcp2_enabled lati RX IP ti wa ni ẹtọ) ati pe fidio ti a firanṣẹ ko jẹ HDCP-encrypted (ie ipo fifi ẹnọ kọ nkan hdcp1_enabled tabi hdcp2_enabled lati TX IP ko ni ẹtọ).
  - Ti fidio ti o gba ba jẹ HDCP TYPE 1 (ie streamid_type lati RX IP ti fi idi rẹ mulẹ) ati pe fidio ti o gbejade jẹ fifi ẹnọ kọ nkan HDCP 1.4 (ie ipo fifi ẹnọ kọ nkan hdcp1_enabled lati TX IP ti jẹri)
• O yẹ ki o ṣetọju aṣiri ati iduroṣinṣin ti awọn bọtini iṣelọpọ HDCP rẹ, ati awọn bọtini fifi ẹnọ kọ nkan olumulo.
• Intel ṣeduro rẹ ni pataki lati ṣe agbekalẹ eyikeyi awọn iṣẹ akanṣe Intel Quartus Prime ati orisun apẹrẹ files ti o ni awọn bọtini fifi ẹnọ kọ nkan ni agbegbe iṣiro to ni aabo lati daabobo awọn bọtini.
• Intel ṣeduro fun ọ ni iyanju lati lo awọn ẹya aabo apẹrẹ ni awọn FPGA lati daabobo apẹrẹ naa, pẹlu eyikeyi awọn bọtini fifi ẹnọ kọ nkan, lati didaakọ laigba aṣẹ, imọ-ẹrọ yiyipada, ati tampsisun.

Alaye ti o jọmọ
AN 556: Lilo Awọn ẹya Aabo Oniru ni Intel FPGAs

4.6. Awọn Itọsọna Atunṣe
Abala yii ṣe apejuwe ifihan ipo HDCP wulo ati awọn paramita sọfitiwia ti o le ṣee lo fun n ṣatunṣe aṣiṣe. O tun ni awọn ibeere ti a beere nigbagbogbo (FAQ) nipa ṣiṣe apẹrẹ tẹlẹample.

4.6.1. HDCP Awọn ifihan agbara Ipo
Awọn ifihan agbara pupọ wa ti o wulo lati ṣe idanimọ ipo iṣẹ ti awọn ohun kohun HDCP IP. Awọn ifihan agbara wọnyi wa ni apẹrẹ example ipele-oke ati pe a so mọ awọn LED ti inu:

Orukọ ifihan agbara	Išẹ
hdcp1_enabled_rx	RX HDCP1x IP Decryption Ipo 0: Aisise 1: Ti nṣiṣe lọwọ
hdcp2_enabled_rx	RX HDCP2x IP Decryption Ipo 0: Aisise 1: Ti nṣiṣe lọwọ
hdcp1_enabled_tx	TX HDCP1x IP ìsekóòdù Ipo 0: Aisise 1: Ti nṣiṣe lọwọ
hdcp2_enabled_tx	TX HDCP2x IP ìsekóòdù Ipo 0: Aisise 1: Ti nṣiṣe lọwọ

Tọkasi Table 57 loju iwe 115 ati Table 58 loju iwe 115 fun awọn oniwun LED placements.
Ipo ti nṣiṣe lọwọ ti awọn ifihan agbara wọnyi tọkasi pe HDCP IP jẹ ifọwọsi ati gbigba/firanṣẹ ṣiṣan fidio ti paroko. Fun itọsọna kọọkan, nikan HDCP1x tabi HDCP2x
ìsekóòdù/decryption ipo awọn ifihan agbara ti nṣiṣe lọwọ. Fun example, ti o ba ti boya hdcp1_enabled_rx tabi hdcp2_enabled_rx ti nṣiṣe lọwọ, ti wa ni HDCP lori RX ẹgbẹ sise ati ki o decrypting awọn ti paroko fidio san lati awọn ita fidio orisun.

4.6.2. Iyipada HDCP Software paramita
Lati dẹrọ ilana n ṣatunṣe aṣiṣe HDCP, o le ṣe atunṣe awọn paramita ni hdcp.c.
Tabili ti o wa ni isalẹ ṣe akopọ atokọ ti awọn aye atunto ati awọn iṣẹ wọn.

Paramita	Išẹ
SUPPORT_HDCP1X	Mu HDCP 1.4 ṣiṣẹ ni ẹgbẹ TX
SUPPORT_HDCP2X	Mu HDCP 2.3 ṣiṣẹ ni ẹgbẹ TX
DEBUG_MODE_HDCP	Mu awọn ifiranṣẹ yokokoro ṣiṣẹ fun TX HDCP
REPEATER_MODE	Mu ipo atunṣe ṣiṣẹ fun apẹrẹ HDCP example

Lati yi awọn paramita pada, yi awọn iye pada si awọn iye ti o fẹ ni hdcp.c. Ṣaaju ki o to bẹrẹ akojọpọ, ṣe iyipada atẹle ni build_sw_hdcp.sh:

1. Wa laini atẹle ki o sọ asọye lati ṣe idiwọ sọfitiwia ti a ṣe atunṣe file ni rọpo nipasẹ atilẹba files lati ọna fifi sori ẹrọ Intel Quartus Prime Software.
   
2.  Ṣiṣe “./build_sw_hdcp.sh” lati ṣajọ sọfitiwia imudojuiwọn.
3. Awọn ti ipilẹṣẹ .elf file O le wa ninu apẹrẹ nipasẹ awọn ọna meji:
   a. Ṣiṣe “nios2-download -g file orukọ >". Tun eto naa pada lẹhin ilana igbasilẹ ti pari lati rii daju iṣẹ ṣiṣe to dara.
   b. Ṣiṣe "quartus_cdb --update_mif" lati ṣe imudojuiwọn ibẹrẹ iranti files. Ṣiṣe assembler lati se ina titun .sof file eyiti o pẹlu sọfitiwia imudojuiwọn.

4.6.3. Awọn ibeere Nigbagbogbo (FAQ)
Table 59. Ikuna Awọn aami aisan ati awọn Itọsọna

Nọmba	Àmì Ìkùnà	Itọsọna
1.	RX n gba fidio ti paroko, ṣugbọn TX n firanṣẹ fidio aimi ni awọ buluu tabi dudu.	Eyi jẹ nitori ijẹrisi TX ti ko ni aṣeyọri pẹlu ifọwọ ita. Atunṣe to lagbara HDCP ko gbọdọ tan fidio naa ni ọna kika ti ko pa akoonu ti fidio ti nwọle lati oke ti wa ni fifi ẹnọ kọ nkan. Lati ṣaṣeyọri eyi, fidio aimi ni awọ buluu tabi dudu rọpo fidio ti njade nigbati ifihan ipo fifi ẹnọ kọ nkan TX HDCP ko ṣiṣẹ lakoko ti ifihan ipo decryption RX HDCP nṣiṣẹ. Fun awọn itọnisọna gangan, tọka si Aabo riro loju iwe 117. Bibẹẹkọ, ihuwasi yii le ṣe idiwọ ilana ṣiṣatunṣe nigbati o ba mu apẹrẹ HDCP ṣiṣẹ. Ni isalẹ ni ọna lati mu idaduro fidio ṣiṣẹ ni apẹrẹ example: 1. Wa ọna asopọ ibudo atẹle ni ipele oke ti apẹrẹ example. Eleyi ibudo je ti si hdmi_tx_top module. 2. Ṣatunṣe asopọ ibudo si laini atẹle:
2.	Ifihan ipo fifi ẹnọ kọ nkan TX HDCP nṣiṣẹ ṣugbọn aworan yinyin ti han ni ibi iwẹ isalẹ.	Eleyi jẹ nitori awọn ibosile rii ko ni decrypt ti njade ti paroko fidio ti tọ. Rii daju pe o pese ibakan agbaye (LC128) si TX HDCP IP. Iye gbọdọ jẹ iye iṣelọpọ ati pe o tọ.
3.	Ifihan ipo fifi ẹnọ kọ nkan TX HDCP jẹ riru tabi aiṣiṣẹ nigbagbogbo.	Eyi jẹ nitori ijẹrisi TX ti ko ṣaṣeyọri pẹlu ifọwọ isalẹ. Lati dẹrọ ilana n ṣatunṣe aṣiṣe, o le mu awọn DEBUG_MODE_HDCP paramita ni hdcp.c. Tọkasi si Iyipada HDCP Software paramita loju iwe 118 lori awọn itọnisọna. 3a-3c atẹle le jẹ awọn okunfa ti o ṣeeṣe ti ijẹrisi TX ti ko ni aṣeyọri.
3a.	Akọọlẹ yokokoro sọfitiwia n tẹsiwaju titẹ sita ifiranṣẹ yii “HDCP 1.4 ko ni atilẹyin nipasẹ isalẹ (Rx)”.	Ifiranṣẹ naa tọkasi ifọwọ isalẹ ko ṣe atilẹyin mejeeji HDCP 2.3 ati HDCP 1.4. Rii daju wipe awọn ifọwọ isalẹ awọn atilẹyin HDCP 2.3 tabi HDCP 1.4.
3b.	Ijeri TX kuna ni agbedemeji.	Eyi jẹ nitori eyikeyi apakan ti ijẹrisi TX gẹgẹbi ijẹrisi ibuwọlu, ṣayẹwo agbegbe ati bẹbẹ lọ le kuna. Rii daju pe ifọwọ isalẹ n lo bọtini iṣelọpọ ṣugbọn kii ṣe bọtini facsimile.
3c.	Akọọlẹ yokokoro sọfitiwia n tẹsiwaju titẹ sita “Atun-ifọwọsi	Ifiranṣẹ yii tọkasi ifọwọ-isalẹ ti beere tun-ifọwọsi nitori fidio ti o gba ko ni idinku ni deede. Rii daju pe o pese ibakan agbaye (LC128) si TX HDCP IP. Iye naa gbọdọ jẹ iye iṣelọpọ ati pe iye naa jẹ deede.
tesiwaju…

Nọmba	Àmì Ìkùnà	Itọsọna
	nilo” lẹhin ti ijẹrisi HDCP ti pari.
4.	Ipo ifihan ipo idinku RX HDCP ko ṣiṣẹ botilẹjẹpe orisun oke ti mu HDCP ṣiṣẹ.	Eyi tọkasi pe RX HDCP IP ko ti ṣaṣeyọri ipo ti o jẹri. Nipa aiyipada, awọn REPEATER_MODE paramita wa ni sise ninu awọn oniru example. Ti o ba ti REPEATER_MODE ti ṣiṣẹ, rii daju pe TX HDCP IP ti jẹri. Nigbati awọn REPEATER_MODE paramita wa ni sise, RX HDCP IP igbiyanju ìfàṣẹsí bi a repeater ti o ba ti TX ti sopọ si a HDCP-agbara ifọwọ. Ijeri naa duro ni agbedemeji lakoko ti o nduro fun TX HDCP IP lati pari ijẹrisi pẹlu ifọwọ isalẹ ki o kọja RECEIVERID_LIST si RX HDCP IP. Ipari akoko bi a ti ṣalaye ni pato HDCP jẹ iṣẹju-aaya 2. Ti TX HDCP IP ko ba le pari ifitonileti ni asiko yii, orisun ti o wa ni oke n tọju ijẹrisi naa bi kuna ati pe o bẹrẹ ijẹri-ifọwọsi gẹgẹbi pato ninu HDCP Specification.
		Akiyesi: Tọkasi si Iyipada HDCP Software paramita loju iwe 118 fun ọna lati mu awọn REPEATER_MODE paramita fun idi ti n ṣatunṣe aṣiṣe. Lẹhin ti disabling awọn REPEATER_MODE paramita, RX HDCP IP nigbagbogbo ngbiyanju ijẹrisi bi olugba ipari. TX HDCP IP ko ni ẹnu-ọna ilana ijẹrisi naa.
		• Ti o ba ti REPEATER_MODE paramita ko ṣiṣẹ, rii daju pe bọtini HDCP ti a pese si HDCP IP jẹ iye iṣelọpọ ati pe iye naa jẹ deede.
5.	Ipo ifihan ipo decryption RX HDCP jẹ riru.	Eyi tumọ si pe RX HDCP IP ti beere tun-ifọwọsi ni kete lẹhin ti ipo ijẹrisi ti waye. Eyi ṣee ṣe nitori fidio fifi ẹnọ kọ nkan ti nwọle ko ni idinku ni deede nipasẹ RX HDCP IP. Rii daju pe ibakan agbaye (LC128) ti a pese si RX HDCP IP mojuto jẹ iye iṣelọpọ ati pe iye naa jẹ deede.

HDMI Intel Arria 10 FPGA IP Design Eksample User Itọsọna Archives

Fun awọn ẹya tuntun ati iṣaaju ti itọsọna olumulo, tọka si HDMI Intel® Arria 10 FPGA IP Design Example User Itọsọna. Ti IP tabi ẹya sọfitiwia ko ba ṣe akojọ, itọsọna olumulo fun IP iṣaaju tabi ẹya sọfitiwia kan.
Awọn ẹya IP jẹ kanna bi awọn ẹya sọfitiwia Intel Quartus Prime Design Suite to v19.1. Lati Intel Quartus Prime Design Suite software version 19.2 tabi nigbamii, IP
ohun kohun ni a titun IP versioning eni.

Itan Atunyẹwo fun HDMI Intel Arria 10 FPGA IP Design Example User Itọsọna

Ẹya Iwe aṣẹ	Intel Quartus NOMBA Version	Ẹya IP	Awọn iyipada
2022.12.27	22.4	19.7.1	Ṣe afikun paramita tuntun kan fun yiyan atunyẹwo kaadi ọmọbinrin HDMI si apakan Hardware ati Awọn ibeere sọfitiwia ti apẹrẹ apẹrẹ.ample fun HDMI 2.0 (ti kii-FRL mode).
2022.07.29	22.2	19.7.0	• Iwifunni yiyọkuro paati Cygwin lati ẹya Windows* ti Nios II EDS ati ibeere lati fi sori ẹrọ WSL fun awọn olumulo Windows*. • Ẹya kaadi ọmọbirin ti a ṣe imudojuiwọn lati Atunyẹwo 4 si 9 nibiti o wulo jakejado iwe-ipamọ naa.
2021.11.12	21.3	19.6.1	• Ṣe imudojuiwọn abala apakan Ile-itaja ti paroko awọn bọtini iṣelọpọ HDCP ni iranti filasi ita tabi EEPROM (Atilẹyin HDCP Key Management = 1) lati ṣapejuwe IwUlO sọfitiwia fifi ẹnọ kọkọrọ tuntun (KEYENC). • Yọ awọn isiro wọnyi kuro: - Data orun ti Facsimile Key R1 fun RX Aladani Key - Awọn akojọpọ data ti awọn bọtini iṣelọpọ HDCP (olugbepo) - Eto data ti bọtini Idaabobo HDCP (bọtini ti a ti yan tẹlẹ) - Bọtini aabo HDCP ti ipilẹṣẹ ni hdcp2x_tx_kmem.mif - Bọtini aabo HDCP ti ipilẹṣẹ ni hdcp1x_rx_kmem.mif - Bọtini aabo HDCP ti ipilẹṣẹ ni hdcp1x_tx_kmem.mif • Ti gbe HDCP Key Mapping lati DCP Key Files lati Awọn Itọsọna yokokoro si Tọju awọn bọtini iṣelọpọ HDCP pẹtẹlẹ ni FPGA (Atilẹyin Iṣakoso Bọtini HDCP = 0).
2021.09.15	21.1	19.6.0	Yọ tọka si ncsim
2021.05.12	21.1	19.6.0	• Fi kun Nigbati SUPPORT FRL = 1 tabi atilẹyin HDCP KEY MANAGEMENT = 1 si apejuwe fun Nọmba 29 HDCP Lori HDMI Design Example Àkọsílẹ aworan atọka. Fikun awọn igbesẹ ni iranti bọtini HDCP files ni Design Ririn. Fi kun Nigbati SUPPORT FRL = 0 si apakan Ṣeto ohun elo ardware. • Fikun igbesẹ lati tan Atilẹyin HDCP Key paramita Iṣakoso ni Ṣẹda Oniru naa. Fi kun abala tuntun Ile-itaja ti paroko awọn bọtini iṣelọpọ HDCP ni iranti filasi ita tabi EEPROM (Atilẹyin HDCP Key Management = 1).
tesiwaju…

Ẹya Iwe aṣẹ	Intel Quartus NOMBA Version	Ẹya IP	Awọn iyipada
			• Bọtini Titari Tabili Ti lorukọmii ati Awọn Atọka LED si Titari Bọtini ati Awọn Atọka LED (SUPPORT FRL = 0). • Bọtini Titari Tabili ti a ṣafikun ati Awọn Atọka LED (SUPPORT FRL = 1). • Ṣafikun ipin titun kan Idaabobo ti Bọtini fifi ẹnọ kọ nkan ti a fi sinu Apẹrẹ FPGA. Fikun ipin tuntun Awọn Itọsọna Iyipada Iyipada ati awọn apakan HDCP Awọn ifihan agbara Ipo, Iyipada HDCP sọfitiwia paramita ati Awọn ibeere ti a beere nigbagbogbo.
2021.04.01	21.1	19.6.0	• Awọn ohun elo nọmba ti a ṣe imudojuiwọn Ti beere fun RX-Nikan tabi Apẹrẹ TX-Nikan. • Table imudojuiwọn ti ipilẹṣẹ RTL Files. • Nọmba imudojuiwọn HDMI RX Top irinše. • Abala ti a yọ kuro HDMI RX Ilana Ikẹkọ Ọna asopọ Top. • Ṣe imudojuiwọn awọn igbesẹ ni Ṣiṣe Apẹrẹ ni Awọn Iwọn FRL oriṣiriṣi. • Nọmba imudojuiwọn HDMI 2.1 Design Example clocking Ero. • Awọn ifihan agbara Titiipa tabili ti a ṣe imudojuiwọn. • Nọmba imudojuiwọn HDMI RX-TX Block Diagram lati ṣafikun asopọ kan lati Transceiver Arbiter si oke TX.
2020.09.28	20.3	19.5.0	• Yọ akiyesi pe HDMI 2.1 design example ni ipo FRL ṣe atilẹyin ipele iyara nikan -1 awọn ẹrọ ni HDMI Intel FPGA IP Design Example Quick Bẹrẹ Itọsọna fun Intel Arria 10 Awọn ẹrọ ati HDMI 2.1 Design Eksample (Support FRL = 1) ruju. Apẹrẹ ṣe atilẹyin fun gbogbo awọn onipò iyara. • Alaye ls_clk kuro lati gbogbo HDMI 2.1 design example jẹmọ ruju. Agbegbe ls_clk ko si ni lilo ninu apẹrẹ tẹlẹample. • Ṣe imudojuiwọn awọn aworan atọka fun HDMI 2.1 apẹrẹ example ni ipo FRL ni HDMI 2.1 Design Example (Atilẹyin FRL = 1), Ṣiṣẹda RX- Nikan tabi TX-Nikan Awọn Irinṣe Apẹrẹ, ati Awọn apakan Eto Titiipa. • Ṣe imudojuiwọn awọn ilana ati ipilẹṣẹ files akojọ ninu awọn apakan Directory Be. • Yọ awọn ifihan agbara ti ko ṣe pataki kuro, ati ṣafikun tabi ṣatunkọ apejuwe ti atẹle HDMI 2.1 apẹrẹ example awọn ifihan agbara ni apakan Awọn ifihan agbara wiwo: - sys_init - txpll_frl_locked - tx_os - txphy_rcfg * awọn ifihan agbara - tx_reconfig_done - txcore_tbcr - pio_in0_external_connection_export Fikun awọn paramita wọnyi ni apakan Awọn paramita RTL apẹrẹ: - EDID_RAM_ADDR_WIDTH - BITEC_DAUGHTER_CARD_REV - LO FPLL - POLARITY_INVERSION
tesiwaju…

Ẹya Iwe aṣẹ	Intel Quartus NOMBA Version	Ẹya IP	Awọn iyipada
			• Ṣe imudojuiwọn awọn aworan atọka fun HDMI 2.0 apẹrẹ example fun Intel Quartus Prime Pro Edition sọfitiwia ni HDMI 2.0 Design Example (Atilẹyin FRL = 0), Ṣiṣẹda RX-Nikan tabi TX-Nikan Awọn Irinṣe Apẹrẹ, ati Awọn apakan Eto Aago. • Ṣe imudojuiwọn aago ati tun awọn orukọ ifihan to ni Ibiti Yiyipo ati Mastering (HDR) InfoFrame Fi sii ati Sisẹ apakan. • Yọ awọn ifihan agbara ti ko ṣe pataki kuro, ati ṣafikun tabi ṣatunkọ apejuwe ti atẹle HDMI 2.0 apẹrẹ example awọn ifihan agbara ni apakan Awọn ifihan agbara wiwo: - clk_fpga_b3_p - REFCLK_FMCB_P - fmcb_la_tx_p_11 - fmcb_la_rx_n_9e - fr_clck - reset_xcvr_powerup - nios_tx_i2c * awọn ifihan agbara - hdmi_ti_i2c * awọn ifihan agbara - tx_i2c_avalon * awọn ifihan agbara - clock_bridge_0_in_clk_clk - reset_bridge_0_reset_reset_n - i2c_master * awọn ifihan agbara - nios_tx_i2c * awọn ifihan agbara - odiwọn_valid_pio_external_connectio n_export - awọn ifihan agbara oc_i2c_av_slave_translator_avalon_an ti_slave_0* - powerup_cal_done_export - rx_pma_cal_busy_export - rx_pma_ch_export - rx_pma_rcfg_mgmt * awọn ifihan agbara • Fi kun akọsilẹ kan pe testbench kikopa ko ni atilẹyin fun awọn aṣa pẹlu awọn Pẹlu I2C paramita ṣiṣẹ ati imudojuiwọn ifiranṣẹ kikopa ni apakan Testbench Simulation. • Ṣe imudojuiwọn apakan Igbegasoke rẹ Oniru.
2020.04.13	20.1	19.4.0	• Fi kun akọsilẹ kan pe HDMI 2.1 design example ni ipo FRL ṣe atilẹyin ipele iyara nikan -1 awọn ẹrọ ni HDMI Intel FPGA IP Design ExampItọsọna Ibẹrẹ Yara fun Intel Arria 10 Awọn ẹrọ ati Apejuwe Alaye fun HDMI 2.1 Oniru Example (Support FRL = 1) ruju. • Ti gbe HDCP Lori HDMI Design Example fun Intel Arria 10 Awọn ẹrọ apakan lati HDMI Intel FPGA IP Itọsọna olumulo. • Ṣatunkọ Simulating apakan Oniru lati fi awọn s ohun naa kunample monomono, sideband data monomono, ati oluranlowo data monomono ati ki o imudojuiwọn awọn aseyori ifiranṣẹ kikopa. • Yọ akọsilẹ kuro ti o sọ kikopa wa fun nikan Ṣe atilẹyin FRL alaabo awọn aṣa akọsilẹ. Simulation wa bayi fun Ṣe atilẹyin FRL Awọn apẹrẹ ti o ṣiṣẹ pẹlu. • Ṣe imudojuiwọn apejuwe ẹya ni Apejuwe Apejuwe fun HDMI 2.1 Design Example (Support FRL ṣiṣẹ) apakan.
tesiwaju…

Ẹya Iwe aṣẹ	Intel Quartus NOMBA Version	Ẹya IP	Awọn iyipada
			• Ṣatunkọ aworan atọka Àkọsílẹ ni HDMI 2.1 RX-TX Design Block Diagram, Awọn ohun elo Apẹrẹ, ati Ṣiṣẹda RX-Nikan tabi TX-Nikan Awọn apakan fun HDMI 2.1 apẹrẹ example. Ti ṣafikun awọn paati tuntun ati awọn paati yiyọ kuro ti ko wulo mọ. • Ṣatunkọ itọnisọna iwe afọwọkọ main.c ni Ṣiṣẹda RX-Nikan tabi apakan Awọn apẹrẹ TX-Nikan. • Ṣe imudojuiwọn awọn apakan Ilana Ilana lati ṣafikun awọn folda titun ati files fun awọn mejeeji HDMI 2.0 ati HDMI 2.1 apẹrẹ examples. • Ṣe imudojuiwọn apakan Awọn ibeere Hardware ati Software fun HDMI 2.1 apẹrẹ example. • Ṣe imudojuiwọn aworan atọka Àkọsílẹ ati awọn apejuwe ifihan agbara ni Ibiti Yiyiyi ati Mastering (HDR) InfoFrame Inserting and Filtering section for HDMI 2.1 design example. Fikun apakan titun kan, Ṣiṣe Apẹrẹ ni Awọn Oṣuwọn FRL ọtọtọ, fun HDMI 2.1 apẹrẹ examples. • Ṣe imudojuiwọn aworan atọka Àkọsílẹ ati awọn apejuwe ifihan agbara ni apakan Eto Clocking fun HDMI 2.1 design example. • Fikun apejuwe nipa olumulo DIP yipada ni Hardware Setup apakan fun HDMI 2.1 oniru example. • Ṣe imudojuiwọn apakan Awọn idiwọn Oniru fun HDMI 2.1 apẹrẹ example. • Ṣe imudojuiwọn apakan Igbegasoke rẹ Oniru. • Ṣe imudojuiwọn awọn apakan Testbench Simulation fun mejeeji HDMI 2.0 ati HDMI 2.1 apẹrẹ examples.
2020.01.16	19.4	19.3.0	• Ṣe imudojuiwọn HDMI Intel FPGA IP Design ExampItọsọna Ibẹrẹ Yara fun Intel Arria 10 Awọn ẹrọ apakan pẹlu alaye nipa HDMI 2.1 apẹrẹ tuntun ti a ṣafikun tẹlẹample pẹlu FRL mode. • Ti ṣafikun ipin tuntun, Apejuwe Apejuwe fun HDMI 2.1 Oniru Example (Ṣiṣe atilẹyin FRL) ti o ni gbogbo alaye ti o yẹ nipa apẹrẹ tuntun ti a ṣafikun tẹlẹample. • Lorukọmii HDMI Intel FPGA IP Design Example Apejuwe Apejuwe si Apejuwe Alaye fun HDMI 2.0 Oniru Example fun dara wípé.
2019.10.31	18.1	18.1	Fi kun ti ipilẹṣẹ files ninu tx_control_src folda: ti_i2c.c ati ti_i2c.h. • Atilẹyin ti a ṣafikun fun atunyẹwo kaadi ọmọbinrin FMC 11 ni Hardware ati Awọn ibeere Software ati Iṣakojọpọ ati Idanwo Awọn apakan Apẹrẹ. • Ti yọkuro apakan Idiwọn Oniru. Idiwọn nipa irufin akoko lori awọn ihamọ skew ti o pọju ni ipinnu ni ẹya 18.1 ti HDMI Intel FPGA IP. • Ti ṣafikun paramita RTL tuntun kan, BITEC_DAUGHTER_CARD_REV, lati jẹ ki o yan atunyẹwo kaadi ọmọbinrin Bitec HDMI.
tesiwaju…

Ẹya Iwe aṣẹ	Intel Quartus NOMBA Version	Ẹya IP	Awọn iyipada
			• Ṣe imudojuiwọn apejuwe fun fmcb_dp_m2c_p ati fmcb_dp_c2m_p awọn ifihan agbara lati ni alaye nipa awọn atunyẹwo kaadi ọmọbinrin FMC 11, 6, ati 4. Ṣe afikun awọn ifihan agbara tuntun wọnyi fun atunyẹwo kaadi ọmọbinrin Bitec 11: - hdmi_tx_ti_i2c_sda - hdmi_tx_ti_i2c_scl - oc_i2c_master_ti_avalon_anti_slave_a ddress - oc_i2c_master_ti_avalon_anti_slave_w rite - oc_i2c_master_ti_avalon_anti_slave_r eaddata - oc_i2c_master_ti_avalon_anti_slave_w ritedata - oc_i2c_master_ti_avalon_anti_slave_w aitrequest Fikun apakan kan nipa Igbegasoke Oniru rẹ.
2017.11.06	17.1	17.1	• Ti lorukọmii HDMI IP mojuto si HDMI Intel FPGA IP gẹgẹbi fun isọdọtun Intel. • Yi oro Qsys pada si Platform onise. Alaye ti a ṣafikun nipa Ibiti Yiyiyi ati Titunto si InfoFrame (HDR) ati ẹya sisẹ. • Ṣe imudojuiwọn ilana ilana: - Fikun iwe afọwọkọ ati awọn folda software ati files. - Imudojuiwọn wọpọ ati hdr files. - Yọ atx files. - Iyatọ files fun Intel kuotisi NOMBA Standard Edition ati Intel kuotisi NOMBA Pro Edition. • Ṣe imudojuiwọn apakan Ṣiṣẹda Apẹrẹ lati ṣafikun ẹrọ ti a lo bi 10AX115S2F4I1SG. • Ṣatunkọ oṣuwọn data transceiver fun igbohunsafẹfẹ aago 50-100 MHz TMDS si 2550-5000 Mbps. • Ṣe imudojuiwọn alaye ọna asopọ RX-TX ti o le tu bọtini olumulo_pb[2] silẹ lati mu sisẹ ita kuro. • Ṣe imudojuiwọn aworan atọka ṣiṣan sọfitiwia Nios II ti o kan awọn idari fun oluwa I2C ati orisun HDMI. Alaye ti a ṣafikun nipa awọn Apẹrẹ Example GUI paramita. • Fi kun HDMI RX ati TX Top oniru sile. • Ṣafikun HDMI RX ati awọn ifihan agbara ipele oke TX: - mgmt_clk - tunto - i2c_clk - hdmi_clk_in - Yọ HDMI RX wọnyi ati awọn ifihan agbara ipele oke TX kuro: • ẹya • i2c_clk
tesiwaju…

Ẹya Iwe aṣẹ	Intel Quartus NOMBA Version	Ẹya IP	Awọn iyipada
			• Fikun akọsilẹ kan pe eto afọwọṣe transceiver ti ni idanwo fun Intel Arria 10 FPGA Development Kit ati Bitec HDMI 2.0 Kaadi ọmọbinrin. O le ṣe atunṣe eto afọwọṣe fun igbimọ rẹ. Fi kun ọna asopọ kan fun workaround lati yago fun jitter ti PLL cascading tabi ti kii-ifiṣootọ aago ona fun Intel Arria 10 PLL itọkasi aago. Fikun akọsilẹ kan pe o ko le lo PIN transceiver RX bi CDR refclk fun HDMI RX tabi bi TX PLL refclk fun HDMI TX. Fikun akọsilẹ kan nipa bi o ṣe le ṣafikun idiwọ set_max_skew fun awọn apẹrẹ ti o lo TX PMA ati isunmọ PCS.
2017.05.08	17.0	17.0	• Rebranded bi Intel. Nọmba apakan ti yipada. • Ṣe imudojuiwọn ilana ilana: - hdr ti a ṣafikun files. - Yi pada qsys_vip_passthrough.qsys si nios.qsys. - Fi kun files pataki fun Intel kuotisi NOMBA Pro Edition. • Alaye imudojuiwọn ti RX-TX Ọna asopọ Àkọsílẹ tun ṣe sisẹ ita lori Ibiti Yiyi to gaju (HDR) Alaye lati inu data iranlọwọ HDMI RX ati fi sii tẹlẹample HDR Infoframe si data iranlọwọ ti HDMI TX nipasẹ Avalon ST multiplexer. Fikun akọsilẹ kan fun apejuwe Transceiver Native PHY pe lati pade HDMI TX inter-channel inter-channel skew, o nilo lati ṣeto aṣayan ipo asopọ ikanni TX ni Arria 10 Transceiver Native PHY olootu paramita si PMA ati PCS imora. Apejuwe imudojuiwọn fun OS ati awọn ifihan agbara wiwọn. • Ṣatunkọ awọn oversampling ifosiwewe fun orisirisi transceiver data oṣuwọn ni kọọkan TMDS aago igbohunsafẹfẹ ibiti o lati se atileyin TX FPLL taara aago ero. • Yi pada TX IOPLL to TX FPLL kasikedi clocking eni to TX FPLL ètò taara. Awọn ifihan agbara atunto TX PMA ti a ṣafikun. • Ṣatunkọ USER_LED[7] oversampipo ling. 1 tọkasi oversampmu (oṣuwọn data <1,000 Mbps ni Arria 10 ẹrọ). • Imudojuiwọn HDMI Design Example Atilẹyin Simulators tabili. VHDL ko ṣe atilẹyin fun NCsim. • Awọn ọna asopọ ti a fikun si ẹya ti a fi pamọ ti Arria 10 HDMI IP Core Design Example User Itọsọna.
2016.10.31	16.1	16.1	Itusilẹ akọkọ.

Intel Corporation. Gbogbo awọn ẹtọ wa ni ipamọ. Intel, aami Intel, ati awọn ami Intel miiran jẹ aami-išowo ti Intel Corporation tabi awọn oniranlọwọ rẹ. Intel ṣe atilẹyin iṣẹ ti FPGA rẹ ati awọn ọja semikondokito si awọn pato lọwọlọwọ ni ibamu pẹlu atilẹyin ọja boṣewa Intel, ṣugbọn ni ẹtọ lati ṣe awọn ayipada si eyikeyi awọn ọja ati iṣẹ nigbakugba laisi akiyesi. Intel ko gba ojuse tabi layabiliti ti o dide lati inu ohun elo tabi lilo eyikeyi alaye, ọja, tabi iṣẹ ti a ṣalaye ninu rẹ ayafi bi a ti gba ni kikun si kikọ nipasẹ Intel. A gba awọn alabara Intel nimọran lati gba ẹya tuntun ti awọn pato ẹrọ ṣaaju gbigbekele eyikeyi alaye ti a tẹjade ati ṣaaju gbigbe awọn aṣẹ fun awọn ọja tabi awọn iṣẹ. * Awọn orukọ miiran ati awọn ami iyasọtọ le jẹ ẹtọ bi ohun-ini ti awọn miiran.

Idajọ Ayelujara
Fi esi ranṣẹ
ID: 683156
Ẹya: 2022.12.27

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intel HDMI Arria 10 FPGA IP Design Eksample [pdf] Itọsọna olumulo HDMI Arria 10 FPGA IP Design Eksample, HDMI Arria, 10 FPGA IP Design Eksample, Apẹrẹ Example

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