HDMI Arria 10 FPGA IP Design Example
Fa'aoga TaialaHDMI Intel® Arria 10 FPGA IP
Design Example User Guide
Fa'afou mo Intel®Quartus®
Prime Design Suite: 22.4
IP Version: 19.7.1

HDMI Intel® FPGA IP Design Example Ta'iala Amata vave mo Intel® Arria® 10 Masini

O masini HDMI Intel® 10 o loʻo faʻaalia ai se faʻataʻitaʻiga faʻataʻitaʻiga ma se meafaigaluega faʻapipiʻi e lagolagoina le tuʻufaʻatasia ma suʻega meafaigaluega.
FPGA IP mamanu example mo Intel Arria®
O le HDMI Intel FPGA IP o loʻo ofoina atu le faʻataʻitaʻiga leaamples:

• HDMI 2.1 RX-TX toe fa'asalalau le mamanu fa'atasi ai ma feso'ota'iga tumau (FRL) fa'aogaina
• HDMI 2.0 RX-TX toe fa'asalalau le mamanu fa'atasi ai ma le FRL fa'aletonu
• HDCP i luga o le HDMI 2.0 mamanu

Fa'aaliga: E le o iai le ata o le HDCP i le polokalama Intel® Quartus Prime Pro Edition.
Ina ia maua le ata HDCP, fa'afeso'ota'i Intel ile https://www.intel.com/content/www/us/en/broadcast/products/programmable/applications/connectivity-solutions.html.
A e fatuina se mamanu example, e otometi lava ona fatuina e le faatonu parameter le files e manaʻomia e faʻataʻitaʻi, faʻapipiʻi, ma suʻe le mamanu i meafaigaluega.
Ata 1. Laasaga Atina'eFa'amatalaga Fa'atatau
HDMI Intel FPGA IP Taiala Tagata Fa'aoga
1.1. Fausiaina o le Fuafuaga
Fa'aoga le HDMI Intel FPGA IP fa'atonu fa'atonu i le polokalama Intel Quartus Prime e fa'atupu ai le fa'ata'ita'igaamples. Intel Corporation. Ua taofia aia tatau uma. Intel, le Intel logo, ma isi fa'ailoga Intel o fa'ailoga fa'ailoga a le Intel Corporation po'o ona lala. E fa'amaonia e Intel le fa'atinoina o ana oloa FPGA ma semiconductor i fa'amatalaga o lo'o iai nei e tusa ai ma le fa'atonuga masani a Intel, ae fa'asaoina le aia tatau e fai ai suiga i so'o se oloa ma auaunaga i so'o se taimi e aunoa ma se fa'aaliga. E leai se tiute po'o se noataga e afua mai i le talosaga po'o le fa'aogaina o so'o se fa'amatalaga, oloa, po'o se auaunaga o lo'o fa'amatalaina i i'i se'i vagana ua malilie i ai i se faiga tusitusia e Intel. Ua fautuaina tagata fa'atau Intel ina ia maua le fa'amatalaga lata mai o fa'amatalaga masini a'o le'i fa'alagolago i so'o se fa'amatalaga fa'asalalau ma a'o le'i tu'uina atu oka mo oloa po'o tautua. *O isi igoa ma fa'ailoga e mafai ona ta'ua o se meatotino a isi.
Amata i le Nios® II EDS i le Intel Quartus Prime Pro Edition software version 19.2 ma le Intel Quartus Prime Standard Edition software version 19.1, ua aveese e Intel le vaega Cygwin i le Windows * version of Nios II EDS, ma suia i le Windows * Subsytem for Linux (WSL). Afai o oe ose Windows* fa'aoga, e tatau ona e fa'apipi'i le WSL a'o le'i fa'atupu lau fa'ata'ita'igaample.
Ata 2. Fa'atupuina o le Fa'asologa o Fuafuaga

1. Fausia se poloketi e faʻatatau i le Intel Arria 10 masini aiga ma filifili le masini manaʻomia.
2. I le IP Catalog, su'e ma kiliki-lua Interface Protocols ➤ Audio & Vitio ➤ HDMI Intel FPGA IP. O lo'o fa'aali mai le fa'amalama o le New IP Variant po'o le New IP Variation.
3. Fa'ailoa se igoa pito i luga mo lau suiga masani IP. E fa'asaoina e le fa'atonu fa'amaufa'ailoga le fa'atulagaina o suiga o le IP ile a file igoa .ip pe .qsys.
4. Kiliki OK. E aliali mai le fa'atonu fa'amaufa'ailoga.
5. I luga o le IP tab, faʻapipiʻi mea e manaʻomia mo TX ma RX.
6. Fa'aola le parakalafa Lagolago FRL e fa'atupu ai le HDMI 2.1 fa'ata'ita'igaample i le FRL mode. Tape e fa'atupu le HDMI 2.0 design example leai FRL.
7. I luga ole Design Exampi le tab, filifili Arria 10 HDMI RX-TX Retransmit.
8. Filifili Fa'ata'ita'iga e fa'atupu ai le su'ega, ma filifili Fa'atasi e fa'atupuina ai le fa'asologa o meafaigaluegaample.E tatau ona e filifilia a itiiti mai o se tasi o nei filifiliga e gaosia ai le mamanu example files. Afai e te filifilia uma e lua, o le taimi o le gaosiga e umi atu.
9. Mo Fausia File Fa'asologa, filifili Verilog po'o VHDL.
10. Mo le Pusa Atina'e, filifili le Intel Arria 10 GX FPGA Development Kit. Afai e te filifilia se pusa atinaʻe, ona sui lea o le masini faʻatatau (filifilia i le laasaga 4) e fetaui ma le masini i luga o le laupapa sini. Mo Intel Arria 10 GX FPGA Development Kit, o le masini fa'aletonu o le 10AX115S2F4I1SG.
11. Kiliki Fausia Example Design.

Fa'amatalaga Fa'atatau
E fa'afefea ona fa'apipi'i le Windows* Subsystem mo Linux* (WSL) i luga ole Windows* OS?
1.2. Fa'ata'ita'iina o le Fuafuaga
Ole su'ega HDMI e fa'ata'ita'iina se fa'asologa o le loopback mai se fa'ata'ita'iga TX i se fa'ata'ita'iga RX. Fa'alotoifale mamanu mamanu vitiō, leo sample generator, sideband fa'amatalaga generator, ma ausilali fa'apipi'i fa'amaumauga e fa'auluina le HDMI TX fa'ata'ita'iga ma le fa'asologa fa'asologa mai le fa'ata'ita'iga TX e feso'ota'i i le fa'ata'ita'iga RX i le su'ega.
Ata 3. Fa'asologa Fa'ata'ita'iga Fa'asologa

1. Alu i le faila simulation e mana'omia.
2. Fa'asolo le fa'asologa fa'ata'ita'iga mo le simulator lagolago o lau filifiliga. O le tusitusiga e tuufaatasia ma faʻatautaia le suʻega suʻega i le simulator.
3. Iloilo i'uga.

Laulau 1. Laasaga e Fa'atino Fa'ata'ita'iga

Simulator	Fa'atonuga Galuega	Faatonuga
Riviera-PRO*	/simulation/aldec	I le laina fa'atonu, fa'aoga
		vsim -c -do aldec.do
ModelSim*	/simulation/mentor	I le laina fa'atonu, fa'aoga
		vsim -c -do mentor.do
VCS*	/simulation/synopsys/vcs	I le laina fa'atonu, fa'aoga
		puna vcs_sim.sh
VCS MX	/simulation/synopsys/vcsmx	I le laina fa'atonu, fa'aoga
		puna vcsmx_sim.sh
Xcelium* Fa'atasi	/simulation/xcelium	I le laina fa'atonu, fa'aoga
		puna xcelium_sim.sh

O se fa'ata'ita'iga manuia e fa'ai'u i le fe'au lea:
# FA'AIGA_PER_UITI = 2
# VIC = 4
# FRL_RATE = 0
# BPP = 0
# FAO_FREQUENCY (kHz) = 48
# AUDIO_CHANNEL = 8
# Pasi fa'atusa
1.3. Tu'ufa'atasia ma Fa'ata'ita'i le Fuafuaga

E fa'aputu ma fa'atino se su'ega fa'ata'ita'iga ile meafaigaluega fa'aample mamanu, mulimuli i laasaga nei:

1. Ia mautinoa meafaigaluega exampua mae'a le fausiaina o mamanu.
2. Tatala le polokalama Intel Quartus Prime ma tatala le .qpf file.
   • HDMI 2.1 mamanu exampfa'atasi ai ma le Lagolago FRL fa'aagaoioia: fa'atonuga o le poloketi/quartus/a10_hdmi21_frl_demo.qpf
   • HDMI 2.0 mamanu example fa'atasi ma le Lagolago FRL fa'aletonu: projected irectory/quartus/a10_hdmi2_demo.qpf
3. Kiliki Processing ➤ Amata Fa'aopoopo.
4. A mae'a le fa'aputuga manuia, a .sof file o le a gaosia i le quartus/output_files directory.
5. Feso'ota'i i le FMC uafu B (J2):
   • HDMI 2.1 mamanu example fa'atasi ma le Lagolago FRL fa'aagaina: Bitec HDMI 2.1 FMC Daughter Card Rev 9
   Fa'aaliga: E mafai ona e filifilia le toe iloiloga o lau Bitec HDMI daughter card. I lalo ole Design Exampi le tab, seti le HDMI Daughter Card Revision i le Toefuataiga 9, Toe Iloilo pe leai se tama teine. Ole tau fa'aletonu ole Toe Iloiloga 9.
   • HDMI 2.0 mamanu example ma le Lagolago FRL fa'aletonu: Bitec HDMI 2.0 FMC Daughter Card Rev 11
6. Fa'afeso'ota'i le TX (P1) o le Bitec FMC daughter card i se puna vitiō fafo.
7. Fa'afeso'ota'i le RX (P2) o le kata tama'ita'i Bitec FMC i se atigi vitiō i fafo po'o se su'esu'e vitiō.
8. Ia mautinoa o ki uma i luga o le laupapa atina'e o lo'o i le tulaga le lelei.
9. Fa'atulaga le masini Intel Arria 10 filifilia i luga o le laupapa atina'e e fa'aaoga ai le .sof file (Meafaigaluega ➤ Polokalama ).
10. E tatau i le tagata su'esu'e ona fa'aalia le vitio na gaosia mai le puna.

Fa'amatalaga Fa'atatau
Intel Arria 10 FPGA Development Kit Taiala mo Tagata
1.4. HDMI Intel FPGA IP Design Example Parameter
Laulau 2.
HDMI Intel FPGA IP Design Example Parameters mo Intel Arria 10 Devices O avanoa nei e avanoa mo Intel Arria 10 masini.

Parameter	Taua	Fa'amatalaga
Avanoa Design Example
Filifili Design	Arria 10 HDMI RX-TX Toe lafo	Filifili le mamanu example e gaosia.

Design Example Files
Fa'ata'oto	Ua pe, ua pe	Fa'aola lenei filifiliga e fa'atupu ai mea e mana'omia files mo le su'ega fa'ata'ita'iga.
Fa'asologa	Ua pe, ua pe	Fa'aola lenei filifiliga e fa'atupu ai mea e mana'omia filemo Intel Quartus Prime tu'ufa'atasiga ma fa'ata'ita'iga meafaigaluega.

Fausia le HDL Format
Fa'atupu File Fa'asologa	Verilog, VHDL	Filifili lau fa'atulagaga HDL e te mana'o iai mo le fa'ata'ita'iga fa'atupuample fileseti. Fa'aaliga: O lenei filifiliga e na'o le fa'atulagaina mo le fa'atupuina o le tulaga maualuga IP files. O isi uma files (egample testbenches ma le tulaga maualuga files mo meafaigaluega faʻataʻitaʻiga) o loʻo i le Verilog HDL format

Pusa Atina'e Sini
Filifili le Komiti Faatino	Leai se atigi pusa,	Filifili le laupapa mo le mamanu fa'atatauample.
	Arria 10 GX FPGA Development Kit, Pusa Atina'e aganu'u	• Leai se Pusa Atina'e: O lenei filifiliga e le aofia ai vaega uma o meafaigaluega mo le mamanu muamuaample. O le IP autu e setiina uma tofitofiga pine i pine mama. • Arria 10 GX FPGA Atiina Atina'e: O lenei filifiliga e otometi lava ona filifilia le masini fa'atatau o le poloketi e fetaui ma le masini i luga o lenei pusa atina'e. E mafai ona e suia le masini sini e faaaoga ai le Suia Mea Fa'atatau parakalafa pe afai o lau su'esu'ega laupapa e ese le masini. O le IP autu e setiina uma tofitofiga pine e tusa ai ma le pusa atinaʻe.
		• Pusa Atina'e Fa'apitoa: O lenei filifiliga e fa'atagaina ai le mamanu fa'atusaampe fa'ata'ita'i i luga o se pusa atina'e lona tolu ma se Intel FPGA. Atonu e te mana'omia le setiina e oe lava o tofiga o pine.

Meafaigaluega Sini
Suia Mea Fa'atatau	Ua pe, ua pe	Fa'aola le filifiliga lea ma filifili le mea e sili ona fiafia i ai masini mo le atina'e pusa.

HDMI 2.1 Design Example ( Lagolago FRL = 1)

Le HDMI 2.1 mamanu exampI le FRL mode e fa'aalia ai le tasi HDMI fa'ata'ita'iga fa'ata'ita'i fa'alava i tua e aofia ai ala RX fa ma ala TX fa.
Laulau 3. HDMI 2.1 Design Example mo Intel Arria 10 Devices

Design Example	Fua Fa'amatalaga	Faiga Ala	Ituaiga Loopback
Arria 10 HDMI RX-TX Toe lafo	• 12 Gbps (FRL) • 10 Gbps (FRL) • 8Gbps (FRL) • 6 Gbps (FRL) • 3 Gbps (FRL) • <6 Gbps (TMDS)	Simplex	Faʻatasi ma le FIFO paʻu

Vaega

• O le mamanu e vave faʻapipiʻi ai le FIFO buffers e faʻatino saʻo HDMI vitio tafe i le va o le HDMI 2.1 goto ma le puna.
• O le mamanu e mafai ona sui i le va o le FRL mode ma le TMDS mode i le taimi o le taʻavale.
• O le mamanu e fa'aogaina le tulaga o le LED mo le vave fa'apipi'iina stage.
• O le mamanu e sau ma HDMI RX ma TX faʻataʻitaʻiga.
• O le mamanu o loʻo faʻaalia ai le faʻaofiina ma le faamamaina o le Dynamic Range and Mastering (HDR) InfoFrame i le RX-TX link module.
• O le mamanu e faʻatalanoa le fua FRL i le va o le pusa e fesoʻotaʻi ma le TX ma le puna e fesoʻotaʻi i le RX. O le mamanu e pasi atu i le EDID mai le pusa i fafo i le RX i luga o le laupapa i le faʻaogaina le lelei. O le Nios II processor e faʻatalanoaina le fesoʻotaʻiga faʻavae i luga o le gafatia o le pusa e fesoʻotaʻi ma TX. E mafai fo'i ona e fa'afeso'ota'i le sui o le user_dipsw i luga o le laupapa e fa'atonutonu lima ai le TX ma le RX FRL.
• O le mamanu e aofia ai le tele o mea faʻapipiʻi.
  O le RX faʻataʻitaʻiga e maua se puna vitio mai le gaosiga o vitio i fafo, ma o faʻamatalaga e alu i totonu o le loopback FIFO ae leʻi tuʻuina atu i le TX instance. E te manaʻomia le faʻafesoʻotaʻi o se suʻesuʻega vitio i fafo, mataʻituina, poʻo se televise e iai le fesoʻotaʻiga HDMI i le TX autu e faʻamaonia ai le gaioiga.

2.1. HDMI 2.1 RX-TX Retransmit Design Block Diagram
O le HDMI RX-TX toe fa'afo'i le mamanu fa'atasiampO lo'o fa'aalia le fa'ata'amilosaga tutusa i luga o le ala faigofie mo HDMI 2.1 fa'atasi ai ma le Lagolago FRL.
Ata 4. HDMI 2.1 RX-TX Retransmit Block Diagram2.2. Fausia le RX-Na'o po'o le TX-Na'o le Designs
Mo tagata faʻaoga maualuga, e mafai ona e faʻaogaina le mamanu HDMI 2.1 e fatu ai se mamanu TX- poʻo RX-naʻo.
Ata 5. Vaega Manaomia mo RX-Na'o po'o TX-Na'o DesignMo le fa'aogaina o vaega RX- po'o TX-na'o, aveese poloka le talafeagai mai le mamanu.
Laulau 4. RX-Na'o ma TX-Na'o Manaoga Fa'atulagaina

Fa'aoga Manaoga	Faasao	Aveese	Faaopoopo
HDMI RX na'o	RX pito i luga	• TX Luga • RX-TX So'oga • CPU Subsystem • Transceiver Arbiter	–
HDMI TX na'o	•TX Luga • CPU So'otaga Fa'atonu	•RX Luga • RX-TX So'oga •Arbiter Transceiver	Vitio Fua Fa'ata'ita'iga (aganu'u fa'apitoa po'o fa'atupu mai le Vitio ma Ata Fa'agasolo (VIP) Suite)

E ese mai i suiga o le RTL, e mana'omia fo'i ona e fa'asa'o le tusitusiga main.c.
• Mo HDMI TX-na'o mamanu, fa'amama le fa'atali mo le tulaga loka HDMI RX e ala i le aveese laina nei ma sui i le
tx_xcvr_reconfig(tx_frl_rate);
rx_hdmi_lock = READ_PIO(PIO_IN0_BASE, PIO_RX_LOCKED_OFFSET,
PIO_RX_LOCKED_WIDTH);
a'o (rx_hdmi_lock == 0) {
afai (siaki_hpd_isr()) { motu; }
// rx_vid_lock = READ_PIO(PIO_IN0_BASE, PIO_VID_LOCKED_OFFSET,
PIO_VID_LOCKED_WIDTH);
rx_hdmi_lock = READ_PIO(PIO_IN0_BASE, PIO_RX_LOCKED_OFFSET,
PIO_RX_LOCKED_WIDTH);
// Reconfig Tx ina ua loka rx
afai (rx_hdmi_lock == 1) {
afai (READ_PIO(PIO_IN0_BASE, PIO_LOOPBACK_MODE_OFFSET,
PIO_LOOPBACK_MODE_WIDTH) == 1) {
rx_frl_rate = READ_PIO(PIO_IN0_BASE, PIO_RX_FRL_RATE_OFFSET,
PIO_RX_FRL_RATE_WIDTH);
tx_xcvr_reconfig(rx_frl_rate);
} isi {
tx_xcvr_reconfig(tx_frl_rate);
} } }
• Mo HDMI RX-na'o mamanu, tausia na'o laina nei i le main.c script:
REDRIVER_INIT();
hdmi_rx_init();
2.3. Meafaigaluega ma Polokalama Manaoga
E fa'aogaina e Intel meafaigaluega ma polokalama fa'akomepiuta nei e su'e ai le mamanu example.
Meafaigaluega

• Intel Arria 10 GX FPGA Atina'e Kit
• HDMI 2.1 Punavai (Quantum Data 980 48G Generator)
• HDMI 2.1 Sink (Quantum Data 980 48G Su'esu'e)
• Bitec HDMI FMC 2.1 kata tama teine ​​(Fa'aaliga 9)
• HDMI 2.1 Vaega 3 uaea (fa'ata'ita'i ile Belkin 48Gbps HDMI 2.1 Uaea)

Polokalama

• Intel Quartus Prime Pro Edition polokalame polokalame 20.1

2.4. Fa'atonuga Fa'atonu
O fa'atonuga o lo'o i ai mea na gaosia files mo le HDMI Intel FPGA IP mamanu example.
Ata 6. Fa'atonuga Fa'atonu mo le Design ExampleLaulau 5. Fausia RTL Files

Folders	Files/Soifolders
masani	clock_control.ip
	clock_crosser.v
	dcfifo_inst.v
	edge_detector.sv
	fifo.ip
	output_buf_i2c.ip

	test_pattern_gen.v
	tpg.v
	tpg_data.v
gxb	gxb_rx.ip
	gxb_rx_reset.ip
	gxb_tx.ip
	gxb_tx_fpll.ip
	gxb_tx_reset.ip
hdmi_rx	hdmi_rx.ip
	hdmi_rx_top.v
	Panasonic.hex
hdmi_tx	hdmi_tx.ip
	hdmi_tx_top.v
i2c_pologa	i2c_avl_mst_intf_gen.v
	i2c_clk_cnt.v
	i2c_condt_det.v
	i2c_databuffer.v
	i2c_rxshifter.v
	i2c_slvfsm.v
	i2c_spksupp.v
	i2c_txout.v
	i2c_txshifter.v
	i2cslave_to_avlmm_bridge.v
pl	pll_hdmi_reconfig.ip
	pll_frl.ip
	pll_reconfig_ctrl.v
	pll_tmds.ip
	pll_vidclk.ip
	quartus.ini
rxtx_link	altera_hdmi_hdr_infoframe.v
	aux_mux.qsys
	aux_retransmit.v
	aux_src_gen.v
	ext_aux_filter.v

	rxtx_link.v
	scfifo_vid.ip
toefaiga	mr_rx_iopll_tmds/
	mr_rxphy/
	mr_tx_fpll/
	altera_xcvr_functions.sv
	mr_compare.sv
	mr_rate_deteksi.v
	mr_rx_rate_detect_top.v
	mr_rx_rcfg_ctrl.v
	mr_rx_reconfig.v
	mr_tx_rate_detect_top.v
	mr_tx_rcfg_ctrl.v
	mr_tx_reconfig.v
	rcfg_array_streamer_iopll.sv
	rcfg_array_streamer_rxphy.sv
	rcfg_array_streamer_rxphy_xn.sv
	rcfg_array_streamer_txphy.sv
	rcfg_array_streamer_txphy_xn.sv
	rcfg_array_streamer_txpll.sv
sdc	a10_hdmi2.sdc
	jtag.sdc

Fuafuaga 6. Fausia Fa'ata'ita'iga Files
Fa'asino i le Simulation Testbench vaega mo nisi fa'amatalaga

Folders	Files
aldec	/aldec.do
	/rivierapro_setup.tcl
fa'alogona	/cds.lib
	/hdl.var
faufautua	/mentor.do
	/msim_setup.tcl
synopsys	/vcs/filelisi.f
	/vcs/vcs_setup.sh

	/vcs/vcs_sim.sh
	/vcsmx/synopsys_sim_setup
	/vcsmx/vcsmx_setup.sh
	/vcsmx/vcsmx_sim.sh
xcelium	/cds.lib
	/hdl.var
	/xcelium_setup.sh
	/xcelium_sim.sh
masani	/modelsim_files.tcl
	/riviera_files.tcl
	/vcs_files.tcl
	/vcsmx_files.tcl
	/xcelium_files.tcl
hdmi_rx	/hdmi_rx.ip
	/Panasonic.hex
hdmi_tx	/hdmi_tx.ip

Laulau 7. Polokalama Faia Files

Folders	Files
tx_control_src Fa'aaliga: O le faila tx_control o loʻo iai foʻi faʻalua o nei mea files.	lalolagi.h
	hdmi_rx.c
	hdmi_rx.h
	hdmi_tx.c
	hdmi_tx.h
	hdmi_tx_read_edid.c
	hdmi_tx_read_edid.h
	intel_fpga_i2c.c
	intel_fpga_i2c.h
	autu.c
	pio_faitau_tusi.c
	pio_faitau_tusi.h

2.5. Fuafuaga Vaega
Le HDMI Intel FPGA IP mamanu exampe aofia ai vaega pito i luga masani ma HDMI TX ma RX vaega pito i luga.
2.5.1. HDMI TX Vaega
O vaega pito i luga o le HDMI TX e aofia ai vaega pito i luga o le TX, ma le IOPLL, transceiver PHY reset controller, transceiver native PHY, TX PLL, TX reconfiguration management, ma poloka pa puipui.
Ata 7. HDMI TX Vaega MaualugaLaulau 8. HDMI TX Vaega Maualuga

Module	Fa'amatalaga
HDMI TX Core	E maua e le IP faʻamatalaga vitio mai le pito i luga ma faʻatino faʻamatalaga ausilali, faʻasologa o faʻamatalaga leo, faʻasologa o faʻamatalaga vitio, scrambling, TMDS encoding poʻo packetization.
IOPLL	O le IOPLL (iopll_frl) e gaosia le uati FRL mo le TX autu. E maua e lenei uati fa'asino le uati TX FPLL. FRL taimi ole uati = Fuainumera o fa'amaumauga ile laina x 4 / (FRL mataitusi ile uati x 18)
Transceiver PHY Toe Seti Pule	O le Transceiver PHY reset controller e fa'amautinoaina le fa'amautuina o le amataga o le TX transceivers. O le toe setiina o le faʻaogaina o lenei pule e faʻaosoina mai le pito i luga, ma faʻatupuina ai le faʻasologa o le analog ma le numera numera i le Transceiver Native PHY poloka e tusa ai ma le toe setiina o le faʻasologa i totonu o le poloka. O le tx_ready output signal mai lenei poloka e galue foi o se toe setiina faailoilo i le HDMI Intel FPGA IP e faʻaalia ai le transceiver o loʻo i luga ma tamoʻe, ma sauni e maua faʻamatalaga mai le autu.
Transceiver Native PHY	Poloka transceiver malosi e maua ai faʻamatalaga tutusa mai le HDMI TX autu ma faʻasalalau faʻamaumauga mai le lafoina. Fa'aaliga: Ina ia ausia le HDMI TX inter-channel skew manaʻomia, seti le TX channel bonding mode filifiliga i le Intel Arria 10 Transceiver Native PHY editor parameter i PMA ma PCS so'oga. E te manaʻomia foʻi le faʻaopoopoina o le maualuga o le skew (set_max_skew) faʻatapulaʻaina manaʻoga i le numera toe setiina faailo mai le transceiver reset controller (tx_digitalreset) e pei ona fautuaina i le Intel Arria 10 Transceiver PHY User Guide.
TX PLL	O le poloka PLL transmitter e maua ai le faasologa vave o le uati i le Transceiver Native PHY poloka. Mo lenei HDMI Intel FPGA IP mamanu example, fPLL o loʻo faʻaaogaina e pei o TX PLL. TX PLL e lua fa'asino uati. • O lo'o feso'ota'i le uati fa'asino 0 i le oscillator e mafai ona fa'apolokalameina (fa'atasi ma le fa'asologa o le uati TMDS) mo le TMDS mode. I lenei mamanu example, RX TMDS uati e faʻaoga e faʻafesoʻotaʻi i le faʻamatalaga uati 0 mo le TMDS mode. Ua fautuaina oe e Intel e fa'aaoga le oscillator e mafai ona fa'apolokalameina ma le TMDS uati taimi mo le fa'asinoga uati 0. • O lo'o feso'ota'i le uati fa'asino 1 i le uati 100 MHz fa'amau mo le fa'aogaina o le FRL.
TX Toe Fa'atonu Pulega	• I le TMDS mode, o le TX reconfiguration management block reconfigures le TX PLL mo faʻasologa eseese o le uati e faʻatatau i le TMDS uati taimi o le vitio patino. • I le faiga FRL, o le TX reconfiguration pulega poloka reconfigures le TX PLL e tuuina atu le faasologa vave uati mo 3 Gbps, 6 Gbps, 8 Gbps, 10 Gbps ma 12 Gbps e tusa ai ma FRL_Rate fanua i le 0x31 SCDC resitala. •O le TX reconfiguration pulega poloka e sui le TX PLL faasinoupu uati i le va o faasinomaga uati 0 mo le TMDS mode ma faasinoga uati 1 mo le faiga FRL.
Fa'aliga fa'apolopolo	O lenei paʻu e galue o se atinaʻe e fegalegaleai ai le I2C faʻaoga o le HDMI DDC ma vaega redriver.

Fuafuaga 9. Transceiver Fa'amatalaga Fua Faatatau ma Ovaampling Factor Ta'itasi Uati Va'aiga Fa'asao

Faiga	Fua Fa'amatalaga	oversample 1 (2x ovaample)	oversample 2 (4x ovaample)	oversample Fa'ailoga	oversampta'ita'i Fua Fa'amatalaga (Mbps)
TMDS	250–1000	On	On	8	2000–8000
TMDS	1000–6000	On	Tape	2	2000–12000
FRL	3000	Tape	Tape	1	3000
FRL	6000	Tape	Tape	1	6000

FRL	8000	Tape	Tape	1	8000
FRL	10000	Tape	Tape	1	10000
FRL	12000	Tape	Tape	1	12000

Ata 8. TX Reconfiguration Fa'asologa Fa'asologa2.5.2. HDMI RX Vaega
O vaega pito i luga o le HDMI RX e aofia ai vaega pito i luga ole RX, pologa I²C ma le EDID RAM, IOPLL, transceiver PHY reset controller, RX native PHY, ma le RX reconfiguration management blocks.
Ata 9. HDMI RX Vaega MaualugaLaulau 10. HDMI RX Vaega Maualuga

Module	Fa'amatalaga
HDMI RX Core	E maua e le IP le fa'asologa o fa'amaumauga mai le Transceiver Native PHY ma fa'atino le fa'aogaina o fa'amaumauga, kesi laina, decoding TMDS, fa'avasegaina o fa'amatalaga fesoasoani, fa'avasegaina o fa'amatalaga vitiō, fa'avasegaina o fa'amatalaga leo, ma fa'amatalaina.
I2C pologa	I2C o le faʻaoga faʻaoga mo le Sink Display Data Channel (DDC) ma le Tulaga ma Faʻamatalaga Faʻamatalaga (SCDC). O le puna HDMI e faʻaaogaina le DDC e fuafua ai le gafatia ma uiga o le goto e ala i le faitauina o le faʻatulagaina o faʻamatalaga Faʻamatalaga Faʻalautele Faʻalautele (E-EDID). O tuatusi pologa 8-bit I2C mo E-EDID o le 0xA0 ma le 0xA1. O le LSB o loʻo faʻaalia ai le ituaiga avanoa: 1 mo le faitau ma le 0 mo le tusitusi. A tupu se mea HPD, e tali atu le pologa I2C i faʻamatalaga E-EDID e ala i le faitau mai luga o le chip. O le I2C pologa-na'o le pule e lagolagoina le SCDC mo HDMI 2.0 ma le 2.1 O le tuatusi pologa 9-bit I2C mo le SCDC o 0xA8 ma 0xA9. A tupu se mea HPD, e faia e le pologa I2C le tusitusi pe faitau fefaʻatauaiga i pe mai le SCDC interface o le HDMI RX core. Feso'ota'iga a'oa'oga fa'agasologa mo Feso'ota'iga Fa'amaumau (FRL) e fa'apea fo'i ona tupu ile I2C I le taimi ole fa'alavelave HPD po'o le taimi e tusi ai e le fa'apogai se isi fua faatatau FRL ile resitara FRL Rate (resitala SCDC 0x31 bit[3:0]), e amata le faiga o a'oa'oga so'o. Fa'aaliga: O lenei I2C pologa-naʻo le pule mo SCDC e le manaʻomia pe afai e le faʻamoemoeina le HDMI 2.0 poʻo le HDMI 2.1.

EDID RAM

O le mamanu e teu ai faʻamatalaga EDID e faʻaaoga ai le RAM 1-Port IP. O se fa'asologa masani e lua-uaea (uati ma fa'amaumauga) fa'asologa o pasi (I2C pologa-na'o le pule) fa'aliliuina le fa'asologa o fa'amaumauga a le CEA-861-D E-EDID. O lenei EDID RAM e teuina faʻamatalaga E-EDID. • A i ai i le TMDS mode, o le mamanu e lagolagoina EDID passthrough mai TX i RX. I le taimi o le EDID passthrough, pe a fesoʻotaʻi le TX i le pusa i fafo, e faitau e le Nios II processor le EDID mai le pusa fafo ma tusi i le EDID RAM. • A i ai i le FRL mode, e tusia e le Nios II processor le EDID muai fetuutuunai mo sooga fua faatatau taitasi e faavae i le HDMI_RX_MAX_FRL_RATE parameter i le global.h script. Fa'aoga mea nei HDMI_RX_MAX_FRL_RATE mo le fua faatatau FRL lagolago: • 1: 3G 3 Lanes • 2: 6G 3 Lanes •3: 6G 4 Ala • 4: 8G 4 Lanes •5: 10G 4 Lanes (tauaga) •6: 12G 4 Ala

IOPLL

O le HDMI RX e fa'aoga lua IOPLLs. • O le IOPLL muamua (pll_tmds) e fa'atupuina le uati fa'asino RX CDR. O lenei IOPLL e na'o le fa'aoga TMDS. Ole uati fa'asino ole IOPLL e maua le uati TMDS. O le TMDS mode e fa'aoga ai le IOPLL lea ona e le mafai e le CDR ona maua fa'amatalaga uati i lalo ole 50 MHz ma ole TMDS ole taimi ole uati mai le 25 MHz i le 340 MHz. O le IOPLL lea e maua ai le taimi o le uati e 5 taimi o le uati fa'asino i totonu mo le va o le 25 MHz i le 50 MHz ma tu'uina atu le taimi tutusa o le uati fa'aoga mo le va o le 50 MHz i le 340 MHz. •O le IOPLL lona lua (iopll_frl) fa'atupuina le uati FRL mo le RX autu. O lenei uati fa'asino e maua le CDR toe fa'aleleia uati. FRL taimi ole uati = Fuainumera o fa'amaumauga ile laina x 4 / (FRL mataitusi ile uati x 18)

Transceiver PHY Toe Seti Pule	O le Transceiver PHY reset controller e fa'amautinoa le fa'amaoniaina o le fa'auluina o le RX transceivers. O le toe setiina o le faʻaogaina o lenei pule e faʻaosoina e le RX reconfiguration, ma faʻatupuina ai le analog ma numera toe setiina faailoilo i le Transceiver Native PHY poloka e tusa ai ma le toe setiina sequencing i totonu o le poloka.
RX Native PHY	Poloka transceiver malosi e maua ai faʻamaumauga faʻasologa mai se puna vitio fafo. E fa'aleaogaina fa'amaumauga fa'asologa i fa'amaumauga tutusa a'o le'i tu'uina atu fa'amaumauga i le HDMI RX autu. Ole poloka lea e fa'aoga ile Enhanced PCS mo le FRL mode. RX CDR e lua fa'asino uati. • O lo'o feso'ota'i le uati fa'asino i le uati o le IOPLL TMDS (pll_tmds), lea e maua mai i le uati TMDS. • O lo'o feso'ota'i le uati fa'asino ile 1 MHz uati. I le TMDS mode, RX CDR ua toe fetuutuunai e filifili faasinoupu uati 100, ma i le FRL mode, RX CDR toe fetuutuunai e filifili faasinoga uati 0.
RX Reconfiguration Pulega	I le TMDS mode, o le RX reconfiguration management block e faʻaaogaina le fua o le suʻesuʻeina o le eletise ma le HDMI PLL e faʻaulu ai le RX transceiver e faʻaogaina i soʻo se fua faatatau soʻotaga e amata mai i le 250 Mbps i le 6,000 Mbps. I le FRL mode, o le RX reconfiguration management block reconfigures le RX transceiver e faʻagaioi i le 3 Gbps, 6 Gbps, 8 Gbps, 10 Gbps, poʻo le 12 Gbps faʻalagolago i le fua FRL i le SCDC_FRL_RATE resitala fanua (0x31[3:0]). O le RX reconfiguration pulega poloka fesuiai i le va o Standard PCS/RX mo le TMDS mode ma le Enhanced PCS mo le FRL mode. Va'ai ile Ata 10 i le itulau 22.

Ata 10. RX Reconfiguration Sequence Flow
O le ata o loʻo faʻaalia ai le tele-rate reconfiguration sequence faʻasologa o le pule pe a maua faʻamatalaga faʻamatalaga ma faʻasino taimi masani, poʻo le taimi e tatala ai le transceiver.2.5.3. Tulaga Maualuga Poloka masani
O poloka masani pito i luga e aofia ai le transceiver arbiter, vaega fesoʻotaʻiga RX-TX, ma le CPU subsystem.
Fuafuaga 11. Tulaga Maualuga Poloka masani

Module

Fa'amatalaga

Transceiver Arbiter

O lenei poloka fa'aoga lautele e taofia ai le transceivers mai le toe fa'avasegaina i le taimi e tasi pe a mana'omia e le RX po'o le TX transceivers i totonu o le laina fa'aletino lava e tasi le toe fa'atulagaina. O le toe fa'aleleia fa'atasi e a'afia ai talosaga pe a tu'uina atu RX ma TX transceivers i totonu o le ala tutusa i fa'atinoga IP tuto'atasi. O lenei transceiver arbiter o se faʻaopoopoga i le iugafono fautuaina mo le tuʻufaʻatasia o le simplex TX ma le simplex RX i le auala faʻaletino tutusa. E fesoasoani foi lenei transceiver arbiter i le tu'ufa'atasia ma le fa'atalanoaina ole Avalon® manatua-fa'ata'ita'iga RX ma TX toe fetuutuunai talosaga e tulimata'i simplex RX ma TX transceivers i totonu o se alaleo ona o le toe fetuutuunaiga uafu interface o le transceivers e mafai ona maua faasolosolo faasolosolo. Le feso'ota'iga feso'ota'iga i le va o le transceiver arbiter ma TX/RX Native PHY/PHY Reset Pule poloka poloka i lenei mamanu example fa'aalia o se faiga lautele e fa'aoga mo so'o se IP tu'ufa'atasiga e fa'aaoga ai le transceiver arbiter. E le mana'omia le transceiver arbiter pe a na'o le RX po'o le TX transceiver e fa'aaogaina i se alalaupapa. O le transceiver arbiter e faailoa mai le tagata talosaga mo se toe fetuutuunai e ala i ona Avalon memory-mapped reconfiguration interfaces ma faʻamautinoa o le tx_reconfig_cal_busy poʻo rx_reconfig_cal_busy e fetaui ma le faitotoa. Mo fa'aoga HDMI, na'o le RX na te amataina le toe fa'atulagaina. E ala i le faʻasalalauina o le talosaga toe faʻafouina o le mafaufau o Avalon e ala i le arbiter, e faʻamaonia e le arbiter o le talosaga toe faʻafouina e afua mai i le RX, lea e faʻafeiloaʻi ai le tx_reconfig_cal_busy mai le faʻamaonia ma faʻatagaina rx_reconfig_cal_busy e faʻamaonia. O le gating e taofia ai le TX transceiver mai le siitia atu i le calibration mode ma le le iloa. Fa'aaliga: Ona o le HDMI na'o le mana'omia o le RX reconfiguration, o le tx_reconfig_mgmt_* faailoilo ua nonoa. E le gata i lea, e le mana'omia le fa'aogaina o le Avalon i le va o le arbiter ma le poloka TX Native PHY. O poloka o loʻo tuʻuina atu i le atinaʻe i le mamanu exampe fa'aalia le feso'ota'iga lautele transceiver arbiter i le TX/RX Native PHY/PHY Reset Pule

RX-TX So'oga

• O fa'amatalaga fa'amatalaga vitio ma fa'ailoilo fa'amaopoopo mai le HDMI RX fa'aoga autu e ala i le DCFIFO i luga o le RX ma le TX uati vitio domains. • O le auxiliary data port o le HDMI TX core e pulea ai faʻamatalaga fesoasoani e tafe atu i le DCFIFO e ala i le backpressure. E fa'amautinoaina e le backpressure e leai se pepa fesoasoani e le'i atoatoa i luga o le auxiliary data port. • O lenei poloka e fa'atino ai fo'i le fa'amama i fafo: — Fa'amama fa'amatalaga fa'alogo ma le pusa fa'afouina uati fa'alogo mai le fa'amaumauga fesoasoani a'o le'i tu'uina atu i le tau feso'ota'iga feso'ota'iga HDMI TX. - Fa'amama le High Dynamic Range (HDR) InfoFrame mai le HDMI RX ausilali fa'amaumauga ma fa'aofi se example HDR InfoFrame i faʻamatalaga ausilali a le HDMI TX e ala i le Avalon streaming multiplexer.

PPU Subsystem

O le CPU subsystem e galue e pei o le SCDC ma le DDC controllers, ma le source reconfiguration controller. • O le source SCDC controller o lo'o iai le I2C master controller. O le pule sili I2C e faʻafeiloaʻi le fausaga o faʻamaumauga a le SCDC mai le puna FPGA i le pusa i fafo mo le faʻaogaina o le HDMI 2.0. Mo example, afai o le tafega o faamatalaga o le 6,000 Mbps, o le Nios II processor faatonuina le pule sili I2C e faafou le TMDS_BIT_CLOCK_RATIO ma SCRAMBLER_ENABLE fasi o le faatanoa TMDS faatulagaga resitala i le 1. • O le matai I2C lava lea e tasi e faʻafeiloaʻi foʻi le fausaga o faʻamaumauga DDC (E-EDID) i le va o le puna HDMI ma le goto fafo. • O le Nios II PPU e galue e pei o le faʻatonuina o le faʻatonuga mo le puna HDMI. O le PPU e faʻalagolago i le suʻesuʻeina o fua o taimi mai le RX Reconfiguration Management module e fuafua ai pe manaʻomia e le TX le toe faʻaleleia. O le fa'aliliuga o pologa Avalon manatua-fa'afanua e maua ai le feso'ota'iga i le va o le Nios II processor Avalon manatua-mapped matai matai ma feso'ota'iga pologa Avalon manatua-fa'afanua o le IOPLL ma TX Native PHY puna HDMI i fafo. • Fa'atino a'oa'oga feso'ota'iga e ala i le I2C matai fa'aoga fa'atasi ma le goto fafo

2.6. Fa'amatalaga Fa'amatalaga Fa'aofiina ma le Fa'asiliina o Fa'amatalaga Fa'amatalaga Fa'amatalaga Fa'amatalaga Fa'atonu ma le Matai (HDR).
Le HDMI Intel FPGA IP mamanu exampe aofia ai se faʻataʻitaʻiga o le faʻaofiina o le HDR InfoFrame i totonu o le RX-TX loopback system.
HDMI Specification version 2.0b fa'atagaina Dynamic Range ma Mastering InfoFrame e tu'uina atu ile HDMI ausilali vaitafe. I le faʻataʻitaʻiga, o le Auxiliary Packet Generator poloka e lagolagoina le faʻaofiina HDR. E te manaʻomia naʻo le faʻatulagaina o le HDR InfoFrame packet e pei ona faʻamaonia i le laulau lisi faʻailoga a le module ma o le faʻaofiina o le HDR InfoFrame e tupu tasi i ata vitio uma.
I lenei example fa'atulagaina, i taimi ua uma ona aofia ai i totonu o le ausilali fesoasoani le HDR InfoFrame, ua fa'amama le anotusi HDR. O le faʻamama e aloese mai feteʻenaʻiga HDR InfoFrames e tuʻuina atu ma faʻamautinoa e naʻo tau faʻamaonia i le HDR Sample Fa'aoga module Fa'amaumauga.
Ata 11. RX-TX So'oga ma le Dynamic Range ma le Mastering InfoFrame Insertion
O le ata o loʻo faʻaalia ai le poloka poloka o le RX-TX soʻotaga e aofia ai le Dynamic Range ma le Mastering InfoFrame faʻaofiina i totonu o le HDMI TX core auxiliary stream.Laulau 12. Auxiliary Data Insertion Block (aux_retransmit) Faailoga

Fa'ailoga	Fa'atonuga	Lautele	Fa'amatalaga
Uati ma Toe Seti
clk	Ulufale	1	Fa'aoga uati. O lenei uati e tatau ona faʻafesoʻotaʻi i le uati vitio.
toe setiina	Ulufale	1	Toe setiina mea e fai.

Fa'ailoga Fa'ailoga Fesoasoani
tx_aux_data	Tuuina atu	72	TX Auxiliary packet output mai le multiplexer.
tx_aux_valid	Tuuina atu	1
tx_aux_sauni	Tuuina atu	1
tx_aux_sop	Tuuina atu	1
tx_aux_eop	Tuuina atu	1
rx_aux_data	Ulufale	72	RX Auxiliary data na pasi atu i le packet filter module aʻo leʻi ulufale i le multiplexer.
rx_aux_valid	Ulufale	1
rx_aux_sop	Ulufale	1
rx_aux_eop	Ulufale	1

Faʻatonutonu Faʻailo
hdmi_tx_vsync	Ulufale	1	HDMI TX Vitio Vsync. O lenei faailo e tatau ona fa'amaopoopoina i le feso'ota'iga saosaoa uati domain. O le 'autu e fa'aofi le HDR InfoFrame i le vaitafe fesoasoani i le pito i luga o lenei faailo.

Laulau 13. HDR Fa'amatalaga Module (altera_hdmi_hdr_infoframe) Fa'ailoga

Fa'ailoga	Fa'atonuga	Lautele	Fa'amatalaga
hb0	Tuuina atu	8	Ulutala byte 0 o le Dynamic Range ma le Mastering InfoFrame: InfoFrame type code.
hb1	Tuuina atu	8	Ulutala byte 1 o le Dynamic Range ma le Mastering InfoFrame: InfoFrame version number.
hb2	Tuuina atu	8	Ulutala byte 2 o le Dynamic Range ma le Mastering InfoFrame: Umi o InfoFrame.
pb	Ulufale	224	Fa'amatalaga byte o le Dynamic Range ma le Mastering InfoFrame.

Fuafuaga 14. Va'aiga Fa'aola ma le Fa'ata'ita'iina o InfoFrame Data Byte Bundle Bit-Fields

Bit-Field	Uiga	Ituaiga Metadata Tulaga 1
7:0	Fa'amatalaga Byte 1: {5'h0, EOTF[2:0]}
15:8	Fa'amatalaga Byte 2: {5'h0, Static_Metadata_Descriptor_ID[2:0]}
23:16	Fa'amatalaga Fa'amatalaga 3: Static_Metadata_Descriptor	display_primaries_x[0], LSB
31:24	Fa'amatalaga Fa'amatalaga 4: Static_Metadata_Descriptor	display_primaries_x[0], MSB
39:32	Fa'amatalaga Fa'amatalaga 5: Static_Metadata_Descriptor	display_primaries_y[0], LSB
47:40	Fa'amatalaga Fa'amatalaga 6: Static_Metadata_Descriptor	display_primaries_y[0], MSB
55:48	Fa'amatalaga Fa'amatalaga 7: Static_Metadata_Descriptor	display_primaries_x[1], LSB
63:56	Fa'amatalaga Fa'amatalaga 8: Static_Metadata_Descriptor	display_primaries_x[1], MSB
71:64	Fa'amatalaga Fa'amatalaga 9: Static_Metadata_Descriptor	display_primaries_y[1], LSB
79:72	Fa'amatalaga Fa'amatalaga 10: Static_Metadata_Descriptor	display_primaries_y[1], MSB
87:80	Fa'amatalaga Fa'amatalaga 11: Static_Metadata_Descriptor	display_primaries_x[2], LSB
95:88	Fa'amatalaga Fa'amatalaga 12: Static_Metadata_Descriptor	display_primaries_x[2], MSB
103:96	Fa'amatalaga Fa'amatalaga 13: Static_Metadata_Descriptor	display_primaries_y[2], LSB
111:104	Fa'amatalaga Fa'amatalaga 14: Static_Metadata_Descriptor	display_primaries_y[2], MSB
119:112	Fa'amatalaga Fa'amatalaga 15: Static_Metadata_Descriptor	white_point_x, LSB
127:120	Fa'amatalaga Fa'amatalaga 16: Static_Metadata_Descriptor	white_point_x, MSB
135:128	Fa'amatalaga Fa'amatalaga 17: Static_Metadata_Descriptor	white_point_y, LSB
143:136	Fa'amatalaga Fa'amatalaga 18: Static_Metadata_Descriptor	white_point_y, MSB
151:144	Fa'amatalaga Fa'amatalaga 19: Static_Metadata_Descriptor	max_display_mastering_luminance, LSB

159:152	Fa'amatalaga Fa'amatalaga 20: Static_Metadata_Descriptor	max_display_mastering_luminance, MSB
167:160	Fa'amatalaga Fa'amatalaga 21: Static_Metadata_Descriptor	min_display_mastering_luminance, LSB
175:168	Fa'amatalaga Fa'amatalaga 22: Static_Metadata_Descriptor	min_display_mastering_luminance, MSB
183:176	Fa'amatalaga Fa'amatalaga 23: Static_Metadata_Descriptor	Tulaga Maualuga Maualuga Malamalama, LSB
191:184	Fa'amatalaga Fa'amatalaga 24: Static_Metadata_Descriptor	Tulaga Maualuga Maualuga Malamalama, MSB
199:192	Fa'amatalaga Fa'amatalaga 25: Static_Metadata_Descriptor	Tulaga maualuga o le Fa'avaa-vave Malamalama, LSB
207:200	Fa'amatalaga Fa'amatalaga 26: Static_Metadata_Descriptor	Tulaga maualuga o le Fa'avaa-vave Malamalama, MSB
215:208	Fa'apolopolo
223:216	Fa'apolopolo

Fa'agata le fa'aofiina o le HDR ma le fa'amamaina
O le faʻagataina o le faʻaofiina o le HDR ma le faamama e mafai ai ona e faʻamaonia le toe faʻaliliuina o mea HDR ua uma ona maua i le punavai fesoasoani e aunoa ma se suiga i le RX-TX Retransmit design ex.ample.
Ina ia fa'amalo le fa'aofiina ma le fa'amamāina o le HDR InfoFrame:

1. Seti block_ext_hdr_infoframe i le 1'b0 ile rxtx_link.v file e taofia ai le faamamaina o le HDR InfoFrame mai le vaitafe Auxiliary.
2. Set multiplexer_in0_valid o le avalon_st_multiplexer instance i le altera_hdmi_aux_hdr.v file i le 1'b0 e taofia ai le Auxiliary Packet Generator mai le faia ma faʻapipiʻi faaopoopo HDR InfoFrame i totonu o le TX Auxiliary stream.

2.7. Fuafuaga Polokalama Fa'agasolo
I totonu o le mamanu autu o polokalama faakomepiuta, o le Nios II processor configures le seti redriver TI ma amataina le ala TX ma RX i luga o le malosiaga.
Ata 12. Polokalama Fa'agasolo ile main.c Script
O lo'o fa'atinoina e le polokalame se taimi e mata'ituina ai le goto ma suiga o puna, ma tali atu i suiga. O le polokalama e mafai ona faʻaosoina le toe faʻatulagaina o le TX, aʻoaʻoga fesoʻotaʻiga TX ma amata faʻasalalau vitio.
Ata 13. TX Ala amatalia Siata Foma'i Fa'amataina TX AlaAta 14. RX Path Initialization FlowchartAta 15. TX Toe fa'atulagaina ma So'oga Fa'asologa o A'oa'ogaAta 16. A'oa'oga So'otaga LTS:3 Fa'agasologa ile Fua Fa'atatau FRL Fa'apitoaAta 17. HDMI TX Fa'aliliuina Vitio Siata Foma'i2.8. Fa'atino le Fuafuaga i Fua Fa'atatau FRL Eseese
E mafai ona e fa'agasolo lau mamanu i fua FRL eseese, e ese mai le fua ole FRL fa'aletonu ole suau'u fafo.
E fa'atino le mamanu i fua FRL eseese:

1. Togi le sui i luga ole laupapa user_dipsw0 ile tulaga ON.
2. Tatala le atigi poloaiga Nios II, ona lolomi lea o le nios2-terminal
3. Ki i totonu o poloaiga nei ma fetaomi Enter e faʻatino.

Poloaiga	Fa'amatalaga
h	Faaali atu le lisi o fesoasoani.
r0	Fa'afou le RX maualuga FRL gafatia ile FRL fua faatatau 0 (TMDS na'o).
r1	Fa'afou le RX maualuga FRL gafatia ile FRL fua faatatau 1 (3 Gbps).
r2	Fa'afou le RX maualuga FRL gafatia ile FRL fua faatatau 2 (6 Gbps, 3 laina).
r3	Fa'afou le RX maualuga FRL gafatia ile FRL fua faatatau 3 (6 Gbps, 4 laina).
r4	Fa'afou le RX maualuga FRL gafatia ile FRL fua faatatau 4 (8 Gbps).
r5	Fa'afou le RX maualuga FRL gafatia ile FRL fua faatatau 5 (10 Gbps).
r6	Fa'afou le RX maualuga FRL gafatia ile FRL fua faatatau 6 (12 Gbps).
t1	TX fetuutuunai so'oga fua faatatau i FRL fua faatatau 1 (3 Gbps).
t2	TX fetuutuunai so'oga fua faatatau i FRL fua faatatau 2 (6 Gbps, 3 laina).
t3	TX fetuutuunai so'oga fua faatatau i FRL fua faatatau 3 (6 Gbps, 4 laina).
t4	TX fetuutuunai so'oga fua faatatau i FRL fua faatatau 4 (8 Gbps).
t5	TX fetuutuunai so'oga fua faatatau i FRL fua faatatau 5 (10 Gbps).
t6	TX fetuutuunai so'oga fua faatatau i FRL fua faatatau 6 (12 Gbps).

2.9. Fuafuaga uati
O lo'o fa'ailoa mai e le fa'ailoga uati le vaega o le uati i le HDMI Intel FPGA IP design example.
Ata 18. HDMI 2.1 Design Example Fuafuaga uatiLaulau 15. Fa'ailoga Fa'ailoga Fa'ailoga

Uati	Igoa Faailoga i le Design	Fa'amatalaga
Pulega Uati	mgmt_clk	Se uati 100 MHz e leai se totogi mo vaega nei: • Avalon-MM feso'ota'iga mo le toe fa'atulagaina - Ole taimi ole fa'aogaina ole va ole 100–125 MHz. • PHY toe setiina pule mo le transceiver toe seti faasologa - Ole fa'asologa ole taimi ole mana'omia ile va ole 1–500 MHz. • IOPLL Toe fetuunaiga - Ole maualuga ole taimi ole uati ole 100 MHz. • RX Reconfiguration Pulega • TX Toe Fa'atonu Pulega • PPU • I2C Matai
Uati I2C	i2c_clk	O le 100 MHz uati fa'aoga e loka ai le pologa I2C, fa'apipi'i galuega, resitala SCDC, ma feso'ota'iga a'oa'oga i le HDMI RX autu, ma EDID RAM.
TX PLL Fa'asinoala Uati 0	tx_tmds_clk	Fa'asino le uati 0 ile TX PLL. Ole taimi ole uati e tutusa ma le fa'amoemoe ole uati ole TMDS mai le HDMI TX TMDS uati alaala. O lenei uati fa'asino e fa'aoga ile TMDS mode. Mo lenei mamanu HDMI example, o lenei uati e fesoʻotaʻi i le RX TMDS uati mo faʻamoemoega faʻataʻitaʻiga. I lau talosaga, e te mana'omia le tu'uina atu o se uati tu'ufa'atasi ma le TMDS uati taimi mai se oscillator e mafai ona fa'apolokalameina mo le sili atu o le fa'atinoga o le jitter.

		Fa'aaliga: Aua le fa'aogaina se pine RX fa'aliliu e fai ma uati fa'asinoga TX PLL. O lau mamanu o le a le fetaui pe afai e te tuʻuina le HDMI TX refclk i luga o se pine RX.
TX PLL Fa'asinoala Uati 1	txfpll_refclk1/ rxphy_cdr_refclk1	Fa'asino le uati ile TX PLL ma le RX CDR, fa'apea fo'i le IOPLL mo vid_clk. Ole taimi ole uati ole 100 MHz.
TX PLL Uati Fa'asologa	tx_bonding_ccks	Uati vave fa'asologa fa'atupu e TX PLL. Ole taimi ole uati e fa'atatau ile fua ole fa'amaumauga.
TX Transceiver Uati I fafo	tx_clk	Uati i fafo toe maua mai le transceiver, ma o le taimi e eseese e faalagolago i le fua faatatau o faamatalaga ma faailoga i le uati. TX transceiver uati i fafo taimi = Transceiver fua faatatau / Transceiver lautele Mo lenei mamanu HDMI example, o le TX transceiver uati i fafo mai alalaupapa 0 uati le TX transceiver autu ulufale (tx_coreclkin), sootaga saoasaoa IOPLL (pll_hdmi) faasinoupu uati, ma le vitio ma FRL IOPLL (pll_vid_frl) faasinoupu uati.
Uati Vitio	tx_vid_clk/rx_vid_clk	Uati vitio i le TX ma le RX autu. O le uati e tamo'e i se taimi tumau o le 225 MHz.
TX/RX FRL Uati	tx_frl_clk/rx_frl_clk	FRL uati i mo TX ma RX autu.
Uati RX TMDS	rx_tmds_clk	TMDS uati alavai mai le HDMI RX connector ma fesootai i se IOPLL e gaosia le uati faasinomaga mo CDR faasinoala uati 0. O le autu e faaaoga lenei uati pe a i ai i le TMDS mode.
RX CDR Fa'asino Uati 0	rxphy_cdr_refclk0	Fa'asino le uati 0 i le RX CDR. O lenei uati e maua mai le uati RX TMDS. Ole taimi ole uati ole RX TMDS e amata mai i le 25 MHz i le 340 MHz ae o le RX CDR aupito maualalo ole taimi ole uati ole 50 MHz. O le IOPLL o lo'o fa'aaogaina e fa'atupu ai le 5 uati mo le TMDS uati i le va o le 25 MHz i le 50 MHz ma fa'atupuina le taimi tutusa o le uati mo le TMDS uati i le va o le 50 MHz - 340 MHz.
RX Transceiver Uati I fafo	rx_clk	Uati i fafo toe maua mai le transceiver, ma o le taimi e eseese e faalagolago i le fua faatatau o faamatalaga ma transceiver lautele. RX transceiver uati i fafo taimi = Transceiver fua faatatau / Transceiver lautele Mo lenei mamanu HDMI example, o le RX transceiver uati i fafo mai alalaupapa 1 uati le RX transceiver autu ulu (rx_coreclkin) ma FRL IOPLL (pll_frl) faasinoupu uati.

2.10. Fa'ailoga Fa'afeso'ota'i
O laulau o lo'o lisiina ai fa'ailo mo le HDMI design example ma le FRL ua mafai.
Laulau 16. Fa'ailoga Tulaga Maualuga

Fa'ailoga	Fa'atonuga	Lautele	Fa'amatalaga
Fa'ailoga ole Oscillator i luga ole laupapa
clk_fpga_b3_p	Ulufale	1	100 MHz uati tamo'e fua mo le uati fa'asino autu.
refclk4_p	Ulufale	1	100 MHz uati tamo'e fua mo transceiver faasinoupu uati.

Fa'aoga Push Buttons ma LED
user_pb	Ulufale	3	Oomi le ki e pulea ai le HDMI Intel FPGA IP design functionality.
cpu_resetn	Ulufale	1	Toe setiina lalolagi.
user_led_g	Tuuina atu	8	Fa'aaliga LED lanu meamata. Fa'asino i Seti Meafaigaluega i le itulau 48 mo nisi fa'amatalaga e uiga i galuega fa'atino a le LED.
user_dipsw	Ulufale	1	Suia DIP fa'aogaina e le tagata. Fa'asino i Seti Meafaigaluega i le itulau 48 mo nisi fa'amatalaga e uiga i galuega fa'afeso'ota'i DIP.

HDMI FMC Daughter Card Pins ile FMC Port B
fmcb_gbtclk_m2c_p_0	Ulufale	1	Uati HDMI RX TMDS.
fmcb_dp_m2c_p	Ulufale	4	HDMI RX uati, mumu, lanu meamata, ma le lanumoana alavai fa'amatalaga.
fmcb_dp_c2m_p	Tuuina atu	4	HDMI TX uati, mumu, lanu meamata, ma le lanumoana alavai faʻamatalaga.
fmcb_la_rx_p_9	Ulufale	1	HDMI RX +5V mana iloa.
fmcb_la_rx_p_8	Tuuina atu	1	HDMI RX pa'u vevela iloa.
fmcb_la_rx_n_8	Ulufale	1	HDMI RX I2C SDA mo DDC ma SCDC.
fmcb_la_tx_p_10	Ulufale	1	HDMI RX I2C SCL mo DDC ma SCDC.
fmcb_la_tx_p_12	Ulufale	1	HDMI TX pa'u vevela iloa.
fmcb_la_tx_n_12	Ulufale	1	HDMI I2C SDA mo DDC ma SCDC.
fmcb_la_rx_p_10	Ulufale	1	HDMI I2C SCL mo DDC ma SCDC.
fmcb_la_tx_n_9	Ulufale	1	HDMI I2C SDA mo redriver pulea.
fmcb_la_rx_p_11	Ulufale	1	HDMI I2C SCL mo le puleaina o le redriver.
fmcb_la_tx_n_13	Tuuina atu	1	HDMI TX +5V Fa'aaliga: Faatoa avanoa pe a Bitec HDMI Daughter Card Toe Iloiloga 9 ua filifilia.

Laulau 17. HDMI RX Fa'ailoga Tulaga Maualuga

Fa'ailoga	Fa'atonuga	Lautele	Fa'amatalaga
Uati ma Toe Seti Faailoga
mgmt_clk	Ulufale	1	Fa'aoga uati fa'aoga (100 MHz).
toe setiina	Ulufale	1	Fa'aoga toe setiina faiga.
rx_tmds_clk	Ulufale	1	Uati HDMI RX TMDS.
i2c_clk	Ulufale	1	Fa'aoga uati mo le DDC ma le SCDC fa'aoga.

Uati ma Toe Seti Faailoga
rxphy_cdr_refclk1	Ulufale	1	Fa'aoga uati mo le uati fa'asino i le RX CDR 1. Ole taimi ole uati ole 100 MHz.
rx_vid_clk	Tuuina atu	1	Fa'atino uati vitiō.
sys_init	Tuuina atu	1	System initialization e toe setiina le faiga i luga o le power-up.

RX Transceiver ma IOPLL faailoilo
rxpll_tmds_loka	Tuuina atu	1	Fa'ailoa mai ua loka le uati TMDS IOPLL.
rxpll_frl_loka	Tuuina atu	1	Fa'ailoa mai ua loka le uati FRL IOPLL.
rxphy_serial_data	Ulufale	4	HDMI fa'amaumauga fa'asologa i le RX Native PHY.
rxphy_sauni	Tuuina atu	1	Fa'ailoa mai ua sauni le RX Native PHY.
rxphy_cal_busy_raw	Tuuina atu	4	RX Native PHY calibration pisi i le transceiver arbiter.
rxphy_cal_busy_gated	Ulufale	4	Fa'ailoilo pisi pisi mai le transceiver arbiter i le RX Native PHY.
rxphy_rcfg_slave_write	Ulufale	4	Transceiver toe fetuutuunai Avalon fa'afanua fa'ata'atiaga manatua mai le RX Native PHY i le transceiver arbiter.
rxphy_rcfg_slave_read	Ulufale	4
rxphy_rcfg_slave_address	Ulufale	40
rxphy_rcfg_slave_writedata	Ulufale	128
rxphy_rcfg_slave_readdata	Tuuina atu	128
rxphy_rcfg_slave_waitrequest	Tuuina atu	4

RX Reconfiguration Pulega
rxphy_rcfg_pisi	Tuuina atu	1	RX Reconfiguration faʻailoga pisi.
rx_tmds_freq	Tuuina atu	24	HDMI RX TMDS fua ole uati (i le 10 ms).
rx_tmds_freq_valid	Tuuina atu	1	Fa'ailoa mai ole fua ole taimi ole uati ole RX TMDS e aoga.
rxphy_os	Tuuina atu	1	oversampmea taua: •0: 1x ovaampling • 1: 5x ovaampling
rxphy_rcfg_master_write	Tuuina atu	1	RX toe fetuutuuna'i pulega Avalon fa'afanua fa'ata'atiaga manatua i le transceiver arbiter.
rxphy_rcfg_master_read	Tuuina atu	1
rxphy_rcfg_master_address	Tuuina atu	12
rxphy_rcfg_master_writedata	Tuuina atu	32
rxphy_rcfg_master_readdata	Ulufale	32
rxphy_rcfg_master_waitrequest	Ulufale	1

HDMI RX Fa'ailoga Autu
rx_vid_clk_loka	Ulufale	1	Fa'ailoa vid_clk o lo'o mautu.
rxcore_frl_rate	Tuuina atu	4	Fa'ailoa le fua FRL o lo'o fa'agasolo le RX core. • 0: Legacy Mode (TMDS) • 1: 3 Gbps 3 laina • 2: 6 Gbps 4 laina • 3: 6 Gbps 4 laina • 4: 8 Gbps 4 laina • 5: 10 Gbps 4 laina • 6: 12 Gbps 4 laina • 7-15: Faasao
rxcore_frl_loka	Tuuina atu	4	O pito ta'itasi o lo'o fa'ailoa mai ai le ala fa'apitoa ua maua le loka FRL. E loka le FRL pe a fa'atino lelei e le RX core le fa'aoga, kesi, ma maua le loka o le laina. • Mo le 3-lane mode, e maua le loka o le laina pe a maua e le RX core le Scrambler Reset (SR) poʻo le Start-Super-Block (SSB) mo taimi uma e 680 FRL mo le itiiti ifo i le 3 taimi. • Mo le 4-lane mode, e maua le loka o le laina pe a maua e le RX core le Scrambler Reset (SR) poʻo le Start-Super-Block (SSB) mo taimi uma e 510 FRL mo le itiiti ifo i le 3 taimi.
rxcore_frl_ffe_levels	Tuuina atu	4	E fetaui ma le FFE_level bit i le SCDC 0x31 register bit [7:4] i le RX core.
rxcore_frl_flt_ready	Ulufale	1	Fa'ailoa e fa'ailoa mai ua sauni le RX mo le fa'agasologa o a'oa'oga so'o e amata. Pe a faʻamaonia, o le FLT_ready bit i le SCDC register 0x40 bit 6 o loʻo faʻamaonia foi.
rxcore_frl_src_test_config	Ulufale	8	Fa'ama'oti mai fa'atonuga o su'ega puna. O le tau o loʻo tusia i totonu o le SCDC Test Configuration register i le SCDC register 0x35.
rxcore_tbcr	Tuuina atu	1	Fa'ailoa mai le fua faatatau o le TMDS bit i le uati; e fetaui ma le resitala TMDS_Bit_Clock_Ratio i le tusi resitala SCDC 0x20 bit 1. • Pe a tamoʻe i le HDMI 2.0 mode, o loʻo faʻamaonia lenei mea. Fa'ailoa le TMDS bit i le fuafaatatau o le uati o le 40:1. • Pe a tamoʻe i le HDMI 1.4b, e le o faʻamaonia lenei mea. Fa'ailoa le TMDS bit i le fua faatatau o le uati o le 10:1. • E le'o fa'aogaina lenei vaega mo le FRL mode.
rxcore_scrambler_enable	Tuuina atu	1	Fa'ailoa mai pe ua fa'asolo fa'amatalaga na maua; e fetaui ma le Scrambling_Enable fanua i le SCDC resitala 0x20 bit 0.
rxcore_audio_de	Tuuina atu	1	HDMI RX feso'ota'iga leo autu Fa'asino i le Fa'agogo Fa'asagaga vaega i le HDMI Intel FPGA IP Taiala Tagata Fa'aoga mo nisi faamatalaga.
rxcore_audio_data	Tuuina atu	256
rxcore_audio_info_ai	Tuuina atu	48

rxcore_audio_N	Tuuina atu	20
rxcore_audio_CTS	Tuuina atu	20
rxcore_audio_metadata	Tuuina atu	165
rxcore_audio_format	Tuuina atu	5
rxcore_aux_pkt_data	Tuuina atu	72	HDMI RX feso'ota'iga fesoasoani autu Fa'asino i le Fa'agogo Fa'asagaga vaega i le HDMI Intel FPGA IP Taiala Tagata Fa'aoga mo nisi faamatalaga.
rxcore_aux_pkt_addr	Tuuina atu	6
rxcore_aux_pkt_wr	Tuuina atu	1
rxcore_aux_data	Tuuina atu	72
rxcore_aux_sop	Tuuina atu	1
rxcore_aux_eop	Tuuina atu	1
rxcore_aux_valid	Tuuina atu	1
rxcore_aux_error	Tuuina atu	1
rxcore_gcp	Tuuina atu	6	HDMI RX fa'ailoga pito i tua Fa'asino i le Fa'agogo Fa'asagaga vaega i le HDMI Intel FPGA IP Taiala Tagata Fa'aoga mo nisi faamatalaga.
rxcore_info_avi	Tuuina atu	123
rxcore_info_vsi	Tuuina atu	61
rxcore_loka	Tuuina atu	1	HDMI RX pito ata vitio autu Manatua: N = pika i le uati Fa'asino i le Fa'agogo Fa'asagaga vaega i le HDMI Intel FPGA IP Taiala Tagata Fa'aoga mo nisi faamatalaga.
rxcore_vid_data	Tuuina atu	N*48
rxcore_vid_vsync	Tuuina atu	N
rxcore_vid_hsync	Tuuina atu	N
rxcore_vid_de	Tuuina atu	N
rxcore_vid_valid	Tuuina atu	1
rxcore_vid_lock	Tuuina atu	1
rxcore_mode	Tuuina atu	1	HDMI RX pulea autu ma tulaga ports. Manatua: N = faailoga i le uati Fa'asino i le Fa'agogo Fa'asagaga vaega i le HDMI Intel FPGA IP Taiala Tagata Fa'aoga mo nisi faamatalaga.
rxcore_ctrl	Tuuina atu	N*6
rxcore_color_depth_sync	Tuuina atu	2
hdmi_5v_deteksi	Ulufale	1	HDMI RX 5V iloa ma maua vevela. Fa'asino i le Fa'agogo Fa'asagaga vaega i le HDMI Intel FPGA IP Taiala Tagata Fa'aoga mo nisi faamatalaga.
hdmi_rx_hpd	Tuuina atu	1
rx_hpd_trigger	Ulufale	1

I2C Faailoga
hdmi_rx_i2c_sda	Ulufale	1	HDMI RX DDC ma le SCDC fa'aoga.
hdmi_rx_i2c_scl	Ulufale	1

RX EDID RAM faailoilo
edid_ram_access	Ulufale	1	HDMI RX EDID RAM avanoa avanoa.

edid_ram_address	Ulufale	8	Fa'ailoa edid_ram_access pe a e mana'o e tusi pe faitau mai le EDID RAM, a le o lea e tatau ona fa'amaulalo lenei fa'ailoga. A e fa'ailoa edid_ram_access, e fa'amalo le fa'ailoga vevela e fa'ataga ai le tusi pe faitau i le EDID RAM. A mae'a le avanoa EDID RAM, e tatau ona e tu'u ese le edid_ram_assess ma fa'ailoa mai le fa'ailoga o le hotplug. O le puna o le a faitau le EDID fou ona o le faʻailoga o le hotplug toggling.
edid_ram_write	Ulufale	1
edid_ram_read	Ulufale	1
edid_ram_readdata	Tuuina atu	8
edid_ram_writedata	Ulufale	8
edid_ram_waitrequest	Tuuina atu	1

Laulau 18. HDMI TX Tulaga Maualuga Fa'ailoga

Fa'ailoga	Fa'atonuga	Lautele	Fa'amatalaga
Uati ma Toe Seti Faailoga
mgmt_clk	Ulufale	1	Fa'aoga uati fa'aoga (100 MHz).
toe setiina	Ulufale	1	Fa'aoga toe setiina faiga.
tx_tmds_clk	Ulufale	1	Uati HDMI RX TMDS.
txfpll_refclk1	Ulufale	1	Fa'aoga uati mo le TX PLL fa'asino uati 1. Ole taimi ole uati ole 100 MHz.
tx_vid_clk	Tuuina atu	1	Fa'atino uati vitiō.
tx_frl_clk	Tuuina atu	1	FRL uati fua.
sys_init	Ulufale	1	System initialization e toe setiina le faiga i luga o le power-up.
tx_init_done	Ulufale	1	TX amatalia e toe setiina le TX reconfiguration pulega poloka ma transceiver reconfiguration interface.

TX Transceiver ma IOPLL faailoilo
txpll_frl_loka	Tuuina atu	1	Fa'ailoa le uati saoasaoa so'otaga ma ua loka FRL IOPLL ua loka.
txfpll_loka	Tuuina atu	1	Fa'ailoa mai ua loka le TX PLL.
txphy_serial_data	Tuuina atu	4	HDMI fa'amaumauga fa'asologa mai le TX Native PHY.
txphy_sauni	Tuuina atu	1	Fa'ailoa mai ua sauni le TX Native PHY.
txphy_cal_busy	Tuuina atu	1	TX Native PHY calibration fa'ailoga pisi.
txphy_cal_busy_raw	Tuuina atu	4	Fa'ailoilo pisi pisi i le transceiver arbiter.
txphy_cal_busy_gated	Ulufale	4	Fa'ailoilo pisi pisi mai le transceiver arbiter i le TX Native PHY.
txphy_rcfg_pisi	Tuuina atu	1	Fa'ailoa mai o lo'o fa'agasolo le toe fa'atulagaina o le TX PHY.
txphy_rcfg_slave_write	Ulufale	4	Transceiver toe fetuutuunai Avalon fa'afanua fa'ata'atiaga manatua mai le TX Native PHY i le transceiver arbiter.
txphy_rcfg_slave_read	Ulufale	4
txphy_rcfg_slave_address	Ulufale	40
txphy_rcfg_slave_writedata Ulufale 128 txphy_rcfg_slave_readdata Tuuina atu 128 txphy_rcfg_slave_waitrequest Tuuina atu 4

TX Toe Fa'atonu Pulega
tx_tmds_freq	Ulufale	24	HDMI TX TMDS tau ole taimi ole uati (i le 10 ms).
tx_os	Tuuina atu	2	oversampmea taua: • 0: 1x ovaampling •1: 2× ovaampling •2: 8x ovaampling
txphy_rcfg_master_write	Tuuina atu	1	TX reconfiguration pulega Avalon manatua-faafanua atigi i transceiver arbiter.
txphy_rcfg_master_read	Tuuina atu	1
txphy_rcfg_master_address	Tuuina atu	12
txphy_rcfg_master_writedata	Tuuina atu	32
txphy_rcfg_master_readdata	Ulufale	32
txphy_rcfg_master_waitrequest	Ulufale	1
tx_reconfig_done	Tuuina atu	1	Fa'ailoa mai ua mae'a le fa'atulagaina o le TX.

HDMI TX Fa'ailoga Autu
tx_vid_clk_loka	Ulufale	1	Fa'ailoa vid_clk o lo'o mautu.
txcore_ctrl	Ulufale	N*6	HDMI TX feso'ota'iga fa'atonutonu autu. Manatua: N = pika i le uati Fa'asino i le Source Interfaces vaega i le HDMI Intel FPGA IP Taiala Tagata Fa'aoga mo nisi faamatalaga.
txcore_mode	Ulufale	1
txcore_audio_de	Ulufale	1	HDMI TX feso'ota'iga leo autu. Fa'asino i le Source Interfaces vaega i le HDMI Intel FPGA IP Taiala Tagata Fa'aoga mo nisi faamatalaga.
txcore_audio_mute	Ulufale	1
txcore_audio_data	Ulufale	256
txcore_audio_info_ai	Ulufale	49
txcore_audio_N	Ulufale	20
txcore_audio_CTS	Ulufale	20
txcore_audio_metadata	Ulufale	166
txcore_audio_format	Ulufale	5
txcore_aux_ready	Tuuina atu	1	HDMI TX feso'ota'iga fesoasoani autu. Fa'asino i le Source Interfaces vaega i le HDMI Intel FPGA IP Taiala Tagata Fa'aoga mo nisi faamatalaga.
txcore_aux_data	Ulufale	72
txcore_aux_sop	Ulufale	1
txcore_aux_eop	Ulufale	1

txcore_aux_valid	Ulufale	1
txcore_gcp	Ulufale	6	HDMI TX fa'ailoga pito pito i tua. Fa'asino i le Source Interfaces vaega i le HDMI Intel FPGA IP Taiala Tagata Fa'aoga mo nisi faamatalaga.
txcore_info_avi	Ulufale	123
txcore_info_vsi	Ulufale	62
txcore_i2c_master_write	Ulufale	1	TX I2C matai Avalon fa'ata'ita'iga fa'ata'ita'iga i le I2C matai i totonu ole TX autu. Fa'aaliga: E maua nei faailoilo pe a e ki le Fa'aaofia le I2C fa'ata'oto.
txcore_i2c_master_read	Ulufale	1
txcore_i2c_master_address	Ulufale	4
txcore_i2c_master_writedata	Ulufale	32
txcore_i2c_master_readdata	Tuuina atu	32
txcore_vid_data	Ulufale	N*48	HDMI TX uafu autu vitio. Manatua: N = pika i le uatiRef er i le Source Interfaces vaega i le HDMI Intel FPGA IP Taiala Tagata Fa'aoga mo nisi faamatalaga.
txcore_vid_vsync	Ulufale	N
txcore_vid_hsync	Ulufale	N
txcore_vid_de	Ulufale	N
txcore_vid_ready	Tuuina atu	1
txcore_vid_overflow	Tuuina atu	1
txcore_vid_valid	Ulufale	1
txcore_frl_rate	Ulufale	4	feso'ota'iga resitala a le SCDC.
txcore_frl_pattern	Ulufale	16
txcore_frl_start	Ulufale	1
txcore_scrambler_enable	Ulufale	1
txcore_tbcr	Ulufale	1

I2C Faailoga
nios_tx_i2c_sda_in	Tuuina atu	1	TX I2C Matai fa'aoga mo SCDC ma DDC mai le Nios II fa'agaioiga i le fa'apolopolo galuega. Fa'aaliga: Afai e te ki le Fa'aaofia le I2C parakalafa, o nei faailo o le a tuʻuina i totonu o le TX autu ma o le a le mafai ona iloa i lenei tulaga.
nios_tx_i2c_scl_in	Tuuina atu	1
nios_tx_i2c_sda_oe	Ulufale	1
nios_tx_i2c_scl_oe	Ulufale	1
nios_ti_i2c_sda_in	Tuuina atu	1	TX I2C Matai fa'aoga mai le Nios II fa'agaioiga i le fa'apolopolo galuega e fa'atonutonu ai le TI redriver ile Bitec HDMI 2.1 FMC tama teine.
nios_ti_i2c_scl_in	Tuuina atu	1
nios_ti_i2c_sda_oe	Ulufale	1
nios_ti_i2c_scl_oe	Ulufale	1
hdmi_tx_i2c_sda	Ulufale	1	TX I2C feso'ota'iga mo feso'ota'iga SCDC ma DDC mai le fa'apolopolo fa'aulu i le feso'ota'iga HDMI TX.
hdmi_tx_i2c_scl	Ulufale	1
hdmi_tx_ti_i2c_sda	Ulufale	1	TX I2C fa'afeso'ota'i mai le pa'u fa'aulufale i le TI redriver i luga o le kata tama teine ​​Bitec HDMI 2.1 FMC.
hdmi_tx_ti_i2c_scl	Ulufale	1

tx_hpd_req	Tuuina atu	1	HDMI TX hotplug iloa feso'ota'iga.
hdmi_tx_hpd_n	Ulufale	1

Laulau 19. Transceiver Arbiter Signals

Fa'ailoga	Fa'atonuga	Lautele	Fa'amatalaga
clk	Ulufale	1	Toe fa'atulagaina uati. O lenei uati e tatau ona fa'asoa tutusa le uati ma poloka fa'atonutonu toe fetuutuunai.
toe setiina	Ulufale	1	Toe seti le faailo. O lenei seti e tatau ona fa'asoa tutusa le seti fa'atasi ma poloka pulega toefa'atonu.
rx_rcfg_en	Ulufale	1	RX reconfiguration mafai ai le faailo.
tx_rcfg_en	Ulufale	1	TX reconfiguration mafai ai le faailo.
rx_rcfg_ch	Ulufale	2	Fa'ailoa mai po'o fea alāvai e toe fa'atulaga ile RX autu. O lenei faailo e tatau ona faʻamaonia i taimi uma.
tx_rcfg_ch	Ulufale	2	Fa'ailoa mai po'o fea alavai e toe fa'afou ile TX autu. O lenei faailo e tatau ona faʻamaonia i taimi uma.
rx_reconfig_mgmt_write	Ulufale	1	Toe fetuutuuna'i Avalon fa'afanua fa'amaufa'ailoga mai le RX reconfiguration pulega.
rx_reconfig_mgmt_read	Ulufale	1
rx_reconfig_mgmt_address	Ulufale	10
rx_reconfig_mgmt_writedata	Ulufale	32
rx_reconfig_mgmt_readdata	Tuuina atu	32
rx_reconfig_mgmt_waitrequest	Tuuina atu	1
tx_reconfig_mgmt_write	Ulufale	1	Toe fetuutuuna'i Avalon fa'afanua fa'amaufa'ailoga mai le TX reconfiguration pulega.
tx_reconfig_mgmt_read	Ulufale	1
tx_reconfig_mgmt_address	Ulufale	10
tx_reconfig_mgmt_writedata	Ulufale	32
tx_reconfig_mgmt_readdata	Tuuina atu	32
tx_reconfig_mgmt_waitrequest	Tuuina atu	1
reconfig_write	Tuuina atu	1	Toe fetuutuuna'i feso'ota'iga ua fa'ata'atia e Avalon i le transceiver.
toeconfig_read	Tuuina atu	1
toeconfig_address	Tuuina atu	10
reconfig_writedata	Tuuina atu	32
rx_reconfig_readdata	Ulufale	32
rx_reconfig_waitrequest	Ulufale	1
tx_reconfig_readdata	Ulufale	1
tx_reconfig_waitrequest	Ulufale	1

rx_cal_busy	Ulufale	1	Fa'ailoga tulaga fa'avasega mai le RX transceiver.
tx_cal_busy	Ulufale	1	Fa'ailoga tulaga fa'avasega mai le transceiver TX.
rx_reconfig_cal_busy	Tuuina atu	1	Fa'ailoga tulaga fa'avasega i le RX transceiver PHY reset control.
tx_reconfig_cal_busy	Tuuina atu	1	Fa'ailoga tulaga fa'avasega mai le TX transceiver PHY reset control.

Laulau 20. Fa'ailoga So'oga RX-TX

Fa'ailoga	Fa'atonuga	Lautele	Fa'amatalaga
vid_clk	Ulufale	1	Uati vitio HDMI.
rx_vid_lock	Ulufale	3	Fa'ailoa le tulaga loka vitio HDMI RX.
rx_vid_valid	Ulufale	1	HDMI RX feso'ota'iga vitio.
rx_vid_de	Ulufale	N
rx_vid_hsync	Ulufale	N
rx_vid_vsync	Ulufale	N
rx_vid_data	Ulufale	N*48
rx_aux_eop	Ulufale	1	HDMI RX feso'ota'iga fesoasoani.
rx_aux_sop	Ulufale	1
rx_aux_valid	Ulufale	1
rx_aux_data	Ulufale	72
tx_vid_de	Tuuina atu	N	HDMI TX feso'ota'iga vitio. Manatua: N = pika i le uati
tx_vid_hsync	Tuuina atu	N
tx_vid_vsync	Tuuina atu	N
tx_vid_data	Tuuina atu	N*48
tx_vid_valid	Tuuina atu	1
tx_vid_ready	Ulufale	1
tx_aux_eop	Tuuina atu	1	HDMI TX feso'ota'iga fesoasoani.
tx_aux_sop	Tuuina atu	1
tx_aux_valid	Tuuina atu	1
tx_aux_data	Tuuina atu	72
tx_aux_sauni	Ulufale	1

Laulau 21. Fa'ailoga Fa'ailoga Fa'atonu a le Platform

Fa'ailoga	Fa'atonuga	Lautele	Fa'amatalaga
cpu_clk_in_clk_clk	Ulufale	1	uati CPU.
cpu_rst_in_reset_reset	Ulufale	1	Toe setiina PPU.

edid_ram_slave_translator_avalon_anti_slave_0_address	Tuuina atu	8	EDID RAM avanoa avanoa.
edit_ram_slave_translator_avalon_anti_slave_0_tusi	Tuuina atu	1
edid_ram_slave_translator_avalon_anti_slave_0_read	Tuuina atu	1
edid_ram_slave_translator_avalon_anti_slave_0_readdata	Ulufale	8
edid_ram_slave_translator_avalon_anti_slave_0_writedata	Tuuina atu	8
edid_ram_slave_translator_avalon_anti_slave_0_waitrequest	Ulufale	1
hdmi_i2c_master_i2c_serial_sda_in	Ulufale	1	I2C Matai fa'afeso'ota'i mai le Nios II fa'agaioiga i le fa'apolopolo galuega mo le DDC ma le SCDC pulea.
hdmi_i2c_master_i2c_serial_scl_in	Ulufale	1
hdmi_i2c_master_i2c_serial_sda_oe	Tuuina atu	1
hdmi_i2c_master_i2c_serial_scl_oe	Tuuina atu	1
redriver_i2c_master_i2c_serial_sda_in	Ulufale	1	I2C Matai fa'afeso'ota'i mai le Nios II processor i le fa'apolopolo galuega mo TI redriver seti seti.
redriver_i2c_master_i2c_serial_scl_in	Ulufale	1
redriver_i2c_master_i2c_serial_sda_oe	Tuuina atu	1
redriver_i2c_master_i2c_serial_scl_oe	Tuuina atu	1
pio_in0_external_connection_export	Ulufale	32	Faiga fa'akomepiuta fa'aoga tutusa. • Bit 0: Fa'afeso'ota'i i le fa'ailoga user_dipsw e fa'atonutonu ai le ala fa'ase'e EDID. • Bit 1: TX HPD talosaga • Bit 2: TX transceiver sauni • Bits 3: TX toe fetuutuunai faia • Bits 4–7: Fa'asao • Pisi 8–11: RX FRL fua • Bit 12: RX TMDS bit clock ratio • Pisi 13–16: RX FRL loka • Pisi 17–20: RX FFE maualuga • Bit 21: Loka le fa'aogaina o le RX

Fa'ailoga	Fa'atonuga	Lautele	Fa'amatalaga
			• Bit 22: loka vitio RX • Bit 23: Fa'amau fa'aoga 2 e faitau tusi resitala SCDC mai le goto fafo • Bits 24–31: Fa'asao
pio_out0_external_connection_export	Tuuina atu	32	Faiga fa'akomepiuta fa'aoga tutusa. • Bit 0: TX HPD fa'ailoa • Bit 1: TX initialization ua faia • Vaega 2–7: Faasao • Bits 8–11: TX FRL fua • Bits 12–27: TX FRL so'otaga a'oa'oga mamanu • Bit 28: TX FRL amata • Vaega 29–31: Faasao
pio_out1_external_connection_export	Tuuina atu	32	Faiga fa'akomepiuta fa'aoga tutusa. • Bit 0: avanoa RX EDID RAM • Bit 1: RX FLT sauni • Vaega 2–7: Faasao • Bits 8–15: RX FRL su'ega su'ega puna • Bits 16–31: Fa'asao

2.1. 1. Fuafua RTL Parameters
Fa'aoga le HDMI TX ma le RX Top RTL fa'amaufa'ailoga e fa'avasega ai le fa'ata'ita'igaample.
O le tele o mamanu mamanu o loʻo maua i le Design Example laupepa o le HDMI Intel FPGA IP fa'atonu fa'atonu. E mafai lava ona e suia le mamanu example fa'atulagaina na e faia i le fa'atonu fa'ata'ita'i e ala i le fa'asologa o le RTL.
Laulau 22. HDMI RX pito i luga

Parameter	Taua	Fa'amatalaga
SUPPORT_DEEP_COLOR	• 0: Leai se lanu loloto • : Lanu loloto	Fuafua pe mafai e le totonugalemu ona faʻapipiʻi faʻailoga lanu loloto.
SUPPORT_AUXILIARY	• 0: Leai AUX •1: AUX	Fuafua pe fa'aaofia ai le fa'asologa o alalaupapa fesoasoani.
SYMBOLS_PER_CLOCK	8	Lagolago 8 faailoga i le uati mo Intel Arria 10 masini.
SUPPORT_AUDIO	• 0: Leai se leo • 1: Leo	Fuafua pe mafai e le autu ona fa'aigoa leo.

EDID_RAM_ADDR_WIDTH	8 (Tauaiga masani)	Fa'amaufa'ailoga 2 o le EDID RAM tele.
BITEC_DAUGHTER_CARD_REV	•0: Le tulimata'i so'o se kata tama teine ​​Bitec HDMI •4: Lagolagoina Bitec HDMI fa'ata'ita'iga pepa tama teine ​​4 •6: Fa'atatauina Bitec HDMI daughter card toe teuteuga 6 • 11: Fa'atatau i le Bitec HDMI daughter card toe teuteuga 11 (fa'aletonu)	Fa'amaoti le toe iloiloga o le Bitec HDMI daughter card fa'aaogaina. A e suia le toe iloiloga, e mafai e le mamanu ona fesuiaʻi auala transceiver ma fesuiaʻi le polarity e tusa ai ma le Bitec HDMI daughter card manaʻomia. Afai e te setiina le BITEC_DAUGHTER_CARD_REV parakalafa i le 0, o le mamanu e le faia ni suiga i le transceiver auala ma le polarity.
POLARITY_INVERSION	• 0: Faaliliuina polarity • 1: Aua le fesuia'i le polarity	Seti lenei ta'otoga i le 1 e fesuia'i ai le tau o vaega ta'itasi o fa'amatalaga fa'aoga. O le setiina o lenei parakalafa i le 1 e tuʻuina atu ai le 4'b1111 i le rx_polinv port o le RX transceiver.

Fuafuaga 23. HDMI TX Parameter pito i luga

Parameter	Taua	Fa'amatalaga
USE_FPLL	1	Lagolago fPLL pei TX PLL mo na'o Intel Arria 10 masini. Seti i taimi uma le parakalafa i le 1.
SUPPORT_DEEP_COLOR	•0: Leai se lanu loloto • 1: Lanu loloto	Fuafua pe mafai e le totonugalemu ona faʻapipiʻi faʻailoga lanu loloto.
SUPPORT_AUXILIARY	• 0: Leai AUX • 1: AUX	Fuafua pe fa'aaofia ai le fa'asologa o alalaupapa fesoasoani.
SYMBOLS_PER_CLOCK	8	Lagolago 8 faailoga i le uati mo Intel Arria 10 masini.
SUPPORT_AUDIO	• 0: Leai se leo • 1: Leo	Fuafua pe mafai e le autu ona fa'aigoa leo.
BITEC_DAUGHTER_CARD_REV	• 0: Le tulimata'i so'o se kata tama teine ​​Bitec HDMI • 4: Lagolago le Bitec HDMI fa'ata'ita'iga pepa tama teine ​​4 • 6: Su'esu'eina Bitec HDMI daughter card toe teuteuga 6 • 11: Fa'atatau i le Bitec HDMI daughter card toe teuteuga 11 (fa'aletonu)	Fa'amaoti le toe iloiloga o le Bitec HDMI daughter card fa'aaogaina. A e suia le toe iloiloga, e mafai e le mamanu ona fesuiaʻi auala transceiver ma fesuiaʻi le polarity e tusa ai ma le Bitec HDMI daughter card manaʻomia. Afai e te setiina le BITEC_DAUGHTER_CARD_REV parakalafa i le 0, o le mamanu e le faia ni suiga i le transceiver auala ma le polarity.
POLARITY_INVERSION	• 0: Faaliliuina polarity • 1: Aua le fesuia'i le polarity	Seti lenei ta'otoga i le 1 e fesuia'i ai le tau o vaega ta'itasi o fa'amatalaga fa'aoga. O le setiina o lenei parakalafa i le 1 e tuʻuina atu ai le 4'b1111 i le tx_polinv port o le TX transceiver.

2.12. Seti Meafaigaluega
Le HDMI FRL-fa'apena mamanu example HDMI 2.1 gafatia ma faia se faʻataʻitaʻiga faʻasolosolo mo se faʻataʻitaʻiga ata vitio HDMI.
Ina ia fa'atino le su'ega o meafaigaluega, fa'afeso'ota'i se masini e mafai ona fa'aogaina le HDMI—e pei o se kata fa'ata'ita'i fa'atasi ai ma le fa'aoga HDMI—i le fa'aoga HDMI. O le mamanu e lagolagoina uma HDMI 2.1 poʻo HDMI 2.0/1.4b puna ma goto.

1. O le su'ega HDMI e fa'aliliuina le uafu i totonu o se ata vitio masani ma auina atu i le uati toe fa'aleleia.
2. O le HDMI RX autu e fa'aliliuina le vitio, ausilali, ma fa'amatalaga fa'alogo e toe fa'atasi i tua i le HDMI TX autu e ala i le DCFIFO.
3. O le HDMI source port o le FMC daughter card e fa'asalalauina le ata i se mata'itu.

Fa'aaliga:
Afai e te manaʻo e faʻaoga se isi Intel FPGA atinaʻe laupapa, e tatau ona e suia le faʻaogaina o masini ma le pine. O le transceiver analog setting e tofotofoina mo le Intel Arria 10 FPGA development kit ma Bitec HDMI 2.1 daughter card. E mafai ona e suia tulaga mo lau lava laupapa.
Fuafuaga 24. Fa'amau Fa'amau i luga o le laupapa ma Galuega Fa'atino a le LED

Oomi Fa'amau/LED	Galuega
cpu_resetn	Oomi tasi e fai le setiina o le system.
user_dipsw	Su'e DIP fa'aogaina e le tagata fa'aoga e fa'asolo i le auala passthrough. • OFF (tulaga fa'aletonu) = Passthrough HDMI RX i luga o le FPGA e maua le EDID mai fafo ma tuʻuina atu i le puna i fafo o loʻo fesoʻotaʻi i ai. • ON = E mafai ona e pulea le maualuga o le RX FRL fua mai le Nios II terminal. O le poloaiga e suia le RX EDID e ala i le faʻaogaina o le maualuga o le tau o le FRL. Va'ai ile Fa'agaioiina o le Fuafuaga i Fua Faatatau FRL Eseese ile itulau 33 mo nisi fa'amatalaga e uiga i le fa'atulagaina o tau FRL eseese.
user_pb[0]	Oomi tasi e sui le faailo HPD i le puna masani HDMI.
user_pb[1]	Fa'apolopolo.
user_pb[2]	Oomi tasi e faitau tusi resitala a le SCDC mai le pusa e feso'ota'i ma le TX o le Bitec HDMI 2.1 FMC daughter card. Fa'aaliga: Ina ia mafai ona faitau, e tatau ona e seti DEBUG_MODE i le 1 i totonu o le polokalama.
USER_LED[0]	RX TMDS uati PLL loka loka. •0 = Tatala • 1 = Loka
USER_LED[1]	RX transceiver tulaga sauni. •0 = Le sauni • 1 = Sauni
USER_LED[2]	RX sootaga saoasaoa uati PLL, ma RX vitio ma FRL uati PLL tulaga loka. • 0 = Po'o se tasi o le uati RX PLL ua tatalaina • 1 = Ua loka uma PLL uati RX
USER_LED[3]	RX HDMI fa'aoga autu ma le tulaga loka kesi. • 0 = Le itiiti ifo ma le 1 alalaupapa ua tatalaina • 1 = Ua loka uma alavai
USER_LED[4]	RX HDMI tulaga loka vitio. • 0 = Tatala • 1 = Loka
USER_LED[5]	TX feso'ota'iga saosaoa uati PLL, ma TX vitio ma FRL uati PLL tulaga loka. •0 = Po'o se tasi o le TX uati PLL ua tatala • 1 = Ua loka uma PLL uati TX
USER_LED[6] USER_LED[7]	TX transceiver tulaga sauni. • 0 = Le sauni • 1 = Sauni Tulaga a'oa'oga feso'ota'i TX. • 0 = Le manuia • 1 = Ua pasi

2.13. Simulation Testbench
O le suʻega faʻataʻitaʻiga faʻataʻitaʻiga faʻataʻitaʻiga le HDMI TX faʻasologa faʻasolosolo i tua i le RX autu.
Fa'aaliga:
Ole su'ega fa'ata'ita'i lea e le'o lagolagoina mo fa'ata'ita'iga fa'atasi ai ma le Fa'aaofia I2C fa'ailoga ua mafai.
Ata 19. HDMI Intel FPGA IP Simulation Testbench Ata polokaLaulau 25. Vaega Su'esu'e

Vaega	Fa'amatalaga
Vitio TPG	O le vitiō su'ega mamanu mamanu (TPG) e maua ai le vitiō fa'aosofia.
Leo Sample Gen	O le leo sample generator maua leo sample stimulus. E fa'atupuina e le afi se fa'asologa fa'aopoopo o fa'amaumauga o su'ega e tu'uina atu i le alaleo leo.
Aux Sample Gen	O le aux sample generator e maua ai le ausilali sample stimulus. O le generator e fa'atupuina se fa'amaumauga tumau e tu'uina atu mai le transmitter.

CRC Siaki	E fa'amaonia e le siaki lenei pe a fetaui le TX transceiver toe maua mai le taimi ole uati ma le fua faatatau o fa'amatalaga mana'omia.
Siaki Fa'amatalaga Fa'alogo	O le su'ega o fa'amatalaga fa'alogo e fa'atusatusaina pe maua ma sa'o le fa'asologa o fa'amaumauga o su'ega.
Aux Fa'amatalaga Siaki	O le su'ega o fa'amatalaga aux e fa'atusatusaina pe maua le fa'amatalaga aux fa'amoemoeina ma fa'avasega sa'o i le itu e taliaina.

O le suʻega faʻataʻitaʻiga HDMI e faia suʻega faʻamaonia nei:

Vaega HDMI	Fa'amaoniga
Vitio fa'amaumauga	• O lo'o fa'atino e le su'ega su'esu'e le CRC i luga o le vitiō o lo'o tu'u mai ma fa'atino. • E siakiina le tau o le CRC o faʻamatalaga tuʻuina atu e faasaga i le CRC faʻatatau i faʻamatalaga vitio maua. • Ona fai lea e le su'ega su'ega pe a uma ona maua faailo V-SYNC mautu e 4 mai le tagata e taliaina.
Fa'amatalaga fesoasoani	• O le aux sample generator fa'atupuina se fa'amaumauga tumau e tu'uina atu mai le transmitter. • I le itu e taliaina, e fa'atusatusa e le afi pe o fa'amoemoeina fa'amatalaga fesoasoani e maua ma fa'avasega sa'o.
Fa'amatalaga leo	•O le leo sample generator e fa'atupuina se fa'asologa o fa'amaumauga o su'ega e tu'uina atu i le alaleo leo. • I le itu e talia ai, e siaki ma fa'atusatusa e le su'ega fa'alogo leo pe ua maua ma fa'avasega sa'o le fa'asologa o fa'amaumauga o su'ega.

O se fa'ata'ita'iga manuia e fa'ai'u i le fe'au lea:
# FA'AIGA_PER_UITI = 2
# VIC = 4
# FRL_RATE = 0
# BPP = 0
# FAO_FREQUENCY (kHz) = 48
# AUDIO_CHANNEL = 8
# Pasi fa'atusa
Laulau 26. HDMI Intel FPGA IP Design Example Simulators Lagolago

Simulator	Verilog HDL	VHDL
ModelSim – Intel FPGA Edition/ ModelSim – Intel FPGA Starter Edition	Ioe	Ioe
VCS/VCS MX	Ioe	Ioe
Riviera-PRO	Ioe	Ioe
Xcelium Fa'atasi	Ioe	Leai

2.14. Fuafuaga Tapulaa
E manaʻomia lou mafaufau i ni tapulaʻa pe a faʻapipiʻi le HDMI 2.1 design example.

• TX e le mafai ona fa'agaoioi i le TMDS mode pe'a e le-passthrough mode. Ina ia fa'ata'ita'i ile TMDS mode, sui le user_dipsw sui i tua ile passthrough mode.
• O le Nios II processor e tatau ona tautua le aʻoaʻoga fesoʻotaʻiga TX e maeʻa e aunoa ma se faʻalavelave mai isi faiga.

2.15. Debugging Features
O lenei mamanu example tu'uina atu nisi vaega fa'apipi'i e fesoasoani ia te oe.
2.15.1. Polokalama Debugging Savali
E mafai ona e kiina le fe'au fa'apolopolo i totonu o le polokalama e tu'uina atu ia te oe fesoasoani ta'avale.
Ina ia ki le savali debugging i le polokalama, mulimuli i laasaga nei:

1. Suia le DEBUG_MODE i le 1 i le global.h script.
2. Fa'asolo le script/build_sw.sh ile Nios II Command Shell.
3. Toe fa'apolokalame le polokalama fa'atupuina/tx_control/tx_control.elf file e ala i le faʻatonuina o le poloaiga ile Nios II Command Shell:
   nios2-download -r -g software/tx_control/tx_control.elf
4. Faʻatonu le faʻatonuga o le Nios II i luga o le Nios II Command Shell:
   nios2-terminal

A e kiina le feʻau faʻapipiʻi, o faʻamatalaga nei e lolomi:

• TI redriver seti i luga uma TX ma RX e faitau ma faʻaalia pe a uma le polokalame ELF file.
• Fe'au tulaga mo le RX EDID fa'atulagaina ma le fa'agasologa o le hotplug
• Fa'ai'uga fa'atasi ma pe leai fo'i fa'amatalaga lagolago a le FRL na maua mai i le EDID i luga ole fa'apa'u e feso'ota'i ile TX. O fa'amatalaga nei e fa'aalia mo so'o se TX hotplug.
• Fe'au tulaga mo le fa'agasologa o a'oa'oga feso'ota'iga TX a'o a'oa'oga feso'ota'iga TX.

2.15.2. Fa'amatalaga a le SCDC mai le Sink e Feso'ota'i ile TX
E mafai ona e fa'aogaina lea vaega e maua ai fa'amatalaga SCDC.

1. Fa'asolo le fa'atonuga fa'amauina o le Nios II i le Nios II Command Shell: nios2-terminal
2. Fa'asalalau le user_pb[2] ile Intel Arria 10 FPGA atina'e pusa.

E faitau ma fa'aalia e le polokalame le fa'amatalaga a le SCDC i luga o le pusa e feso'ota'i ma le TX i luga o le laina Nios II.
2.15.3. Fua Fa'atatau ole Uati
Fa'aoga le vaega lea e siaki ai le taimi mo uati eseese.

1. I le hdmi_rx_top ma le hdmi_tx_top files, aveese fa'amatalaga "/'fa'amatala DEBUG_EN 1".
2. Fa'aopoopo le fa'ailoga o le refclock_measure mai fa'ata'ita'iga ta'itasi mr_rate_detect i le Signal Tap Logic Analyzer e maua ai le taimi o le uati o uati ta'itasi (i le 10 ms le umi).
3. Tuufaatasia le mamanu ma le Signal Tap Logic Analyzer.
4. Polokalama le SOF file ma fa'agasolo le Signal Tap Logic Analyzer.

Laulau 27. Uati

Module	mr_rate_detect Fa'ata'ita'iga	Uati e Fua
hdmi_rx_top	rx_pll_tmds	RX CDR fa'asino uati 0
	rx_clk0_freq	RX transceiver uati i fafo mai le alalaupapa 0
	rx_vid_clk_freq	Uati vitio RX
	rx_frl_clk_freq	Uati RX FRL
	rx_hsync_freq	Hsync taimi ole ata vitio maua
hdmi_tx_top	tx_clk0_freq	TX transceiver uati i fafo mai le alalaupapa 0
	vid_clk_freq	TX uati vitio
	frl_clk_freq	TX FRL uati
	tx_hsync_freq	Hsync taimi ole ata vitio e lafo

2.16. Fa'aleleia lau Fa'ailoga
Laulau 28. HDMI Design Example Fegalegaleai ma le Intel Quartus Prime Pro Edition Software Version

Design Example Variant	Malosiaga e faʻaleleia i le Intel Quartus Prime Pro Edition 20.3
HDMI 2.1 Design Example ( Lagolago FRL = 1)	Leai

Mo so'o se mamanu e le fetaui fa'atasiample, e tatau ona e faia mea nei:

1. Fausia se mamanu fou example i le taimi nei Intel Quartus Prime Pro Edition polokalama faakomepiuta faʻaoga faʻaoga tutusa o lau mamanu o iai.
2. Faatusatusa le mamanu atoa example directory ma le mamanu exampna fa'atupuina i le fa'aaogaina o le polokalama muamua a le Intel Quartus Prime Pro Edition. Taulaga i luga o suiga na maua.

HDMI 2.0 Design Example ( Lagolago FRL = 0)

Le HDMI Intel FPGA IP mamanu exampO lo'o fa'aalia ai le tasi HDMI fa'ata'ita'iga fa'ata'ita'i fa'atusa fa'atasi e aofia ai laina RX e tolu ma laina TX e fa.
Laulau 29. HDMI Intel FPGA IP Design Example mo Intel Arria 10 Devices

Design Example	Fua Fa'amatalaga	Faiga Ala	Ituaiga Loopback
Arria 10 HDMI RX-TX Toe lafo	<6,000 Mbps	Simplex	Faʻatasi ma le FIFO paʻu

Vaega

• O le mamanu e vave faʻapipiʻi ai le FIFO paʻu e faʻatino saʻo HDMI vitio tafe i le va o le HDMI ma le puna.
  
• O le mamanu e fa'aogaina le tulaga o le LED mo le vave fa'apipi'iina stage.
• O le mamanu e sau ma RX ma TX na'o filifiliga.
• O le mamanu o loʻo faʻaalia ai le faʻaofiina ma le faamamaina o le Dynamic Range and Mastering (HDR) InfoFrame i le RX-TX link module.
• O le mamanu o loʻo faʻaalia ai le puleaina o le EDID passthrough mai le pito i fafo o le HDMI i se puna HDMI i fafo pe a faʻaosoina e se TX hot-plug event.
• O le mamanu e mafai ai ona faʻatonutonu le taʻavale e ala i le DIP switch ma le paʻu-tuomi e pulea ai faʻailoga autu HDMI TX:
  - faʻailoga faʻailoga e filifili ai le DVI poʻo le HDMI faʻailoga ata vitio
  — info_avi[47], info_vsi[61], ma leo_info_ai[48] faailoilo e filifili ai le felauaiga o pusa fesoasoani e ala i fusi i autafa po o uafu o faamatalaga fesoasoani.

O le RX faʻataʻitaʻiga e maua se punaoa vitio mai le gaosiga vitio fafo, ona alu lea o faʻamatalaga i se loopback FIFO aʻo leʻi tuʻuina atu i le TX instance.
E te manaʻomia le faʻafesoʻotaʻi o se suʻesuʻega vitio i fafo, mataʻituina, poʻo se televise e iai le fesoʻotaʻiga HDMI i le TX autu e faʻamaonia ai le gaioiga.
3.1. HDMI 2.0 RX-TX Retransmit Design Block Diagram
O le HDMI 2.0 RX-TX toe fa'asalalau le mamanu fa'atasiampO lo'o fa'aalia le fa'alava fa'atusa i luga o le auala faigofie mo HDMI Intel FPGA IP.
Ata 20. HDMI RX-TX Retransmit Block Diagram (Intel Quartus Prime Pro Edition)Ata 21. HDMI RX-TX Retransmit Block Diagram (Intel Quartus Prime Standard Edition)Fa'amatalaga Fa'atatau
Jitter of PLL Cascading or Non-Dedicated Clock Path for Arria 10 PLL Reference Clock Va'ai i lenei fofo mo le fofoina pe a fai o lau mamanu uati e fa'aopoopoina.
fa'anoanoa.
3.2. Meafaigaluega ma Polokalama Manaoga
E fa'aogaina e Intel meafaigaluega ma polokalama fa'akomepiuta nei e su'e ai le mamanu example.
Meafaigaluega

• Intel Arria 10 GX FPGA Atina'e Kit
• Punavai HDMI (Vaega Fa'ata'ita'iga Ata (GPU))
• Su'ega HDMI (Monitor)
• Bitec HDMI FMC 2.0 kata tama teine ​​(Fa'aaliga 11)
• Uaea HDMI

Fa'aaliga:
E mafai ona e filifilia le toe iloiloga o lau Bitec HDMI daughter card. Seti le parakalafa fa'apitonu'u BITEC_DAUGHTER_CARD_REV i le 4, 6, po'o le 11 ile pito i luga. file (a10_hdmi2_demo.v). A e suia le toe iloiloga, e mafai e le mamanu ona fesuiaʻi auala transceiver ma fesuiaʻi le polarity e tusa ai ma le Bitec HDMI daughter cardrequirements. Afai e te setiina le BITEC_DAUGHTER_CARD_REV parakalafa i le 0, o le mamanu e le faia ni suiga i le transceiver auala ma le polarity. Mo HDMI 2.1 mamanu examples, i lalo o le Design Example tab, seti le HDMI Daughter Card Revision i le Toefuataiga 9, Toe Iloiloga 4, poʻo le leai se tama teine. Ole tau fa'aletonu ole Toe Iloiloga 9.
Polokalama

• Intel Quartus Prime version 18.1 ma mulimuli ane (mo su'ega meafaigaluega)
• ModelSim – Intel FPGA Edition, ModelSim – Intel FPGA Starter Edition, , RivieraPRO, VCS (Verilog HDL na'o)/VCS MX, po'o le Xcelium Parallel simulator

3.3. Fa'atonuga Fa'atonu
O fa'atonuga o lo'o i ai mea na gaosia files mo le HDMI Intel FPGA IP mamanu example.
Ata 22. Fa'atonuga Fa'atonu mo le Design ExampleLaulau 30. Fausia RTL Files

Folders	Files
gxb	• /gxb_rx.qsys (Intel Quartus Prime Standard Edition) • /gxb_rx.ip (Intel Quartus Prime Pro Edition)
	• /gxb_rx_reset.qsys (Intel Quartus Prime Standard Edition) • /gxb_rx_reset.ip (Intel Quartus Prime Pro Edition)
	• /gxb_tx.qsys (Intel Quartus Prime Standard Edition) • /gxb_tx.ip (Intel Quartus Prime Pro Edition)
	• /gxb_tx_fpll.qsys (Intel Quartus Prime Standard Edition) • /gxb_tx_fpll.ip (Intel Quartus Prime Pro Edition)
	• /gxb_tx_reset.qsys (Intel Quartus Prime Standard Edition) • /gxb_tx_reset.ip (Intel Quartus Prime Pro Edition)
hdmi_rx	•/hdmi_rx.qsys (Intel Quartus Prime Standard Edition) •/hdmi_rx.ip (Intel Quartus Prime Pro Edition)
	/hdmi_rx_top.v
	/mr_clock_sync.v (Intel Quartus Prime Standard Edition)
	/mr_hdmi_rx_core_top.v (Intel Quartus Prime Standard Edition)
	/mr_rx_oversample.v (Intel Quartus Prime Standard Edition)
	/symbol_aligner.v
	Panasonic.hex (Intel Quartus Prime Pro Edition)
hdmi_tx	• /hdmi_tx.qsys (Intel Quartus Prime Standard Edition) •/hdmi_tx.ip (Intel Quartus Prime Pro Edition)

	/hdmi_tx_top.v
	/mr_ce.v (Intel Quartus Prime Standard Edition)
	/mr_hdmi_tx_core_top.v (Intel Quartus Prime Standard Edition)
	/mr_tx_oversample.v (Intel Quartus Prime Standard Edition)
i2c_master (Intel Quartus Prime Standard Edition)	/i2c_master_bit_ctrl.v
	/i2c_master_byte_ctrl.v
	/i2c_master_defines.v
	/i2c_master_top.v
	/oc_i2c_master.v
	/oc_i2c_master_hw.tcl
	/timescale.v
i2c_pologa	/edid_ram.qsys (Intel Quartus Prime Standard Edition)
	/Panasonic.hex (Intel Quartus Prime Standard Edition)
	/i2c_avl_mst_intf_gen.v
	/i2c_clk_cnt.v
	/i2c_condt_det.v
	/i2c_databuffer.v
	/i2c_rxshifter.v
	/i2c_slvfsm.v
	/i2c_spksupp.v
	/i2c_txout.v
	/i2c_txshifter.v
	/i2cslave_to_avlmm_bridge.v
pl	• /pll_hdmi.qsys (Intel Quartus Prime Standard Edition) • /pll_hdmi.ip (Intel Quartus Prime Pro Edition)
	• /pll_hdmi_reconfig.qsys (Intel Quartus Prime Standard Edition) • /pll_hdmi_reconfig.ip (Intel Quartus Prime Pro Edition)
	quartus.ini
masani	• /clock_control.qsys (Intel Quartus Prime Standard Edition) • /clock_control.ip (Intel Quartus Prime Pro Edition)
	• /fifo.qsys (Intel Quartus Prime Standard Edition) • /fifo.ip (Intel Quartus Prime Pro Edition)
	• /output_buf_i2c.qsys (Intel Quartus Prime Standard Edition) •/output_buf_i2c.ip (Intel Quartus Prime Pro Edition)
	/reset_controller.qsys (Intel Quartus Prime Standard Edition)
	/clock_crosser.v

	dcfifo_inst.v
	debouncer.sv (Intel Quartus Prime Pro Edition)
hdr	/altera_hdmi_aux_hdr.v
	/altera_hdmi_aux_snk.v
	/altera_hdmi_aux_src.v
	/altera_hdmi_hdr_infoframe.v
	/avalon_st_mutiplexer.qsys
reconfig_mgmt	/mr_compare_pll.v
	/mr_compare_rx.v
	/mr_rate_detect.v
	/mr_reconfig_master_pll.v
	/mr_reconfig_master_rx.v
	/mr_reconfig_mgmt.v
	/mr_rom_pll_dprioaddr.v
	/mr_rom_pll_valuemask_8bpc.v
	/mr_rom_pll_valuemask_10bpc.v
	/mr_rom_pll_valuemask_12bpc.v
	/mr_rom_pll_valuemask_16bpc.v
	/mr_rom_rx_dprioaddr_bitmask.v
	/mr_rom_rx_valuemask.v
	/mr_state_machine.v
sdc	/a10_hdmi2.sdc
	/mr_reconfig_mgmt.sdc
	/jtag.sdc
	/rxtx_link.sdc
	/mr_clock_sync.sdc (Intel Quartus Prime Standard Edition)

Fuafuaga 31. Fausia Fa'ata'ita'iga Files
Va'ai ile Simulation Testbench vaega mo nisi fa'amatalaga.

Folders	Files
aldec	/aldec.do
	/rivierapro_setup.tcl
fa'alogona	/cds.lib
	/hdl.var
	<cds_libs faila>

faufautua	/mentor.do
	/msim_setup.tcl
synopsys	/vcs/filelisi.f
	/vcs/vcs_setup.sh
	/vcs/vcs_sim.sh
	/vcsmx/vcsmx_setup.sh
	/vcsmx/vcsmx_sim.sh
	/vcsmx/synopsys_sim_setup
xcelium (Intel Quartus Prime Pro Edition)	/cds.lib
	/hdl.var
	/xcelium_setup.sh
	/xcelium_sim.sh
masani (Intel Quartus Prime Pro Edition)	/modelsim_files.tcl
	/riviera_files.tcl
	/vcs_files.tcl
	/vcsmx_files.tcl
	/xcelium_files.tcl
hdmi_rx	• /hdmi_rx.qsys (Intel Quartus Prime Standard Edition) • /hdmi_rx.ip (Intel Quartus Prime Pro Edition)
	/hdmi_rx.sopcinfo (Intel Quartus Prime Standard Edition)
	/Panasonic.hex (Intel Quartus Prime Pro Edition)
	/symbol_aligner.v (Intel Quartus Prime Pro Edition)
hdmi_tx	• /hdmi_tx.qsys (Intel Quartus Prime Standard Edition) • /hdmi_tx.ip (Intel Quartus Prime Pro Edition)
	/hdmi_tx.sopcinfo (Intel Quartus Prime Standard Edition)

Laulau 32. Polokalama Faia Files

Folders	Files
tx_control_src Fa'aaliga: O le faila tx_control o loʻo iai foʻi faʻalua o nei mea files.	/intel_fpga_i2c.c (Intel Quartus Prime Pro Edition)
	/intel_fpga_i2c.h (Intel Quartus Prime Pro Edition)
	/i2c.c (Intel Quartus Prime Standard Edition)
	/i2c.h (Intel Quartus Prime Standard Edition)
	/main.c
	/xcvr_gpll_rcfg.c /xcvr_gpll_rcfg.h /ti_i2c.c (Intel Quartus Prime Standard Edition) /ti_i2c.h (Intel Quartus Prime Standard Edition)

3.4. Fuafuaga Vaega
Le HDMI Intel FPGA IP mamanu exampLe manaʻomia o vaega nei.
Laulau 33. HDMI RX Vaega Maualuga

Module	Fa'amatalaga
HDMI RX Core	E maua e le IP le fa'asologa o fa'amaumauga mai le Transceiver Native PHY ma fa'atino le fa'aogaina o fa'amaumauga, kesi laina, decoding TMDS, fa'avasegaina o fa'amatalaga fesoasoani, fa'avasegaina o fa'amatalaga vitiō, fa'avasegaina o fa'amatalaga leo, ma fa'amatalaina.
I2	I2C o le faʻaoga faʻaoga mo le Sink Display Data Channel (DDC) ma le Tulaga ma Faʻamatalaga Faʻamatalaga (SCDC). O le puna HDMI e faʻaaogaina le DDC e fuafua ai le gafatia ma uiga o le goto e ala i le faitauina o le faʻatulagaina o faʻamatalaga Faʻamatalaga Faʻalautele Faʻalautele (E-EDID). • O tuatusi pologa I8C 2-bit mo E-EDID o le 0xA0 ma le 0xA1. O le LSB o loʻo faʻaalia ai le ituaiga avanoa: 1 mo le faitau ma le 0 mo le tusitusi. A tupu se mea HPD, e tali atu le pologa I2C i faʻamatalaga E-EDID e ala i le faitau mai le RAM i luga o le chip. • O le I2C pologa-na'o le pule e lagolagoina le SCDC mo le HDMI 2.0 gaioiga. Ole tuatusi pologa I8C 2-bit mo le SCDC ole 0xA8 ma le 0xA9. A tupu se mea HPD, e faia e le pologa I2C le tusitusi pe faitau fefaʻatauaiga i pe mai le SCDC interface o le HDMI RX core. Fa'aaliga: O lenei I2C pologa-naʻo le pule mo SCDC e le manaʻomia pe afai e le faʻamoemoeina le HDMI 2.0b. Afai e te ki le Fa'aaofia le I2C parakalafa, o lenei poloka o le a aofia i totonu o le totonugalemu ma o le a le mafai ona iloa i lenei tulaga.
EDID RAM	O le mamanu e teu ai faʻamatalaga EDID e faʻaaoga ai le RAM 1-port IP core. O se fa'ata'ita'iga e lua-uaea (uati ma fa'amaumauga) fa'asologa o pasi pasi (I2C pologa-na'o le pule) fa'afeiloa'i le fa'asologa o fa'amaumauga a le CEA-861-D E-EDID. O lenei EDID RAM e teuina faʻamatalaga E-EDID. Fa'aaliga: Afai e te ki le Fa'aaofia EDID RAM parakalafa, o lenei poloka o le a aofia i totonu o le totonugalemu ma o le a le mafai ona iloa i lenei tulaga.
IOPLL	O le IOPLL e fa'atupuina le uati fa'asinoga RX CDR, feso'ota'iga uati saoasaoa, ma le uati vitiō mo le uati TMDS sau. • Uati fa'atino 0 (CDR reference clock) • Uati fa'aoso 1 (So'oga uati saoasaoa) • Uati fa'atino 2 (Uati vitiō) Fa'aaliga: Ole fa'aogaina ole IOPLL e le aoga mo so'o se iugafono HDMI. O le IOPLL ua toe fa'atulagaina i tulaga talafeagai i luga o le eletise.
Transceiver PHY Toe Seti Pule	O le Transceiver PHY reset controller e fa'amautinoa le fa'amaoniaina o le fa'auluina o le RX transceivers. O le toe setiina o le faʻaogaina o lenei pule e faʻaosoina e le RX reconfiguration, ma faʻatupuina ai le analog ma numera toe setiina faailoilo i le Transceiver Native PHY poloka e tusa ai ma le toe setiina sequencing i totonu o le poloka.
RX Native PHY	Poloka transceiver malosi e maua ai faʻamaumauga faʻasologa mai se puna vitio fafo. E fa'aleaogaina fa'amaumauga fa'asologa i fa'amaumauga tutusa a'o le'i tu'uina atu fa'amaumauga i le HDMI RX autu.
RX Reconfiguration Pulega	RX reconfiguration pulega lea e fa'atinoina le fa'asologa o le su'esu'eina o fua fa'atasi ma le HDMI PLL e fa'aulu ai le RX transceiver e fa'agaioi i so'o se fua fa'atatau feso'ota'iga e amata mai i le 250 Mbps i le 6,000 Mbps. Va'ai le Ata 23 i le itulau 63 i lalo.

IOPLL Toe fetuunaiga

IOPLL reconfiguration poloka e faafaigofie ai le malosi o le toe fetuunaiga o PLL i le Intel FPGAs. O lenei poloka e faʻafouina le faʻasologa o le uati ma le PLL bandwidth i le taimi moni, e aunoa ma le toe faʻafouina o le FPGA atoa. O lenei poloka e tamoe i le 100 MHz i le Intel Arria 10 masini. Ona o le IOPLL reconfiguration tapulaʻa, faʻaaoga le Quartus INI permit_nf_pll_reconfig_out_of_lock=on i le taimi o le IOPLL reconfiguration IP generation. Ina ia fa'aoga le Quartus INI, ia aofia ai le "pemita_nf_pll_reconfig_out_of_lock=on" i le quartus.ini file ma tuu i totonu o le file le Intel Quartus Prime directory poloketi. E tatau ona e vaʻai i se faʻamatalaga lapatai pe a e faʻasaʻo le IOPLL reconfiguration poloka (pll_hdmi_reconfig) i le Quartus Prime software ma le INI. Fa'aaliga: A aunoa ma lenei Quartus INI, e le mafai ona maeʻa le toe faʻaleleia o le IOPLL pe a leiloa le loka a le IOPLL i le taimi o le toe faʻatulagaina.

PIO

O le poloka fa'aoga tutusa / fa'aulu (PIO) e galue e pei o le pulea, tulaga ma toe setiina feso'ota'iga i po'o mai le CPU sub-system.

Ata 23. Fa'asologa o Fa'asologa Fa'asologa Fa'atele
O le ata o loʻo faʻaalia ai le tele-rate reconfiguration sequence faʻasologa o le pule pe a maua faʻamatalaga faʻamatalaga ma faʻasino taimi masani, poʻo le taimi e tatala ai le transceiver.Laulau 34. HDMI TX Vaega Maualuga

Module	Fa'amatalaga
HDMI TX Core	O le IP autu e mauaina faʻamatalaga vitio mai le pito i luga ma faʻatino le TMDS encoding, auxiliary data encoding, audio data encoding, video data encoding, ma scrambling.
I2C Matai	I2C o le faʻaoga faʻaoga mo le Sink Display Data Channel (DDC) ma le Tulaga ma Faʻamatalaga Faʻamatalaga (SCDC). O le puna HDMI e faʻaaogaina le DDC e fuafua ai le gafatia ma uiga o le goto e ala i le faitauina o le faʻatulagaina o faʻamatalaga Faʻamatalaga Faʻalautele Faʻalautele (E-EDID). • I le avea ai o le DDC, I2C Master e faitau le EDID mai le suauʻu fafo e faʻapipiʻi ai faʻamatalaga EDID EDID RAM i le HDMI RX Top poʻo mo le gaioiga vitio. • I le avea ai ma SCDC, faʻafeiloaʻi e le matai I2C le fausaga o faʻamaumauga a le SCDC mai le puna FPGA i le pusa i fafo mo le faʻaogaina o le HDMI 2.0b. Mo example, afai o le tafe o faamatalaga e sili atu i le 3,400 Mbps, o le Nios II processor faatonuina le matai I2C e faafou le TMDS_BIT_CLOCK_RATIO ma SCRAMBLER_ENABLE fasi o le faatanoa SCDC resitara faatulagaga i le 1.
IOPLL	O le IOPLL e tu'uina atu le feso'ota'iga saosaoa uati ma vitiō uati mai le TMDS uati o'o mai. • Uati fa'aoso 1 (So'oga uati saoasaoa) • Uati fa'atino 2 (Uati vitiō) Fa'aaliga: Ole fa'aogaina ole IOPLL e le aoga mo so'o se iugafono HDMI. O le IOPLL ua toe fa'atulagaina i tulaga talafeagai i luga o le eletise.
Transceiver PHY Toe Seti Pule	O le Transceiver PHY reset controller e fa'amautinoaina le fa'amautuina o le amataga o le TX transceivers. O le toe setiina o le faʻaogaina o lenei pule e faʻaosoina mai le pito i luga, ma faʻatupuina ai le faʻasologa o le analog ma le numera numera i le Transceiver Native PHY poloka e tusa ai ma le toe setiina o le faʻasologa i totonu o le poloka. O le tx_ready output signal mai lenei poloka e galue foi o se toe setiina faailoilo i le HDMI Intel FPGA IP e faʻaalia ai le transceiver o loʻo i luga ma tamoʻe, ma sauni e maua faʻamatalaga mai le autu.
Transceiver Native PHY	Poloka transceiver malosi e maua ai faʻamatalaga tutusa mai le HDMI TX autu ma faʻasalalau faʻamaumauga mai le lafoina. E mafai ona toe fetuutuuna'i le feso'ota'iga i le poloka TX Native PHY e fa'aalia ai le feso'ota'iga i le va o le TX Native PHY ma le transceiver arbiter. Leai se toe fetuutuunaiga e faia mo TX Native PHY. Fa'aaliga: Ina ia ausia le HDMI TX inter-channel skew manaʻomia, seti le TX channel bonding mode filifiliga i le Intel Arria 10 Transceiver Native PHY editor parameter i PMA ma PCS so'oga. E te manaʻomia foʻi le faʻaopoopoina o le maualuga o le skew (set_max_skew) faʻatapulaʻaina manaʻoga i le numera toe setiina faailo mai le transceiver reset controller (tx_digitalreset) e pei ona fautuaina i le Intel Arria 10 Transceiver PHY User Guide.
TX PLL	O le poloka PLL transmitter e maua ai le faasologa vave o le uati i le Transceiver Native PHY poloka. Mo lenei HDMI Intel FPGA IP mamanu example, fPLL o loʻo faʻaaogaina e pei o TX PLL.
IOPLL Toe fetuunaiga	IOPLL reconfiguration poloka e faafaigofie ai le malosi o le toe fetuunaiga o PLL i le Intel FPGAs. O lenei poloka e faʻafouina le faʻasologa o le uati ma le PLL bandwidth i le taimi moni, e aunoa ma le toe faʻafouina o le FPGA atoa. O lenei poloka e tamoe i le 100 MHz i le Intel Arria 10 masini. Ona o le IOPLL reconfiguration tapulaʻa, faʻaaoga le Quartus INI permit_nf_pll_reconfig_out_of_lock=on i le taimi o le IOPLL reconfiguration IP generation. Ina ia fa'aoga le Quartus INI, ia aofia ai le "pemita_nf_pll_reconfig_out_of_lock=on" i le quartus.ini file ma tuu i totonu o le file le Intel Quartus Prime directory poloketi. E tatau ona e vaʻai i se faʻamatalaga lapatai pe a e faʻasaʻo le IOPLL reconfiguration poloka (pll_hdmi_reconfig) i le Intel Quartus Prime software ma le INI. Fa'aaliga: A aunoa ma lenei Quartus INI, e le mafai ona maeʻa le toe faʻaleleia o le IOPLL pe a leiloa le loka a le IOPLL i le taimi o le toe faʻatulagaina.
PIO	O le poloka fa'aoga tutusa / fa'aulu (PIO) e galue e pei o le pulea, tulaga ma toe setiina feso'ota'iga i po'o mai le CPU sub-system.

Fuafuaga 35. Transceiver Fa'amatalaga Fua Faatatau ma Ovaampling Factor mo Ta'itasi TMDS Uati Va'aiga Va'aiga

TMDS Uati Taimi (MHz)	TMDS Bit Clock Ratio	oversampling Factor	Fua Fa'amatalaga Fa'amatalaga (Mbps)
85–150	1	E le agavaa ai	3400–6000
100–340	0	E le agavaa ai	1000–3400
50–100	0	5	2500–5000
35–50	0	3	1050–1500
30–35	0	4	1200–1400
25–30	0	5	1250–1500

Fuafuaga 36. Tulaga Maualuga Poloka masani

Module

Fa'amatalaga

Transceiver Arbiter

O lenei poloka fa'aoga lautele e taofia ai le transceivers mai le toe fa'avasegaina i le taimi e tasi pe a mana'omia e le RX po'o le TX transceivers i totonu o le laina fa'aletino lava e tasi le toe fa'atulagaina. O le toe fa'aleleia fa'atasi e a'afia ai talosaga pe a tu'uina atu RX ma TX transceivers i totonu o le ala tutusa i fa'atinoga IP tuto'atasi. O lenei transceiver arbiter o se faʻaopoopoga i le iugafono fautuaina mo le tuʻufaʻatasia o le simplex TX ma le simplex RX i le auala faʻaletino tutusa. O lenei transceiver arbiter e fesoasoani foi i le tuʻufaʻatasia ma le faʻatalanoaina ole Avalon-MM RX ma le TX reconfiguration talosaga e tulimataʻi simplex RX ma TX transceivers i totonu o se alalaupapa ona o le toe fetuutuunaiga tau fesoʻotaʻiga o le transceivers e mafai ona maua sequentially. Le feso'ota'iga feso'ota'iga i le va o le transceiver arbiter ma TX/RX Native PHY/PHY Reset Pule poloka poloka i lenei mamanu example fa'aalia se faiga lautele e fa'aoga mo so'o se fa'atasiga IP e fa'aaoga ai le transceiver arbiter. E le mana'omia le transceiver arbiter pe a na'o le RX po'o le TX transceiver e fa'aaogaina i se alalaupapa. O le transceiver arbiter e faailoa ai le tagata talosaga mo se toe fetuunaiga e ala i ona Avalon-MM reconfiguration interfaces ma faamautinoa o le tx_reconfig_cal_busy po o le rx_reconfig_cal_busy e fetaui ma ua faitotoa e tusa ai. Mo le fa'aoga HDMI, na'o le RX na te amataina le toe fa'atulagaina. E ala i le faʻasalalauina o le Avalon-MM reconfiguration talosaga e ala i le arbiter, o le arbiter faailoa mai o le reconfiguration talosaga e afua mai i le RX, lea ona faitotoa tx_reconfig_cal_busy mai le faʻamaonia ma faʻatagaina rx_reconfig_cal_busy e faʻamaonia. O le gating e taofia ai le TX transceiver mai le siitia atu i le calibration mode ma le le iloa.

	Fa'aaliga: Ona o le HDMI na'o le mana'omia o le RX reconfiguration, o le tx_reconfig_mgmt_* faailoilo ua nonoa. E le gata i lea, o le Avalon-MM interface e le manaʻomia i le va o le arbiter ma le TX Native PHY poloka. O poloka o loʻo tuʻuina atu i le atinaʻe i le mamanu exampe fa'aalia le feso'ota'iga lautele transceiver arbiter i le TX/RX Native PHY/PHY Reset Pule.
RX-TX So'oga	• O fa'amatalaga fa'amatalaga vitio ma fa'ailoilo fa'amaopoopo mai le HDMI RX fa'aoga autu e ala i le DCFIFO i luga o le RX ma le TX uati vitio domains. • O le General Control Packet (GCP), InfoFrames (AVI, VSI ma AI), ausilali faʻamatalaga, ma faʻamatalaga faʻalogo leo e ala i DCFIFO i luga o le RX ma le TX soʻotaga saosaoa uati domains. • O le auxiliary data port o le HDMI TX core e pulea ai faʻamatalaga fesoasoani e tafe atu i le DCFIFO e ala i le backpressure. E fa'amautinoaina e le backpressure e leai se pepa fesoasoani e le'i atoatoa i luga o le auxiliary data port. • O lenei poloka e fa'atino ai fo'i le fa'amama i fafo: — Fa'amama fa'amatalaga fa'alogo ma le pusa fa'afouina uati fa'alogo mai le fa'amaumauga fesoasoani a'o le'i tu'uina atu i le tau feso'ota'iga feso'ota'iga HDMI TX. Fa'aaliga: Ina ia fa'agata lenei fa'amama, lolomi le user_pb[2]. Fa'aaga lea fa'amama ina ia mautinoa e leai se fa'aluaina o fa'amaumauga fa'alogo ma le pusa fa'afouina uati leo i totonu o le fa'aliliuga o fa'amaumauga fesoasoani. - Fa'amama le High Dynamic Range (HDR) InfoFrame mai le HDMI RX ausilali fa'amaumauga ma fa'aofi se example HDR InfoFrame i faʻamatalaga ausilali a le HDMI TX e ala i le Avalon ST multiplexer.
PPU So'ofa'aiga	O le CPU sub-system e galue e pei o le SCDC ma le DDC controllers, ma le source reconfiguration controller. • O le source SCDC controller o lo'o iai le I2C master controller. O le pule sili I2C e faʻafeiloaʻi le fausaga o faʻamaumauga a le SCDC mai le puna FPGA i le pusa i fafo mo le faʻaogaina o le HDMI 2.0b. Mo example, afai o le tafega o faamatalaga o le 6,000 Mbps, o le Nios II processor faatonuina le pule sili I2C e faafou le TMDS_BIT_CLOCK_RATIO ma SCRAMBLER_ENABLE fasi o le faatanoa TMDS faatulagaga resitala i le 1. • O le matai I2C lava lea e tasi e faʻafeiloaʻi foʻi le fausaga o faʻamaumauga DDC (E-EDID) i le va o le puna HDMI ma le goto fafo. • O le Nios II CPU o loʻo galue e pei o le faʻatonuina o le faʻatonuga mo le puna HDMI. O le PPU e faʻalagolago i le suʻesuʻeina o fua o taimi mai le RX Reconfiguration Management module e fuafua ai pe manaʻomia e le TX le toe faʻaleleia. O le fa'aliliuga pologa Avalon-MM e maua ai le feso'ota'iga i le va o le Nios II processor Avalon-MM matai atina'e ma le Avalon-MM pologa feso'ota'iga o le IOPLL ma le TX Native PHY puna HDMI fa'apitoa. • O le fa'asologa o le fa'asologa mo le TX e tutusa ma le RX, vagana ai o le PLL ma le transceiver reconfiguration ma le toe setiina fa'asologa e faia fa'asolosolo. Va'ai le Ata 24 i le itulau e 67.

Ata 24. Toe Fa'atonu Fa'asologa Fa'asologa
O le ata o loʻo faʻaalia ai le faʻaogaina o polokalama faakomepiuta Nios II e aofia ai faʻatonuga mo le I2C master ma le HDMI puna.3.5. Fa'amatalaga Fa'amatalaga Fa'aofiina ma le Fa'asiliina o Fa'amatalaga Fa'amatalaga Fa'amatalaga Fa'amatalaga Fa'atonu ma le Matai (HDR).
Le HDMI Intel FPGA IP mamanu exampe aofia ai se faʻataʻitaʻiga o le faʻaofiina o le HDR InfoFrame i totonu o le RX-TX loopback system.
HDMI Specification version 2.0b fa'atagaina Dynamic Range ma Mastering InfoFrame e tu'uina atu ile HDMI ausilali vaitafe. I le faʻataʻitaʻiga, o le Auxiliary Data Insertion poloka e lagolagoina le faʻaofiina HDR. E te manaʻomia naʻo le faʻatulagaina o le HDR InfoFrame faʻamoemoe e pei ona faʻamaonia i le laulau lisi faʻailoga a le module ma faʻaoga le AUX Insertion Control module e faʻatulaga ai le faʻaofiina o le HDR InfoFrame i le tasi taimi i ata vitio uma.
I lenei example fa'atulagaina, i taimi ua uma ona aofia ai i totonu o le ausilali fesoasoani le HDR InfoFrame, ua fa'amama le anotusi HDR. O le faʻamama e aloese mai feteʻenaʻiga HDR InfoFrames e tuʻuina atu ma faʻamautinoa e naʻo tau faʻamaonia i le HDR Sample Fa'aoga module Fa'amaumauga.
Ata 25. RX-TX So'oga ma le Dynamic Range ma le Mastering InfoFrame Insertion
O le ata o loʻo faʻaalia ai le poloka poloka o le RX-TX soʻotaga e aofia ai le Dynamic Range ma le Mastering InfoFrame faʻaofiina i totonu o le HDMI TX core auxiliary stream.
Laulau 37. Poloka Fa'aofiina Fa'amatalaga Fesoasoani (altera_hdmi_aux_hdr) Fa'ailoga

Fa'ailoga	Fa'atonuga	Lautele	Fa'amatalaga
Uati ma Toe Seti
clk	Ulufale	1	Fa'aoga uati. O lenei uati e tatau ona faʻafesoʻotaʻi i le fesoʻotaʻiga saosaoa uati.
toe setiina	Ulufale	1	Toe setiina mea e fai.

Auxiliary Packet Generator ma Multiplexer Signals
multiplexer_out_data	Tuuina atu	72	Avalon fa'asolo atu mea e maua mai le multiplexer.
multiplexer_out_valid	Tuuina atu	1
multiplexer_out_ready	Tuuina atu	1
multiplexer_out_startofpacket	Tuuina atu	1
multiplexer_out_endofpacket	Tuuina atu	1
multiplexer_out_channel	Tuuina atu	11
multiplexer_in_data	Ulufale	72	Avalon fa'aulu i totonu o le In1 uafu o le multiplexer. HDMI TX Vitio Vsync. E tatau ona fa'amaopoopo lea fa'ailoga i le vaega o le uati saosaoa feso'ota'iga. O le autu e faʻapipiʻi le HDR InfoFrame i le vaitafe fesoasoani i le pito i luga o lenei faailo.
multiplexer_in_valid	Ulufale	1
multiplexer_in_ready	Ulufale	1
multiplexer_in_startofpacket	Ulufale	1
multiplexer_in_endofpacket hdmi_tx_vsync	Ulufale Ulufale	1 1

Laulau 38. HDR Fa'amatalaga Module (altera_hdmi_hdr_infoframe) Fa'ailoga

Fa'ailoga	Fa'atonuga	Lautele	Fa'amatalaga
hb0	Tuuina atu	8	Ulutala byte 0 o le Dynamic Range ma le Mastering InfoFrame: InfoFrame type code.
hb1	Tuuina atu	8	Ulutala byte 1 o le Dynamic Range ma le Mastering InfoFrame: InfoFrame version number.
hb2	Tuuina atu	8	Ulutala byte 2 o le Dynamic Range ma le Mastering InfoFrame: Umi o InfoFrame.
pb	Ulufale	224	Fa'amatalaga byte o le Dynamic Range ma le Mastering InfoFrame.

Fuafuaga 39. Va'aiga Fa'aola ma le Fa'ata'ita'iina o InfoFrame Data Byte Bundle Bit-Fields

Bit-Field	Uiga	Ituaiga Metadata Tulaga 1
7:0	Fa'amatalaga Byte 1: {5'h0, EOTF[2:0]}
15:8	Fa'amatalaga Byte 2: {5'h0, Static_Metadata_Descriptor_ID[2:0]}
23:16	Fa'amatalaga Fa'amatalaga 3: Static_Metadata_Descriptor	display_primaries_x[0], LSB
31:24	Fa'amatalaga Fa'amatalaga 4: Static_Metadata_Descriptor	display_primaries_x[0], MSB
39:32	Fa'amatalaga Fa'amatalaga 5: Static_Metadata_Descriptor	display_primaries_y[0], LSB
47:40	Fa'amatalaga Fa'amatalaga 6: Static_Metadata_Descriptor	display_primaries_y[0], MSB
55:48	Fa'amatalaga Fa'amatalaga 7: Static_Metadata_Descriptor	display_primaries_x[1], LSB
63:56	Fa'amatalaga Fa'amatalaga 8: Static_Metadata_Descriptor	display_primaries_x[1], MSB
71:64	Fa'amatalaga Fa'amatalaga 9: Static_Metadata_Descriptor	display_primaries_y[1], LSB
79:72	Fa'amatalaga Fa'amatalaga 10: Static_Metadata_Descriptor	display_primaries_y[1], MSB
87:80	Fa'amatalaga Fa'amatalaga 11: Static_Metadata_Descriptor	display_primaries_x[2], LSB
95:88	Fa'amatalaga Fa'amatalaga 12: Static_Metadata_Descriptor	display_primaries_x[2], MSB
103:96	Fa'amatalaga Fa'amatalaga 13: Static_Metadata_Descriptor	display_primaries_y[2], LSB
111:104	Fa'amatalaga Fa'amatalaga 14: Static_Metadata_Descriptor	display_primaries_y[2], MSB
119:112	Fa'amatalaga Fa'amatalaga 15: Static_Metadata_Descriptor	white_point_x, LSB
127:120	Fa'amatalaga Fa'amatalaga 16: Static_Metadata_Descriptor	white_point_x, MSB
135:128	Fa'amatalaga Fa'amatalaga 17: Static_Metadata_Descriptor	white_point_y, LSB

143:136	Fa'amatalaga Fa'amatalaga 18: Static_Metadata_Descriptor	white_point_y, MSB
151:144	Fa'amatalaga Fa'amatalaga 19: Static_Metadata_Descriptor	max_display_mastering_luminance, LSB
159:152	Fa'amatalaga Fa'amatalaga 20: Static_Metadata_Descriptor	max_display_mastering_luminance, MSB
167:160	Fa'amatalaga Fa'amatalaga 21: Static_Metadata_Descriptor	min_display_mastering_luminance, LSB
175:168	Fa'amatalaga Fa'amatalaga 22: Static_Metadata_Descriptor	min_display_mastering_luminance, MSB
183:176	Fa'amatalaga Fa'amatalaga 23: Static_Metadata_Descriptor	Tulaga Maualuga Maualuga Malamalama, LSB
191:184	Fa'amatalaga Fa'amatalaga 24: Static_Metadata_Descriptor	Tulaga Maualuga Maualuga Malamalama, MSB
199:192	Fa'amatalaga Fa'amatalaga 25: Static_Metadata_Descriptor	Tulaga maualuga o le Fa'avaa-vave Malamalama, LSB
207:200	Fa'amatalaga Fa'amatalaga 26: Static_Metadata_Descriptor	Tulaga maualuga o le Fa'avaa-vave Malamalama, MSB
215:208	Fa'apolopolo
223:216	Fa'apolopolo

Fa'agata le fa'aofiina o le HDR ma le fa'amamaina
O le faʻagataina o le faʻaofiina o le HDR ma le faamama e mafai ai ona e faʻamaonia le toe faʻaliliuina o mea HDR ua uma ona maua i le punavai fesoasoani e aunoa ma se suiga i le RX-TX Retransmit design ex.ample.
Ina ia fa'amalo le fa'aofiina ma le fa'amamāina o le HDR InfoFrame:

1. Seti block_ext_hdr_infoframe i le 1'b0 ile rxtx_link.v file e taofia ai le faamamaina o le HDR InfoFrame mai le vaitafe Auxiliary.
2. Set multiplexer_in0_valid o le avalon_st_multiplexer instance i le altera_hdmi_aux_hdr.v file i le 1'b0 e taofia ai le Auxiliary Packet Generator mai le faia ma faʻapipiʻi faaopoopo HDR InfoFrame i totonu o le TX Auxiliary stream.
   

3.6. Fuafuaga uati
O lo'o fa'ailoa mai e le fa'ailoga uati le vaega o le uati i le HDMI Intel FPGA IP design example.
Ata 26. HDMI Intel FPGA IP Design Example Fuafuaga uati (Intel Quartus Prime Pro Edition)Ata 27. HDMI Intel FPGA IP Design Example Fuafuaga Fa'ailoga (Intel Quartus Prime Standard Edition)Laulau 40. Fa'ailoga Fa'ailoga Fa'ailoga

Uati	Igoa Faailoga i le Design	Fa'amatalaga
TX IOPLL/TX PLL Fa'asinoala Uati 1	hdmi_clk_in	Fa'asino le uati ile TX IOPLL ma le TX PLL. Ole taimi ole uati e tutusa ma le fa'amoemoe ole uati ole TMDS mai le HDMI TX TMDS uati alaala. Mo lenei HDMI Intel FPGA IP mamanu example, o lenei uati e fesoʻotaʻi i le RX TMDS uati mo faʻamoemoega faʻataʻitaʻiga. I lau talosaga, e te mana'omia le tu'uina atu o se uati tu'ufa'atasi ma le TMDS uati taimi mai se oscillator e mafai ona fa'apolokalameina mo le sili atu o le fa'atinoga o le jitter. Fa'aaliga: Aua le fa'aogaina se pine RX fa'aliliu e fai ma uati fa'asinoga TX PLL. O lau mamanu o le a le fetaui pe afai e te tuʻuina le HDMI TX refclk i luga o se pine RX.
TX Transceiver Uati I fafo	tx_clk	Uati i fafo toe maua mai le transceiver, ma o le taimi e eseese e faalagolago i le fua faatatau o faamatalaga ma faailoga i le uati. TX transceiver uati i fafo taimi = Transceiver fua faatatau / (Fa'ailoga i le uati*10)
TX PLL Uati Fa'asologa	tx_bonding_ccks	Uati vave fa'asologa fa'atupu e TX PLL. Ole taimi ole uati e fa'atatau ile fua ole fa'amaumauga.
TX/RX Link Speed ​​Clock	ls_clk	So'oga uati saoasaoa. Ole feso'ota'iga ole saoasaoa ole uati e fa'alagolago ile fa'amoemoe ole uati ole TMDS, ovaampling factor, faailoga i le uati, ma le TMDS bit clock ratio.

		TMDS Bit Clock Ratio	Feso'ota'i Saosaoa Uati Fa'atele
		0	TMDS taimi ole uati/ Fa'ailoga ile uati
		1	TMDS taimi ole uati *4 / Fa'ailoga ile uati
TX/RX Uati Vitio	vid_clk	Uati fa'amatalaga vitiō. Ole taimi ole uati ole fa'amaumauga ole vitio e maua mai ile TX link speed clock e fa'atatau ile loloto ole lanu.
		TMDS Bit Clock Ratio	Vitio Fa'amatalaga Uati Fa'atele
		0	Uati TMDS/ Fa'ailoga i le uati/ Fa'ailoga loloto o lanu
		1	Uati TMDS *4 / Fa'ailoga i le uati/ Fa'ailoga loloto o lanu
		Bits i Lanu	Lanu loloto Fa'ailoga
		8	1
		10	1.25
		12	1.5
		16	2.0
Uati RX TMDS	tmds_clk_in	TMDS uati alaala mai le HDMI RX ma fesootai i le uati faasinomaga i le IOPLL.
RX CDR Fa'asinoala Uati 0 /TX PLL Fa'asinoala Uati 0	fr_clk	Uati fa'asinoga fua ile RX CDR ma le TX PLL. O lenei uati e manaʻomia mo le faʻaogaina o le eletise.
RX CDR Fa'asino Uati 1	iopll_outclk0	Fa'asino le uati ile RX CDR ole RX transceiver.
		Fua Fa'amatalaga	RX Reference Clock Frequency
		Fa'amatalaga <1 Gbps	5× TMDS uati taimi
		1 Gbps< Fa'amaumauga <3.4 Gbps	TMDS taimi ole uati
		Fua o fa'amaumauga >3.4 Gbps	4× TMDS uati taimi
		• Fua Fa'amatalaga <1 Gbps: Mo ovaampling e fa'amalieina le transceiver aupito maualalo le mana'omia o fua faatatau o fa'amaumauga. • Fa'amatalaga Fa'amatalaga>3.4 Gbps: E fa'ataui ai le TMDS bit rate i le fua faatatau o le uati o le 1/40 e fa'amautu ai le transceiver fa'amatalaga fa'amatalaga i le fua faatatau o le uati i le 1/10. Fa'aaliga: Aua le fa'aogaina se pine RX fa'aliliu e fai ma uati fa'asino CDR. O lau mamanu o le a le fetaui pe afai e te tuʻuina le HDMI RX refclk i luga o se pine RX.
RX Transceiver Uati I fafo	rx_clk	Uati i fafo toe maua mai le transceiver, ma o le taimi e eseese e faalagolago i le fua faatatau o faamatalaga ma faailoga i le uati. RX transceiver uati i fafo taimi = Transceiver fua faatatau / (Fa'ailoga i le uati*10)
Pulega Uati	mgmt_clk	Se uati 100 MHz e leai se totogi mo vaega nei:

		• Avalon-MM feso'ota'iga mo le toe fa'atulagaina - Ole taimi ole fa'aogaina ole va ole 100–125 MHz. •, PHY toe setiina pule mo transceiver toe seti faasologa - Ole fa'asologa ole taimi ole mana'omia ile va ole 1–500 MHz. • IOPLL Toe fetuunaiga - Ole maualuga ole taimi ole uati ole 100 MHz. • RX Reconfiguration mo pulega • PPU • I2C Matai
Uati I2C	i2c_clk	O le 100 MHz fa'aoga uati e loka ai le pologa I2C, SCDC resitala i le HDMI RX autu, ma EDID RAM.

Fa'amatalaga Fa'atatau

• Fa'aaoga le Transceiver RX Pin e fai ma CDR Reference Clock
• Fa'aaogaina o le Transceiver RX Pin e pei ole TX PLL Reference Clock

3.7. Fa'ailoga Fa'afeso'ota'i
O laulau o loʻo lisiina ai faʻailoga mo le HDMI Intel FPGA IP design example.
Laulau 41. Fa'ailoga Tulaga Maualuga

Fa'ailoga	Fa'atonuga	Lautele	Fa'amatalaga
Fa'ailoga ole Oscillator i luga ole laupapa
clk_fpga_b3_p	Ulufale	1	100 MHz uati tamo'e fua mo le uati faasinomaga autu
REFCLK_FMCB_P (Intel Quartus Prime Pro Edition)	Ulufale	1	625 MHz uati tamo'e fua mo transceiver faasinoupu uati; o lenei uati e mafai ona i soo se taimi

Fa'aoga Push Buttons ma LED
user_pb	Ulufale	1	Oomi le ki e pulea ai le HDMI Intel FPGA IP design functionality
cpu_resetn	Ulufale	1	Toe fa'alelalolagi
user_led_g	Tuuina atu	4	Fa'aaliga LED lanu meamata Va'ai ile Seti Meafaigaluega i le itulau 89 mo nisi fa'amatalaga e uiga ile fa'aogaina ole LED.
user_led_r	Tuuina atu	4	Fa'aaliga LED mumu Va'ai ile Seti Meafaigaluega i le itulau 89 mo nisi fa'amatalaga e uiga ile fa'aogaina ole LED.

HDMI FMC Daughter Card Pins ile FMC Port B
fmcb_gbtclk_m2c_p_0	Ulufale	1	Uati HDMI RX TMDS
fmcb_dp_m2c_p	Ulufale	3	HDMI RX mūmū, lanu meamata, ma le lanumoana alavai fa'amatalaga • Su'esu'ega pepa tama teine ​​Bitec 11 — [0]: RX TMDS Alaala 1 (Munumea) — [1]: RX TMDS Alaala 2 (Mula) — [2]: RX TMDS Alaala 0 (Laumanu) • Su'ega 4 po'o le 6 pepa tama teine ​​Bitec — [0]: RX TMDS Alaala 1 (Green)— polarity liliu — [1]: RX TMDS Channel 0 (Blue)— polarity liliu — [2]: RX TMDS Alaala 2 (Mula)— polarity liliu
fmcb_dp_c2m_p	Tuuina atu	4	HDMI TX uati, mumu, lanu meamata, ma le lanumoana alavai faʻamatalaga • Su'esu'ega pepa tama teine ​​Bitec 11 — [0]: TX TMDS Alaala 2 (Mula) — [1]: TX TMDS Alaala 1 (Munumea) — [2]: TX TMDS Alaala 0 (Laumanu) — [3]: Alaala Uati TX TMDS • Su'ega 4 po'o le 6 pepa tama teine ​​Bitec — [0]: Alaala Uati TX TMDS — [1]: TX TMDS Alaala 0 (Laumanu) — [2]: TX TMDS Alaala 1 (Munumea) — [3]: TX TMDS Alaala 2 (Mula)
fmcb_la_rx_p_9	Ulufale	1	HDMI RX +5V mana iloa
fmcb_la_rx_p_8	I fafo	1	HDMI RX so'o vevela iloa
fmcb_la_rx_n_8	I fafo	1	HDMI RX I2C SDA mo DDC ma SCDC
fmcb_la_tx_p_10	Ulufale	1	HDMI RX I2C SCL mo DDC ma SCDC
fmcb_la_tx_p_12	Ulufale	1	HDMI TX pa'u vevela iloa
fmcb_la_tx_n_12	I fafo	1	HDMI I2C SDA mo DDC ma SCDC
fmcb_la_rx_p_10	I fafo	1	HDMI I2C SCL mo DDC ma SCDC
fmcb_la_tx_p_11	I fafo	1	HDMI I2C SDA mo redriver pulea
fmcb_la_rx_n_9	I fafo	1	HDMI I2C SCL mo le puleaina o le redriver

Laulau 42. HDMI RX Fa'ailoga Tulaga Maualuga

Fa'ailoga	Fa'atonuga	Lautele	Fa'amatalaga
Uati ma Toe Seti Faailoga
mgmt_clk	Ulufale	1	Fa'aoga o le uati (100 MHz)
fr_clk (Intel Quartus Prime Pro Edition)	Ulufale	1	Uati ta'avale fua (625 MHz) mo le uati fa'asinoga fa'aliliu muamua. O lenei uati e manaʻomia mo le faʻavasegaina o le transceiver i le taimi o le eletise. O lenei uati e mafai ona i soo se taimi.
toe setiina	Ulufale	1	Fa'aoga toe setiina faiga

Fa'ailoga	Fa'atonuga	Lautele	Fa'amatalaga
Uati ma Toe Seti Faailoga
reset_xcvr_powerup (Intel Quartus Prime Pro Edition)	Ulufale	1	Transceiver toe setiina mea e fai. O lenei fa'ailoga e fa'ailoa i le taimi o le fa'agasologa o suiga o le uati (mai le uati e leai se totogi i le uati TMDS) ile tulaga fa'aola.
tmds_clk_in	Ulufale	1	Uati HDMI RX TMDS
i2c_clk	Ulufale	1	Fa'aoga uati mo le DDC ma le SCDC fa'aoga
vid_clk_out	Tuuina atu	1	Fa'atino uati vitiō
ls_clk_out	Tuuina atu	1	Feso'ota'i le saosaoa fa'aola uati
sys_init	Tuuina atu	1	System initialization e toe setiina le faiga i luga o le power-up

RX Transceiver ma IOPLL faailoilo
rx_serial_data	Ulufale	3	HDMI fa'amaumauga fa'asologa i le RX Native PHY
gxb_rx_sauni	Tuuina atu	1	Fa'ailoa mai ua sauni le RX Native PHY
gxb_rx_cal_busy_out	Tuuina atu	3	RX Native PHY calibration pisi i le transceiver arbiter
gxb_rx_cal_busy_in	Ulufale	3	Fa'ailoilo pisi pisi mai le transceiver arbiter i le RX Native PHY
iopll_loka	Tuuina atu	1	Faailoa le IOPLL ua loka
gxb_reconfig_write	Ulufale	3	Transceiver toe fetuunaiga Avalon-MM interface mai le RX Native PHY i le transceiver arbiter
gxb_reconfig_read	Ulufale	3
gxb_reconfig_address	Ulufale	30
gxb_reconfig_writedata	Ulufale	96
gxb_reconfig_readdata	Tuuina atu	96
gxb_reconfig_waitrequest	Tuuina atu	3

RX Reconfiguration Pulega
rx_reconfig_en	Tuuina atu	1	RX Reconfiguration e mafai ai le faailo
fua	Tuuina atu	24	HDMI RX TMDS fua ole uati (i le 10 ms)
fua_aoga	Tuuina atu	1	Fa'ailoa mai o le fua fa'ailoga e aoga
os	Tuuina atu	1	oversampmea taua: • 0: Leai se ovaampling • 1: 5x ovaampling
reconfig_mgmt_write	Tuuina atu	1	RX toe fetuutuunaiga pulega Avalon manatua-fa'afanua fa'aoga i le transceiver arbiter
reconfig_mgmt_read	Tuuina atu	1
reconfig_mgmt_address	Tuuina atu	12

reconfig_mgmt_writedata	Tuuina atu	32
reconfig_mgmt_readdata	Ulufale	32
reconfig_mgmt_waitrequest	Ulufale	1

HDMI RX Fa'ailoga Autu
TMDS_Bit_clock_Ratio	Tuuina atu	1	feso'ota'iga resitala a le SCDC
audio_de	Tuuina atu	1	HDMI RX feso'ota'iga leo autu Va'ai i le vaega Fa'afeso'ota'i Fa'agogo i le HDMI Intel FPGA IP Taiala mo le fa'amatalaga atili.
fa'amatalaga_leo	Tuuina atu	256
audio_info_ai	Tuuina atu	48
leo_N	Tuuina atu	20
leo_CTS	Tuuina atu	20
audio_metadata	Tuuina atu	165
audio_format	Tuuina atu	5
aux_pkt_data	Tuuina atu	72	HDMI RX feso'ota'iga fesoasoani autu Va'ai i le vaega Fa'afeso'ota'i Fa'agogo i le HDMI Intel FPGA IP Taiala mo le fa'amatalaga atili.
aux_pkt_addr	Tuuina atu	6
aux_pkt_wr	Tuuina atu	1
aux_data	Tuuina atu	72
aux_sop	Tuuina atu	1
aux_eop	Tuuina atu	1
aux_valid	Tuuina atu	1
aux_error	Tuuina atu	1
gcp	Tuuina atu	6	HDMI RX fa'ailoga pito i tua Va'ai i le vaega Fa'afeso'ota'i Fa'agogo i le HDMI Intel FPGA IP Taiala mo le fa'amatalaga atili.
info_avi	Tuuina atu	112
info_vsi	Tuuina atu	61
colordepth_mgmt_sync	Tuuina atu	2
vid_data	Tuuina atu	N*48	HDMI RX pito ata vitio autu Manatua: N = faailoga i le uati Fa'asino i le Fa'agogo Fa'asagaga vaega i le HDMI Intel FPGA IP Taiala Tagata Fa'aoga mo nisi faamatalaga.
vid_vsync	Tuuina atu	N
vid_hsync	Tuuina atu	N
vid_de	Tuuina atu	N
faiga	Tuuina atu	1	HDMI RX pulea autu ma tulaga ports Manatua: N = faailoga i le uati Fa'asino i le Fa'agogo Fa'asagaga vaega i le HDMI Intel FPGA IP Taiala Tagata Fa'aoga mo nisi faamatalaga.
ctrl	Tuuina atu	N*6
lokaina	Tuuina atu	3
vid_lock	Tuuina atu	1
i_5v_mana	Ulufale	1	HDMI RX 5V iloa ma maua hotplug Va'ai ile Fa'agogo Fa'asagaga vaega i le HDMI Intel FPGA IP Taiala Tagata Fa'aoga mo nisi faamatalaga.
hdmi_rx_hpd_n	I fafo	1

hdmi_rx_i2c_sda	I fafo	1	HDMI RX DDC ma le SCDC fa'aoga
hdmi_rx_i2c_scl	I fafo	1

RX EDID RAM faailoilo
edid_ram_access	Ulufale	1	HDMI RX EDID RAM avanoa avanoa. Fa'ailoa edid_ram_access pe a e mana'o e tusi pe faitau mai le EDID RAM, a le o lea e tatau ona fa'amaulalo lenei fa'ailoga.
edid_ram_address	Ulufale	8
edid_ram_write	Ulufale	1
edid_ram_read	Ulufale	1
edid_ram_readdata	Tuuina atu	8
edid_ram_writedata	Ulufale	8
edid_ram_waitrequest	Tuuina atu	1

Laulau 43. HDMI TX Tulaga Maualuga Fa'ailoga

Fa'ailoga	Fa'atonuga	Lautele	Fa'amatalaga
Uati ma Toe Seti Faailoga
mgmt_clk	Ulufale	1	Fa'aoga o le uati (100 MHz)
fr_clk (Intel Quartus Prime Pro Edition)	Ulufale	1	Uati ta'avale fua (625 MHz) mo le uati fa'asinoga fa'aliliu muamua. O lenei uati e manaʻomia mo le faʻavasegaina o le transceiver i le taimi o le eletise. O lenei uati e mafai ona i soo se taimi.
toe setiina	Ulufale	1	Fa'aoga toe setiina faiga
hdmi_clk_in	Ulufale	1	Fa'asino le uati ile TX IOPLL ma le TX PLL. Ole taimi ole uati e tutusa ma le taimi ole uati ole TMDS.
vid_clk_out	Tuuina atu	1	Fa'atino uati vitiō
ls_clk_out	Tuuina atu	1	Feso'ota'i le saosaoa fa'aola uati
sys_init	Tuuina atu	1	System initialization e toe setiina le faiga i luga o le power-up
reset_xcvr	Ulufale	1	Toe seti i le TX transceiver
reset_pll	Ulufale	1	Toe seti i le IOPLL ma le TX PLL
reset_pll_reconfig	Tuuina atu	1	Toe seti i le PLL toe fetuutuunai

TX Transceiver ma IOPLL faailoilo
tx_serial_data	Tuuina atu	4	HDMI fa'amaumauga fa'asologa mai le TX Native PHY
gxb_tx_ready	Tuuina atu	1	Fa'ailoa TX Native PHY ua sauni
gxb_tx_cal_busy_out	Tuuina atu	4	TX Native PHY calibration pisi faailoilo i le transceiver arbiter
gxb_tx_cal_busy_in	Ulufale	4	Fa'ailoilo pisi pisi mai le transceiver arbiter i le TX Native PHY

TX Transceiver ma IOPLL faailoilo
iopll_loka	Tuuina atu	1	Faailoa le IOPLL ua loka
txpll_loka	Tuuina atu	1	Faailoa TX PLL ua loka
gxb_reconfig_write	Ulufale	4	Transceiver toe fetuutuuna'i Avalon fa'afanua fa'ata'atiaga manatua mai le TX Native PHY i le transceiver arbiter
gxb_reconfig_read	Ulufale	4
gxb_reconfig_address	Ulufale	40
gxb_reconfig_writedata	Ulufale	128
gxb_reconfig_readdata	Tuuina atu	128
gxb_reconfig_waitrequest	Tuuina atu	4

TX IOPLL ma TX PLL Fa'ailoga Fa'atonu
pll_reconfig_write/tx_pll_reconfig_write	Ulufale	1	TX IOPLL/TX PLL toe fetuutuunai Avalon manatua-faafanua interfaces
pll_reconfig_read/ tx_pll_reconfig_read	Ulufale	1
pll_reconfig_address/ tx_pll_reconfig_address	Ulufale	10
pll_reconfig_writedata/tx_pll_reconfig_writedata	Ulufale	32
pll_reconfig_readdata/tx_pll_reconfig_readdata	Tuuina atu	32
pll_reconfig_waitrequest/tx_pll_reconfig_waitrequest	Tuuina atu	1
os	Ulufale	2	oversampmea taua: • 0: Leai se ovaampling • 1: 3x ovaampling • 2: 4x ovaampling • 3: 5x ovaampling
fua	Ulufale	24	Fa'ailoa mai le TMDS uati fa'avevesi o le felauaiga vitiō fa'ai'uga.

HDMI TX Fa'ailoga Autu
ctrl	Ulufale	6*N	HDMI TX feso'ota'iga fa'atonutonu autu Manatua: N = Faailoga i le uati Va'ai i le vaega Source Interfaces i le HDMI Intel FPGA IP User Guide mo nisi faʻamatalaga.
faiga	Ulufale	1
TMDS_Bit_clock_Ratio	Ulufale	1	SCDC resitala feso'ota'iga Va'ai ile vaega Fa'afeso'ota'i Punaoa ile HDMI Intel FPGA IP User Guide mo nisi fa'amatalaga.
Scrambler_Enable	Ulufale	1
audio_de	Ulufale	1	HDMI TX feso'ota'iga leo autu Fa'asino i le Source Interfaces vaega i le HDMI Intel FPGA IP Taiala Tagata Fa'aoga mo nisi faamatalaga.
leo_mute	Ulufale	1
fa'amatalaga_leo	Ulufale	256
faaauau…

HDMI TX Fa'ailoga Autu
audio_info_ai	Ulufale	49
leo_N	Ulufale	22
leo_CTS	Ulufale	22
audio_metadata	Ulufale	166
audio_format	Ulufale	5
i2c_master_write	Ulufale	1	TX I2C matai Avalon fa'ata'ita'iga fa'ata'ita'iga i le I2C matai i totonu ole TX autu. Fa'aaliga: E maua nei faailoilo pe a e ki le Fa'aaofia le I2C fa'ata'oto.
i2c_master_read	Ulufale	1
i2c_master_address	Ulufale	4
i2c_master_writedata	Ulufale	32
i2c_master_readdata	Tuuina atu	32
aux_sauni	Tuuina atu	1	HDMI TX feso'ota'iga fesoasoani autu Va'ai ile vaega Fa'afeso'ota'i Punaoa ile HDMI Intel FPGA IP User Guide mo nisi fa'amatalaga.
aux_data	Ulufale	72
aux_sop	Ulufale	1
aux_eop	Ulufale	1
aux_valid	Ulufale	1
gcp	Ulufale	6	HDMI TX fa'ailoga pito i tua Va'ai ile vaega Fa'afeso'ota'i Punaoa ile HDMI Intel FPGA IP User Guide mo nisi fa'amatalaga.
info_avi	Ulufale	113
info_vsi	Ulufale	62
vid_data	Ulufale	N*48	HDMI TX uafu autu vitio Manatua: N = fa'ailoga ile uati Va'ai ile vaega Fa'afeso'ota'i Punaoa ile HDMI Intel FPGA IP User Guide mo nisi fa'amatalaga.
vid_vsync	Ulufale	N
vid_hsync	Ulufale	N
vid_de	Ulufale	N

I2C ma Vevela Su'e Fa'ailoga
nios_tx_i2c_sda_in (Intel Quartus Prime Pro Edition) Fa'aaliga: A e ki le Fa'aaofia le I2C parakalafa, o lenei faailo o loʻo tuʻuina i le TX autu ma o le a le mafai ona iloa i lenei tulaga.	Tuuina atu	1	I2C Master Avalon feso'ota'iga fa'amaufa'ailoga
nios_tx_i2c_scl_in (Intel Quartus Prime Pro Edition) Fa'aaliga: A e ki le Fa'aaofia le I2C parakalafa, o lenei faailo o loʻo tuʻuina i le TX autu ma o le a le mafai ona iloa i lenei tulaga.	Tuuina atu	1
nios_tx_i2c_sda_oe (Intel Quartus Prime Pro Edition) Fa'aaliga: A e ki le Fa'aaofia le I2C parakalafa, o lenei faailo o loʻo tuʻuina i le TX autu ma o le a le mafai ona iloa i lenei tulaga.	Ulufale	1
faaauau…

I2C ma Vevela Su'e Fa'ailoga
nios_tx_i2c_scl_oe (Intel Quartus Prime Pro Edition) Fa'aaliga: A e ki le Fa'aaofia le I2C parakalafa, o lenei faailo o loʻo tuʻuina i le TX autu ma o le a le mafai ona iloa i lenei tulaga.	Ulufale	1
nios_ti_i2c_sda_in (Intel Quartus Prime Pro Edition)	Tuuina atu	1
nios_ti_i2c_scl_in (Intel Quartus Prime Pro Edition)	Tuuina atu	1
nios_ti_i2c_sda_oe (Intel Quartus Prime Pro Edition)	Ulufale	1
nios_ti_i2c_scl_oe (Intel Quartus Prime Pro Edition)	Ulufale	1
hdmi_tx_i2c_sda	I fafo	1	HDMI TX DDC ma fesoʻotaʻiga SCDC
hdmi_tx_i2c_scl	I fafo	1
hdmi_ti_i2c_sda (Intel Quartus Prime Pro Edition)	I fafo	1	I2C fa'aoga mo Bitec Daughter Card Toe Iloiloga 11 TI181 Pulea
hdmi_tx_ti_i2c_sda (Intel Quartus Prime Standard Edition)	I fafo	1
hdmi_ti_i2c_scl (Intel Quartus Prime Pro Edition)	I fafo	1
hdmi_tx_ti_i2c_scl (Intel Quartus Prime Standard Edition)	I fafo	1
tx_i2c_avalon_waitrequest	Tuuina atu	1	Avalon fa'afanua fa'amaufa'ailoga o le I2C matai
tx_i2c_avalon_address (Intel Quartus Prime Standard Edition)	Ulufale	3
tx_i2c_avalon_writedata (Intel Quartus Prime Standard Edition)	Ulufale	8
tx_i2c_avalon_readdata (Intel Quartus Prime Standard Edition)	Tuuina atu	8
tx_i2c_avalon_chipselect (Intel Quartus Prime Standard Edition)	Ulufale	1
tx_i2c_avalon_write (Intel Quartus Prime Standard Edition)	Ulufale	1
tx_i2c_irq (Intel Quartus Prime Standard Edition)	Tuuina atu	1
tx_ti_i2c_avalon_waitrequest (Intel Quartus Prime Standard Edition)	Tuuina atu	1
tx_ti_i2c_avalon_address (Intel Quartus Prime Standard Edition)	Ulufale	3
tx_ti_i2c_avalon_writedata (Intel Quartus Prime Standard Edition)	Ulufale	8
tx_ti_i2c_avalon_readdata (Intel Quartus Prime Standard Edition)	Tuuina atu	8
faaauau…

I2C ma Vevela Su'e Fa'ailoga
tx_ti_i2c_avalon_chipselect (Intel Quartus Prime Standard Edition)	Ulufale	1
tx_ti_i2c_avalon_write (Intel Quartus Prime Standard Edition)	Ulufale	1
tx_ti_i2c_irq (Intel Quartus Prime Standard Edition)	Tuuina atu	1
hdmi_tx_hpd_n	Ulufale	1	HDMI TX hotplug iloa feso'ota'iga
tx_hpd_ack	Ulufale	1
tx_hpd_req	Tuuina atu	1

Laulau 44. Transceiver Arbiter Signals

Fa'ailoga	Fa'atonuga	Lautele	Fa'amatalaga
clk	Ulufale	1	Toe fa'atulagaina uati. O lenei uati e tatau ona fa'asoa tutusa le uati ma poloka fa'atonutonu toe fetuutuunai.
toe setiina	Ulufale	1	Toe seti le faailo. O lenei seti e tatau ona fa'asoa tutusa le seti fa'atasi ma poloka pulega toefa'atonu.
rx_rcfg_en	Ulufale	1	RX reconfiguration mafai ai le faailo
tx_rcfg_en	Ulufale	1	TX reconfiguration mafai ai le faailo
rx_rcfg_ch	Ulufale	2	Fa'ailoa mai po'o fea alāvai e toe fa'atulaga ile RX autu. O lenei faailo e tatau ona faʻamaonia i taimi uma.
tx_rcfg_ch	Ulufale	2	Fa'ailoa mai po'o fea alavai e toe fa'afou ile TX autu. O lenei faailo e tatau ona faʻamaonia i taimi uma.
rx_reconfig_mgmt_write	Ulufale	1	Toe fetuunaiga Avalon-MM fesoʻotaʻiga mai le RX reconfiguration pulega
rx_reconfig_mgmt_read	Ulufale	1
rx_reconfig_mgmt_address	Ulufale	10
rx_reconfig_mgmt_writedata	Ulufale	32
rx_reconfig_mgmt_readdata	Tuuina atu	32
rx_reconfig_mgmt_waitrequest	Tuuina atu	1
tx_reconfig_mgmt_write	Ulufale	1	Toe fetuutuunai Avalon-MM fesoʻotaʻiga mai le TX reconfiguration pulega
tx_reconfig_mgmt_read	Ulufale	1
tx_reconfig_mgmt_address	Ulufale	10
tx_reconfig_mgmt_writedata	Ulufale	32
tx_reconfig_mgmt_readdata	Tuuina atu	32
tx_reconfig_mgmt_waitrequest	Tuuina atu	1
reconfig_write	Tuuina atu	1	Toe fetuunaiga Avalon-MM feso'ota'iga i le transceiver
toeconfig_read	Tuuina atu	1
faaauau…

Fa'ailoga	Fa'atonuga	Lautele	Fa'amatalaga
toeconfig_address	Tuuina atu	10
reconfig_writedata	Tuuina atu	32
rx_reconfig_readdata	Ulufale	32
rx_reconfig_waitrequest	Ulufale	1
tx_reconfig_readdata	Ulufale	1
tx_reconfig_waitrequest	Ulufale	1
rx_cal_busy	Ulufale	1	Fa'ailoga tulaga fa'avasega mai le RX transceiver
tx_cal_busy	Ulufale	1	Fa'ailoga tulaga fa'avasega mai le transceiver TX
rx_reconfig_cal_busy	Tuuina atu	1	Fa'ailoga tulaga fa'avasega i le RX transceiver PHY reset control
tx_reconfig_cal_busy	Tuuina atu	1	Fa'ailoga tulaga fa'avasega mai le TX transceiver PHY reset control

Laulau 45. Fa'ailoga So'oga RX-TX

Fa'ailoga	Fa'atonuga	Lautele	Fa'amatalaga
toe setiina	Ulufale	1	Toe seti i le vitiō/leo/fesoasoani/sidebands FIFO buffer.
hdmi_tx_ls_clk	Ulufale	1	HDMI TX feso'ota'iga uati saoasaoa
hdmi_rx_ls_clk	Ulufale	1	HDMI RX feso'ota'iga uati saoasaoa
hdmi_tx_vid_clk	Ulufale	1	HDMI TX uati vitio
hdmi_rx_vid_clk	Ulufale	1	Uati vitio HDMI RX
hdmi_rx_loka	Ulufale	3	Fa'ailoa le tulaga loka HDMI RX
hdmi_rx_de	Ulufale	N	HDMI RX feso'ota'iga vitio Manatua: N = faailoga i le uati
hdmi_rx_hsync	Ulufale	N
hdmi_rx_vsync	Ulufale	N
hdmi_rx_data	Ulufale	N*48
rx_audio_format	Ulufale	5	HDMI RX fa'alogo leo
rx_audio_metadata	Ulufale	165
rx_audio_info_ai	Ulufale	48
rx_audio_CTS	Ulufale	20
rx_audio_N	Ulufale	20
rx_audio_de	Ulufale	1
rx_audio_data	Ulufale	256
rx_gcp	Ulufale	6	HDMI RX feso'ota'iga pito i tua
rx_info_avi	Ulufale	112
rx_info_vsi	Ulufale	61
faaauau…

Fa'ailoga	Fa'atonuga	Lautele	Fa'amatalaga
rx_aux_eop	Ulufale	1	HDMI RX feso'ota'iga fesoasoani
rx_aux_sop	Ulufale	1
rx_aux_valid	Ulufale	1
rx_aux_data	Ulufale	72
hdmi_tx_de	Tuuina atu	N	HDMI TX feso'ota'iga vitio Manatua: N = faailoga i le uati
hdmi_tx_hsync	Tuuina atu	N
hdmi_tx_vsync	Tuuina atu	N
hdmi_tx_data	Tuuina atu	N*48
tx_audio_format	Tuuina atu	5	HDMI TX feso'ota'iga leo
tx_audio_metadata	Tuuina atu	165
tx_audio_info_ai	Tuuina atu	48
tx_audio_CTS	Tuuina atu	20
tx_leo_N	Tuuina atu	20
tx_audio_de	Tuuina atu	1
tx_audio_data	Tuuina atu	256
tx_gcp	Tuuina atu	6	HDMI TX fa'afeso'ota'i fa'atasi
tx_info_avi	Tuuina atu	112
tx_info_vsi	Tuuina atu	61
tx_aux_eop	Tuuina atu	1	HDMI TX feso'ota'iga fesoasoani
tx_aux_sop	Tuuina atu	1
tx_aux_valid	Tuuina atu	1
tx_aux_data	Tuuina atu	72
tx_aux_sauni	Tuuina atu	1

Laulau 46. Fa'ailoga Fa'ailoga Fa'atonu a le Platform

Fa'ailoga	Fa'atonuga	Lautele	Fa'amatalaga
cpu_clk (Intel Quartus Prime Standard Edition)	Ulufale	1	uati CPU
clock_bridge_0_in_clk_clk (Intel Quartus Prime Pro Edition)
cpu_clk_reset_n (Intel Quartus Prime Standard Edition)	Ulufale	1	Toe setiina PPU
reset_bridge_0_reset_reset_n (Intel Quartus Prime Pro Edition)
tmds_bit_clock_ratio_pio_external_connectio n_export	Ulufale	1	TMDS bit clock ratio
fua_pio_external_connection_export	Ulufale	24	Fa'amoemoe TMDS uati taimi
faaauau…

Fa'ailoga	Fa'atonuga	Lautele	Fa'amatalaga
fua_aoga_pio_fafo_feso'ota'iga_fa'aola t	Ulufale	1	Fa'ailoa le fua PIO e aoga
i2c_master_i2c_serial_sda_in (Intel Quartus Prime Pro Edition)	Ulufale	1	I2C Master feso'ota'iga
i2c_master_i2c_serial_scl_in (Intel Quartus Prime Pro Edition)	Ulufale	1
i2c_master_i2c_serial_sda_oe (Intel Quartus Prime Pro Edition)	Tuuina atu	1
i2c_master_i2c_serial_scl_oe (Intel Quartus Prime Pro Edition)	Tuuina atu	1
i2c_master_ti_i2c_serial_sda_in (Intel Quartus Prime Pro Edition)	Ulufale	1
i2c_master_ti_i2c_serial_scl_in (Intel Quartus Prime Pro Edition)	Ulufale	1
i2c_master_ti_i2c_serial_sda_oe (Intel Quartus Prime Pro Edition)	Tuuina atu	1
i2c_master_ti_i2c_serial_scl_oe (Intel Quartus Prime Pro Edition)	Tuuina atu	1
oc_i2c_master_av_slave_translator_avalon_an ti_slave_0_address (Intel Quartus Prime Pro Edition)	Tuuina atu	3	I2C Master Avalon feso'ota'iga fa'amaufa'ailoga mo DDC ma SCDC
oc_i2c_master_av_slave_translator_avalon_an ti_slave_0_write (Intel Quartus Prime Pro Edition)	Tuuina atu	1
oc_i2c_master_av_slave_translator_avalon_an ti_slave_0_readdata (Intel Quartus Prime Pro Edition)	Ulufale	32
oc_i2c_master_av_slave_translator_avalon_an ti_slave_0_writedata (Intel Quartus Prime Pro Edition)	Tuuina atu	32
oc_i2c_master_av_slave_translator_avalon_an ti_slave_0_waitrequest (Intel Quartus Prime Pro Edition)	Ulufale	1
oc_i2c_master_av_slave_translator_avalon_an ti_slave_0_chipselect (Intel Quartus Prime Pro Edition)	Tuuina atu	1
oc_i2c_master_ti_avalon_anti_slave_address (Intel Quartus Prime Standard Edition)	Tuuina atu	3	I2C Master Avalon feso'ota'iga fa'amaufa'ailoga mo le Bitec daughter card toe teuteuga 11, T1181 pulea
oc_i2c_master_ti_avalon_anti_slave_write (Intel Quartus Prime Standard Edition)	Tuuina atu	1
oc_i2c_master_ti_avalon_anti_slave_readdata (Intel Quartus Prime Standard Edition)	Ulufale	32
oc_i2c_master_ti_avalon_anti_slave_writedat a (Intel Quartus Prime Standard Edition)	Tuuina atu	32
oc_i2c_master_ti_avalon_anti_slave_waitrequ est (Intel Quartus Prime Standard Edition)	Ulufale	1
oc_i2c_master_ti_avalon_anti_slave_chipsele ct (Intel Quartus Prime Standard Edition)	Tuuina atu	1
faaauau…

Fa'ailoga	Fa'atonuga	Lautele	Fa'amatalaga
edid_ram_access_pio_external_connection_exp ort	Tuuina atu	1	EDID RAM avanoa avanoa. Fa'ailoa edid_ram_access_pio_ external_connection_ export pe ae mana'o e tusi pe faitau mai le EDID RAM ile pito i luga ole RX. Faʻafesoʻotaʻi le EDID RAM avanoa Avalon-MM pologa i le Platform Designer i le EDID RAM interface i luga o le pito i luga RX modules.
edid_ram_slave_translator_address	Tuuina atu	8
edit_ram_slave_translator_write	Tuuina atu	1
edit_ram_slave_translator_read	Tuuina atu	1
edit_ram_slave_translator_readdata	Ulufale	8
edit_ram_slave_translator_writedata	Tuuina atu	8
edid_ram_slave_translator_waitrequest	Ulufale	1
powerup_cal_done_export (Intel Quartus Prime Pro Edition)	Ulufale	1	RX PMA Toe fetuutuuna'i Avalon fa'afanua fa'amaufa'ailoga
rx_pma_cal_busy_export (Intel Quartus Prime Pro Edition)	Ulufale	1
rx_pma_ch_export (Intel Quartus Prime Pro Edition)	Tuuina atu	2
rx_pma_rcfg_mgmt_address (Intel Quartus Prime Pro Edition)	Tuuina atu	12
rx_pma_rcfg_mgmt_write (Intel Quartus Prime Pro Edition)	Tuuina atu	1
rx_pma_rcfg_mgmt_read (Intel Quartus Prime Pro Edition)	Tuuina atu	1
rx_pma_rcfg_mgmt_readdata (Intel Quartus Prime Pro Edition)	Ulufale	32
rx_pma_rcfg_mgmt_writedata (Intel Quartus Prime Pro Edition)	Tuuina atu	32
rx_pma_rcfg_mgmt_waitrequest (Intel Quartus Prime Pro Edition)	Ulufale	1
rx_pma_waitrequest_export (Intel Quartus Prime Pro Edition)	Ulufale	1
rx_rcfg_en_export (Intel Quartus Prime Pro Edition)	Tuuina atu	1
rx_rst_xcvr_export (Intel Quartus Prime Pro Edition)	Tuuina atu	1
tx_pll_rcfg_mgmt_translator_avalon_anti_sla ve_waitrequest	Ulufale	1	TX PLL Reconfiguration Avalon faʻafanua faʻafanua faʻaoga
tx_pll_rcfg_mgmt_translator_avalon_anti_sla ve_writedata	Tuuina atu	32
tx_pll_rcfg_mgmt_translator_avalon_anti_sla ve_address	Tuuina atu	10
tx_pll_rcfg_mgmt_translator_avalon_anti_sla ve_write	Tuuina atu	1
tx_pll_rcfg_mgmt_translator_avalon_anti_sla ve_read	Tuuina atu	1
tx_pll_rcfg_mgmt_translator_avalon_anti_sla ve_readdata	Ulufale	32
faaauau…

Fa'ailoga	Fa'atonuga	Lautele	Fa'amatalaga
tx_pll_waitrequest_pio_external_connection_ export	Ulufale	1	TX PLL fa'atalitali
tx_pma_rcfg_mgmt_translator_avalon_anti_sla ve_address	Tuuina atu	12	TX PMA Reconfiguration Avalon fa'afanua fa'afanua fa'amaufa'ailoga
tx_pma_rcfg_mgmt_translator_avalon_anti_sla ve_write	Tuuina atu	1
tx_pma_rcfg_mgmt_translator_avalon_anti_sla ve_read	Tuuina atu	1
tx_pma_rcfg_mgmt_translator_avalon_anti_sla ve_readdata	Ulufale	32
tx_pma_rcfg_mgmt_translator_avalon_anti_sla ve_writedata	Tuuina atu	32
tx_pma_rcfg_mgmt_translator_avalon_anti_sla ve_waitrequest	Ulufale	1
tx_pma_waitrequest_pio_external_connection_ export	Ulufale	1	TX PMA fa'atalitali
tx_pma_cal_busy_pio_external_connection_exp ort	Ulufale	1	TX PMA Recalibration Pisi
tx_pma_ch_export	Tuuina atu	2	TX PMA alavai
tx_rcfg_en_pio_external_connection_export	Tuuina atu	1	TX PMA Toe fetuunaiga Fa'aaga
tx_iopll_rcfg_mgmt_translator_avalon_anti_s lave_writedata	Tuuina atu	32	TX IOPLL Reconfiguration Avalon faʻafanua faʻafanua faʻaoga
tx_iopll_rcfg_mgmt_translator_avalon_anti_s lave_readdata	Ulufale	32
tx_iopll_rcfg_mgmt_translator_avalon_anti_s lave_waitrequest	Ulufale	1
tx_iopll_rcfg_mgmt_translator_avalon_anti_s lave_address	Tuuina atu	9
tx_iopll_rcfg_mgmt_translator_avalon_anti_s lave_write	Tuuina atu	1
tx_iopll_rcfg_mgmt_translator_avalon_anti_s lave_read	Tuuina atu	1
tx_os_pio_external_connection_export	Tuuina atu	2	oversampmea taua: • 0: Leai se ovaampling • 1: 3x ovaampling • 2: 4x ovaampling • 3: 5x ovaampling
tx_rst_pll_pio_external_connection_export	Tuuina atu	1	Toe seti i le IOPLL ma le TX PLL
tx_rst_xcvr_pio_external_connection_export	Tuuina atu	1	Toe seti i le TX Native PHY
wd_timer_resetrequest_reset	Tuuina atu	1	Toe setiina le taimi o le Watchdog
color_depth_pio_external_connection_export	Ulufale	2	loloto lanu
tx_hpd_ack_pio_external_connection_export	Tuuina atu	1	Mo TX hotplug iloa limalima
tx_hpd_req_pio_external_connection_export	Ulufale	1

3.8. Fuafua RTL Parameters
Fa'aoga le HDMI TX ma le RX Top RTL fa'amaufa'ailoga e fa'avasega ai le fa'ata'ita'igaample.
O le tele o fa'asologa o mamanu o lo'o maua ile Design Example tab o le HDMI Intel FPGA IP fa'atonu fa'atonu. E mafai lava ona e suia le mamanu example faatulagaina oe
faia i le fa'atonu fa'asologa e ala i fa'amaufa'ailoga RTL.

Laulau 47. HDMI RX pito i luga

Parameter	Taua	Fa'amatalaga
SUPPORT_DEEP_COLOR	• 0: Leai se lanu loloto • 1: Lanu loloto	Fuafua pe mafai e le totonugalemu ona faʻapipiʻi faʻailoga lanu loloto.
SUPPORT_AUXILIARY	• 0: Leai AUX • 1: AUX	Fuafua pe fa'aaofia ai le fa'asologa o alalaupapa fesoasoani.
SYMBOLS_PER_CLOCK	8	Lagolago 8 faailoga i le uati mo Intel Arria 10 masini.
SUPPORT_AUDIO	• 0: Leai se leo • 1: Leo	Fuafua pe mafai e le autu ona fa'aigoa leo.
EDID_RAM_ADDR_WIDTH (Intel Quartus Prime Standard Edition)	8 (Tauaiga masani)	Fa'amaufa'ailoga 2 o le EDID RAM tele.
BITEC_DAUGHTER_CARD_REV	• 0: Le tulimata'i so'o se kata tama teine ​​Bitec HDMI • 4: Lagolago le Bitec HDMI fa'ata'ita'iga pepa tama teine ​​4 • 6: Su'esu'eina Bitec HDMI daughter card toe teuteuga 6 •11: Fa'atatau i le Bitec HDMI daughter card toe teuteuga 11 (fa'aletonu)	Fa'amaoti le toe iloiloga o le Bitec HDMI daughter card fa'aaogaina. A e suia le toe iloiloga, e mafai e le mamanu ona fesuiaʻi auala transceiver ma fesuiaʻi le polarity e tusa ai ma le Bitec HDMI daughter card manaʻomia. Afai e te setiina le BITEC_DAUGHTER_CARD_REV parakalafa i le 0, o le mamanu e le faia ni suiga i le transceiver auala ma le polarity.
POLARITY_INVERSION	• 0: Faaliliuina polarity • 1: Aua le fesuia'i le polarity	Seti lenei ta'otoga i le 1 e fesuia'i ai le tau o vaega ta'itasi o fa'amatalaga fa'aoga. O le setiina o lenei parakalafa i le 1 e tuʻuina atu ai le 4'b1111 i le rx_polinv port o le RX transceiver.

Fuafuaga 48. HDMI TX Parameter pito i luga

Parameter	Taua	Fa'amatalaga
USE_FPLL	1	Lagolago le fPLL pei TX PLL mo na'o le Intel Cyclone® 10 GX masini. Seti i taimi uma le parakalafa i le 1.
SUPPORT_DEEP_COLOR	• 0: Leai se lanu loloto • 1: Lanu loloto	Fuafua pe mafai e le totonugalemu ona faʻapipiʻi faʻailoga lanu loloto.
SUPPORT_AUXILIARY	• 0: Leai AUX • 1: AUX	Fuafua pe fa'aaofia ai le fa'asologa o alalaupapa fesoasoani.
SYMBOLS_PER_CLOCK	8	Lagolago 8 faailoga i le uati mo Intel Arria 10 masini.
faaauau…

Parameter	Taua	Fa'amatalaga
SUPPORT_AUDIO	• 0: Leai se leo • 1: Leo	Fuafua pe mafai e le autu ona fa'aigoa leo.
BITEC_DAUGHTER_CARD_REV	• 0: Le tulimata'i so'o se kata tama teine ​​Bitec HDMI • 4: Lagolago le Bitec HDMI fa'ata'ita'iga pepa tama teine ​​4 • 6: Su'esu'eina Bitec HDMI daughter card toe teuteuga 6 • 11: Fa'atatau i le Bitec HDMI daughter card toe teuteuga 11 (fa'aletonu)	Fa'amaoti le toe iloiloga o le Bitec HDMI daughter card fa'aaogaina. A e suia le toe iloiloga, e mafai e le mamanu ona fesuiaʻi auala transceiver ma fesuiaʻi le polarity e tusa ai ma le Bitec HDMI daughter card manaʻomia. Afai e te setiina le BITEC_DAUGHTER_CARD_REV parakalafa i le 0, o le mamanu e le faia ni suiga i le transceiver auala ma le polarity.
POLARITY_INVERSION	• 0: Faaliliuina polarity • 1: Aua le fesuia'i le polarity	Seti lenei ta'otoga i le 1 e fesuia'i ai le tau o vaega ta'itasi o fa'amatalaga fa'aoga. O le setiina o lenei parakalafa i le 1 e tuʻuina atu ai le 4'b1111 i le tx_polinv port o le TX transceiver.

3.9. Seti Meafaigaluega
Le HDMI Intel FPGA IP mamanu example HDMI 2.0b gafatia ma faia se faʻataʻitaʻiga faʻasolosolo mo se faʻataʻitaʻiga ata vitio HDMI.
Ina ia fa'atautaia le su'ega o meafaigaluega, fa'afeso'ota'i se masini e mafai ona fa'aogaina le HDMI—e pei o se kata fa'ata'ita'i fa'atasi ai ma le fa'aoga HDMI—i le poloka Transceiver Native PHY RX, ma le fa'amau HDMI.
fa'aoga.

1. O le su'ega HDMI e fa'aliliuina le uafu i totonu o se ata vitio masani ma auina atu i le uati toe fa'aleleia.
2. O le HDMI RX autu e fa'aliliuina le vitio, ausilali, ma fa'amatalaga fa'alogo e toe fa'atasi i tua i le HDMI TX autu e ala i le DCFIFO.
3. O le HDMI source port o le FMC daughter card e fa'asalalauina le ata i se mata'itu.

Fa'aaliga:
Afai e te manaʻo e faʻaoga se isi Intel FPGA atinaʻe laupapa, e tatau ona e suia le faʻaogaina o masini ma le pine. O le transceiver analog setting e tofotofoina mo le Intel Arria 10 FPGA development kit ma Bitec HDMI 2.0 daughter card. E mafai ona e suia tulaga mo lau lava laupapa.

Fuafuaga 49. Fa'amau Fa'amau i luga o le laupapa ma Galuega Fa'atino a le LED

Oomi Fa'amau/LED	Galuega
cpu_resetn	Oomi tasi e fai le setiina o le system.
user_pb[0]	Oomi tasi e sui le faailo HPD i le puna masani HDMI.
user_pb[1]	• Oomi ma taofi e fa'atonu le TX core e lafo le fa'ailoga DVI. • Fa'asa'oloto e lafo le fa'ailoga fa'ailoga HDMI.
user_pb[2]	• Oomi ma taofi e faatonu le TX core e taofi le auina atu o InfoFrames mai faailoilo itu. • Fa'asa'oloto e toe fa'aauau le lafoina o InfoFrames mai fa'ailo fa'amaufa'ailoga.
USER_LED[0]	RX HDMI PLL loka loka. • 0 = Tatala • 1 = Loka
USER_LED[1]	RX transceiver tulaga sauni.
faaauau…

Oomi Fa'amau/LED	Galuega
	• 0 = Le sauni • 1 = Sauni
USER_LED[2]	RX HDMI tulaga loka autu. • 0 = Le itiiti ifo i le 1 alalaupapa tatala • 1 = Ua loka uma alavai e 3
USER_LED[3]	RX sili atuamptulaga ling. • 0 = E le'i ovaampta'ita'ia (fa'amaumauga > 1,000 Mbps i le masini Intel Arria 10) • 1 = Ovaampta'ita'iina (fa'amatalaga <100 Mbps ile Intel Arria 10 masini)
USER_LED[4]	TX HDMI PLL loka loka. • 0 = Tatala • 1 = Loka
USER_LED[5]	TX transceiver tulaga sauni. • 0 = Le sauni • 1 = Sauni
USER_LED[6]	TX transceiver PLL loka loka. • 0 = Tatala • 1 = Loka
USER_LED[7]	TX sili atuamptulaga ling. • 0 = E le'i ovaampta'ita'ia (fa'amaumauga > 1,000 Mbps i le masini Intel Arria 10) • 1 = Ovaampta'ita'iina (fa'amatalaga <1,000 Mbps ile Intel Arria 10 masini)

3.10. Simulation Testbench
O le suʻega faʻataʻitaʻiga faʻataʻitaʻiga faʻataʻitaʻiga le HDMI TX faʻasologa faʻasolosolo i tua i le RX autu.
Fa'aaliga:
Ole su'ega fa'ata'ita'i lea e le'o lagolagoina mo fa'ata'ita'iga fa'atasi ai ma le Fa'aaofia I2C fa'ailoga ua mafai.

3. HDMI 2.0 Design Example ( Lagolago FRL = 0)
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Ata 28. HDMI Intel FPGA IP Simulation Testbench Block Diagram

Laulau 50. Vaega Su'esu'e

Vaega	Fa'amatalaga
Vitio TPG	O le vitiō su'ega mamanu mamanu (TPG) e maua ai le vitiō fa'aosofia.
Leo Sample Gen	O le leo sample generator maua leo sample stimulus. E fa'atupuina e le afi se fa'asologa fa'aopoopo o fa'amaumauga o su'ega e tu'uina atu i le alaleo leo.
Aux Sample Gen	O le aux sample generator e maua ai le ausilali sample stimulus. O le generator e fa'atupuina se fa'amaumauga tumau e tu'uina atu mai le transmitter.
CRC Siaki	E fa'amaonia e le siaki lenei pe a fetaui le TX transceiver toe maua mai le taimi ole uati ma le fua faatatau o fa'amatalaga mana'omia.
Siaki Fa'amatalaga Fa'alogo	O le su'ega o fa'amatalaga fa'alogo e fa'atusatusaina pe maua ma sa'o le fa'asologa o fa'amaumauga o su'ega.
Aux Fa'amatalaga Siaki	O le su'ega o fa'amatalaga aux e fa'atusatusaina pe maua le fa'amatalaga aux fa'amoemoeina ma fa'avasega sa'o i le itu e taliaina.

O le suʻega faʻataʻitaʻiga HDMI e faia suʻega faʻamaonia nei:

Vaega HDMI	Fa'amaoniga
Vitio fa'amaumauga	• O lo'o fa'atino e le su'ega su'esu'e le CRC i luga o le vitiō o lo'o tu'u mai ma fa'atino. • E siakiina le tau o le CRC o faʻamatalaga tuʻuina atu e faasaga i le CRC faʻatatau i faʻamatalaga vitio maua. • Ona fai lea e le su'ega su'ega pe a uma ona maua faailo V-SYNC mautu e 4 mai le tagata e taliaina.
Fa'amatalaga fesoasoani	• O le aux sample generator fa'atupuina se fa'amaumauga tumau e tu'uina atu mai le transmitter. • I le itu e taliaina, e fa'atusatusa e le afi pe o fa'amoemoeina fa'amatalaga fesoasoani e maua ma fa'avasega sa'o.
Fa'amatalaga leo	• O le leo sample generator e fa'atupuina se fa'asologa o fa'amaumauga o su'ega e tu'uina atu i le alaleo leo. • I le itu e talia ai, e siaki ma fa'atusatusa e le su'ega fa'alogo leo pe ua maua ma fa'avasega sa'o le fa'asologa o fa'amaumauga o su'ega.

O se fa'ata'ita'iga manuia e fa'ai'u i le fe'au lea:
# FA'AIGA_PER_UITI = 2
# VIC = 4
# FRL_RATE = 0
# BPP = 0
# FAO_FREQUENCY (kHz) = 48
# AUDIO_CHANNEL = 8
# Pasi fa'atusa

Laulau 51. HDMI Intel FPGA IP Design Example Simulators Lagolago

Simulator	Verilog HDL	VHDL
ModelSim – Intel FPGA Edition/ ModelSim – Intel FPGA Starter Edition	Ioe	Ioe
VCS/VCS MX	Ioe	Ioe
Riviera-PRO	Ioe	Ioe
Xcelium Fa'atasi	Ioe	Leai

3.11. Fa'aleleia lau Fa'ailoga
Laulau 52. HDMI Design Example Fegalegaleai ma le Intel Quartus Prime Pro Edition Software Version

Design Example Variant	Malosiaga e faʻaleleia i le Intel Quartus Prime Pro Edition 20.3
HDMI 2.0 Design Example ( Lagolago FRL = 0)	Leai

Mo so'o se mamanu e le fetaui fa'atasiample, e tatau ona e faia mea nei:

1. Fausia se mamanu fou example i le taimi nei Intel Quartus Prime Pro Edition polokalama faakomepiuta faʻaoga faʻaoga tutusa o lau mamanu o iai.
2. Faatusatusa le mamanu atoa example directory ma le mamanu exampna fa'atupuina i le fa'aaogaina o le polokalama muamua a le Intel Quartus Prime Pro Edition. Taulaga i luga o suiga na maua.

HDCP I luga o le HDMI 2.0/2.1 Fuafuaga Example

O le HDCP i luga o le HDMI mea faigaluega fa'ata'ita'igaampe fesoasoani ia te oe e iloilo le aoga o le HDCP vaega ma mafai ai e oe ona faʻaogaina le ata i lau Intel Arria 10 mamanu.
Fa'aaliga:
E le o iai le ata o le HDCP i le polokalama Intel Quartus Prime Pro Edition. Ina ia maua le ata HDCP, fa'afeso'ota'i Intel ile https://www.intel.com/content/www/us/en/broadcast/products/programmable/applications/connectivity-solutions.html.

4.1. Puipuiga o Mataupu Fa'atekinolosi (HDCP)
Puipuiga Fa'atekonolosi Fa'akomepiuta Maualuga-bandwidth (HDCP) o se ituaiga o puipuiga o aia tatau fa'atekinolosi e fausia ai se feso'ota'iga malupuipuia i le va o le puna i le fa'aaliga.
Na faia e Intel le uluai tekonolosi, lea ua laiseneina e le Digital Content Protection LLC vaega. O le HDCP ose auala e puipuia ai kopi lea e fa'ailogaina ai le leo/vitio i le va o le transmitter ma le receiver, e puipuia ai mai le kopiina faasolitulafono.
Ole vaega ole HDCP ole fa'atatau ile HDCP Specification version 1.4 ma le HDCP Specification version 2.3.
O le HDCP 1.4 ma le HDCP 2.3 IPs e fa'atino uma fa'atusatusaga i totonu o le fa'atonuga autu o masini e aunoa ma ni tulaga fa'alilolilo (pei o le ki fa'apitoa ma le ki o le sauniga) e mafai ona maua mai fafo atu o le IP fa'ailoga.

Laulau 53. Galuega a le HDCP IP

HDCP IP	Galuega
HDCP 1.4 IP	• Fa'amatalaga fa'amaonia — Fuafuaga ole ki matai (Km) — Tupulaga o An — Fuafuaga o ki o le sauniga (Ks), M0 ma le R0. • Fa'amaoni ma le toe fai - Fa'atusatusaga ma fa'amaoniga o V ma V' • So'oga fa'amaoni fa'amaoni — Fuafuaga o ki fa'avaa (Ki), Mi ma Ri.
faaauau…

Intel Corporation. Ua taofia aia tatau uma. Intel, le Intel logo, ma isi fa'ailoga Intel o fa'ailoga fa'ailoga a le Intel Corporation po'o ona lala. E fa'amaonia e Intel le fa'atinoina o ana oloa FPGA ma semiconductor i fa'amatalaga o lo'o iai nei e tusa ai ma le fa'atonuga masani a Intel, ae fa'asaoina le aia tatau e fai ai suiga i so'o se oloa ma auaunaga i so'o se taimi e aunoa ma se fa'aaliga. E leai se tiute po'o se noataga e afua mai i le talosaga po'o le fa'aogaina o so'o se fa'amatalaga, oloa, po'o se auaunaga o lo'o fa'amatalaina i i'i se'i vagana ua malilie i ai i se faiga tusitusia e Intel. Ua fautuaina tagata fa'atau Intel ina ia maua le fa'amatalaga lata mai o fa'amatalaga masini a'o le'i fa'alagolago i so'o se fa'amatalaga fa'asalalau ma a'o le'i tu'uina atu oka mo oloa po'o tautua.
*O isi igoa ma fa'ailoga e mafai ona ta'ua o se meatotino a isi.

ISO
9001:2015
Resitala

HDCP IP	Galuega
	• Faiga sipi uma e aofia ai le hdcpBlockCipher, hdcpStreamCipher, hdcpRekeyCipher, ma le hdcpRngCipher • Fa'ailoga tulaga fa'amaufa'ailoga (DVI) ma fa'ailoga fa'ailoga tulaga fa'amanino (HDMI) • Fa'afuainumera numera moni (TRNG) - Fa'avae meafaigaluega, fa'atinoga fa'akomepiuta atoa ma fa'atupu numera fa'afuase'i
HDCP 2.3 IP	• Matai (km), Sauniga Ki (ks) ma le nonce (rn, riv). — Fa'amalie ile NIST.SP800-90A fa'atupuina numera fa'afuase'i • Fa'amaoni ma fefa'ataua'iga ki - Fausiaina o numera faʻafuaseʻi mo le rtx ma le rrx faʻamalieina ile NIST.SP800-90A faʻatupuina numera faʻafuaseʻi - Fa'amaoniga saini o le tusi faamaonia (certrx) fa'aaoga le DCP public key (kpubdcp) — 3072 bits RSASSA-PKCS#1 v1.5 — RSAES-OAEP (PKCS#1 v2.1) fa'ailoga ma le fa'ailoga ole Master Key (km) — Fa'atupuina o le kd (dkey0, dkey1) fa'aaoga le AES-CTR mode - Fa'asologa ma fa'amaonia o le H ma le H' — Fuafuaga o Ekh(km) ma km (faiga) • Fa'amaoni ma le toe fai - Fa'atusatusaga ma fa'amaoniga o V ma V' - Fa'asologa ma fa'amaonia o M ma M' • Fa'afouina faiga (SRM) - SRM fa'amaoniga saini fa'aaoga kpubdcp — 3072 bits RSASSA-PKCS#1 v1.5 • Fetufaaiga o Ki • Fa'atupuina ma fa'atusatusaga o Edkey(ks) ma riv. • Fa'atupuina o le dkey2 e fa'aaoga ai le AES-CTR mode • Siaki Fa'alotoifale - Fa'asologa ma fa'amaonia o le L ma le L' - Tupulaga o le nonce (rn) • Puleaina o fa'amaumauga — AES-CTR ala fa'avae fa'atupu alavai autu • Asymmetric crypto algorithms - RSA ma le umi o le modulus o le 1024 (kpubrx) ma le 3072 (kpubdcp) bits — RSA-CRT (Chinese Remainder Theorem) fa'atasi ai ma le umi o le umi o le 512 (kprivrx) bits ma le umi fa'ateleina o le 512 (kprivrx) bits • Maualalo tulaga tau cryptographic galuega — Fa'ata'otoga o le crypto algorithms • Faiga AES-CTR ma le umi ki o le 128 bits - Hash, MGF ma HMAC algorithms • SHA256 • HMAC-SHA256 • MGF1-SHA256 - Fa'atupu numera fa'afuase'i moni (TRNG) • NIST.SP800-90A tausisia • Fa'avae meafaigaluega, fa'atino fa'akomepiuta atoatoa ma fa'atupu numera fa'afuase'i

4.1.1. HDCP I luga o le HDMI Design Example Fausiaina
O le ata o le HDCP e puipuia ai fa'amaumauga a'o fa'asalalauina fa'amaumauga i le va o masini feso'ota'i e ala i se HDMI po'o isi feso'ota'iga numera puipuia HDCP.
O faiga puipuia HDCP e aofia ai ituaiga masini e tolu:

4. HDCP I luga HDMI 2.0/2.1 Design Example
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• Punaoa (TX)
• Togo (RX)
• Toe fai
O lenei mamanu example fa'aalia le faiga o le HDCP i se masini toe fa'afo'i lea e talia ai fa'amaumauga, fa'a'ese'ese, ona toe fa'ailogaina lea o fa'amaumauga, ma mulimuli ane toe fa'asalalau fa'amaumauga. Repeters o loʻo i ai uma faʻaoga HDMI ma gaioiga. E vave fa'apipi'i le FIFO fa'apipi'i e fa'atino sa'o fa'ata'ita'i ata vitio HDMI e ui atu i le va o le magoto ma le puna HDMI. E mafai ona fa'atinoina nisi o fa'ailoga fa'ailoga, e pei o le fa'aliliuina o vitiō i se fa'atonuga maualuga atu e ala i le suiina o fa'aputuga FIFO i le Vitio ma Fa'asologa o Ata (VIP) Suite IP cores.

Ata 29. HDCP I luga o le HDMI Design Example Ata poloka

O fa'amatalaga nei e uiga i le fausaga o le mamanu exampe fetaui ma le HDCP i luga o le mamanu HDMI example poloka ata. Pe a LAGOLAGO FRL = 1 pe
Lagolago HDCP PULEGA AUTU = 1, le mamanu exampE ese teisi le fa'atonuga mai le Ata 29 i le itulau 95 ae o galuega fa'avae HDCP o lo'o tumau pea
tutusa.

1. O le HDCP1x ma le HDCP2x o IP o loʻo avanoa e ala ile HDMI Intel FPGA IP editor parameter. A e fa'atulagaina le HDMI IP i le fa'atonu fa'amaufa'ailoga, e mafai ona e fa'aogaina ma aofia ai le HDCP1x po'o le HDCP2x po'o IP uma e lua o se vaega o le subsystem. Faatasi ai ma le HDCP IP uma e mafai, o le HDMI IP e faʻapipiʻi ia lava i le topology cascade lea e fesoʻotaʻi ai le HDCP2x ma le HDCP1x IP i tua.
   • O le HDCP egress interface o le HDMI TX e auina atu ai fa'amatalaga vitiō leo e le'i fa'ailogaina.
   • O fa'amatalaga e le'i fa'ailogaina e fa'ailogaina e le poloka HDCP galue ma toe fa'afo'i atu i le HDMI TX i luga o le HDCP Ingress interface mo le fa'asalalauina i luga ole so'otaga.
   • O le PPU subsystem e pei o le fa'amaoni fa'atonu pule e fa'amautinoa e na'o le tasi o le HDCP TX IP o lo'o galue i so'o se taimi ae o le isi e leai.
   • E fa'apena fo'i, o le HDCP RX na te fa'amuta fa'amaumauga na maua i luga ole so'oga mai fafo HDCP TX.
2. E mana'omia le fa'apolokalameina o le HDCP IPs ma le Digital Content Protection (DCP) na tu'uina atu ki gaosiga. uta ki nei:
   Fuafuaga 54. Ki o Gaosia na tu'uina atu e le DCP
   

   HDCP	TX / RX	Ki
   HDCP2x	TX	16 paita: Global Constant (lc128)
   	RX	• 16 paita (tutusa ma le TX): Global Constant (lc128) • 320 paita: RSA Private Key (kprivrx) • 522 paita: RSA Public Key Certificate (certrx)
   HDCP1x	TX	• 5 paita: TX Key Selection Vector (Aksv) • 280 paita: TX Private Device Keys (Akeys)
   	RX	• 5 paita: RX Key Selection Vector (Bksv) • 280 paita: RX Private Device Ki (Bkeys)

   Le mamanu exampLe fa'atinoina o mea taua e manatua e pei o le faigofie lua-taulaga, lua-clock synchronous RAM. Mo le laʻititi laʻititi e pei o le HDCP2x TX, o le IP o loʻo faʻaaogaina le manatua autu e faʻaaoga ai tusi resitala i mafaufauga masani.
   Fa'aaliga: E le tu'uina atu e Intel le ki o le gaosiga o le HDCP fa'atasi ai ma le mamanu muamuaample po'o Intel FPGA IP i lalo o so'o se tulaga. Le fa'aogaina o le HDCP IP po'o le mamanu fa'atusaampO lea, e tatau ona avea oe ma se tagata e fa'aaogaina le HDCP ma maua sa'o mai ki o le gaosiga mai le Digital Content Protection LLC (DCP).
   E fa'atautaia le mamanu example, e te fa'asa'o le manatua autu files i le taimi faʻapipiʻi e aofia ai ki gaosiga poʻo le faʻatinoina o poloka faʻaoga e faitau saogalemu ai ki gaosiga mai se masini teu oloa fafo ma tusi i totonu o manatuaga autu i le taimi taʻavale.

3. E mafai ona e fa'ailo galuega fa'ata'oto fa'atino ile HDCP2x IP ma so'o se taimi e o'o atu ile 200 MHz. Ole taimi ole uati lea e iloa ai le vave ole
   O lo'o fa'agaoioi le fa'amaoniga HDCP2x. E mafai ona e filifili e faʻasoa le 100 MHz uati faʻaaogaina mo le Nios II processor ae o le faʻamaoniga faʻamaonia o le a faaluaina pe a faʻatusatusa i le faʻaaogaina o le 200 MHz uati.
4. O tau e tatau ona fesuiai i le va o le HDCP TX ma le HDCP RX e fesoʻotaʻi atu i luga o le HDMI DDC interface (I2 C serial interface) o le HDCP-
   fa'aoga puipuia. E tatau i le HDCP RX ona tu'uina atu se masini talafeagai i luga o le pasi I2C mo so'oga ta'itasi e lagolagoina. O le pologa I2C o lo'o fa'aluaina mo le uafu HDCP ma le tuatusi masini o le 0x74. O lo'o fa'auluina le taulaga resitala o le HDCP (Avalon-MM) o le HDCP2x ma le HDCP1x RX IP.
5. O le HDMI TX e faʻaaogaina le matai IC e faitau le EDID mai le RX ma faʻafeiloaʻi le SCDC faʻamaumauga e manaʻomia mo le HDMI 2.0 faʻaogaina i le RX. O le matai I2C lava e tasi o loʻo faʻauluina e le Nios II processor e faʻaaogaina foi e faʻafeiloaʻi ai feʻau HDCP i le va o TX ma RX. O le matai I2C o loʻo faʻapipiʻiina i totonu o le CPU subsystem.
6. O le Nios II processor e galue e pei o le matai i le faʻamaoniga faʻamaonia ma faʻauluina le pule ma le tulaga resitala (Avalon-MM) o le HDCP2x ma le HDCP1x TX.
   IPs. O aveta'avale fa'akomepiuta latou te fa'atinoina le fa'amaoniaina o masini fa'amalo e aofia ai le fa'amaoniaina o le saini fa'amaonia, fa'afesuia'i ki matai, siaki fa'apitonu'u, fefa'asoaa'i ki sauniga, pa'iga, siaki fa'amaoni feso'ota'iga (HDCP1x), ma fa'amaoniga fa'atasi, e pei o le fa'asalalauga fa'amatalaga topology ma le fa'asalalauina o fa'amatalaga fa'asalalau. E le fa'atinoina e aveta'avale masini so'o se galuega fa'ata'oto e mana'omia e le fa'amaoniga fa'amaonia. Nai lo lena, o le HDCP IP hardware e faʻaogaina uma galuega faʻataʻitaʻi e faʻamautinoa ai e leai ni faʻatauga faalilolilo e mafai ona maua.
   7. I se faʻataʻitaʻiga moni toe fai pe a manaʻomia le faʻalauteleina o faʻamatalaga topology i luga, o le Nios II processor e faʻauluina le Repeater Message Port (Avalon-MM) o le HDCP2x ma le HDCP1x RX IPs. O le Nios II processor e faʻamama le RX REPEATER bit i le 0 pe a iloa le fesoʻotaʻiga i lalo e le mafai ona HDCP pe a leai se faʻaoga i lalo. A aunoa ma se fesoʻotaʻiga i lalo, o le RX system ua avea nei ma se faʻaiʻuga, nai lo le toe fai. I le isi itu, o le Nios II processor e setiina le RX REPEATER bit i le 1 pe a iloa le pito i lalo o le HDCP-mafai.

4.2. Nios II Processor Software Flow
O le fa'asologa o polokalama faakomepiuta Nios II e aofia ai le fa'amaoniaina o le HDCP i luga ole talosaga HDMI.
Ata 30. Nios II Processor Software Flowchart

1. O le polokalama Nios II e amataina ma toe setiina le HDMI TX PLL, TX transceiver PHY, I2C matai ma le TI i fafo.
2. O le polokalame a le Nios II e su'esu'e fua fa'aitaita'i fa'ailoga fa'amaonia mai le RX rate detection circuit e iloa ai pe ua suia le fa'ai'uga o le vitiō ma pe mana'omia le toe fa'atulagaina o le TX. E su'esu'e fo'i e le masini komepiuta le fa'ailoga o le TX hot-plug e iloa ai pe na tupu se mea na tupu.
3. Pe a maua se faailoilo aoga mai le RX rate detection circuit, o le Nios II software e faitau le SCDC ma le loloto o le uati mai le HDMI RX ma toe maua mai le uati faʻasolosolo faʻavae i luga o le fua faʻatatau e iloa ai pe manaʻomia le toe faʻafouina o le HDMI TX PLL ma le transceiver PHY. Afai e manaʻomia le toe faʻaleleia o le TX, e faʻatonuina e le polokalama Nios II le matai I2C e lafo le tau SCDC i fafo RX. Ona faatonu lea e toe fetuutuunai le HDMI TX PLL ma le TX transceiver
   PHY, sosoo ai ma le toe fa'avasegaina o masini, ma toe setiina le fa'asologa. Afai e le suia le fua faatatau, e le mana'omia le TX reconfiguration po'o le HDCP toe fa'amaonia.
4. Pe a tupu se mea TX vevela-plug, o le Nios II polokalama faʻatonu le matai I2C e lafo le tau SCDC i fafo RX, ona faitau lea EDID mai RX.
   ma faʻafouina le EDID RAM i totonu. Ona fa'asalalauina lea e le polokalama fa'amatalaga EDID i luga.
5. O le polokalama Nios II e amata le gaioiga HDCP e ala i le faʻatonuina o le matai I2C e faitau le offset 0x50 mai fafo RX e iloa ai pe o le pito i lalo e mafai ona HDCP, poʻo
   a leai:
   • Afai ole tau ole HDCP2Version ua toe faafoi mai ole 1, ole pito i lalo ole HDCP2xcapable.
   • Afai o le tau toe faafoi o le faitau atoa o le 0x50 e 0, o le pito i lalo e mafai ona HDCP1x.
   • Afai o le tau toe faafoi o le 0x50 faitau atoa o le 1, o le pito i lalo e le mafai ona HDCP pe leai foi.
   • Afai o le pito i lalo e le'i mafaia e le HDCP po'o le le gaioi ae o lo'o mafai nei i le HDCP, o le polokalama e setiina le REPEATER bit o le repeater upstream (RX) i le 1 e ta'u mai ai o le RX ua avea nei ma toe fai.
   • Afai o le pito i lalo e mafai ona HDCP muamua ae e le'o mafai ona maua i le HDCP pe le gaioi, e setiina e le polokalama le REPEATER bit o le 0 e ta'u mai ai o le RX ua avea nei ma mea e taliaina.
6. O le polokalama e amataina le faʻamaoniga faʻamaonia o le HDCP2x e aofia ai le faʻamaoniaina o le saini o le tusi faamaonia RX, fefaʻatauaʻiga ki matai, siaki faʻapitonuʻu, fefaʻatauaʻiga autu o sauniga, faʻapipiʻi, faʻamaonia ma toe fai e pei o faʻasalalauga faʻamatalaga topology.
7. A i ai i le tulaga faʻamaonia, o le Nios II polokalama faʻatonuina le I2C matai e palota le RxStatus resitala mai fafo RX, ma afai e iloa e le polokalama le REAUTH_REQ bit ua seti, e amataina le toe faʻamaonia ma faʻamalo le faʻailoga TX.
8. Afai o le pito i lalo o se toe fai ma o le READY bit o le RxStatus register ua seti i le 1, e masani ona faʻaalia ai ua suia le topology i lalo. O lea la, o le Nios II polokalama faʻatonuina le I2C matai e faitau le ReceiverID_List mai lalo ma faʻamaonia le lisi. Afai e aoga le lisi ma e leai se mea sese e iloa ai le topology, e alu le polokalama i le Content Stream Management module. A leai, e amataina le toe faʻamaonia ma faʻamalo le faʻailoga TX.
9. O le polokalama Nios II e saunia ai le ReceiverID_List ma le RxInfo fa'atatau ona tusi lea i le Avalon-MM Repeater Message port o le repeater upstream (RX). Ona faʻasalalau lea e le RX le lisi i fafo TX (luga).
10. Ua mae'a le fa'amaoni i le taimi lea. O le polokalama e mafai ai le faʻailoga TX.
11. O le polokalama faʻapipiʻi e amataina le faʻamaoniga faʻamaonia HDCP1x lea e aofia ai fefaʻatauaʻiga autu ma faʻamaonia ma toe fai.
12. O le Nios II software e fa'atino feso'ota'iga siaki fa'amaoni e ala i le faitau ma fa'atusatusa Ri' ma Ri mai fafo RX (lalo) ma HDCP1x TX ta'itasi. Afai o tau
    e le fetaui, o le mea lea e faʻaalia ai le leiloa o le faʻamaopoopoina ma le polokalama e amataina le toe faʻamaonia ma faʻamalo le TX encryption.
13. Afai o le pito i lalo o se toe fai ma o le READY bit o le resitala Bcaps ua seti i le 1, e masani ona faʻaalia ai ua suia le topology i lalo. O lea la, o le Nios II polokalama faʻatonuina le I2C matai e faitau le KSV lisi tau mai lalo ma faʻamaonia le lisi. Afai o le lisi e aoga ma e leai se mea sese o le topology e iloa, e saunia e le polokalama le lisi KSV ma le Bstatus tau ma tusi i le Avalon-MM Repeater Message port o le repeater upstream (RX). Ona faʻasalalau lea e le RX le lisi i fafo TX (luga). A leai, e amataina le toe faʻamaonia ma faʻamalo le faʻailoga TX.

4.3. Design Walkthrough
Fa'atūina ma fa'agaoioia le HDCP i luga o le HDMI fa'ata'ita'igaample aofia ai le lima stages.

1. Seti meafaigaluega.
2. Fausia le mamanu.
3. Fa'asa'o le manatua autu o le HDCP files ia fa'aaofia ai au ki o gaosiga o le HDCP.
   a. Teu ki fa'apitoa ole gaosiga o le HDCP ile FPGA (Support HDCP Key Management = 0)
   e. Teu ki fa'ailoga HDCP gaosiga i totonu o le flash memory fafo po'o le EEPROM ( Lagolago HDCP Key Management = 1)
4. Tuufaatasia le mamanu.
5. View o taunuuga.

4.3.1. Seti Meafaigaluega
O le stagu o le faʻataʻitaʻiga o le faʻatulagaina o meafaigaluega.
A oʻo ina SUPPORT FRL = 0, mulimuli i laasaga nei e faʻatulaga ai meafaigaluega mo le faʻataʻitaʻiga:

1. Fa'afeso'ota'i le Bitec HDMI 2.0 FMC daughter card (toe iloilo 11) ile Arria 10 GX development kit ile FMC port B.
2. Fa'afeso'ota'i le Arria 10 GX development kit i lau PC e fa'aaoga ai se uaea USB.
3. Fa'afeso'ota'i se uaea HDMI mai le feso'ota'iga HDMI RX i le kata tama'ita'i Bitec HDMI 2.0 FMC i se masini HDMI e mafai ona fa'aogaina e le HDCP, e pei o se kata fa'akomepiuta e iai le HDMI.
4. Fa'afeso'ota'i le isi uaea HDMI mai le feso'ota'iga HDMI TX i luga o le kata tama'ita'i Bitec HDMI 2.0 FMC i se masini HDMI e mafai ona fa'aogaina e HDCP, e pei o le televise e iai le HDMI.

A'o le SUPPORT FRL = 1, mulimuli i laasaga nei e seti ai meafaigaluega mo le fa'aaliga:

1. Fa'afeso'ota'i le Bitec HDMI 2.1 FMC daughter card (Revision 9) i le Arria 10 GX development kit i le FMC port B.
2. Fa'afeso'ota'i le Arria 10 GX development kit i lau PC e fa'aaoga ai se uaea USB.
3. Faʻafesoʻotaʻi se HDMI 2.1 Category 3 uaea mai le HDMI RX fesoʻotaʻiga i luga o le Bitec HDMI 2.1 FMC daughter card i se HDCP-enabled HDMI 2.1 source, e pei o le Quantum Data 980 48G Generator.
4. Fa'afeso'ota'i isi uaea HDMI 2.1 Category 3 mai le feso'ota'iga HDMI TX i luga o le kata tama teine ​​Bitec HDMI 2.1 FMC i se pusa HDMI 2.1 e mafai ona fa'aogaina e HDCP, pei ole
   Quantum Data 980 48G Analyzer.

4.3.2. Fausia le Fuafuaga
A maeʻa ona faʻatulagaina meafaigaluega, e tatau ona e faʻatupuina le mamanu.
Ae e te leʻi amataina, ia mautinoa e faʻapipiʻi le ata HDCP i le polokalama Intel Quartus Prime Pro Edition.

1. Kiliki Meafaigaluega ➤ IP Catalog, ma filifili Intel Arria 10 o le aiga masini sini.
   Fa'aaliga: Le mamanu HDCP exampe na'o Intel Arria 10 ma Intel Stratix® 10 masini e lagolagoina.
2. I le IP Catalog, su'e ma kiliki-lua HDMI Intel FPGA IP. Ua aliali mai le faamalama fou ole suiga ole IP.
3. Fa'ailoa se igoa pito i luga mo lau suiga masani IP. E fa'asaoina e le fa'atonu fa'amaufa'ailoga le fa'atulagaina o suiga o le IP ile a file igoa .qsys pe .ip.
4. Kiliki OK. E aliali mai le fa'atonu fa'amaufa'ailoga.
5. I luga o le IP tab, faʻapipiʻi mea e manaʻomia mo TX ma RX.
6. Fa'aola le lagolago HDCP 1.4 po'o le Lagolago HDCP 2.3 parakalafa e fa'atupuina le HDCP design example.
7. Fa'aola le lagolago HDCP Key Management parameter pe afai e te mana'o e teu le ki o le gaosiga o le HDCP i se fa'ailoga fa'ailoga i totonu o le flash memory fafo po'o le EEPROM. A leai, tape le Support HDCP Key Management parameter e teu ai le HDCP production key i le faatulagaga manino i le FPGA.
8. I luga ole Design Exampi le tab, filifili Arria 10 HDMI RX-TX Retransmit.
9. Filifili le Synthesis e fa'atupuina ai le fa'ata'ita'iga o meafaigaluega e iaiample.
10. Mo Fausia File Fa'asologa, filifili Verilog po'o VHDL.
11. Mo Atina'e Atina'e, filifili Arria 10 GX FPGA Atina'e Kit. Afai e te filifilia le pusa atinaʻe, ona sui lea o le masini faʻatatau (filifilia i le laasaga 4) e fetaui ma le masini i luga o le pusa atinaʻe. Mo Arria 10 GX FPGA Development Kit, o le masini fa'aletonu o le 10AX115S2F45I1SG.
12. Kiliki Fausia Example Fuafuaga e gaosia ai le poloketi files ma le polokalame o le Executable and Linking Format (ELF) polokalame file.

4.3.3. Fa'aaofia le HDCP Production Keys
4.3.3.1. Teu ki fa'apitoa ole HDCP ile FPGA (Support HDCP Key Pulega = 0)
A mae'a ona fa'atupuina le mamanu, fa'asa'o le manatua autu o le HDCP files e aofia ai au ki gaosiga.
Ina ia aofia ai ki gaosiga, mulimuli i laasaga nei.

1. Su'e le manatua autu lea files i le /rtl/hdcp/ directory:
   • hdcp2x_tx_kmem.v
   • hdcp2x_rx_kmem.v
   • hdcp1x_tx_kmem.v
   • hdcp1x_rx_kmem.v
2. Tatala le hdcp2x_rx_kmem.v file ma su'e le facsimile key R1 mo le Receiver Public Certificate ma le RX Private Key ma Global Constant e pei ona fa'aalia i le ex.ample i lalo.
   Ata 31. Uaea Fa'asologa o Facsimile Key R1 mo le Receiver Public Certificate
   Ata 32. Uaea Fa'asologa o Facsimile Key R1 mo RX Private Key ma Global Constant
   
3. Su'e le mea e tu'u ai ki o le gaosiga ma sui i au lava ki gaosiga i la latou laina uaea i le tele endian format.
   Ata 33. Uaea Fa'asologa o Ki Gaosia o le HDCP (Fa'anofo)
   
4. Toe fai le Laasaga 3 mo isi manatuaga autu uma files. A mae'a fa'aaofia au ki o le gaosiga i totonu o manatuaga autu uma files, ia mautinoa o le USE_FACSIMILE parakalafa ua seti i le 0 i le mamanu example tulaga maualuga file (a10_hdmi2_demo.v)

4.3.3.1.1. HDCP Key Mapping mai le DCP Key Files
O vaega o lo'o mulimuli mai o lo'o fa'amatalaina ai le fa'afanua o ki gaosiga HDCP o lo'o teuina i le ki DCP files i le laina uaea o le kmem HDCP files.
4.3.3.1.2. hdcp1x_tx_kmem.v ma hdcp1x_rx_kmem.v files
Mo hdcp1x_tx_kmem.v ma hdcp1x_rx_kmem.v files

• O nei mea e lua files o lo'o fa'asoa le fa'atulagaga tutusa.
• Ina ia iloa le ki sa'o HDCP1 TX DCP file mo hdcp1x_tx_kmem.v, ia mautinoa o le 4 paita muamua o le file o le “0x01, 0x00, 0x00, 0x00”.
• Ina ia iloa le ki sa'o HDCP1 RX DCP file mo hdcp1x_rx_kmem.v, ia mautinoa o le 4 paita muamua o le file o le “0x02, 0x00, 0x00, 0x00”.
• O ki i le ki DCP files o lo'o i totonu o le laititi-endian faatulagaga. E faʻaaoga ile kmem files, e tatau ona e faaliliuina i latou i big-endian.

Ata 34. Fa'afanua Byte mai HDCP1 TX DCP ki file i totonu hdcp1x_tx_kmem.v

Fa'aaliga:
O le numera byte o loʻo faʻaalia i lalo ifo:

• Tele ki i paita * numera ki + numera paita i le laina o lo'o i ai nei + fa'asolo faifai pea + lapo'a laina i paita * numera laina.
• 308*n o lo'o fa'ailoa mai ai o seti ki ta'itasi e 308 paita.
• 7*y fa'ailoa mai o laina ta'itasi e 7 paita.

Ata 35. HDCP1 TX DCP ki file fa'atumuina i fa'atauga leaga

Ata 36. Uaea Fa'asologa o le hdcp1x_tx_kmem.v
Example o le hdcp1x_tx_kmem.v ma pe faʻafefea ona faʻapipiʻi faʻafanua i le example o HDCP1 TX DCP ki file i le Ata 35 i le itulau e 105.

4.3.3.1.3. hdcp2x_rx_kmem.v file
Mo hdcp2x_rx_kmem.v file

• Ina ia iloa le ki sa'o HDCP2 RX DCP file mo hdcp2x_rx_kmem.v, ia mautinoa o le 4 paita muamua o le file o le “0x00, 0x00, 0x00, 0x02”.
• O ki i le ki DCP files o lo'o i totonu o le laititi-endian faatulagaga.

Ata 37. Fa'afanua Byte mai le ki HDCP2 RX DCP file i totonu hdcp2x_rx_kmem.v
O le ata o loʻo i lalo o loʻo faʻaalia ai le faʻafanua saʻo mai le HDCP2 RX DCP ki file i totonu hdcp2x_rx_kmem.v.

Fa'aaliga:
O le numera byte o loʻo faʻaalia i lalo ifo:

• Tele ki i paita * numera ki + numera paita i le laina o lo'o i ai nei + fa'asolo faifai pea + lapo'a laina i paita * numera laina.
• 862*n o lo'o fa'ailoa mai ai o seti ki ta'itasi e 862 paita.
• 16*y fa'ailoa mai o laina ta'itasi e 16 paita. E iai se tuusaunoaga ile cert_rx_prod lea ole ROW 32 e na'o le 10 paita.

Ata 38. HDCP2 RX DCP ki file fa'atumuina i fa'atauga leaga

Ata 39. Uaea Fa'asologa o le hdcp2x_rx_kmem.v
O lenei ata o lo'o fa'aalia ai le fa'asologa o uaea mo hdcp2x_rx_kmem.v (cert_rx_prod, kprivrx_qinv_prod, ma le lc128_prod) fa'afanua i le fa'afanua muamua.ample ole ki HDCP2 RX DCP file in
Ata 38 i le itulau e 108.

4.3.3.1.4. hdcp2x_tx_kmem.v file
Mo hdcp2x_tx_kmem.v file:

• Ina ia iloa le ki sa'o HDCP2 TX DCP file mo hdcp2x_tx_kmem.v, ia mautinoa o le 4 paita muamua o le file o le “0x00, 0x00, 0x00, 0x01”.
• O ki i le ki DCP files o lo'o i totonu o le laititi-endian faatulagaga.
• I le isi itu, e mafai ona e fa'aogaina le lc128_prod mai le hdcp2x_rx_kmem.v sa'o i le hdcp2x_tx_kmem.v. O ki e tutusa tulaga taua.

Ata 40. Uaea laina o hdcp2x_tx_kmem.v
O lenei fuainumera o loʻo faʻaalia ai le faʻafanua saʻo o le byte mai le HDCP2 TX DCP key file i totonu hdcp2x_tx_kmem.v.

4.3.3.2. Teu ki fa'ailoga HDCP gaosiga i totonu o le flash memory fafo po'o EEPROM ( Lagolago HDCP Fa'atonu Fa'atonu = 1)
Ata 41. Tulaga maualuga i lugaview a le HDCP Pulega autu

Pe a ki le lagolago HDCP Key Management parameter, e te umiaina le pule ole HDCP production key encryption e ala ile fa'aogaina ole key encryption software utility (KEYENC) ma le polokalame autu o le mamanu lea e saunia e Intel. E tatau ona e tu'uina atu le ki o le gaosiga o le HDCP ma le 128 bits HDCP puipuiga ki. Le ki puipuiga HDCP
fa'ailogaina le ki o le gaosiga o le HDCP ma teu le ki i totonu o le manatuaga moli fafo (mo fa'ataample, EEPROM) i luga o le HDMI afafine card.
Fa'aola le lagolago HDCP Key Management parameter ma o le ki decryption feature (KEYDEC) e maua i totonu ole HDCP IP cores. Le puipuiga tutusa HDCP
e tatau ona fa'aoga ki i le KEYDEC e toe maua mai ai ki gaosiga HDCP i le taimi e fa'agasolo ai masini. KEYENC ma KEYDEC lagolago Atmel AT24CS32 32-Kbit serial EEPROM, Atmel AT24C16A 16-Kbit serial EEPROM ma talafeagai I2C EEPROM masini ma le itiiti ifo 16-Kbit tele rom.

Fa'aaliga:

1. Mo HDMI 2.0 FMC daughter card Toe Iloiloga 11, ia mautinoa o le EEPROM i luga o le afafine card o le Atmel AT24CS32. E lua lapopoa eseese o le EEPROM o loʻo faʻaogaina ile Bitec HDMI 2.0 FMC daughter card Revision 11.
2. Afai na e fa'aogaina muamua le KEYENC e fa'aigoa ai ki o le gaosiga o le HDCP ma fa'aola le Support HDCP Key Management i le version 21.2 po'o le taimi muamua atu, e tatau ona e toe fa'aigoaina ki fa'aoga HDCP e fa'aaoga ai le KEYENC software utility ma toe fa'afouina le HDCP IPs mai le version 21.3.
   agai i luma.

4.3.3.2.1. Intel KEYENC
KEYENC ose fa'aoga fa'akomepiuta laina fa'atonu e fa'aoga e Intel e fa'aigoa ai ki fa'atupuina o le HDCP ma se ki e puipuia ai le HDCP e 128 bits e te tu'uina atu. KEYENC o lo'o fa'ailogaina ki fa'atupuina o le HDCP i le hex po'o le pini po'o le ulutala file faatulagaga. KEYENC fa'atupuina fo'i mif file o lo'o iai lau ki e puipui ai le HDCP 128 bits. KEYDEC
mana'omia le mif file.

System Manaomia:

1. x86 64-bit masini ma le Windows 10 OS
2. Vaaiga C++ Toe tufatufaina atu pusa mo Visual Studio 2019(x64)

Fa'aaliga:
E tatau ona e faʻapipiʻi le Microsoft Visual C ++ mo VS 2019. E mafai ona e siaki pe faʻapipiʻi le Visual C ++ redistributable mai le Windows ➤ Control Panel ➤ Polokalama ma Faʻaaliga. Afai ua fa'apipi'i le Microsoft Visual C++, e mafai ona e va'ai i le Visual C++ xxxx
Toe tufatufaina atu (x64). A leai, e mafai ona e siiina ma faʻapipiʻi le Visual C++
Toe tufatufaina mai Microsoft webnofoaga. Va'ai i fa'amatalaga fa'afeso'ota'i mo le feso'ota'iga download.

Laulau 55. KEYENC Filifiliga Laina Poloaiga

Filifiliga Laina Poloaiga	Finauga/Faamatalaga
-k	<HDCP protection key file> Tusitusi file o lo'o i ai na'o le 128 bits HDCP puipuiga ki i le hexadecimal. Example: f0f1f2f3f4f5f6f7f8f9fafbfcfdfeff
-hdcp1tx	<HDCP 1.4 TX production keys file> HDCP 1.4 transmitter ki gaosiga file mai le DCP (.bin file)
-hdcp1rx	<HDCP 1.4 RX production keys file> HDCP 1.4 fa'atauga ki gaosiga file mai le DCP (.bin file)
-hdcp2tx	<HDCP 2.3 TX production keys file> HDCP 2.3 transmitter ki gaosiga file mai le DCP (.bin file)
-hdcp2rx	<HDCP 2.3 RX production keys file> HDCP 2.3 fa'atauga ki gaosiga file mai le DCP (.bin file)
-hdcp1txkeys	Fa'ailoa mai le vaega autu mo mea na filifilia (.bin) files -hdcp1txkeys|hdcp1rxkeys|hdcp2rxkeys nm o fea n = ki amata (1 po'o >1) m = fa'ai'uga ki (n po'o >n) ExampLe: Filifili 1 i le 1000 ki mai HDCP 1.4 TX ta'itasi, HDCP 1.4 RX ma HCDP 2.3 RX gaosiga ki file. “-hdcp1txkeys 1-1000 -hdcp1rxkeys 1-1000 -hdcp2rxkeys 1-1000”
-hdcp1rxkeys
-hdcp2rxkeys
faaauau…

Filifiliga Laina Poloaiga	Finauga/Faamatalaga
	Fa'aaliga: 1. Afai e te le'o fa'aogaina so'o se ki o le gaosiga o le HDCP file, e te le mana'omia le laina ki HDCP. Afai e te le o faʻaogaina le finauga i le laina o le faʻatonuga, o le faʻaogaina o le ki o le 0. 2. E mafai fo'i ona e filifilia fa'ailoga eseese o ki mo ki gaosiga HDCP file. Ae ui i lea, numera o ki e tatau ona fetaui ma filifiliga filifilia. Example: Filifili 100 ki eseese Filifili muamua 100 ki mai HDCP 1.4 TX gaosiga ki file “-hdcp1txkeys 1-100” Filifili ki 300 i le 400 mo HDCP 1.4 RX ki gaosiga file “-hdcp1rxkeys 300-400” Filifili ki 600 i le 700 mo HDCP 2.3 RX ki gaosiga file “-hdcp2rxkeys 600-700”
-o	Tuuina atu file faatulagaga . O le tulaga masani o le hex file. Fausia ki fa'ailoga HDCP gaosiga i le binary file fa'asologa: -o bin Fa'atupu fa'ailoga HDCP ki gaosiga i le hex file fa'asologa: -o hex Fa'atupu fa'ailoga HDCP ki fa'atupu i le ulutala file faatulagaga: -oi
– siaki-ki	Lolomi numera o ki o lo'o avanoa i totonu files. EsoampLe:
	keyenc.exe -hdcp1tx file> -hdcp1rx <HDCP 1.4 RX production keys file> -hdcp2tx file> -hdcp2rx file> – siaki-ki
	Fa'aaliga: faʻaaoga parakalafa - siaki-ki i le pito o le laina o le poloaiga e pei ona taʻua i lugaample.
–faiga	Lolomi numera fa'aliliu KEYENC

E mafai ona e filifili filifiliga HDCP 1.4 ma/po'o le HDCP 2.3 ki gaosiga e fa'ailoga. Mo example, ia fa'aaoga na'o le HDCP 2.3 RX ki fa'ailoga e fa'ailoga, fa'aaoga na'o -hdcp2rx
<HDCP 2.3 RX production keys file> -hdcp2rxkeys i laina fa'atonu laina.
Fuafuaga 56. KEYENC Ta'iala Fe'au Sese masani

Feau Sese	Taiala
SESE: Ki puipui HDCP file misi	Ua misi le laina fa'atonu -k file>
SESE: ki e tatau ona 32 numera hex (fa'ata'ita'iga f0f1f2f3f4f5f6f7f8f9fafbfcfdfeff)	HDCP puipuiga ki file e tatau ona i ai na'o le ki o le puipuiga o le HDCP ile 32 numera hexadecimal.
ERROR: Fa'amolemole fa'ailoa mai le vaega autu	E le'o fa'amaoti mai le laina autu mo ki fa'aoga o le HDCP file.
SESE: Le sa'o le fa'asologa o ki	E le sa'o le vaega autu ua fa'amaoti mo -hdcp1txkeys po'o -hdcp1rxkeys po'o -hdcp2rxkeys.
SESE: e le mafai ona faiFileigoa>	Siaki le faʻatagaga o faila mai le keyenc.exe o loʻo faʻatautaia.
SESE: -hdcp1txkeys fa'aoga e le aoga	E le aoga le fa'atulagaina o le fa'asologa o ki fa'aoga mo HDCP 1.4 TX. Sa'o le fa'atulagaina o le "-hdcp1txkeys nm" lea n >= 1, m >= n
SESE: -hdcp1rxkeys fa'aoga e le aoga	E le aoga le fa'atulagaina o fa'asologa o ki fa'aoga mo HDCP 1.4 RX. Sa'o le fa'atulagaina o le "-hdcp1rxkeys nm" lea n >= 1, m >= n
SESE: -hdcp2rxkeys fa'aoga e le aoga	E le aoga le fa'atulagaina o fa'asologa o ki fa'aoga mo HDCP 2.3 RX. Sa'o le fa'atulagaina o le "-hdcp2rxkeys nm" lea n >= 1, m >= n
faaauau…

Feau Sese	Taiala
SESE: Le aoga file <fileigoa>	E le aoga ki gaosiga HDCP file.
SESE: file ituaiga o misi mo le -o filifiliga	O lo'o misi le parakalafa o laina fa'atonu mo -o .
SESE: le aoga fileigoa-fileigoa>	<fileigoa> e le aoga, faʻamolemole faʻaaoga le aoga fileigoa e aunoa ma ni mataitusi faapitoa.

Fa'ailoga le Ki Tasi mo le EEPROM Tasi
Fa'asolo le laina o lo'o i lalo mai le fa'atonuga a le Windows e fa'apipi'i ai le ki se tasi o le HDCP 1.4 TX, HDCP 1.4 RX, HDCP 2.3 TX ma le HDCP 2.3 RX fa'atasi ai ma gaioiga. file faatulagaga o ulutala file mo le EEPROM tasi:
keyenc.exe -k file> -hdcp1tx file> -hdcp1rx file> -hdcp2tx file> -hdcp2rx file> -hdcp1txkeys 1-1 -hdcp1rxkeys 1-1 -hdcp2rxkeys 1-1 -oh

Fa'ailoga N Ki mo N EEPROMs
Fa'asolo le laina fa'atonu mai le fa'atonuga a le Windows e fa'ailoga N ki (amata mai le ki 1) o le HDCP 1.4 TX, HDCP 1.4 RX, HDCP 2.3 TX ma le HDCP 2.3 RX ma le gaosiga. file faatulagaga o le hex file mo N EEPROMs:
keyenc.exe -k file> -hdcp1tx file> -hdcp1rx file> -hdcp2tx file> -hdcp2rx file> -hdcp1txkeys 1 -hdcp1rxkeys 1- -hdcp2rxkeys 1- -o hex pe a N o> = 1 ma e tatau ona fetaui mo filifiliga uma.

Fa'amatalaga Fa'atatau
Microsoft Visual C++ mo Visual Studio 2019
Tuuina atu le Microsoft Visual C++ x86 toe tufatufaina atu pusa (vc_redist.x86.exe) mo le la'uina. Afai e suia le fesoʻotaʻiga, e fautuaina oe e Intel e suʻe "Visual C++ redistributable" mai le masini suʻesuʻe a Microsoft.

4.3.3.2.2. Polokalame autu
Ina ia fa'apolokalame ki fa'ailoga HDCP gaosiga i luga ole EEPROM, mulimuli i laasaga nei:

1. Kopi le mamanu autu o le polokalame files mai le auala lenei i lau tusi galuega: /hdcp2x/hw_demo/key_programmer/
2. Kopi le ulutala polokalame file (hdcp_key .h) fa'atupuina mai le KEYENC software utility (vaega Encrypt Single Key for Single EEPROM on page 113 ) i le software/key_programmer_src/ directory ma toe faaigoa o le hdcp_key.h.
3. Tamomoe ./runall.tcl. O lenei tusitusiga e faʻatinoina tulafono nei:
   • Fausia fa'amaumauga IP files
   • Fausia le faiga o le Platform Designer
   • Fausia se poloketi Intel Quartus Prime
   • Fausia se avanoa faigaluega polokalame ma fausia le polokalama
   • Faia se tuufaatasiga atoatoa
4. La'u mai le Polokalama Object File (.sof) i le FPGA e fa'apolokalame ai ki fa'ailoga HDCP gaosiga i luga ole EEPROM.

Fausia le Stratix 10 HDMI RX-TX Retransmit design example fa'atasi ma le Lagolago HDCP 2.3 ma le Lagolago HDCP 1.4 fa'amaufa'ailoga e ki, ona mulimuli lea i le la'asaga o lo'o i lalo e aofia ai le ki puipui HDCP.

• Kopi le mif file (hdcp_kmem.mif) fa'atupuina mai le KEYENC software utility (vaega Encrypt Single Key for Single EEPROM i le itulau 113) i le /quartus/hdcp/ directory.

4.3.4. Tuufaatasia le Fuafuaga
A mae'a ona e fa'aofia au lava ki fa'atupuina o le HDCP i le FPGA po'o le polokalame le fa'ailogaina o ki fa'atupuina o le HDCP ile EEPROM, e mafai nei ona e fa'aputuina le mamanu.

1. Tatala le polokalama Intel Quartus Prime Pro Edition ma tatala /quartus/a10_hdmi2_demo.qpf.
2. Kiliki Processing ➤ Amata Fa'aopoopo.

4.3.5. View o I'uga
I le faaiuga o le faʻataʻitaʻiga, o le a mafai ona e faia view o fa'ai'uga ile HDCPenabled HDMI goto fafo.
I view iʻuga o le faʻataʻitaʻiga, mulimuli i laasaga nei:

1. Fa'aola le Intel FPGA laupapa.
2. Suia le lisi i /quartus/.
3. Fa'aoga le fa'atonuga o lo'o i lalo ile Nios II Command Shell e si'i mai ai le Polokalama Fa'atonu File (.sof) i le FPGA. nios2-configure-of output_files/ .sof
4. Fa'aola le HDCP-fa'aogaina HDMI puna mai fafo ma goto (pe afai e te le'i faia). O le HDMI pito i fafo e faʻaalia ai le gaioiga o lau HDMI fafo puna.

4.3.5.1. Oomi Fa'amau ma Galuega Fa'atino
Fa'aaogā fa'amau oomi ma fa'aoga LED i luga o le laupapa e fa'atonutonu ai lau fa'ata'ita'iga.

Fuafuaga 57. Oomi Fa'amau ma fa'ailoga ta'ita'i (SUPPORT FRL = 0)

Oomi Fa'amau/LED	Galuega
cpu_resetn	Oomi tasi e fai le setiina o le system.
user_pb[0]	Oomi tasi e sui le faailo HPD i le puna masani HDMI.
user_pb[1]	• Oomi ma taofi e fa'atonu le TX core e lafo le fa'ailoga DVI. • Fa'asa'oloto e lafo le fa'ailoga fa'ailoga HDMI. • Ia mautinoa o le vitio o loʻo sau i totonu ole 8 bpc avanoa lanu RGB.
user_pb[2]	• Oomi ma taofi e faatonu le TX core e taofi le auina atu o InfoFrames mai faailoilo itu. • Fa'asa'oloto e toe fa'aauau le lafoina o InfoFrames mai fa'ailo fa'amaufa'ailoga.
ta'ita'ia e tagata [0]	RX HDMI PLL loka loka. • 0: Tatala • 1: Loka
ta'ita'ia e tagata [1]	RX HDMI tulaga loka autu • 0: Le itiiti ifo i le 1 alalaupapa tatala • 1: Ua loka uma alavai e 3
ta'ita'ia e tagata [2]	RX HDCP1x IP decryption tulaga. • 0: Le toaga • 1: Toaga
ta'ita'ia e tagata [3]	RX HDCP2x IP decryption tulaga. • 0: Le toaga • 1: Toaga
ta'ita'ia e tagata [4]	TX HDMI PLL loka loka. • 0: Tatala • 1: Loka
ta'ita'ia e tagata [5]	TX transceiver PLL loka loka. • 0: Tatala • 1: Loka
ta'ita'ia e tagata [6]	TX HDCP1x tulaga fa'ailoga IP. • 0: Le toaga • 1: Toaga
ta'ita'ia e tagata [7]	TX HDCP2x tulaga fa'ailoga IP. • 0: Le toaga • 1: Toaga

Fuafuaga 58. Oomi Fa'amau ma fa'ailoga ta'ita'i (SUPPORT FRL = 1)

Oomi Fa'amau/LED	Galuega
cpu_resetn	Oomi tasi e fai le setiina o le system.
user_dipsw	Su'e DIP fa'aogaina e le tagata fa'aoga e fa'asolo i le auala passthrough. • OFF (tulaga faaletonu) = Passthrough HDMI RX i luga o le FPGA e maua le EDID mai fafo ma tuʻuina atu i le puna i fafo o loʻo fesoʻotaʻi i ai. • ON = E mafai ona e pulea le maualuga o le RX FRL fua mai le Nios II terminal. O le poloaiga e suia le RX EDID e ala i le faʻaogaina o le maualuga o le tau o le FRL. Fa'asino i Fa'atino le Fuafuaga i Fua Fa'atatau FRL Eseese i le itulau 33 mo nisi fa'amatalaga e uiga i le fa'atulagaina o fua faatatau FRL eseese.
faaauau…

Oomi Fa'amau/LED	Galuega
user_pb[0]	Oomi tasi e sui le faailo HPD i le puna masani HDMI.
user_pb[1]	Fa'apolopolo.
user_pb[2]	Oomi tasi e faitau tusi resitala a le SCDC mai le pusa e feso'ota'i ma le TX o le Bitec HDMI 2.1 FMC daughter card. Fa'aaliga: Ina ia mafai ona faitau, e tatau ona e seti DEBUG_MODE i le 1 i totonu o le polokalama.
user_led_g[0]	RX FRL uati PLL loka loka. • 0: Tatala • 1: Loka
user_led_g[1]	RX HDMI tulaga loka vitio. • 0: Tatala • 1: Loka
user_led_g[2]	RX HDCP1x IP decryption tulaga. • 0: Le toaga • 1: Toaga
user_led_g[3]	RX HDCP2x IP decryption tulaga. • 0: Le toaga • 1: Toaga
user_led_g[4]	TX FRL uati PLL loka loka. • 0: Tatala • 1: Loka
user_led_g[5]	TX HDMI tulaga loka vitio. • 0 = Tatala • 1 = Loka
user_led_g[6]	TX HDCP1x tulaga fa'ailoga IP. • 0: Le toaga • 1: Toaga
user_led_g[7]	TX HDCP2x tulaga fa'ailoga IP. • 0: Le toaga • 1: Toaga

4.4. Puipuiga o Fa'ailoga Fa'amaufa'ailoga ua Fa'amauina ile FPGA Design
O le tele o mamanu FPGA o loʻo faʻaogaina faʻamatalaga, ma e masani ona manaʻomia le faʻapipiʻiina o ki faalilolilo i le FPGA bitstream. I aiga masini fou, e pei o le Intel Stratix 10 ma le Intel Agilex, o loʻo i ai se poloka Secure Device Manager e mafai ona tuʻuina atu ma pulea nei ki faalilolilo. Afai e le o iai nei foliga, e mafai ona e faʻamautu le anotusi o le FPGA bitstream, e aofia ai soʻo se ki faʻaoga faalilolilo faʻaoga, faʻatasi ai ma faʻamatalaga.
O ki fa'aoga e tatau ona fa'amautu lelei i totonu o lau si'osi'omaga mamanu, ma fa'aopoopo lelei i le mamanu e fa'aoga ai se faiga fa'amautu otometi. O laasaga nei o loʻo faʻaalia ai pe faʻapefea ona e faʻatinoina sea faiga faʻatasi ma meafaigaluega a le Intel Quartus Prime.

1. Atia'e ma fa'alelei le HDL ile Intel Quartus Prime ile si'osi'omaga e le maluelue.
2. Faʻafeiloaʻi le mamanu i se siosiomaga malupuipuia ma faʻatino se faʻagasologa otometi e faʻafou ai le ki faalilolilo. O lo'o fa'apipi'i i luga ole masini le fa'atauga autu. A fa'afou le ki, o le fa'amuamua manatua file (.mif) e mafai ona sui ma le "quartus_cdb –update_mif" assembler tafe e mafai ona suia le ki puipuiga HDCP e aunoa ma le toe tuufaatasia. O lenei laʻasaga e vave tele e tamoʻe ma faʻasaoina le taimi muamua.
3. O le Intel Quartus Prime bitstream ona fa'ailogaina lea i le ki FPGA a'o le'i fa'afeiloa'i le bitstream fa'ailoga i tua i le si'osi'omaga e le maluelue mo su'ega mulimuli ma le fa'atinoina.

E fautuaina e fa'amalo uma le fa'aogaina o le debug e mafai ona toe maua mai le ki faalilolilo mai le FPGA. E mafai ona e faʻamalo atoatoa le mafai debug e ala i le tapeina o le JTAG uafu, po'o le filifili fa'amalo ma toeview e leai ni fa'ailoga fa'apipi'i e pei o le fa'atonu fa'amanatu i totonu po'o le Signal Tap e mafai ona toe maua mai le ki. Va'ai i le AN 556: Fa'aaogaina o le Fuafuaga Saogalemu Design i Intel FPGAs mo nisi fa'amatalaga i le fa'aogaina o vaega saogalemu o le FPGA e aofia ai laasaga ma'oti ile auala e fa'ailoga ai le FPGA bitstream ma fetuutuunai filifiliga saogalemu e pei ole fa'agata JTAG avanoa.

Fa'aaliga:
E mafai ona e mafaufau i le laasaga faaopoopo o le faʻafefe poʻo le faʻailoga ma se isi ki o le ki faalilolilo i le teuina o le MIF.
Fa'amatalaga Fa'atatau
AN 556: Fa'aaogaina o Fa'ailoga Puipuiga i totonu ole Intel FPGAs

4.5. Manatuga Puipuiga
Pe a fa'aogaina le ata HDCP, ia e manatua manatu nei mo le saogalemu.

• Pe a mamanuina se faiga toe fai, e tatau ona e poloka le vitio na maua mai le ulufale atu i le TX IP i tulaga nei:
  - Afai o le vitio na maua e HDCP-encrypted (fa'ata'ita'iga tulaga fa'ailoga hdcp1_enabled po'o hdcp2_enabled mai le RX IP ua fa'amaonia) ma o le vitio na lafoina e le'o fa'ailogaina HDCP (fa'ata'ita'iga tulaga fa'ailoga hdcp1_enabled po'o le hdcp2_enabled mai le TX IP e le o fa'amaonia).
  - Afai o le vitio na maua o le HDCP TYPE 1 (o lona uiga, streamid_type mai le RX IP o loʻo faʻamaonia) ma o le vitio na lafoina o le HDCP 1.4 faʻailoga (ie faʻailoga tulaga hdcp1_enabled mai le TX IP ua faʻamaonia)
• E tatau ona e tausia le agatapuia ma le fa'amaoni o au ki gaosiga o le HDCP, ma so'o se ki fa'ailoga tagata fa'aoga.
• Ua fautuaina malosi oe e Intel e atia'e so'o se poloketi a le Intel Quartus Prime ma le puna mamanu files o lo'o i ai ki fa'ailoga i totonu o se si'osi'omaga fa'akomepiuta malupuipuia e puipuia ai ki.
• E fautuaina malosi oe e Intel e fa'aoga foliga saogalemu o mamanu i totonu o FPGA e puipuia ai le mamanu, e aofia ai so'o se ki fa'ailoga fa'apipi'i, mai kopi e le'i fa'atagaina, fa'ainisinia fa'aliliu, ma tampsese.

Fa'amatalaga Fa'atatau
AN 556: Fa'aaogaina o Fa'ailoga Puipuiga i totonu ole Intel FPGAs

4.6. Debug Taiala
O lenei vaega o loʻo faʻamatalaina ai le faʻailoga o le tulaga HDCP aoga ma faʻasologa o polokalama e mafai ona faʻaogaina mo le faʻaogaina. O lo'o iai fo'i fesili e masani ona fesiligia (FAQ) e uiga i le fa'atinoina o le mamanu fa'amuaample.

4.6.1. HDCP Tulaga Fa'ailoga
E tele faʻailoga e aoga e faʻamaonia ai le tulaga galue o le HDCP IP cores. O fa'ailoga nei o lo'o maua ile design example pito i luga ma o loʻo nonoa i luga o LEDs:

Igoa Faailoga	Galuega
hdcp1_enabled_rx	RX HDCP1x IP Decryption Tulaga 0: Le toaga 1: Gaoioiga
hdcp2_enabled_rx	RX HDCP2x IP Decryption Tulaga 0: Le toaga 1: Gaoioiga
hdcp1_enabled_tx	TX HDCP1x IP Encryption Tulaga 0: Le toaga 1: Gaoioiga
hdcp2_enabled_tx	TX HDCP2x IP Encryption Tulaga 0: Le toaga 1: Gaoioiga

Va'ai le Laulau 57 i le itulau 115 ma le Laulau 58 i le itulau 115 mo a la'ua fa'apipi'i LED.
O le tulaga malosi o nei faailo e faʻaalia ai o le HDCP IP o loʻo faʻamaonia ma mauaina / lafoina ata vitio faʻailoga. Mo itu ta'itasi, na'o le HDCP1x po'o le HDCP2x
fa'ailoga fa'ailoga/ decryption o lo'o galue. Mo example, pe afai o le hdcp1_enabled_rx poʻo le hdcp2_enabled_rx o loʻo galue, o le HDCP i luga o le RX e mafai ona faʻaogaina ma faʻamalo le ata vitio faʻailoga mai le puna vitio fafo.

4.6.2. Suia Fuafuaga Polokalama HDCP
Ina ia faʻafaigofieina le faʻaogaina o le HDCP, e mafai ona e suia faʻamaufaʻailoga i hdcp.c.
O le laulau o lo'o i lalo o lo'o aoteleina ai le lisi o ta'iala e mafai ona fa'atulagaina ma a latou galuega.

Parameter	Galuega
SUPPORT_HDCP1X	Fa'amalo le HDCP 1.4 ile itu TX
SUPPORT_HDCP2X	Fa'amalo le HDCP 2.3 ile itu TX
DEBUG_MODE_HDCP	Fa'aaga fe'au debug mo TX HDCP
REPEATER_MODE	Fa'aaga le faiga toe fai mo HDCP design example

Ina ia suia le fa'asologa, sui tau i mea taua i le hdcp.c. Aʻo leʻi amataina le tuʻufaʻatasia, fai le suiga lea i le build_sw_hdcp.sh:

1. Su'e le laina o lo'o i lalo ma fa'ailoa mai e puipuia ai le fa'aogaina o polokalame file ua suia i le uluai files mai le ala fa'apipi'i Intel Quartus Prime Software.
   
2.  Tafe le “./build_sw_hdcp.sh” e tuufaatasia ai le polokalame fou.
3. O le .elf ua gaosia file e mafai ona aofia i le mamanu e ala i auala e lua:
   a. Faʻaauau le "nios2-download -g file igoa>". Toe setiina le faiga pe a maeʻa le faʻagasologa o le downloadina ina ia mautinoa le faʻatinoina lelei.
   e. Faʻasolo le "quartus_cdb --update_mif" e faʻafou ai le amataga o le mafaufau files. Tafe le assembler e fau .sof fou file lea e aofia ai le polokalame faafou.

4.6.3. Fesili e fai soo (FAQ)
Laulau 59. Fa'ailoga Fa'aletonu ma Ta'iala

Numera	Fa'ailoga Fa'aletonu	Taiala
1.	O loʻo maua e le RX se vitio faʻailoga, ae o le TX o loʻo tuʻuina atu se ata vitio i le lanumoana poʻo le lanu uliuli.	E mafua ona o le le manuia o le TX faʻamaonia ma le goto fafo. E le tatau i se tagata e toe faia le HDCP ona mafai ona fa'asalalauina le vitio i se fa'ailoga e le'i fa'ailoga pe a fa'ailoga le vitio o lo'o sau mai le pito i luga. Ina ia ausia lenei mea, e suitulaga e se ata vitiō i le lanu moana po o le uliuli le ata e alu ese pe a le toaga le faailo o le tulaga fa'ailoga TX HDCP a'o fa'agaoioi le faailo o le tulaga decryption RX HDCP. Mo ta'iala sa'o, tagai ile Manatuga Puipuiga i le itulau 117. Peita'i, o lenei amio e ono fa'alavelaveina ai le fa'agasologa o le fa'aogaina pe a fa'ataga le ata HDCP. O loʻo i lalo le auala e faʻamalo ai le poloka vitio i le mamanu exampLe: 1. Su'e le feso'ota'iga uafu o lo'o i lalo i le pito i luga ole mamanu fa'aample. O lenei uafu e patino ile module hdmi_tx_top. 2. Suia le feso'ota'iga uafu i le laina lea:
2.	TX HDCP fa'ailoga tulaga fa'ailoga o lo'o ola ae o le ata o le kiona o lo'o fa'aalia i le pito i lalo.	E mafua ona o le goto i lalo e le o sa'o le fa'ailogaina o le vitio fa'ailoga. Ia mautinoa e te tuʻuina atu le lalolagi tumau (LC128) i le TX HDCP IP. O le tau e tatau ona avea ma tau o le gaosiga ma sa'o.
3.	TX HDCP fa'ailoga tulaga fa'ailoga e le mautu pe le toaga i taimi uma.	E mafua lenei mea ona o le le manuia o le TX faʻamaonia ma le goto i lalo. Ina ia faafaigofieina le faiga o le debugging, e mafai ona e mafaia le DEBUG_MODE_HDCP parakalafa i hdcp.c. Fa'asino i Suia Fuafuaga Polokalama HDCP i le itulau e 118 i taiala. O le 3a-3c o loʻo mulimuli mai e mafai ona avea ma mafuaʻaga o le le manuia TX faʻamaonia.
3a.	O lo'o lolomi pea e le log debug software lenei fe'au "HDCP 1.4 e le o lagolagoina e le pito i lalo (Rx)".	O le fe'au o lo'o fa'ailoa mai e le lagolagoina uma e le goto i lalo le HDCP 2.3 ma le HDCP 1.4. Ia mautinoa o lo'o lagolagoina e le goto i lalo le HDCP 2.3 po'o le HDCP 1.4.
3b.	TX fa'amaoni ua le manuia i le afa.	E mafua lenei mea i soʻo se vaega o le faʻamaoniga TX e pei o le saini faʻamaonia, siaki nofoaga ma isi e mafai ona toilalo. Ia mautinoa o lo'o fa'aogaina e le fa'apa i lalo le ki o le gaosiga ae le o le facsimile key.
3c.	O lo'o lolomi pea e le log debug software le “Re-authentication	O le fe'au lea e ta'u mai ai ua talosaga le goto i lalo e toe fa'amaonia ona e le'i fa'asa'o sa'o le vitio na maua. Ia mautinoa e te tuʻuina atu le lalolagi tumau (LC128) i le TX HDCP IP. O le tau e tatau ona avea ma tau o le gaosiga ma sa'o le tau.
faaauau…

Numera	Fa'ailoga Fa'aletonu	Taiala
	e mana'omia” pe a mae'a le fa'amaoniga a le HDCP.
4.	RX HDCP decryption tulaga faailo e le o galue e ui o le puna i luga ua mafai ai le HDCP.	O loʻo faʻaalia ai o le RX HDCP IP e leʻi ausia le tulaga faʻamaonia. Ona o le faaletonu, o le REPEATER_MODE ua mafai le parakalafa i le mamanu example. Afai o le REPEATER_MODE ua mafai, ia mautinoa ua fa'amaonia le TX HDCP IP. Ina ua le REPEATER_MODE e mafai ona fa'agata, o le RX HDCP IP e taumafai e fa'amaonia e fai ma toe fai pe afai e feso'ota'i le TX i se fa'agogo e mafai ona maua i le HDCP. O le faʻamaoniga e tu i le afa aʻo faʻatali mo le TX HDCP IP e faʻamaeʻa le faʻamaoniga i lalo ifo o le goto ma pasi le RECEIVERID_LIST i le RX HDCP IP. Taimi e fa'amanino i le HDCP Fa'amatalaga e 2 sekone. Afai e le mafai e le TX HDCP IP ona faʻamaeʻaina le faʻamaoniga i lenei vaitau, o le puna i luga e faʻaogaina le faʻamaoniga e le manuia ma amataina le toe faʻamaonia e pei ona faʻamaonia i le HDCP Specification.
		Fa'aaliga: • Fa'asino i Suia Fuafuaga Polokalama HDCP i le itulau 118 mo le auala e tape ai le REPEATER_MODE parakalafa mo le faʻamoemoeina o le debugging. Ina ua uma ona tape le REPEATER_MODE parakalafa, o le RX HDCP IP taumafai i taimi uma le faʻamaoni e avea o se faʻaiʻuga e taliaina. O le TX HDCP IP e le faʻaogaina le faʻagasologa o faʻamaoniga.
		• Afai o le REPEATER_MODE e le mafai ona fa'aogaina, ia mautinoa o le ki HDCP o lo'o tu'uina atu i le HDCP IP o le tau o le gaosiga ma sa'o le tau.
5.	RX HDCP decryption tulaga faailo e le mautu.	O lona uiga ua talosagaina e le RX HDCP IP le toe faʻamaonia i le taimi lava na ausia ai le tulaga faʻamaonia. Atonu e mafua ona o le vitio faʻailoga o loʻo sau e le o faʻasaʻo saʻo e le RX HDCP IP. Ia mautinoa o le lalolagi tumau (LC128) o loʻo tuʻuina atu i le RX HDCP IP autu o le gaosiga o le tau ma le tau e saʻo.

HDMI Intel Arria 10 FPGA IP Design Example User Guide Archives

Mo fa'amatalaga lata mai ma muamua o lenei ta'iala fa'aoga, fa'asino ile HDMI Intel® Arria 10 FPGA IP Design Example User Guide. Afai e le o lisiina se IP po'o se polokalama faakomepiuta, e fa'aoga le ta'iala mo le IP muamua po'o le polokalama faakomepiuta.
IP versions e tutusa ma le Intel Quartus Prime Design Suite software versions up to v19.1. Mai le Intel Quartus Prime Design Suite software version 19.2 pe mulimuli ane, IP
o lo'o iai se polokalame fa'aliliuga IP fou.

Toe Iloilo Tala'aga mo HDMI Intel Arria 10 FPGA IP Design Example User Guide

Fa'amatalaga Fa'amaumauga	Intel Quartus Prime Version	IP Version	Suiga
2022.12.27	22.4	19.7.1	Fa'aopoopoina se fa'ailoga fou mo le filifilia o le HDMI daughter card revision i le vaega Meafaigaluega ma Polokalama Manaoga o le mamanu example mo HDMI 2.0 (le-FRL mode).
2022.07.29	22.2	19.7.0	• Fa'asilasilaga o le aveeseina o le vaega Cygwin mai le Windows* version of Nios II EDS ma le mana'oga e fa'apipi'i le WSL mo Windows* tagata fa'aoga. • Fa'afouina le fa'asologa o kata tama teine ​​mai le Toefuata'iga 4 i le 9 pe a talafeagai i le pepa atoa.
2021.11.12	21.3	19.6.1	• Fa'afou le vaega Fa'atau oloa ki fa'ailoga HDCP i totonu o le flash memory i fafo po'o le EEPROM (Support HDCP Key Management = 1) e fa'amatala ai le fa'aoga fou o le fa'aogaina o polokalama fa'ailoga (KEYENC). • Aveese fuainumera nei: — Fa'asologa o fa'amaumauga o Facsimile Key R1 mo RX Private Key — Fa'asologa o fa'amaumauga o ki o le HDCP Production (Placeholder) - Fa'asologa o fa'amaumauga o le HDCP Protection Key (fa'a'i fa'asinomaga) — O le ki puipui o le HDCP na amatalia ile hdcp2x_tx_kmem.mif — HDCP puipuiga ki na amata i hdcp1x_rx_kmem.mif — O le ki puipui o le HDCP na amatalia ile hdcp1x_tx_kmem.mif • Siitia le vaega ole HDCP Key Mapping mai le DCP Key Files mai le Debug Guidelines e teu ai ki fa'apitoa o le gaosiga o le HDCP i le FPGA (Support HDCP Key Management = 0).
2021.09.15	21.1	19.6.0	Ave'esea fa'amatalaga ile ncsim
2021.05.12	21.1	19.6.0	• Faaopoopo pe a SUPPORT FRL = 1 poʻo le SUPPORT HDCP KEY MANAGEMENT = 1 i le faʻamatalaga mo le Ata 29 HDCP Over HDMI Design Example Ata poloka. • Fa'aopoopoina laasaga ile HDCP key memory files i Design Walkthrough. • Fa'aopoopo pe a SUPPORT FRL = 0 i le vaega Seti le ardware. • Fa'aopoopo le la'asaga e fa'aola ai le Lagolago HDCP Fa'atonu Fa'atonu Fa'atonu i le Fa'atupuina le Fuafuaga. • Fa'aopoopoina se vaega fou Fa'atau ki fa'ailoga HDCP i totonu o le flash memory fafo po'o le EEPROM (Support HDCP Key Management = 1).
faaauau…

Fa'amatalaga Fa'amaumauga	Intel Quartus Prime Version	IP Version	Suiga
			• Toe fa'aigoaina le Fa'aigoa o le La'a'ai Fa'amau ma fa'ailoga ta'ita'i i le Push Button ma fa'ailoga LED (SUPPORT FRL = 0). • Fa'aopoopoina le Fa'amau o le Laulaupapa ma Fa'ailoga Fa'ailoga (SUPPORT FRL = 1). • Fa'aopoopoina se mataupu fou Puipuiga o Fa'ailoga Fa'amaufa'ailoga Fa'apipi'i ile FPGA Design. • Fa'aopoopoina se mataupu fou Debug Guidelines ma subsections HDCP Status Signals, Suia HDCP Software Parameter ma Fesili e Fai soo.
2021.04.01	21.1	19.6.0	• Fa'afouina Vaega Fa'atusa Mana'omia mo RX-Na'o po'o TX-Na'o Design. • Fa'afouina le Laulau ua Faia RTL Files. • Fa'afouina Ata HDMI RX Vaega Maualuga. • Ave'esea le Vaega HDMI RX Top Link Toleniga Fa'aa'oa'oga. • Fa'afouina laasaga i le Fa'atinoina o le Fuafuaga i Tau FRL Eseese. • Fa'afou Ata HDMI 2.1 Design Example Fuafuaga uati. • Fa'afou Fa'ailoga Fa'ailoga Fa'ailoga Fa'ailoga. • Fa'afouina Ata HDMI RX-TX Block Diagram e fa'aopoopo ai se feso'ota'iga mai le Transceiver Arbiter i le TX pito i luga.
2020.09.28	20.3	19.5.0	• Aveese le fa'amatalaga o le HDMI 2.1 mamanu example i le FRL mode e lagolagoina na o le saoasaoa grade –1 masini i le HDMI Intel FPGA IP Design Example Quick Start Guide mo Intel Arria 10 Devices ma HDMI 2.1 Design Example ( Lagolago FRL = 1) vaega. O le mamanu e lagolagoina uma togi saoasaoa. • Ave'esea fa'amatalaga ls_clk mai fa'ata'ita'iga uma HDMI 2.1 fa'atasiample vaega fesootai. O le ls_clk domain ua le toe fa'aogaina i le mamanu example. • Fa'afouina ata poloka mo le HDMI 2.1 fa'ata'ita'igaample i le FRL mode i le HDMI 2.1 Design Example ( Lagolago FRL = 1), Fausia RX- Na'o po'o TX-Na'o Fuafuaga Fuafuaga Vaega, ma vaega Clocking Scheme. • Fa'afouina fa'atonuga ma fa'atupuina files lisi i vaega Fa'atonu Fa'atonu. • Ave'ese fa'ailoga le talafeagai, ma fa'aopoopo pe fa'asa'o le fa'amatalaga o le fa'ailoga HDMI 2.1 fa'atasiampfaailoilo i le vaega o Fa'ailoga Fa'afeso'ota'i: — sys_init - txpll_frl_loka — tx_os — txphy_rcfg* faailoilo - tx_reconfig_done — txcore_tbcr — pio_in0_external_connection_export • Fa'aopoopo fa'amaufa'ailoga nei i le vaega Fa'ata'ita'i RTL Parameters: — EDID_RAM_ADDR_WIDTH — BITEC_DAUGHTER_CARD_REV - FA'A'OGA FPLL — POLARITY_INVERSION
faaauau…

Fa'amatalaga Fa'amaumauga	Intel Quartus Prime Version	IP Version	Suiga
			• Fa'afouina ata poloka mo le HDMI 2.0 fa'ata'ita'igaample mo le polokalama Intel Quartus Prime Pro Edition i le HDMI 2.0 Design Example ( Lagolago FRL = 0), Fausia RX-Na'o po'o TX-Na'o Fuafuaga Fuafuaga Vaega, ma vaega Clocking Scheme. • Fa'afouina le uati ma toe seti igoa fa'ailo i le vaega Dynamic Range and Mastering (HDR) InfoFrame Insertion and Filtering. • Ave'ese fa'ailoga le talafeagai, ma fa'aopoopo pe fa'asa'o le fa'amatalaga o le fa'ailoga HDMI 2.0 fa'ata'ita'iampfaailoilo i le vaega o Fa'ailoga Fa'afeso'ota'i: — clk_fpga_b3_p — REFCLK_FMCB_P — fmcb_la_tx_p_11 — fmcb_la_rx_n_9e — fr_clck - reset_xcvr_powerup — nios_tx_i2c* faailoilo — hdmi_ti_i2c* faailoilo — tx_i2c_avalon* faailoilo — alalaupapa_0_i_clk_clk — reset_bridge_0_reset_reset_n — i2c_master* faailoilo — nios_tx_i2c* faailoilo — fua_valid_pio_external_connectio n_fa'atau atu — oc_i2c_av_slave_translator_avalon_an ti_slave_0* faailoilo — powerup_cal_done_export — rx_pma_cal_busy_export — rx_pma_ch_export — rx_pma_rcfg_mgmt* faailoilo • Fa'aopoopoina se fa'amatalaga e le lagolagoina le su'ega fa'ata'ita'iga mo fa'ata'ita'iga ma le Fa'aaofia le I2C ua fa'ataga ma fa'afou le fe'au fa'ata'ita'i ile vaega Fa'ata'ita'iga Testbench. • Fa'afou le vaega Fa'aleleia o Lau Fuafuaga.
2020.04.13	20.1	19.4.0	• Faʻaopoopoina se faʻamatalaga e faʻapea o le HDMI 2.1 mamanu faʻatasiample i le FRL mode e lagolagoina na o le saoasaoa grade –1 masini i le HDMI Intel FPGA IP Design Example Quick Start Guide mo Intel Arria 10 Devices ma Fa'amatalaga Auiliili mo HDMI 2.1 Design Example ( Lagolago FRL = 1) vaega. • Si'i le HDCP I luga o le HDMI Design Example mo le vaega Intel Arria 10 Devices mai le HDMI Intel FPGA IP User Guide. • Fa'asa'o le vaega Fa'ata'ita'i o le Fuafuaga e aofia ai le leo sample generator, sideband fa'amaumauga fa'amaumauga, ma ausilali fa'amatalaga fa'aola ma fa'afou le fa'asologa manuia fe'au. • Aveese le fa'amatalaga o lo'o ta'ua fa'atusa e na'o avanoa mo Lagolago FRL fa'amatalaga mamanu fa'aletonu. Fa'ata'ita'iga ua avanoa nei mo Lagolago FRL fa'apena fo'i mamanu. • Faʻafouina le faʻamatalaga faʻamatalaga i le Faʻamatalaga Faʻamatalaga mo HDMI 2.1 Design Example ( Lagolago FRL Enabled) vaega.
faaauau…

Fa'amatalaga Fa'amaumauga	Intel Quartus Prime Version	IP Version	Suiga
			• Fa'asa'o le ata poloka i le HDMI 2.1 RX-TX Design Block Diagram, Design Components, ma le Fausiaina o vaega RX-Na'o po'o TX-Na'o Fuafuaga mo le HDMI 2.1 mamanu fa'atasi.ample. Fa'aopoopo vaega fou ma 'ave'ese vaega ua le toe fa'aogaina. • Fa'asa'o le fa'atonuga o tusitusiga main.c i le vaega Fa'atupu RX-Na'o po'o TX-Na'o Fuafuaga. • Fa'afou vaega Fa'atonu Fa'atonu e fa'aopoopo ai faila fou ma filemo HDMI 2.0 ma HDMI 2.1 mamanu examples. • Fa'afou le vaega o Meafaigaluega ma Polokalama Manaoga mo HDMI 2.1 fa'ata'ita'iga fa'atusaample. • Fa'afouina le poloka poloka ma fa'amatalaga fa'ailoga i le Dynamic Range and Mastering (HDR) InfoFrame Insertion and Filtering section mo HDMI 2.1 design example. • Fa'aopoopoina se vaega fou, Fa'agaoioi le Design i Eseese FRL Fuafuaga, mo le HDMI 2.1 design examples. • Fa'afouina le ata poloka ma fa'amatalaga fa'ailo i le vaega o le Clocking Scheme mo HDMI 2.1 design example. • Fa'aopoopo fa'amatalaga e uiga i sui DIP fa'aoga ile vaega Seti Meafaigaluega mo le HDMI 2.1 fa'ata'ita'iga fa'atusaample. • Fa'afouina le vaega Fa'atapula'a o Fuafuaga mo le HDMI 2.1 fa'ata'ita'iga fa'atasiample. • Fa'afou le vaega Fa'aleleia o Lau Fuafuaga. • Fa'afouina vaega o le Simulation Testbench mo le HDMI 2.0 ma le HDMI 2.1 design examples.
2020.01.16	19.4	19.3.0	• Fa'afouina le HDMI Intel FPGA IP Design Example Quick Start Guide mo Intel Arria 10 Devices vaega faʻatasi ai ma faʻamatalaga e uiga i le fou faʻaopoopo HDMI 2.1 design example fa'atasi ma le FRL mode. • Faʻaopoopoina se mataupu fou, Faʻamatalaga Faʻamatalaga mo HDMI 2.1 Design Example ( Lagolago FRL Enabled) o lo'o i ai fa'amatalaga talafeagai uma e uiga i le mamanu fou fa'aopoopo muamuaample. • Toe faaigoa le HDMI Intel FPGA IP Design Example Faʻamatalaga Faʻamatalaga i Faʻamatalaga Faʻamatalaga mo HDMI 2.0 Design Example mo le manino atili.
2019.10.31	18.1	18.1	• Fa'aopoopo fa'atupuina files i le faila tx_control_src: ti_i2c.c ma ti_i2c.h. • Fa'aopoopoina le lagolago mo le FMC daughter card toe teuteuga 11 i le Vaega o Meafaigaluega ma Polokalama Fa'atonu ma le Tu'ufa'atasia ma le Su'ega o le Fuafuaga. • Aveese le vaega Fa'atapula'a o Fuafuaga. O le tapula'a e uiga i le solia o le taimi i le maualuga o le fa'alavelave fa'aletonu na fo'ia i le fa'aliliuga 18.1 o le HDMI Intel FPGA IP. • Fa'aopoopoina se parakalafa RTL fou, BITEC_DAUGHTER_CARD_REV, ina ia mafai ai ona e filifilia le toe teuteuga o le Bitec HDMI daughter card.
faaauau…

Fa'amatalaga Fa'amaumauga	Intel Quartus Prime Version	IP Version	Suiga
			• Fa'afouina le fa'amatalaga mo fa'ailoga fmcb_dp_m2c_p ma fmcb_dp_c2m_p e aofia ai fa'amatalaga e uiga i fa'amatalaga FMC daughter card 11, 6, ma le 4. • Fa'aopoopo fa'ailoga fou nei mo le toe iloiloga 11 o le kata tama a le Bitec: — hdmi_tx_ti_i2c_sda — hdmi_tx_ti_i2c_scl — oc_i2c_master_ti_avalon_anti_slave_a ddress — oc_i2c_master_ti_avalon_anti_slave_w sauniga — oc_i2c_master_ti_avalon_anti_slave_r eaddata — oc_i2c_master_ti_avalon_anti_slave_w ritedata — oc_i2c_master_ti_avalon_anti_slave_w aitrequest • Fa'aopoopoina se vaega e uiga i le Fa'aleleia o Lau Fuafuaga.
2017.11.06	17.1	17.1	• Toe fa'aigoa HDMI IP autu ile HDMI Intel FPGA IP e pei ole Intel rebranding. • Suia le upu Qsys i le Platform Designer. • Fa'aopoopo fa'amatalaga e uiga i le Dynamic Range ma le Mastering InfoFrame (HDR) fa'aofiina ma le fa'avasegaina. • Fa'afouina le fa'atulagaina o fa'amaumauga: - Faʻaopoopo faʻamaumauga ma faila polokalama ma files. - Faʻafouina masani ma hdr files. — Aveese atx files. — Eseese filemo le Intel Quartus Prime Standard Edition ma le Intel Quartus Prime Pro Edition. • Fa'afouina le vaega o le Fa'atupuina o le Fuafuaga e fa'aopoopo ai le masini fa'aoga 10AX115S2F4I1SG. • Fa'asa'o le fua faatatau o fa'amatalaga mo le 50-100 MHz TMDS uati i le 2550-5000 Mbps. • Fa'afou le fa'amatalaga feso'ota'iga RX-TX e mafai ona e fa'amatu'u le fa'amau user_pb[2] e fa'amalo ai le fa'amama i fafo. • Fa'afouina le fa'asologa o polokalame fa'atekonolosi a le Nios II e aofia ai fa'atonuga mo le I2C matai ma le puna HDMI. • Fa'aopoopoina fa'amatalaga e uiga i le Design Example GUI tapula'a. • Fa'aopoopoina le HDMI RX ma le TX pito i luga ole mamanu. • Fa'aopoopoina fa'ailoga pito i luga o le HDMI RX ma le TX: — mgmt_clk - toe setiina — i2c_clk — hdmi_clk_in - Aveese nei faʻailoga maualuga HDMI RX ma TX: • lomiga • i2c_clk
faaauau…

Fa'amatalaga Fa'amaumauga	Intel Quartus Prime Version	IP Version	Suiga
			• Faʻaopoopoina se faʻamatalaga o le transceiver analog setting e suʻeina mo le Intel Arria 10 FPGA Development Kit ma le Bitec HDMI 2.0 Daughter card. E mafai ona e suia le seti analog mo lau laupapa. • Fa'aopoopoina se feso'ota'iga mo le ta'amilosaga e aloese ai mai le fa'afefe o le PLL cascading po'o ala e le fa'apitoa mo le Intel Arria 10 PLL fa'asino uati. • Fa'aopoopoina se fa'amatalaga e le mafai ona e fa'aogaina se pine transceiver RX e fai ma CDR refclk mo HDMI RX po'o se TX PLL refclk mo HDMI TX. • Fa'aopoopoina se fa'amatalaga e fa'atatau i le fa'aopoopoina o le fa'agata set_max_skew mo mamanu e fa'aogaina ai le TX PMA ma le PCS so'oga.
2017.05.08	17.0	17.0	• Toe fa'ailogaina o le Intel. • Suia le numera o vaega. • Fa'afouina le fa'atulagaina o fa'amaumauga: - Faʻaopoopo hdr files. — Suia qsys_vip_passthrough.qsys i le nios.qsys. — Faaopoopo files ua tofia mo Intel Quartus Prime Pro Edition. • Fa'amatalaga fa'afou e fa'apea o lo'o fa'atinoina fo'i e le poloka RX-TX Link le fa'amama i fafo i le High Dynamic Range (HDR) Infoframe mai le HDMI RX auxiliary data ma fa'aofi se ex.ample HDR Infoframe i faʻamatalaga ausilali o le HDMI TX e ala i Avalon ST multiplexer. • Faʻaopoopoina se faʻamatalaga mo le Transceiver Native PHY faʻamatalaga e faʻamalieina le HDMI TX inter-channel skew manaʻomia, e te manaʻomia le setiina o le TX channel bonding mode option i le Arria 10 Transceiver Native PHY editor parameter i PMA ma PCS so'oga. • Fa'afou fa'amatalaga mo os ma fua fa'ailoga. • Suia le ovaampling factor mo fa'amatalaga fa'amatalaga eseese transceiver i ta'i ta'itasi TMDS uati fa'avevesi laina e lagolago TX FPLL polokalame uati sa'o. • Suia le TX IOPLL ile TX FPLL cascade clocking scheme ile TX FPLL direct scheme. • Fa'aopoopo TX PMA fa'ailoga toe fa'atulagaina. • Fa'atonu USER_LED[7] ovaamptulaga ling. 1 o loʻo faʻaalia ai le sili atuamptaʻitaʻia (faʻamatalaga faʻamatalaga <1,000 Mbps i Arria 10 masini). • Fa'afouina HDMI Design Example laulau Simulators Lagolago. VHDL e le lagolagoina mo NCSim. • Fa'aopoopo le feso'ota'iga i fa'amaumauga fa'amaumauga o le Arria 10 HDMI IP Core Design Example User Guide.
2016.10.31	16.1	16.1	Fa'asalalauga muamua.

Intel Corporation. Ua taofia aia tatau uma. Intel, le Intel logo, ma isi fa'ailoga Intel o fa'ailoga fa'ailoga a le Intel Corporation po'o ona lala. E fa'amaonia e Intel le fa'atinoina o ana oloa FPGA ma semiconductor i fa'amatalaga o lo'o iai nei e tusa ai ma le fa'atonuga masani a Intel, ae fa'asaoina le aia tatau e fai ai suiga i so'o se oloa ma auaunaga i so'o se taimi e aunoa ma se fa'aaliga. E leai se tiute po'o se noataga e afua mai i le talosaga po'o le fa'aogaina o so'o se fa'amatalaga, oloa, po'o se auaunaga o lo'o fa'amatalaina i i'i se'i vagana ua malilie i ai i se faiga tusitusia e Intel. Ua fautuaina tagata fa'atau Intel ina ia maua le fa'amatalaga lata mai o fa'amatalaga masini a'o le'i fa'alagolago i so'o se fa'amatalaga fa'asalalau ma a'o le'i tu'uina atu oka mo oloa po'o tautua. *O isi igoa ma fa'ailoga e mafai ona ta'ua o se meatotino a isi.

Faʻasinomaga Faʻainitaneti
Lauina Manatu
ID: 683156
Fa'aliliuga: 2022.12.27

Pepa / Punaoa

intel HDMI Arria 10 FPGA IP Design Example [pdf] Taiala mo Tagata Fa'aoga HDMI Arria 10 FPGA IP Design Example, HDMI Arria, 10 FPGA IP Design Example, Design Example

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