Kusintha kwa Microsemi IGLOO2 HPMS DDR Controller
Mawu Oyamba
IGLOO2 HPMS ili ndi chowongolera cha DDR (HPMS DDR). Chowongolera ichi cha DDR chimapangidwa kuti chiziwongolera kukumbukira kwa DDR. Wowongolera wa HPMS DDR atha kupezeka kuchokera ku HPMS (pogwiritsa ntchito HPDMA) komanso kuchokera ku nsalu ya FPGA.
Mukamagwiritsa ntchito System Builder kuti mupange chipika chomwe chimaphatikizapo HPMS DDR, System Builder imakukonzerani chowongolera cha HPMS DDR kutengera zomwe mwalemba komanso zomwe mwasankha.
Palibe kusintha kosiyana kwa HPMS DDR kofunikira ndi wogwiritsa ntchito. Kuti mudziwe zambiri, chonde onani Buku la IGLOO2 System Builder User's Guide.
Womanga System
Womanga System
Mu em Builder kukonza HPMS DDR basi.
- Pazida za Chipangizo cha System Builder, onani HPMS External DDR Memory (HPMS DDR).
- Patsamba la Memories, sankhani Mtundu wa Memory wa DDR:
- DDR2
- DDR3
- Chithunzi cha LPDDR
- Sankhani Kukula kwa DDR Memory: 8, 16 kapena 32
- Onani ECC ngati mukufuna kukhala ndi ECC ya DDR.
- Lowetsani DDR kukumbukira nthawi. Iyi ndi nthawi yomwe kukumbukira kwa DDR kumafuna kuyambitsa.
- Dinani Import Registry Configuration kuti mulowetse zolembera za FDDR kuchokera pamawu omwe alipo file zomwe zili ndi ma registry. Onani Table 1 ya kasinthidwe ka registry file mawu ofotokozera.
Libero amangosunga zosintha izi mu eNVM. FPGA ikakhazikitsanso, zosinthazi zidzakopera zokha ku HPMS DDR.
Chithunzi 1 • Womanga System ndi HPMS DDR
Table 1 • Kulembetsa Kukonzekera File Syntax
- ddrc_dyn_soft_reset_CR 0x00 ;
- ddrc_dyn_refresh_1_CR 0x27DE ;
- ddrc_dyn_refresh_2_CR 0x30F ;
- ddrc_dyn_powerdown_CR 0x02 ;
- ddrc_dyn_debug_CR 0x00 ;
- ddrc_ecc_data_mask_CR 0x0000 ;
- ddrc_addr_map_col_1_CR 0x3333 ;
Kusintha kwa HPMS DDR Controller
Mukamagwiritsa ntchito HPMS DDR Controller kuti mupeze DDR Memory yakunja, DDR Controller iyenera kukhazikitsidwa panthawi yothamanga. Izi zimachitika polemba zidziwitso zamasinthidwe kumakaundula odzipatulira a DDR. Mu IGLOO2, eNVM imasunga zidziwitso za kasinthidwe kaundula ndipo FPGA ikakhazikitsanso, zosinthazo zimakopera kuchokera ku eNVM kupita ku zolembetsa zodzipatulira za HPMS DDR kuti ziyambitsidwe.
HPMS DDR Control Registers
HPMS DDR Controller ili ndi zolembera zomwe ziyenera kukonzedwa panthawi yothamanga. Miyezo ya masinthidwe a zolembetsazi imayimira magawo osiyanasiyana, monga DDR mode, PHY wide, burst mode, ndi ECC. Kuti mumve zambiri za kaundula wa kasinthidwe ka DDR chonde onani Maupangiri Ogwiritsa Ntchito a Microsemi IGLOO2
HPMS MDDR Registry Configuration
Kufotokozera za DDR Register mfundo:
- Gwiritsani ntchito cholembera kunja kwa Libero SoC, konzekerani mawu file zomwe zili ndi mayina a Register ndi zikhalidwe, monga momwe zilili Chithunzi 1-1.
- Kuchokera pa Memory Builder's Memory tabu, dinani Kukonzekera Kulembetsa kwa Import.
- Yendani mpaka pomwe pali zolemba za Registration Configuration file mwakonzekera mu Gawo 1 ndikusankha file kuitanitsa.
Chithunzi 1-1 • Lembani Zosintha Zosintha - Mawonekedwe a Malemba
HPMS DDR Kuyambitsa
Deta ya Register Configuration yomwe mumatumiza ku HPMS DDR imakwezedwa mu eNVM ndikukopereredwa ku registry ya kasinthidwe ka HPMS DDR mukakhazikitsanso FPGA. Palibe chochita chofunikira kuti muyambitse HPMS DDR panthawi yothamanga. Kukhazikitsa kodzipangira kumeneku kumapangidwanso mongoyerekeza.
Kufotokozera kwa Port
DDR PHY mawonekedwe
Madoko awa amawonekera pamlingo wapamwamba wa block yopangidwa ndi System Builder. Kuti mudziwe zambiri, onani Buku la IGLOO2 System Builder User Guide. Lumikizani madoko awa ku kukumbukira kwanu kwa DDR.
Table 2-1 • DDR PHY Interface
| Dzina la Port | Mayendedwe | Kufotokozera |
| MDDR_CAS_N | OUT | Chithunzi cha DRAM CASN |
| MDDR_CKE | OUT | Chithunzi cha DRAM CKE |
| MDDR_CLK | OUT | Clock, P side |
| MDDR_CLK_N | OUT | Clock, N side |
| MDDR_CS_N | OUT | Chithunzi cha DRAM CSN |
| MDDR_ODT | OUT | Chithunzi cha DRAM ODT |
| MDDR_RAS_N | OUT | Chithunzi cha DRAM RASN |
| MDDR_RESET_N | OUT | Kukonzanso kwa DRAM kwa DDR3 |
| MDDR_WE_N | OUT | DRAM WEN |
| MDDR_ADDR[15:0] | OUT | Ma adilesi a Dram |
| MDDR_BA[2:0] | OUT | Adilesi ya Dram Bank |
| MDDR_DM_RDQS ([3:0]/[1:0]/[0]) | PAKATI | Dram Data Mask |
| MDDR_DQS ([3:0]/[1:0]/[0]) | PAKATI | Kulowetsa / Kutulutsa kwa Dram Data Strobe - P Side |
| MDDR_DQS_N ([3:0]/[1:0]/[0]) | PAKATI | Kulowetsa / Kutulutsa kwa Dram Data Strobe - N Mbali |
| MDDR_DQ ([31:0]/[15:0]/[7:0]) | PAKATI | DRAM Data Input/Zotulutsa |
| MDDR_DQS_TMATCH_0_IN | IN | FIFO mu chizindikiro |
| MDDR_DQS_TMATCH_0_OUT | OUT | Chizindikiro cha FIFO |
| MDDR_DQS_TMATCH_1_IN | IN | FIFO mu siginecha (32-bit kokha) |
| MDDR_DQS_TMATCH_1_OUT | OUT | Chizindikiro cha FIFO (32-bit kokha) |
| MDDR_DM_RDQS_ECC | PAKATI | Dram ECC Data Mask |
| MDDR_DQS_ECC | PAKATI | Dram ECC Data Strobe Input / Output - P Side |
| MDDR_DQS_ECC_N | PAKATI | Dram ECC Data Strobe Input / Output - N Mbali |
| MDDR_DQ_ECC ([3:0]/[1:0]/[0]) | PAKATI | DRAM ECC Data Input/Output |
| MDDR_DQS_TMATCH_ECC_IN | IN | ECC FIFO mu chizindikiro |
| MDDR_DQS_TMATCH_ECC_OUT | OUT | Chizindikiro cha ECC FIFO (32-bit kokha) |
M'lifupi mwa madoko pamadoko ena amasintha malinga ndi kusankha kwa PHY m'lifupi. Mawu akuti “[a:0]/[b:0]/[c:0]” amagwiritsidwa ntchito kutanthauza madoko, pomwe “[a:0]” amatanthauza m'lifupi mwa doko pamene m'lifupi mwa 32-bit PHY wasankhidwa. , "[b:0]" imagwirizana ndi 16-bit PHY m'lifupi, ndipo "[c:0]" imagwirizana ndi 8-bit PHY m'lifupi.
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Kusintha kwa Microsemi IGLOO2 HPMS DDR Controller [pdf] Buku Logwiritsa Ntchito IGLOO2 HPMS DDR Configuration Controller, IGLOO2, HPMS DDR Configuration Configuration, DDR Controller Configuration, Configuration |
