Microsemi IGLOO2 HPMS DDR Kanfigareshan

Gabatarwa

IGLOO2 HPMS yana da mai sarrafa DDR (HPMS DDR). An yi nufin wannan mai sarrafa DDR don sarrafa ƙwaƙwalwar DDR-chip. Ana iya samun dama ga mai sarrafa HPMS DDR daga HPMS (ta amfani da HPDMA) da kuma daga masana'anta na FPGA.
Lokacin da kuke amfani da Mai Gina Tsarin don gina shingen tsarin wanda ya haɗa da HPMS DDR, Mai Gina Tsarin yana tsara muku mai sarrafa HPMS DDR dangane da shigarwar ku da zaɓinku.
Babu keɓantaccen saitin HPMS DDR ta mai amfani da ake buƙata. Don cikakkun bayanai, da fatan za a koma zuwa Jagorar Mai Amfani da Mai Gina Tsarin IGLOO2.
Mai Gina Tsarin

Mai Gina Tsarin

A cikin em Builder don saita HPMS DDR ta atomatik.

1.  A cikin Siffofin Na'ura shafin na Mai Gina Tsarin, duba HPMS External DDR Memory (HPMS DDR).
2. A cikin Memories tab, zaɓi nau'in ƙwaƙwalwar DDR:
   • DDR2
   •  DDR3
   • LPDDR
3. Zaɓi Nisa na ƙwaƙwalwar DDR: 8, 16 ko 32
4. Bincika ECC idan kuna son samun ECC don DDR.
5. Shigar da lokacin saitin ƙwaƙwalwar ajiyar DDR. Wannan shine lokacin da ƙwaƙwalwar DDR ke buƙatar farawa.
6. Danna Shigo da Kanfigareshan Rijistar don shigo da ƙimar Rajista na FDDR daga rubutun da ke akwai file mai ɗauke da ƙimar rajista. Duba Tebu 1 don daidaitawar rajista file syntax.
   Libero yana adana bayanan sanyi ta atomatik a cikin eNVM. Bayan sake saitin FPGA, wannan bayanan sanyi za a kwafi ta atomatik zuwa cikin HPMS DDR.

Hoto 1 • Mai Gina Tsari da HPMS DDR

Tebur 1 • Kanfigareshan Rijista File Daidaitawa

• ddrc_dyn_soft_reset_CR 0x00 ;
• ddrc_dyn_refresh_1_CR 0x27DE ;
• ddrc_dyn_refresh_2_CR 0x30F ;
• ddrc_dyn_powerdown_CR 0x02 ;
• ddrc_dyn_debug_CR 0x00 ;
• ddrc_ecc_data_mask_CR 0x0000 ;
• ddrc_addr_map_col_1_CR 0x3333 ;

HPMS DDR Kanfigareshan

Lokacin da kake amfani da Mai Kula da HPMS DDR don samun dama ga ƙwaƙwalwar DDR na waje, dole ne a fara mai sarrafa DDR a lokacin aiki. Ana yin wannan ta hanyar rubuta bayanan daidaitawa zuwa keɓaɓɓen rijistar daidaitawar mai sarrafa DDR. A cikin IGLOO2, eNVM yana adana bayanan saitin rijistar kuma bayan sake saitin FPGA, ana kwafin bayanan daidaitawa daga eNVM zuwa rijistar kwazo na HPMS DDR don farawa.

HPMS DDR Control Rajista
Mai Kula da DDR DDR na HPMS yana da saitin rajista waɗanda ke buƙatar saita su a lokacin aiki. Ƙimar daidaitawa don waɗannan rijistar suna wakiltar sigogi daban-daban, kamar yanayin DDR, faɗin PHY, yanayin fashewa, da ECC. Don cikakkun bayanai game da rijistar daidaitawar mai sarrafa DDR don Allah koma zuwa Jagorar Mai amfani Microsemi IGLOO2
Kanfigareshan Rijistar HPMS MDDR

Don tantance ƙimar rajistar DDR:

1. Yi amfani da editan rubutu a wajen Libero SoC, shirya rubutu file dauke da sunaye da dabi'u na Rajista, kamar yadda yake cikin Hoto 1-1.
2. Daga Maginin Ƙwaƙwalwar Ƙwaƙwalwar Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwaƙwalwa na Ƙaddamarwa ya yi, danna Shigo da Kanfigareshan Rijista.
3. Kewaya zuwa wurin rubutun Kanfigareshan Rijista file kun shirya a Mataki na 1 kuma zaɓi file shigo da kaya.

Hoto 1-1 • Bayanan Kanfigareshan Rijistar – Tsarin Rubutu

HPMS DDR Ƙaddamarwa
Ana loda bayanan Kanfigareshan Rijista da kuke shigo da su don HPMS DDR cikin eNVM kuma ana kwafe su zuwa rijistar sanyi na HPMS DDR akan sake saitin FPGA. Ba a buƙatar aikin mai amfani don fara HPMS DDR a lokacin aiki. Wannan farawa ta atomatik kuma ana ƙirƙira shi a cikin siminti.

Bayanin tashar jiragen ruwa

DDR PHY Interface
Ana fallasa waɗannan tashoshin jiragen ruwa a saman matakin da aka samar da Tsarin Mai Gina. Don cikakkun bayanai, tuntuɓi IGLOO2 Jagorar Mai Amfani Mai Gina Tsarin. Haɗa waɗannan tashoshin jiragen ruwa zuwa ƙwaƙwalwar ajiyar DDR ɗin ku.

Table 2-1 • DDR PHY Interface

Sunan tashar jiragen ruwa	Hanyar	Bayani
MDR_CAS_N	FITA	DRAM CASN
MDR_CKE	FITA	DRAM CKE
MDR_CLK	FITA	Agogo, P gefe
MDR_CLK_N	FITA	Agogo, N gefe
MDR_CS_N	FITA	DRAM CSN
MDR_ODT	FITA	Farashin ODT
MDR_RAS_N	FITA	Farashin RASN
MDR_RESET_N	FITA	Sake saitin DRAM don DDR3
MDR_WE_N	FITA	DRAM WEN
MDR_ADDR[15:0]	FITA	Dram Address ragowa
MDR_BA[2:0]	FITA	Adireshin Banki Dram
MDDR_DM_RDQS ([3:0]/[1:0]/[0])	CIKI	Dram Data Mask
MDDR_DQS ([3:0]/[1:0]/[0])	CIKI	Dram Data Strobe Input/Fitarwa - P Side
MDDR_DQS_N ([3:0]/[1:0]/[0])	CIKI	Dram Data Strobe Input/Fitarwa - N Gefe
MDDR_DQ ([31:0]/[15:0]/[7:0])	CIKI	Shigar da Bayanan DRAM / Fitarwa
MDR_DQS_TMATCH_0_IN	IN	FIFO a cikin sigina
MDR_DQS_TMATCH_0_OUT	FITA	FIFO fita siginar
MDR_DQS_TMATCH_1_IN	IN	FIFO a sigina (32-bit kawai)
MDR_DQS_TMATCH_1_OUT	FITA	Fitar siginar FIFO (32-bit kawai)
MDR_DM_RDQS_ECC	CIKI	Dram ECC Data Mask
MDR_DQS_ECC	CIKI	Dram ECC Data Strobe Input/Fitarwa - P Side
MDR_DQS_ECC_N	CIKI	Dram ECC Data Strobe Input/Fitarwa - N Gefe
MDDR_DQ_ECC ([3:0]/[1:0]/[0])	CIKI	DRAM ECC Data Input/Fitarwa
MDR_DQS_TMATCH_ECC_IN	IN	ECC FIFO a cikin sigina
MDR_DQS_TMATCH_ECC_OUT	FITA	ECC FIFO siginar fita (32-bit kawai)

Faɗin tashar jiragen ruwa na wasu tashoshin jiragen ruwa suna canzawa dangane da zaɓin faɗin PHY. Ana amfani da bayanin “[a:0]/[b:0]/[c:0]” don nuna irin waɗannan tashoshin jiragen ruwa, inda “[a:0]” ke nufin faɗin tashar idan aka zaɓi faɗin 32-bit PHY , "[b:0]" yayi daidai da fadin PHY-bit 16, kuma "[c:0]" yayi daidai da fadin PHY-bit 8.

Tallafin samfur

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Takardu / Albarkatu

Microsemi IGLOO2 HPMS DDR Kanfigareshan [pdf] Jagorar mai amfani IGLOO2 HPMS DDR Kanfigareshan, IGLOO2, HPMS DDR Kanfigareshan, DDR Controller Kanfigareshan, Kanfigareshan

Magana

• Manual mai amfani