Microsemi In-Circuit FPGA Debug

Ulwazi lweMveliso

Iinkcukacha

• Uhlobo lwesiXhobo: Microsemi SmartFusion2 SoC FPGA
• Umhla wokukhupha: ngoMeyi 2014
• Ubunakho bokulungisa ingxaki: KwiSekethe yeFPGA Debug, i-Embedded Logic Analyzer
• Ubuninzi beData yokuXhobisa iFrequency: Ukuya kuthi ga kwi-100MHz

Abstract
Ii-FPGA zizinto zoyilo ezinamandla kwiinkqubo ezizinzisiweyo ezine-advan yoyilo oluninzitages, kodwa ezi zixhobo zinokuba noyilo oluntsonkothileyo olunemiba yoyilo oluntsonkothileyo efuna ukulungiswa. Ukulandelela imiba yoyilo efana neempazamo zenkcazo, iingxaki zokusebenzisana kwenkqubo, kunye neempazamo zexesha lenkqubo kunokuba ngumngeni. Ukufakwa kwesakhono sokulungisa i-in-circuit debug kwi-FPGA kunokuphucula ngokumangalisayo i-hardware debug, kwaye kunqande iiyure ezingabalulekanga zokuphoxeka. Eli phepha lichaza iindlela ezininzi ezahlukeneyo zokulungisa ingxaki ye-FPGAs, ichonge urhwebo oluphambili, kunye ne-ex.ampi-design le, ejoliswe kwi-Microsemi SmartFusion®2 ye-SoC FPGA isixhobo, iya kubonisa indlela amandla amatsha angasetyenziselwa ngayo ukukhawuleza kunye nokuvavanya.

Intshayelelo

IiFPGA zizinto zoyilo ezigqubayo kwaye zinamandla kwaye ngoku zifumaneka phantse kuzo zonke iinkqubo ezizinzisiweyo. Ngokunyuka komthamo, ukubandakanywa kweebhloko ezisebenzayo kwi-chip kunye nojongano oluphezulu lwe-serial ezi zixhobo zinokuba neengxaki zoyilo ezintsonkothileyo ezifuna ukulungiswa. Ukulandelela imiba efana neempazamo zenkcazo yokusebenza (kwi-FPGA okanye kwinqanaba lenkqubo), iingxaki zokusebenzisana kwenkqubo yokusebenza, imiba yexesha lenkqubo, kunye nemiba yokuthembeka komqondiso phakathi kwe-ICs (njengengxolo, i-crosstalk, okanye izibonakaliso) zonke ziba nzima ngakumbi xa usebenzisa ii-FPGA eziphambili. Ukulinganisa ngokuqinisekileyo luncedo olukhulu ekuchongeni iingxaki ezininzi zoyilo, kodwa unxibelelwano oluninzi lwehlabathi lokwenyani aluyi kubonakala de uyilo luphunyezwe kwihardware. Iindlela ezininzi ezahlukeneyo zokulungisa imiba yoyilo oluntsonkothileyo ziye zaphuhliswa ukwenza inkqubo ibe lula. Ukuqonda ngokucokisekileyo nganye yezi ndlela ziphambili, kubandakanywa ne-advan eyahlukeneyotages kunye ne disadvantages, iluncedo xa kujongwa ukuba kobuphi na ubuchule okanye indibaniselwano yeendlela ezifanelekileyo kuyilo oluthile.
UmdalaampI-design ye-FPGA, ejoliswe kwisixhobo se-Microsemi SmartFusion2 SoC FPGA, ingasetyenziselwa ukubonisa ezinye ze-advantages kunye ne disadvantagEzobu buchule busemgangathweni ngokunjalo nobona buchule butsha bokulungisa kwisekethe. Lo mzekeliso exampLe izakubonisa ukuba ezi ndlela zahlukeneyo zingasetyenziswa njani ukukhawulezisa uchongo kunye nokuphelisa iingxaki zehardware ngexesha lolungiso lwehardware.

Kutheni le nto iFPGA iDebugging iNxibelelwano eBalulekileyo yoYilo lweNkqubo kunye noPhuhliso?
Ii-FPGA zinemifuziselo emibini ephambili yokusetyenziswa ezohlula kwezinye izinto zoyilo. Ii-FPGAs zinokusetyenziswa kwimveliso yemveliso okanye zinokusetyenziswa njengesithuthi sophuhliso ukubonisa okanye umboniso woyilo loyilo lwemveliso. Xa isetyenziswe njengesithuthi sokuvelisa, ii-FPGA zinokuba yinto ekujoliswe kuyo eguquguqukayo ngakumbi kune-ASIC okanye i-CPU-based based vehicles production. Oku kubaluleke ngakumbi kuyilo olutsha, olungekaphunyezwa kwihardware okwangoku. Uyilo oluneenketho ezahlukeneyo zokwakha zinokudalwa ngokulula kwaye zivavanywe ukuze ichongiwe uyilo olufanelekileyo. Ii-FPGA ezine-on-chip processors (SoC FPGAs) zenza kube nokwenzeka ukurhweba-off CPU-based processing kunye nehardware incediswe FPGA-based acceleration function. Ezi advantagI-es inokunciphisa kakhulu ixesha elifunekayo loyilo, ukuqinisekiswa, uvavanyo, kunye nohlalutyo lokungaphumeleli kuphuhliso lwemveliso entsha.
Xa isetyenziselwa iprototyping uyilo, mhlawumbi kwimveliso ye-ASIC, ukuguquguquka kweFPGA kuyinzuzo ephambili. Iqonga lokwenyani le-hardware, nelinye elingaqhubi ngesantya esipheleleyo, lenza kube lula kakhulu ukufumana i-metrics yenkqubo eneenkcukacha, idatha yokuhlalutya i-throughput kunye neziphumo zobungqina boyilo lwe-architecture. Inkxaso ye-FPGA yokwenziwa lukhuni kweebhasi ezisemgangathweni (ezifana ne-PCIe®, i-Gigabit Ethernet, i-XAUI, i-USB, i-CAN, kunye nezinye) yenza lula uvavanyo oluhambelana nolu nxibelelwano. Ezona ntsapho zintsha zeFPGAs ezineeprosesa ze-ARM ezikwi-chip (SoC FPGAs), zenza kube lula ukuphunyezwa kweprototype kunye neprosesa ezizinzisiweyo. Ikhowudi yeprosesa ephuhliswe ngaphambili inokufakwa kwiprototype kunye nekhowudi entsha eyenziwe ngokuhambelana nomzamo woyilo lwehardware.

Le ndibaniselwano yeprosesa esemgangathweni eneebhasi zojongano oluqhelekileyo yenza ukuba kukwazeke ukonyusa inkqubo enkulu yendalo ekhoyo yamathala eencwadi ekhowudi, abaqhubi, ii-API ezisebenzayo, iiNkqubo zokuSebenza ngexesha lokwenyani, kunye neeNkqubo zokuSebenza ezigcweleyo ukwenza ngokukhawuleza ngakumbi iprototype esebenzayo. Ukongeza, xa uyilo luqinisiwe, iprototype yeFPGA inokusetyenziselwa ukubamba iiseti zovavanyo olubanzi lokulinganisa (zombini uvuselelo kunye nempendulo) ebonisa idatha yenkqubo yokwenyani. Ezi seti zedatha zinokuba luncedo ekudaleni ukulinganisa kokugqibela kwe-ASIC okanye enye ukuphunyezwa kwemveliso. I-advantagUkusebenzisa i-FPGA njengeprototype yoyilo kunokunciphisa kakhulu ixesha loyilo, ukuqinisekiswa, ukuvavanywa, kunye nohlalutyo lokusilela ekuphunyezweni kwemveliso yokugqibela.
Kuzo zombini ezi ntlobo ziqhelekileyo zokusebenzisa i-FPGA ukuguquguquka kweFPGA njengenjongo yoyilo yi-advan engundoqo.tage. Oku kuthetha ukuba utshintsho oluninzi loyilo kunye nophindaphindo luya kuba yinto eqhelekileyo, kwaye ke amandla okulungisa ngokukhawuleza iimpazamo zoyilo kuya kubaluleka ekuvumela ukuba ube nokhetho loyilo oluninzi kangangoko kunokwenzeka. Ngaphandle kwesakhono esisebenzayo solungiso lweempazamo uninzi lwe-advantage ye FPGA uyilo bhetyebhetye iya kuncitshiswa ngexesha elongezelelweyo debugging elifunekayo. Ngethamsanqa, ii-FPGAs zinokubonelela ngeempawu ezongezelelweyo zehardware ezenza lula ulungiso lwexesha lokwenyani. Phambi kokujonga obu buchule, masiqale sijonge ezona ntlobo zixhaphakileyo zemiba uyilo lweFPGA enokujongana nayo ukuze sibe nemvelaphi efanelekileyo yokuvavanya ukusebenza kakuhle kunye norhwebo oluhambelanayo lwezixhobo ezahlukeneyo zokulungisa iimpazamo.

Imiba eqhelekileyo xa uLungisa ii-FPGA zoYilo

Kunye nesakhono esandisiweyo esiziswa ziiFPGAs zangoku, ukonyuka kobunzima obunxulumeneyo kwenza kube nzima ngakumbi ukwenza uyilo olungenaziphene. Ngapha koko, kuqikelelwa ukuba ukulungisa ingxaki kunokuthatha ngaphezulu kwe-50% yomjikelo woyilo lwenkqubo olungisiweyo. Ngoxinzelelo lwexesha lokuya kwintengiso oluqhubekayo ukucudisa umjikelezo wophuhliso, ukulungiswa kwe-hardware yenkqubo yokuqala kuhanjiswe emva kwengcamango-kaninzi kucingelwa ukuba ukuqinisekiswa (ngokwayo ipesenti enkulutage yeshedyuli yophuhliso), iyakubamba zonke iibugs phambi kokuzisa inkqubo yokuqala. Makhe sijonge kwiindidi ezimbalwa eziqhelekileyo zemiba yenkqubo ukuqonda ngcono imiceli mngeni uyilo oluqhelekileyo oluya kujongana nayo ngexesha lokuziswa kwenkqubo yokuqala.

Iimpazamo zenkcazo yokusebenza kunokuba nzima ngokuphindwe kabini ukuyifumana kuba umyili engayiqondi imfuneko ethile, ngoko ke impazamo inokungahoywa naxa ujongwa ngononophelo kwiinkcukacha zoyilo. Umzekeloample yempazamo yenkcazo yokusebenza eqhelekileyo iyakuba apho utshintsho lomatshini wombuso alupheli kwimeko elungileyo. Iimpazamo zinokuvela kwiinkqubo zojongano njengengxaki yonxibelelwano. Interface latency, umzekeloampI-le, inokuchazwa ngendlela engeyiyo ebangele ukuphuphuma kwebuffer engalindelekanga okanye imeko yokuphuphuma kwayo.
Imiba yexesha lenqanaba lenkqubo ngomnye umthombo oxhaphake kakhulu weempazamo zoyilo. Iziganeko ze-Asynchronous, ngokukodwa, zingumthombo oqhelekileyo weempazamo xa ungqamaniso okanye ukunqumla iziphumo zesizinda sexesha zingaqwalaselwa ngononophelo. Xa usebenza ngesantya ezi ntlobo zeempazamo zinokuba yingxaki kakhulu kwaye zinokubonakala zinqabile, mhlawumbi kuphela xa iipateni zedatha ethile zizibonakalisa. Ulwaphulo-mthetho oluninzi oluqhelekileyo lwexesha luwela kolu luhlu kwaye luhlala lunzima kakhulu, ukuba akunakwenzeka ukulinganisa.

Ulwaphulo lwexesha lunokuba ngumphumo wokunyaniseka kwesignali ephantsi phakathi kweesekethe ezidibeneyo, ngokukodwa kwiinkqubo ezinomzila wamandla amaninzi kwisekethe nganye. Ukunyaniseka kwesignali ephantsi kunokubangela ingxolo yomqondiso, i-crosstalk, izibonakaliso, ukulayisha ngokugqithiseleyo kunye nemiba ye-Electro-Magnetic Interference (EMI) ehlala ibonakalisa njengokuphulwa kwexesha. Imiba yobonelelo lwamandla, njengezinto ezidlulayo (ingakumbi ngexesha lokuqalisa inkqubo okanye ukuvala), ukwahluka komthwalo kunye noxinzelelo oluphezulu lokuchitha amandla nako kunokubangela iimpazamo ezingaqondakaliyo, amaxesha amaninzi azilandelelwanga ngokulula kumthombo wonikezelo lwamandla. Naxa uyilo luchanekile ngokupheleleyo imiba yokwenziwa kwebhodi inokubangela iimpazamo. Amalungu e-solder angalunganga kunye neziqhagamshelo ezincanyathiselwe ngokungafanelekanga, kwi-example, inokuba ngumthombo weempazamo kwaye inokuba ubushushu okanye indawo yebhodi ixhomekeke. Ukusetyenziswa kobuchule bokupakisha be-FPGA obuphambili bunokwenza kube nzima ukuphonononga imiqondiso kwibhodi yesekethe eprintiweyo ukuya, ke ukufikelela nje kuphawu olufunekayo kunokuba yingxaki. Amaxesha amaninzi imiba yoyilo ayidali mpazamo yangoko kwaye kufuneka iqhube kuyilo de impazamo izibonakalise. Ukulandela imposiso yokuqala ukubuyisela unobangela wengcambu kunokuba ngumsebenzi okhathazayo, onzima kwaye otya ixesha.

UmzekeloampLe, intwana enye engalunganga kwitafile yoguqulo ayinakukhokelela kwimpazamo kude kube yimijikelo emininzi kamva. Ezinye zezixhobo esiza kuxoxa ngazo kamva kweli phepha, ezisebenzisa ihardware yolungiso lweempazamo kwisekethe, zijolise ngokukodwa ekwenzeni oku 'kuzingelwa kweebug' kukhawuleze kwaye kube lula. Ngaphambi kokungena kwiinkcukacha zezi zixhobo, masiqale sijonge isoftware edumileyo esekwe kwi-debugging yokulinganisa ukulinganisa ukuze uqonde ngcono i-advan.tages kunye ne disadvantagukusebenzisa ukulinganisa ukulungisa ingxaki.

Ukusetyenziswa kokulinganisa ukulungisa ingxaki
Ngokwesiqhelo kulinganiso loyilo, zonke izinto zobomi bokwenyani ngaphakathi nangaphandle kuyilo zimodelwa ngokwezibalo njengeenkqubo zesoftware ezenziwa ngokulandelelanayo kwi-CPU eqhelekileyo. Ukusebenzisa uluhlu olubanzi lwe-stimulus kuyilo kunye nokujonga imveliso elindelekileyo ngokuchasene nemveliso yoyilo olufanisiweyo, yindlela elula yokubamba iimpazamo ezicacileyo zoyilo. Ifestile ebonisa ukubaleka okuqhelekileyo kunikwa kuMfanekiso 1 ngezantsi. I-advan ecacileyotagi-e ye-simulation verses hardware-based debugging, kukuba ukulinganisa kunokwenziwa kwi-software-akukho yi-hardware-based design kunye ne-testbench efunekayo. Ukulinganisa kunokukhawuleza ukubamba iimpazamo ezininzi zoyilo, ngakumbi ezo zinxulunyaniswa neenkcukacha ezingachanekanga, ukungaqondi kakuhle kweemfuno zojongano, iimpazamo zokusebenza, kunye nezinye iintlobo ezininzi zeempazamo ezibonwa ngokulula ngokusebenzisa iivektha ezilula zokuvuselela.

Ukulinganisa kusebenza ngokukodwa xa udibaniso olubanzi lwe-stimulus lufumaneka kumyili kwaye iziphumo ziyaziwa kakuhle. Kwezi meko, ukulinganisa kunokwenza uvavanyo oluphantse luphelele loyilo. Ngelishwa, uninzi loyilo alukwazi ukufikelela lula kwiisuti zovavanyo ezibanzi kwaye inkqubo yokuyidala inokuthatha ixesha elininzi. Ukudala i-suite yovavanyo egubungela i-100% yoyilo ngenyani ayinakwenzeka kuyilo olukhulu olusekwe kwiFPGA kunye neendlela ezimfutshane kufuneka zisetyenziswe ukuzama ukugubungela izinto eziphambili zoyilo. Obunye ubunzima bokulinganisa, kukuba ayisiyo 'ihlabathi lokwenyani' kwaye ayikwazi ukubamba iminyhadala engahambelaniyo, unxibelelwano lwenkqubo yesantya, okanye ukwaphulwa kwexesha. Okokugqibela, inkqubo yokulinganisa inokucotha kakhulu kwaye ukuba uphindaphindo oluninzi luyafuneka ukulinganisa ngokukhawuleza kuba lelona xesha lidlayo, kwaye kaninzi elona candelo libiza kakhulu lenkqubo yophuhliso.

Njengenye indlela (okanye mhlawumbi ichazwe ngcono, njengokongeza kukulinganisa) abaqulunqi beFPGA bafumanise ukuba banokongeza ihardware yolungiso kuyilo lweFPGA ukuze bajonge kwaye balawule imiqondiso engundoqo ngaphakathi kwesixhobo. Obu buchule buphuhliswe ekuqaleni njengeendlela ze-ad-hoc, kodwa ziye zaphuhliswa kancinci kancinci zaba sisicwangciso esiqhelekileyo sokulungiswa kwehardware. Oku kusetyenziswa kobuchule bokulungisa ingxaki kwisekethe kunika i-advan ebalulekileyotages kuyilo olusekwe FPGA kwaye icandelo elilandelayo liza kuphonononga amacebo amathathu aqhelekileyo kunye ne-advan yabo eyahlukeneyotages kunye ne disadvantages.

IiNdlela zokuLungisa kwiSekethe eziqhelekileyo kwiiFPGAs
Abona buchule buxhaphakileyo bokuphumeza isakhono se-in-circuit debug kwi-FPGAs sisebenzisa nokuba sisihlalutyi esizinzisiweyo se-logic, izixhobo zovavanyo lwangaphandle, okanye i-hardware ye-signal probe ezinikeleyo efakwe ngaphakathi kwelaphu le-FPGA. Isihlalutyi sengqiqo esizinzisiweyo siqhele ukusetyenziswa kusetyenziswa ilaphu leFPGA kwaye ifakwe kuyilo. UJTAG i-port isetyenziselwa ukufikelela kwi-analyzer kwaye idatha efunyenweyo ingaboniswa kwi-PC. Xa kusetyenziswa izixhobo zovavanyo lwangaphandle, uyilo lweFPGA phantsi kovavanyo luguqulwa ukuze imiqondiso ekhethiweyo yeFPGA yangaphakathi ihanjiswe kwizikhonkwane zemveliso. Ezi zikhonkwane zinokujongwa ngezixhobo zovavanyo lwangaphandle. Xa i-hardware yeprobe yesignali enikezelweyo isetyenziswa, ukhetho olubanzi lweempawu zangaphakathi lunokufundwa ngexesha langempela. Olunye uphunyezo lophando lunokusetyenziselwa ukubhala ukubhalisa okanye iindawo zememori eziphucula ngakumbi ubuchule bokulungisa. Makhe sijonge ngakumbi kwi-advantages kunye ne disadvantages nganye yezi ndlela kwaye ujonge i example uyilo ukuze ubone ukuba ezi ndlela zahlukeneyo zinokuchaphazela njani ixesha lokulungisa ngokupheleleyo.

KwiSekethe yeFPGA Debug-Embedded Logic Analyzer
Ingqikelelo yomhlalutyi wengqiqo ehlonyelweyo yaba sisiphumo esithe ngqo se-ad-hoc kwi-circuit debugging izakhono eziphunyezwe ngabayili xa iiFPGAs zaqala ukusetyenziswa. Abahlalutyi beengqiqo ezifakwe ngaphakathi bongeze amandla amatsha kwaye basusa imfuneko yokuba umyili aphuhlise i-analyzer yakhe. Uninzi lweeFPGAs zibonelela ngobu buchule kwaye amaqela esithathu anikezela ngabahlalutyi abasemgangathweni (Identify®, evela kwiSynopsys, yenye ex edumileyo.ample) enokuthi ngokulula ijongane nezixhobo zomgangatho ophezulu ukuphucula ngakumbi imveliso.

Umsebenzi we-logic analyser ufakwe kuyilo, usebenzisa i-FPGA ilaphu kunye neebhloko zememori ezizinzisiweyo njenge-trace buffers, njengoko kubonisiwe kuMzobo 2. Izixhobo zokuvuselela nazo zenziwe ukuze ukudibanisa kweempawu ezinzima kukhethwe ngokulula kwaye kubanjwe. Ukufikelela kumhlalutyi wolawulo kunye nokudluliselwa kwedatha ngokuqhelekileyo kwenziwa ngomgangatho oqhelekileyo JTAG izibuko ukwenza lula iimfuno zojongano. Idatha ethathiweyo inokuboniswa kwiPC usebenzisa eqhelekileyo viewing isoftware kwaye ngokwesiqhelo izibuko imveliso ye-wave simulator enengqondo viewisitayile.

I-advantages yale ndlela yeyokuba akukho zikhonkwane zongeziweyo zeFPGA I/O zisetyenziswayo, umgangatho nje JTAG iimpawu. Uhlalutyi lwe-logic oludityanisiweyo lwe-IP cores luhlala lungabizi kakhulu kwaye kwezinye iimeko lunokuba lukhetho lwe-FPGA esele ikhona, okanye izixhobo zokulinganisa. Kwezinye iimeko, umhlalutyi wengqiqo elungisiweyo unokubonelela ngeziphumo ezongezelelweyo kwi-I/Os engasetyenziswanga, ukuba ilunge ngakumbi. Enye ye-disadvantages kule ndlela yeyokuba isixa esikhulu semithombo yeFPGA siyafuneka. Ngokukodwa, ukuba i-trace buffers iyasetyenziswa oku kuya kunciphisa inani leenkumbulo zebhloko ezikhoyo. Ukuba isithinteli esibanzi siyafuneka oku kuya kuba lurhwebo ngokuchasene nobunzulu benkumbulo (ukusukela ukusetyenziswa kwememori ebanzi kuphumela kubunzulu benkumbulo obunzulu)—ingxaki enkulutage xa usebenzisa izixhobo ezincinci. Mhlawumbi eyona nto inkulu yokubuya kobu buchule kukuba ngalo lonke ixesha uhlengahlengiso lokubekwa kweemvavanyo lusenziwa, kuyafuneka ukuba kuqokelelwe kwakhona kwaye kucwangciswe ngokutsha uyilo. Xa usebenzisa isixhobo esikhulu le nkqubo inokuthatha ixesha elininzi. Ngenxa yendlela i-signal probes ibekwe ngayo kuyilo kunokuba nzima ukunxibelelanisa ubudlelwane bexesha lomqondiso. Ukongezelela, ukulibaziseka phakathi kweeprobes zesignali azihambelani kwaye ngoko ubudlelwane bexesha kunzima ukuthelekisa. Oku bunzima obuthile xa uthelekisa imiqondiso ye-asynchronous okanye iimpawu ezivela kwiindawo ezahlukeneyo zamaxesha.

In-Circuit FPGA Debug – Isixhobo soVavanyo lwangaphandle
Ukusetyenziswa kwekhowudi ye-debug ye-circuit ngokubambisana nezixhobo zovavanyo lwangaphandle yayiluphuhliso lwendalo xa i-analyzer ye-logic yangaphandle yayisele ikhona kuvavanyo lwenkqubo. Ngokwenza ikhowudi yokucoca elula ukuchonga kunye nokukhetha imiqondiso yovavanyo lwangaphakathi kwaye uyisebenzise kwi-FPGA I / Os, njengoko kubonisiwe kuMzobo 3, kwakunokwenzeka ukunyusa amandla abahlalutyi abaphezulu (ezifana ne-trace buffers enkulu, ulandelelwano lokuqalisa oluntsonkothileyo, kunye ne-multiple buffers. viewing iinketho) ukwenza iimeko-bume ezilula kodwa ezinamandla zokulungisa. Ubunakho obuntsonkothileyo obukwisekethe kwiinketho zokuxhobisa eziphambili kunokunciphisa inani leziphumo ezifunekayo. UmzekeloampLe, ukukhetha iidilesi ezithile kwibhasi ebanzi kunokuba luthintelo ukuba izikhonkwane zangaphandle bezifuneka.
Ukusebenzisa ingqiqo yeFPGA yangaphakathi kunciphisa kakhulu iimfuno ze-I/O kwaye kunokukhangela iipateni zeedilesi ezithile (mhlawumbi umnxeba kunye nolandelelwano lokubuyisela) ukulungisa iingxaki ezinzima ngakumbi. Ukuba ujongano lomsebenzisi oluqhelekileyo luyafumaneka, oku kunokwenza lula ijika lokufunda kunye nokuphucula imveliso.

I-advantages yale ndlela yeyokuba iphakamisa iindleko zezixhobo zovavanyo lwangaphandle kwaye ngoko akukho ndleko yesixhobo esongezelelweyo. Ezinye zesekethe ye-IP cores ziyafumaneka kubavelisi bezixhobo okanye abavelisi beFPGA, kwaye zingabiza kakhulu okanye zisimahla. Ubungakanani bemithombo yeFPGA efunekayo ukuphumeza ingqiqo yokukhetha umqondiso incinci kakhulu, kwaye ekubeni umsebenzi womkhondo wenziwa kusetyenziswa i-analyzer ye-logic yangaphandle, akukho zinkumbulo zebhloko ezifunekayo. Ekubeni ingqiqo yokukhetha ingabizi, inani elikhulu leetshaneli ezine-triggering ebanzi zinokuxhaswa nazo. Umhlalutyi wengqiqo unokusebenza kuzo zombini imowudi yeXesha kunye nemowudi yeSizwe enceda ukwahlula imiba yexesha.
UkungafanitagIindlela zale ndlela zinokubandakanya imfuno yokuthenga i-logic analyzer, ukuba umntu akakabelwanga kwiprojekthi. Le disadvantage inokwanela ukuyityhafisa le ndlela kwiimeko ezininzi. Qaphela nangona kunjalo, ukuba ezinye iinketho zohlalutyi lwexabiso eliphantsi ziyafumaneka ezisebenzisa iPC okanye ithebhulethi yokubonisa, nto leyo eyenza olu khetho lusebenze kakhulu kwiimfuno ezilula zolungiso.
Inani lezikhonkwane zeFPGA ezisetyenzisiweyo zingaba yenye i-disadvantage kwaye ukuba iibhasi ezibanzi kufuneka ziqwalaselwe, isicwangciso esibalulekileyo soyilo lwebhodi kunye nodibaniso lweziqhagamshelo zolungiso luyafuneka. Le mfuno ngamaxesha amaninzi kunzima ukuqikelela kwangaphambili kwisigaba soyilo kunye nobunye ubunzima obungafunekiyo. Ngokufanayo nendlela yokujonga i-logic analyser isicwangciso sovavanyo lwangaphandle sifuna ukuphinda kuhlaziywe kunye nokuhlelwa ngokutsha koyilo, xa kufuneka umfuniselo omtsha ngamnye.

I-disadvan eqhelekileyotagUkusetyenziswa kwezi zixhobo zimbini-ukusetyenziswa kwemithombo ye-chip (enokuthi kwakhona ibe nefuthe ekusebenzeni kwexesha loyilo kunye nokudala iimfuno ezongezelelweyo zokulungisa) imfuno yokuqokelela kwakhona kunye nokucwangcisa ngokutsha uyilo (olunokongeza iiyure okanye iintsuku kwishedyuli yolungiso) ucwangciso oluphambili olufunekayo ekuchongeni iimeko zovavanyo ezinokwenzeka, kunye nokusetyenziswa kwe-chip eyongezelelweyo ye-I/O yezixhobo ezidaliweyo ngaphandle kwesidingo se-drawback. Enye impendulo yaba kokongezwa kwengqiqo yolungiso oluzinikeleyo kwilaphu leFPGA kwezinye izixhobo. Ukulungiswa kwe-in-circuit debug usebenzisa i-hardware probes yaba sisiphumo.

In-Circuit FPGA Debug – Hardware Probes
Ukusetyenziswa kweprobes zehardware kwenza lula ngokumangalisayo iindlela zokucoca kwisekethe kwiiFPGAs. Obu buchule buphunyezwe njengophawu lwe-Live Probe kwi-SmartFusion2®SoC FPGA kunye nezixhobo ze-IGLOO®2 FPGA, yongeza imigca yokuhlola ezinikeleyo kwilaphu le-FPGA ukujonga imveliso yayo nayiphi na into yokubhalisa. Njengoko kubonisiwe kumzobo webhloko kuMzobo 4, iiprobe zehardware ziyafumaneka kwiitshaneli ezimbini zeprobe A kunye ne-B.

Iziphumo ezikhethiweyo zerejista (amanqaku ophando), njengaleyo ifunyenwe emazantsi omfanekiso, zihanjiswa ngentla kweetshaneli ezimbini zophando kwaye ukuba zikhethiwe zingasetyenziswa nokuba kukwijelo uA okanye u-B. Ezi zibonakaliso zetshaneli zexesha lokwenyani zinokuthunyelwa kwiProbe A ezinikeleyo kunye nezikhonkwane zeProbe B kwisixhobo. Iimpawu zeProbe A kunye neProbe B nazo zinokuhanjiswa ngaphakathi kwi-analyser logic efakwe ngaphakathi.

Qaphela ukuba iimpawu zexesha zezikhonkwane zeprobe ziqhelekileyo kwaye zinokutenxa okungafunekiyo ukusuka kwindawo enye ukuya kwenye, okwenza kube lula kakhulu ukuthelekisa iimpawu zexesha leempawu zexesha lokwenyani. Idatha inokubanjwa ukuya kuthi ga kwi-100MHz iyenze ilungele uninzi loyilo loyilo.
Mhlawumbi okona kubalulekileyo iindawo zophando, kuba azikhethwanga njengenxalenye yoyilo oluphunyeziweyo (zikhethwe ngehardware ezinikeleyo ngelixa uyilo lusebenza kwiFPGA), zinokutshintshwa ngokukhawuleza ngokuthumela idatha yokhetho kwisixhobo. Akukho kuphinda kuqulunqwe kwakhona kunye nokuhlelwa ngokutsha kuyadingeka.
Ukwenza lula usetyenziso lwesakhono seLive Probe nangakumbi, isixhobo sesoftware esihambelanayo sinofikelelo kuzo zonke iindawo zesignali yeprobe ngedebug eyenziwe ngokuzenzekelayo. file. Njengoko kubonisiwe kuMfanekiso 5, igama lesignali lingakhethwa kuluhlu lwesignali kwaye lisetyenziswe kwisitishi esifunwayo. Oku kunokwenziwa nokuba uyilo luqhuba ukuze umsebenzi wokuhlola ngaphakathi kuyilo ungamthungo kwaye usebenze kakhulu.

Kwiimeko ezininzi, iprobe ye-hardware, njenge-Live Probe, inokusetyenziswa ngokubambisana ne-analyzer edibeneyo echazwe ngaphambili kunye neendlela zokuvavanya zangaphandle.

Njengoko kubonisiwe kuMfanekiso wesi-6, ukukwazi kwe-Live Probe ukukhetha imiqondiso 'kwi-fly' yenza kube lula ukutshintsha imiqondiso ngokukhawuleza naphantsi koqwalaselo ngaphandle kokufuna ukuphinda kuqokelelwe uyilo. Umhlalutyi wengqiqo wangaphandle okanye umda unokujonga ngokulula imiqondiso ephononongwayo, njengoko kubonisiwe kwindawo ephezulu ngasekunene yomzobo kwizikhonkwane zemveliso ezinikezelweyo. Ngenye indlela (okanye mhlawumbi nangaphezulu) i-analyzer ye-logic yangaphakathi (i-ILA Chonga ibhloko, eboniswe kumzobo) ingasetyenziselwa ukujonga izikhonkwane zeprobe. Iimpawu zeprobe zingabanjwa yi-ILA kwaye zijongwe kwifestile ye-waveform. Iindawo zeprobe zinokutshintshwa ngaphandle kwesidingo sokuphinda kuqokelelwe uyilo ekujoliswe kulo.
Qaphela ukuba ubuchule obongezelelweyo bokuxhokonxa kunye nomkhondo bunokusetyenziselwa ukuphucula ukusebenza kweprobe, yenze kube lula ukubona imiba yoyilo entsonkothileyo.

Izixhobo ezongezelelweyo zokulungisa ihardware nazo ziyafumaneka kwi-SmartFusion2 SoC FPGA kunye nezixhobo ze-IGLOO2 FPGA. Enye yezi zakhono, ebizwa ngokuba yi-Active Probe, inokufunda ngokuguqukayo nange-asynchronously okanye ibhale kuyo nayiphi na i-logic element element yerejista. Ixabiso elibhaliweyo liyaqhubeleka kumjikelo wewotshi enye ukuze ukusebenza okuqhelekileyo kuqhubeke, kuyenza ibe sisixhobo esixabiseke kakhulu sokulungisa ingxaki. I-Active Probe inomdla othile ukuba uqwalaselo olukhawulezayo lophawu lwangaphakathi luyafunwa (mhlawumbi ukujonga nje ukuba luyasebenza okanye lukwimeko efunwayo, njengophawu lokuseta kwakhona), okanye ukuba kukho imfuneko yokuvavanya ngokukhawuleza umsebenzi wengqiqo ngokubhalela kwindawo yophando.
(mhlawumbi ukuqalisa ukutshintshwa komatshini wombuso ngokubeka ngokukhawuleza ixabiso legalelo lokuhlukanisa ingxaki yokulawula ukuhamba).

Olunye uhlengahlengiso olunikezwa yiMicrosemi yiMemory Debug. Eli nqaku livumela umyili ukuba afunde ngokuguquguqukayo nange-asynchronously okanye abhale kwibhloko ekhethiweyo ye-FPGA ilaphu ye-SRAM. Njengoko kubonisiwe kumfanekiso weskrini weSixhobo seDebug (Umfanekiso 7), xa isithuba seebhloko zeMemori ikhethiwe umsebenzisi unokukhetha inkumbulo efunwayo ukuba ayifunde, enze umfanekiso okhawulezayo wenkumbulo, aguqule amaxabiso ememori, kwaye emva koko abhale amaxabiso emva kwisixhobo. Oku kunokuba luncedo ngakumbi ukujonga okanye ukuseta izithinteli zedatha ezisetyenziswa kumazibuko onxibelelwano ukwenzela ukubala okujoliswe kukrwela iphedi okanye nakwikhowudi ephunyezwe yi-CPU elungisiweyo. Ukulungisa iimpazamo ezixhomekeke kwidatha entsonkothileyo kukhawuleza kwaye kulula xa iinkumbulo zinokujongwa kwaye zilawulwe ngokukhawuleza.

Nje ukuba uyilo lucociwe kunganqweneleka ukucima isakhono sokulungisa ihardware ukukhusela ulwazi olubuthathaka. Umhlaseli unokusebenzisa olu ncedo lufanayo ukufunda-ulwazi olubalulekileyo okanye ukutshintsha isethingi yenkqubo enokuvumela ukufikelela lula kwiindawo ezibuthathaka zenkqubo. I-Microsemi yongeze iimpawu zokuvumela umyili ukuba akhusele isixhobo emva kokuba ukulungiswa kugqityiwe. Umzekeloample, ufikelelo kwi-Live Probe kunye ne-Active Probe inokutshixwa ukuvala ngokupheleleyo umsebenzi njengendlela yokuhlasela enokwenzeka (ide isuse ukuba nokwenzeka komsebenzi wokuphanda ukudala naziphi na iipateni kunikezelo lwangoku olunokusetyenziswa ukuzama ukuphonononga idatha ngokungathanga ngqo). Kungenjalo, ukufikelela kwiinxalenye ezikhethiweyo zoyilo kunokuvalelwa ngaphandle ukuze kuthintelwe ukufikelela kuloo macandelo kuphela. Oku kunokuba lula ukuba kuphela inxalenye yoyilo kufuneka ikhuseleke ukwenza ukuba lonke uyilo lufikeleleke kuvavanyo lwentsimi okanye uhlalutyo lwemposiso.

Itshathi yokuthelekisa i-In-Circuit Debug
Ngoku ukuba a eneenkcukacha review kweendlela ezintathu eziphambili ze-hardware debug zichazwe itshathi yesishwankathelo, njengoko kubonisiwe kuMfanekiso 8, yenziwe ukuba iinkcukacha ezahlukeneyo ze-advan.tages kunye ne disadvantages yendlela nganye. Ukukhumbula ukuba ezinye iindlela zobuchule zingasetyenziswa ngokudibeneyo (i-Live Probe kunye ne-Internal Logic Analyzer (ILA), njenge-Synopsys Chonga, kwi-ex.ample), sinokubona amandla angundoqo kunye nobuthathaka bendlela nganye. Ingqokelela ye-in-circuit hardware debug capabilities (i-Live Probe, i-Active Probe, kunye ne-Memory Debug-ebizwa ngokuba yi-SmartDebug), ibuthathaka kakhulu xa kuthelekiswa nezinye iindlela zobuchule xa kuziwa kwinani leeprobes ezipheleleyo ezikhoyo (isangqa esibomvu) kwaye zibuthathaka kunezona zilungileyo (isangqa esiphuzi) xa isantya sokubamba siqwalaselwa (izixhobo zokuvavanya zangaphandle zinokukhawuleza).
Ubuchule obusekwe kwi-ILA, njenge-Synopsys Chonga, bubuthathaka xa buthelekiswa nobunye ubuchule kunye naxa iimfuno zomthombo weFPGA ziqwalaselwa. Ubuchule obusekwe kwisixhobo sovavanyo lwangaphandle bubuthathaka ngaphezu kwenani lengqwalasela kunye neendleko, impembelelo yoyilo lwexesha, kunye nentshukumo yophando ngaphezulu (ngenxa yesidingo sokuphinda kuqokelelwe uyilo) eyona inzima kakhulu. Mhlawumbi esona sisombululo sisidityaniso se-SmartDebug kunye nenye yeendlela zobuchule, ukuze inani letshaneli ezibuthathaka ze-SmartDebug zinokuncitshiswa kunye ne-probe point movement disadvan.tages zezinye iindlela zincitshisiwe ngokunjalo.

Ukuhlelwa koMqondiso
Ukwahlula okuluncedo kunokwenziwa phakathi kwezinye zezona ntlobo zixhaphakileyo zemiqondiso kwaye oku kunokunceda xa ucwangcisa indlela yokulungisa ingxaki. UmzekeloampLe, imiqondiso engatshintshi ngaphandle kwangexesha lokuqaliswa kwenkqubo, njengokusetwa ngokutsha kwenkqubo, ukusetwa ngokutsha kwebhloko okanye iirejista zokuqalisa zinokuhlelwa njengemiqondiso engatshintshiyo. Ezi ntlobo zezibonakaliso zifikeleleke ngokufanelekileyo ngokusebenzisa indawo enokuthi ibone ngokulula kunye nokulawula umqondiso, ngaphandle kokufuna umjikelo omde wokubuyisela. I-Active Probe sisixhobo esigqwesileyo sokulungisa iisignali ezimileyo. Ngokufanayo, iimpawu ezitshintsha rhoqo kodwa zimile kuninzi lwexesha, zinokuhlelwa njenge-pseudo-static kwaye zilungiswa ngokufanelekileyo kusetyenziswa i-Active Probe. Iimpawu ezitshintsha rhoqo, njengeempawu zewotshi, zingahlelwa njengeziguquguqukayo kwaye azifikeleleki ngokulula nge-Active Probe. I-Live Probe lukhetho olungcono lokujonga le miqondiso.

Ukusetyenziswa kwe-Debug elula

Ngoku ngoku sinokuqonda okungcono kokhetho olwahlukeneyo lwe-debug kwisekethi, makhe sijonge kuyilo olulula.ample ukubona ukuba ezi ndlela zisebenza njani. Umzobo we-9, ubonisa uyilo olulula lweFPGA kwisixhobo se-SmartFusion2 SoC FPGA. I-Microcontroller Subsystem (MSS) isetwa kwakhona yi-CoreSF2Reset Soft IP block. Amagalelo ale block ngaMandla okuSetha ngokutsha, ukuseta kwakhona ilaphu lomsebenzisi, kunye noKuseta kwakhona kwaNgaphandle. Iziphumo zicwangciswa ngokutsha kwiFabric yoMsebenzisi, ukusetwa ngokutsha kweMSS, kunye nokuseta ngokutsha kweM3. Iimpawu zemposiso kukuba akukho msebenzi kwi-I/Os nangona isixhobo siphuma kwimeko ye-POR ngempumelelo. Iinketho ezintathu ezahlukeneyo zokulungisa le mpazamo zibonisiwe kumzobo ngokunjalo: Ibhokisi eluhlaza okwesibhakabhaka (ephawulwe nge-ETE) yeyendlela yeSixhobo soVavanyo lwaNgaphandle; ibhokisi eluhlaza (ebhalwe ILA) yeyendlela yaNgaphakathi yoHlalutyi Logic; kunye nebhokisi e-orenji (ebhalwe AP) yeyendlela ye-Active Probe. Siza kucinga ukuba ezona zizathu zinokuthi zenzeke zempazamo zifakwe ngendlela engafanelekanga kwi-CoreSF2Reset Soft IP block.

Ngoku makhe sijonge inkqubo yolungiso lweempazamo kwiindlela ezintathu ezichazwe ngaphambili kwisekethe.

Izixhobo zovavanyo lwangaphandle
Ukusebenzisa le ndlela, kucingelwa ukuba izixhobo zokuvavanya ziyafumaneka kwaye azisetyenziswa yiprojekthi ephambili. Ukongeza, kubalulekile ukucwangciswa kwangaphambili ukuze ezinye ii-FPGA I/Os zifumaneke kwaye zinokuqhagamshelwa ngokulula kwizixhobo zovavanyo. Ukuba neheader kwiPCB for exampLe, inokuba luncedo kakhulu kwaye icuthe ixesha elichithwe ukuzama ukuchonga nokudibanisa 'nomrhanelwa onokubakho' okanye ushokoxeko olunokubakho lwezikhonkwane ngexesha lokuvavanywa. Uyilo luya kufuneka luhlaziywe ukukhetha imiqondiso esifuna ukuyiphanda. Ngethemba, asisayi 'kulikrazula umva itswele' kwaye kufuneka sikhethe ezinye iimpawu zophando oluqhubekayo, kuba rhoqo uphando lwethu lokuqala lukhokelela kwimibuzo emininzi. Kuwo nawuphi na umcimbi, inkqubo yokuqokelela ngokutsha kunye nenkqubo yohlengahlengiso inokuthatha ixesha elininzi, kwaye ukuba kukhokelela ekunyhashweni kwexesha uhlengahlengiso luyafuneka (sonke siyayazi indlela ekukhathaza ngayo ukuzama ukusombulula imiba yokuvalwa kwexesha, ngakumbi, xa usenza uhlengahlengiso loyilo ukufumana ibug yoyilo-yonke inkqubo inokuthatha ukusuka kwimizuzu ukuya kwiiyure)! Kwakhona kubalulekile ukukhumbula ukuba ukuba uyilo alunamsebenzisi wamahhala I / Os, le ndlela ayikwazi ukuphunyezwa. Ngaphaya koko, le ndlela yolwakhiwo iyangenelela kuyilo-kwaye iibhugi ezinxulumene nexesha zinokunyamalala okanye ziphinde zivele phakathi kokuphindaphinda.

IsiHlalutyi seNgcaciso yangaphakathi
Ukusebenzisa le ndlela i-ILA kufuneka ifakwe kuyilo kusetyenziswa izixhobo zelaphu, kwaye emva koko kufuneka iphinde ihlanganiswe. Qaphela ukuba ukuba i-ILA sele iqinisiwe, iimpawu esifuna ukuphanda ngazo azizange zisetyenziswe, ezinokuthi zifune ukuphinda kuhlanganiswe. Le nkqubo ibeka emngciphekweni wokutshintsha uyilo lokuqala kunye nokwaphula imiqobo yexesha. Ukuba ixesha lifikelelwe, uyilo kufuneka lucwangciswe ngokutsha kwaye luqaliswe ngokutsha. Yonke le nkqubo inokuthatha imizuzu emininzi okanye iiyure ukuba ixesha lokubuyisela lide kwaye kufuneka kudlulelwe ngeendlela ezininzi.Le ndlela iphazamisana nesakhiwo kwaye ingabangela iingxaki ezifanayo kwezo zichazwe xa usebenzisa le ndlela ingentla.

Ukuhlola okusebenzayo
Ukusebenzisa le ndlela i-Active Probe ingalathwa kumthombo weempawu ezahlukeneyo zokuseta kwakhona, zonke zifunyenwe ngeziphumo zerejista (njengoko kuqhelekile kuyo nayiphi na indlela yoyilo oluhle lwedijithali). Iimpawu zikhethwa ibe nye ngexesha, kwimenyu ye-Active Probe eboniswe kuMfanekiso we-10 ngezantsi. Amaxabiso omqondiso akhethiweyo anokufundwa kwaye aboniswe kwifestile yedatha yeProbe eSebenzayo. Naziphi na ii-mis-assertions zichongwa ngokulula. Olu vavanyo lunokwenziwa ngokukhawuleza ngaphandle kwesidingo sokuqokelela ngokutsha kunye nokucwangcisa ngokutsha isixhobo kwaye alusolwakhiwo okanye alungeneleli ngokwenkqubo. Yonke le nkqubo ithatha nje imizuzwana embalwa. Le ndlela inokuphinda idale ukulawulwa (ukutshintsha amaxabiso asynchronously) apho ezinye iindlela ezimbini zingayi kuvumela. Kule exampLe, isignali yokusetha ngokutsha efunyenwe yirejista inokuphicothwa ngokulula kwaye ifunyanwe igcinwe kwimeko esebenzayo.

Ukuguqulelwa komzuzwana komqondiso wokusetha ngokutsha kunokufezekiswa ngokuguqula ngokungafaniyo irejista ukuvelisa ezinye iimpawu.

Imeko yokusetyenziswa kwe-Debug Complex
Uyilo olungasentla lwalulula kakhulu kwaye luluncedo njengentshayelelo ekusebenziseni iindlela zoyilo ezichazwe, kodwa i-ex enzima ngakumbiampinokuba ngumzekeliso ngakumbi. Amaxesha amaninzi umqondiso womdla awungowophawu olumileyo njengoko kwakunjalo kwi-ex yethu elulaample kodwa inamandla. Umqondiso oguquguqukayo oqhelekileyo yiwotshi ephakathi, mhlawumbi esetyenziselwa ukulinganisa ixesha lokuxhawulana kujongano olulandelelanayo. Umzobo we-11 ubonisa uyilo olunjalo kunye nomsebenzisi i-Soft IP core, kulo mzekelo, i-interface ye-serial yesiko exhunywe kwinkqubo yebhasi ye-APB. Iimpawu zeempazamo kukuba akukho msebenzi kubasebenzisi be-serial interface yesiko, kwaye xa inkosi yebhasi ye-APB ikhupha intengiselwano ukufikelela kwi-interface ye-serial ingena kwimeko engaphandle ebonisa ukuxhawula ngesandla okungalunganga. Le miqathango ibonakala ikhupha isizathu esisisigxina, njengesignali yokusetha ngokutsha engalunganga, ekubeni umatshini we-transaction state ubonakala ngathi awusebenzi kwizinga elilindelekileyo kwaye ngaloo ndlela ubangela ukungafani. Oyena nobangela ucingelwa ukuba yi-clock frequency generator ngaphakathi kondoqo we-IP yomsebenzisi.

Ukuba ayisebenzi ngesantya esichanekileyo, iimpazamo ezichaziweyo zingakhokelela.

Kule meko inokuba sisicwangciso esingcono sokubuyisela inkqubo ye-Active Probe kunye ne-Live Probe. Oku kubonakaliswe kulo mfanekiso ungasentla ngebhokisi ye-LP enombala o-orenji, kusetyenziswa i-JTAG uphawu lokhetho lomthombo weprobe.

Izixhobo zovavanyo lwangaphandle
Kule meko, indlela yokusebenza ifana kakhulu ne-ex elula echazwe ngaphambiliample. Umqondiso wewotshi yomsebenzisi ukhutshelwa kwindawo yovavanyo (ngethemba kwi-header) kwaye ukubuyisela kwakhona ixesha elidliwayo liyafuneka. Kwakhona kunokuba luncedo ukukhupha isignali yereferensi, mhlawumbi iwashi yenkqubo esetyenziselwa ukuvala abasebenzisi be-IP njengophawu lokuthelekisa. Siza kuphinda sibe phantsi kwemfuneko yokudibanisa kunye nokucwangcisa ngokutsha ukuze yonke inkqubo ithathe ixesha elibalulekileyo.

IsiHlalutyi seNgcaciso yangaphakathi
Eli tyala lifana kakhulu ne-ex elulaample. I-ILA mayifakwe, okanye kuchazwe isignali efunekayo, kuze kwenziwe umjikelo wokuphinda uqokelelwe kunye nohlengahlengiso. Yonke imiba echazwe ngaphambili isakhokelela kwixesha elibalulekileyo lokulungisa ingxaki. Kukho ukuntsonkotha okongezelelweyo, nangona kunjalo. Iwotshi eqhuba i-ILA kufuneka ihambelane, kwaye ngokufanelekileyo ikhawuleze kakhulu ngokubhekiselele kwiwotshi ekufuneka ijongwe kumsebenzisi weSoft IP core. Ukuba ezi wotshi zi-asynchronous, okanye azinabudlelwane bexesha obuchanekileyo, ukuthathwa kwedatha akuyi kuqikelelwa kwaye kube ngumthombo wokubhideka wenkqubo yolungiso.
Qaphela ukuba ukuba umsebenzisi Soft IP clock ayiveliswanga kwi-chip (mhlawumbi ifunyenwe kwi-serial interface) umyili unokufuna ukongeza imodyuli yewotshi ukuvelisa iwashi ye-ILA ekhawulezayo usebenzisa izibonelelo ezongezelelweyo kwaye mhlawumbi ukudala ukuphulwa kwexesha.

Live Probe
Ukusebenzisa le ndlela, i-Live Probe inokuboniswa ngokukhawuleza kumthombo wewashi yomsebenzisi kunye nawuphi na omnye umthombo wewashi ukusuka kwirejista ukugxotha ingcambu yephutha. I-Live Probe iya kubonisa iziphumo ezikhethiweyo zesignali ngexesha lokwenyani kwaye naluphi na unxulumano lwexesha phakathi kweempawu ngoko kulula kakhulu ukumisela. Yonke le nkqubo ithatha nje imizuzwana embalwa.

Eminye iMiboniso yeDebug yoSetyenziso lweNdibaniselwano
Kukwabalulekile ukubonisa ukuba maninzi amandla okulungisa ezongezelelweyo kwi-SmartFusion2 SoC FPGA kunye nezixhobo ze-IGLOO2 FPGA ezinokuthi zisetyenziswe kujongano lwe-serial, njengaleyo ikwi-ex yangaphambili.ample uyilo apho iimpazamo zintsonkothe ​​ngakumbi. I-SERDES Debug, umzekeloample, ibonelela ngobuchule obuthile bokulungisa ujongano lweserial olunikezelweyo lwesantya esiphezulu. Ezinye zeempawu ze-SERDES Debug ziquka inkxaso yovavanyo lwe-PMA (njengokuveliswa kwepateni ye-PRBS kunye novavanyo lwe-loopback) inkxaso yohlengahlengiso lovavanyo lwe-SERDES ezininzi kunye nohlengahlengiso lwenqanaba lokubhalisa ukuphepha ukusetyenziswa kokuhamba koyilo olupheleleyo ukwenza utshintsho lohlengahlengiso, kunye neengxelo ezibhaliweyo ezibonisa iiprothokholi ezicwangcisiweyo, iirejista zokucwangcisa iSERDES, kunye nerejista yoqwalaselo lweLane. Ezi mpawu zenza i-SERDES debug ibe lula kakhulu kwaye ingasetyenziswa ngokudityaniswa neLive Probe kunye neActive Probe ukuqhubela phambili ulungiso lweempazamo kwiisekethe ezinzima.
Isixhobo esichazwe ngaphambili seMemory Debug sinokusetyenziswa ngokubambisana neSERDES Debug kuvavanyo lwesantya. Kuba izithinteli zememori zinokukhawuleza kwaye zihlolwe ngokulula kwaye zitshintshwe ngeMemori Debug, kuyenzeka ukuba udale ngokukhawuleza 'iipakethi zovavanyo' kwaye ujonge iziphumo ze-loopback okanye phakathi kwenkqubo yonxibelelwano. Umyili unokusebenzisa obu buchule kwaye ngaloo ndlela anciphise imfuno 'yeentsimbi zokuvavanya' ezikhethekileyo ezisebenzisa ilaphu leFPGA elongezelelweyo kwaye oko kunokuchaphazela ixesha letshiphu.

Ukuqukumbela
Eli phepha lichaze ngokweenkcukacha iindlela ezininzi ezahlukeneyo zokuphumeza i-in-circuit debug ye-FPGAs kunye ne-SoC FPGAs-ukusetyenziswa kwe-Integrated Logic Analyzer, ukusetyenziswa kwezixhobo zokuvavanya zangaphandle, kunye nokusetyenziswa kweesekethe zeprobe ezizinikeleyo ezihlanganiswe kwilaphu le-FPGA. Ukongezwa kweesekethe zeprobe ezikhethekileyo kunye nezinikezelweyo, njenge-Active Probe kunye ne-Live Probe enikezelwa yi-Microsemi kwi-SmartFusion2 SoC FPGA kunye nezixhobo ze-IGLOO2 FPGA, ziboniswe ngokukhawuleza kwaye zenza lula inkqubo yokulungisa. Ukukwazi ukuguqula ngokukhawuleza ukhetho lweempawu zangaphakathi (ngaphandle kwesidingo sokwenza umjikelo wokuphinda uqokelele ixesha elininzi kunye nohlengahlengiso lwenkqubo), kunye nokukwazi ukuphonononga imiqondiso yangaphakathi (ngaphandle kwesidingo sokusebenzisa ilaphu leFPGA kunye nokwazisa ngokunyhashwa kwexesha) kwaboniswa njenge-advan enkulu.tages xa ususa iimpazamo kuyilo lweFPGA. Ukongeza, ukusetyenziswa kweendlela ezininzi, ezinokuthi zisebenze kunye ukubonelela ngesakhono esibanzi sokusombulula ingxaki kwachazwa. Ekugqibeleni, ababini exampIimeko zokusetyenziswa kwe-debug zanikezelwa ukubonisa urhwebo phakathi kweendlela ezichaziweyo.

Ukufunda Ngakumbi

1. IGLOO2 FPGAs
2. SmartFusion2 SoC FPGAs

I-Microsemi Corporation (i-Nasdaq: i-MSCC) inikezela ngepotfoliyo ebanzi ye-semiconductor kunye nezisombululo zenkqubo yonxibelelwano, ukukhusela kunye nokhuseleko, i-aerospace kunye neemarike zoshishino. Iimveliso zibandakanya ukusebenza okuphezulu kunye ne-radiation-hardened analog mix-signal integrated circuits, FPGAs, SoCs kunye ne-ASICs; iimveliso zolawulo lwamandla; izixhobo zexesha kunye nongqamaniso kunye nezisombululo zexesha ezichanekileyo, ukumisela umgangatho wehlabathi wexesha; izixhobo zokulungisa ilizwi; Izisombululo zeRF; amacandelo ahlukeneyo; iiteknoloji zokhuseleko kunye anti-t scalableampiimveliso ze-er; I-Power-over-Ethernet ICs kunye ne-midspans; ngokunjalo noyilo lwesakhono kunye neenkonzo. Ikomkhulu leMicrosemi lihlala e-Aliso Viejo, eCalifornia, kwaye inabasebenzi abamalunga nama-3,400 kwihlabathi liphela. Funda ngakumbi kwi www.microsemi.com.

© 2014 Microsemi Corporation. Onke Amalungelo Agciniwe. I-Microsemi kunye ne-logo ye-Microsemi ziimpawu zorhwebo ze-Microsemi Corporation. Zonke ezinye iimpawu zorhwebo kunye namanqaku eenkonzo ziyipropathi yabanini bazo.

Ikomkhulu leMicrosemi Corporate

• Nye Enterprise, Aliso Viejo CA 92656 USA
• Ngaphakathi i-USA: +1 800-713-4113
• Ngaphandle i-USA: +1 949-380-6100
• Intengiso: +1 949-380-6136
• Ifeksi: +1 949-215-4996
• I-imeyile: sales.support@microsemi.com

FAQ

• Umbuzo: Yintoni eyona nto iphezulu yokuthatha idatha yesixhobo?
  A: Isixhobo sixhasa ukuthathwa kwedatha ukuya kuthi ga kwi-100MHz, ilungele uninzi loyilo olujoliswe kuyo.
• Umbuzo: Ngaba kufuneka ndihlanganise uyilo xa ndisebenzisa iisekethe zeprobe ukulungisa ingxaki?
  A: Hayi, iindawo zophando zinokutshintshwa ngokukhawuleza ngaphandle kokufuna ukuphinda kuqulunqwe ngokutsha okanye ukuphinda kucwangciswe ngokutsha.

Amaxwebhu / Izibonelelo

Microsemi In-Circuit FPGA Debug [pdf] Imiyalelo KwiSekethe yeFPGA Debug, FPGA Debug, Debug

Iimbekiselo

• Incwadi yokusebenzisa