DS50003319C-13 Ethernet HDMI TX IP
Pandhuan pangguna IP HDMI TX
Pambuka (Njaluk Pitakonan)
IP pemancar High-Definition Multimedia Interface (HDMI) Microchip ndhukung ngirim data paket video lan audio sing diterangake ing spesifikasi standar HDMI.
HDMI nggunakake Transition Minimized Differential Signaling (TMDS) kanggo ngirimake volume data digital kanthi efisien ing jarak kabel sing luwih dawa, njamin transmisi sinyal digital kanthi kacepetan, serial, lan dipercaya. Link TMDS kasusun saka saluran jam siji lan telung saluran data. Jam piksel video ditularake ing saluran jam TMDS, sing mbantu supaya sinyal tetep sinkron. Data video digawa minangka piksel 24-bit ing telung saluran data TMDS, ing ngendi saben saluran data ditetepake kanggo komponen werna abang, ijo, lan biru. Data audio digawa minangka paket 8-bit ing saluran ijo lan abang TMDS.
TMDS encoder ngidini ngirim data serial ing kacepetan dhuwur, nalika nyilikake potensial kanggo Electro-Magnetic Interference (EMI) liwat kabel tembaga dening nyilikake nomer transisi (ngurangi gangguan antarane saluran), lan entuk imbangan Direct Current (DC), ing kabel. , kanthi tetep nomer siji lan nul ing baris meh padha.
HDMI TX IP dirancang kanggo digunakake bebarengan karo PolarFire® Transceiver piranti SoC lan PolarFire. IP kompatibel karo HDMI 1.4 lan HDMI 2.0, sing ndhukung nganti 60 pigura per detik, kanthi bandwidth maksimal 18 Gbps. IP nggunakake encoder TMDS sing ngowahi data video 8-dicokot saben saluran lan paket audio menyang 10-dicokot DC-imbang, lan transisi nyilikake urutan. Banjur dikirim kanthi serial kanthi tingkat 10-bit saben piksel, saben saluran. Sajrone periode blanking video, token kontrol ditularake. Token iki digawe adhedhasar sinyal hsync lan vsync. Sajrone periode pulo data, paket audio dikirim minangka paket 10-bit ing saluran abang lan ijo.
Pandhuan pangguna
DS50003319C – 1
© 2024 Microchip Technology Inc lan anak perusahaan
Ringkesan
Tabel ing ngisor iki nyedhiyakake ringkesan karakteristik HDMI TX IP.
Tabel 1. HDMI TX IP Karakteristik
|
Versi inti |
Pandhuan pangguna iki ndhukung HDMI TX IP v5.2.0 |
|
Didhukung Kulawarga piranti |
• PolarFire® SoC • PolarFire |
|
Aliran Alat sing Didhukung |
Mbutuhake Libero® SoC v11.4 utawa luwih anyar dirilis |
|
Didhukung Antarmuka |
Antarmuka sing didhukung dening HDMI TX IP yaiku: • AXI4-Stream - Inti iki ndhukung AXI4-Stream menyang port input. Nalika diatur ing mode iki, IP njupuk AXI4 Stream sinyal complaint standar minangka input. • Antarmuka Konfigurasi AXI4-Lite - Inti iki ndhukung antarmuka konfigurasi AXI4-Lite kanggo syarat 4Kp60. Ing mode iki, input IP diwenehake saka SoftConsole. • pribumi - Nalika dikonfigurasi ing mode iki, IP njupuk sinyal video lan audio asli minangka input. |
|
Lisensi |
HDMI TX IP diwenehake karo rong opsi lisensi ing ngisor iki: • ndhelik: Kode RTL ndhelik lengkap diwenehake kanggo inti. Kasedhiya gratis karo lisensi Libero, sing ngidini inti bisa instantiated karo SmartDesign. Sampeyan bisa nindakake Simulasi, Sintesis, Layout, lan program silikon FPGA nggunakake Suite desain Libero. • RTL: Kode sumber RTL lengkap dikunci lisensi, sing kudu dituku kanthi kapisah. |
Fitur
HDMI TX IP nduweni fitur ing ngisor iki:
• Kompatibel kanggo HDMI 2.0 lan 1.4b
• Ndhukung siji utawa papat simbol / piksel saben input jam
• Ndhukung Résolusi nganti 3840 x 2160 ing 60 fps
• Ndhukung ambane werna 8, 10, 12, lan 16-bit
• Ndhukung format warna kayata RGB, YUV 4:2:2, lan YUV 4:4:4
• Ndhukung audio nganti 32 saluran
• Ndhukung Encoding Scheme - TMDS
• Ndhukung Native lan AXI4 Stream Video lan antarmuka Data Audio
• Ndhukung antarmuka Konfigurasi Native lan AXI4-Lite kanggo modifikasi parameter
Pandhuan Instalasi
Inti IP kudu diinstal menyang Katalog IP Libero® Piranti lunak SoC kanthi otomatis liwat fungsi nganyari Katalog IP ing piranti lunak Libero SoC, utawa diundhuh kanthi manual saka katalog. Sawise inti IP diinstal ing Libero SoC software IP Catalog, dikonfigurasi, digawe, lan instantiated ing SmartDesign kanggo dilebokake ing proyek Libero.
Pandhuan pangguna
DS50003319C – 2
© 2024 Microchip Technology Inc lan anak perusahaan
Panggunaan sumber daya (Njaluk Pitakonan)
HDMI TX IP dileksanakake ing PolarFire® FPGA (MPF300T – 1FCG1152I Paket).
Tabel ing ngisor iki nampilake sumber daya sing digunakake nalika g_PIXELS_PER_CLK = 1PXL.
Tabel 2. Panggunaan sumber daya kanggo 1PXL
|
|
g_COLOR_FORMAT g_BITS_PER_COMPONENT (Bit) |
g_AUX_CHANNEL_ENABLE g_4K60_SUPPORT Kain |
|
4 LUT |
Kain DFF |
Antarmuka 4LUT |
Antarmuka DFF |
uSRAM (64×12) |
|
RGB |
8 |
Aktifake |
Pateni |
787 |
514 |
108 |
108 |
9 |
|
Pateni |
Pateni |
819 |
502 |
108 |
108 |
9 |
||
|
10 |
Pateni |
Pateni |
1070 |
849 |
156 |
156 |
13 |
|
|
12 |
Pateni |
Pateni |
1084 |
837 |
156 |
156 |
13 |
|
|
16 |
Pateni |
Pateni |
1058 |
846 |
156 |
156 |
13 |
|
|
YCbCr422 |
8 |
Pateni |
Pateni |
696 |
473 |
96 |
96 |
8 |
|
YCbCr444 |
8 |
Pateni |
Pateni |
819 |
513 |
108 |
108 |
9 |
|
10 |
Pateni |
Pateni |
1068 |
849 |
156 |
156 |
13 |
|
|
12 |
Pateni |
Pateni |
1017 |
837 |
156 |
156 |
13 |
|
|
16 |
Pateni |
Pateni |
1050 |
845 |
156 |
156 |
13 |
Tabel ing ngisor iki nampilake sumber daya sing digunakake nalika g_PIXELS_PER_CLK = 4PXL.
Tabel 3. Panggunaan sumber daya kanggo 4PXL
|
|
g_COLOR_FORMAT g_BITS_PER_COMPONENT (Bit) |
g_AUX_CHANNEL_ENABLE g_4K60_SUPPORT Kain |
|
4 LUT |
Kain DFF |
Antarmuka 4LUT |
Antarmuka DFF |
uSRAM (64×12) |
|
RGB |
8 |
Pateni |
Aktifake |
4078 |
2032 |
144 |
144 |
12 |
|
Aktifake |
Pateni |
1475 |
2269 |
144 |
144 |
12 |
||
|
Pateni |
Pateni |
1393 |
1092 |
144 |
144 |
12 |
||
|
10 |
Pateni |
Pateni |
2151 |
1635 |
264 |
264 |
22 |
|
|
12 |
Pateni |
Pateni |
1909 |
1593 |
264 |
264 |
22 |
|
|
16 |
Pateni |
Pateni |
1645 |
1284 |
264 |
264 |
22 |
|
|
YCbCr422 |
8 |
Pateni |
Pateni |
1265 |
922 |
144 |
144 |
12 |
|
YCbCr444 |
8 |
Pateni |
Pateni |
1119 |
811 |
144 |
144 |
12 |
|
10 |
Pateni |
Pateni |
2000 |
1627 |
264 |
264 |
22 |
|
|
12 |
Pateni |
Pateni |
1909 |
1585 |
264 |
264 |
22 |
|
|
16 |
Pateni |
Pateni |
1604 |
1268 |
264 |
264 |
22 |
Pandhuan pangguna
DS50003319C – 3
© 2024 Microchip Technology Inc lan anak perusahaan
HDMI TX IP Configurator
1. HDMI TX IP Configurator (Njaluk Pitakonan)
Bagian iki menehi liwatview antarmuka HDMI TX Configurator lan macem-macem komponen.
HDMI TX Configurator nyedhiyakake antarmuka grafis kanggo nyetel inti HDMI TX kanggo syarat transmisi video tartamtu. Configurator iki ngidini pangguna milih paramèter kayata Bits Per Component, Format Warna, Jumlah Piksel, Mode Audio, Antarmuka, Testbench, lan Lisensi. Penting kanggo nyetel setelan kasebut kanthi bener kanggo njamin transmisi data video sing efektif liwat HDMI.
Antarmuka saka HDMI TX Configurator kasusun saka macem-macem menu gulung mudhun lan opsi sing ngidini pangguna kanggo ngatur setelan transmisi HDMI. Konfigurasi tombol diterangake ing Tabel 3-1.
Tokoh ing ngisor iki menehi rincian view saka antarmuka HDMI TX Configurator.
Gambar 1-1. HDMI TX IP Configurator
Antarmuka uga kalebu OK lan Batal tombol kanggo konfirmasi utawa discarding konfigurasi digawe.
Pandhuan pangguna
DS50003319C – 5
© 2024 Microchip Technology Inc lan anak perusahaan
Implementasi Hardware
2. Implementasi Hardware (Njaluk Pitakonan)
HDMI Transmitter (TX) kasusun saka rong stages:
• Operasi XOR / XNOR, sing nyuda jumlah transisi
• INV / NONINV, kang nyilikake disparity (imbangan DC). Tambahan rong bit ditambahake ing s ikitage operasi. Data kontrol (hsync lan vsync) dienkode dadi 10 bit ing papat kombinasi sing bisa kanggo mbantu panrima nyinkronake jam karo jam pemancar. Transceiver kudu digunakake bebarengan karo HDMI TX IP kanggo serialize 10 bit (1 mode piksel) utawa 40 bit (4 piksel mode).
Configurator uga nampilake perwakilan inti HDMI Tx, kanthi label HDMI_TX_0, nuduhake macem-macem sambungan input lan output sing disambungake karo inti. Ana telung mode kanggo antarmuka HDMI TX lan diterangake kaya ing ngisor iki:
Mode Format Warna RGB
Port HDMI TX IP kanggo siji piksel saben jam nalika mode audio diaktifake lan format Warna RGB kanggo PolarFire® piranti ditampilake ing gambar ing ngisor iki. Perwakilan visual port inti HDMI Tx kaya ing ngisor iki:
• Sinyal jam kontrol yaiku R_CLK_LOCK, G_CLK_LOCK, lan B_CLK_LOCK. Sinyal Jam yaiku R_CLK_I, G_CLK_I, lan B_CLK_I.
• Saluran data kalebu DATA_R_I, DATA_G_I, lan DATA_B_I.
• Sinyal Data Tambahan yaiku AUX_DATA_R_I lan AUX_DATA_G_I.
Gambar 2-1. Diagram Blok IP HDMI TX (Format Warna RGB)
Kanggo informasi luwih lengkap babagan sinyal I/O kanggo format werna RGB, waca Tabel 3-2.
Mode Format Warna YCbCr444
Port HDMI TX IP kanggo siji piksel saben jam nalika mode audio diaktifake lan format Warna YCbCr444 ditampilake ing gambar ing ngisor iki. Perwakilan visual port inti HDMI Tx kaya ing ngisor iki:
• Sinyal kontrol yaiku Y_CLK_LOCK, Cb_CLK_LOCK, lan Cr_CLK_LOCK.
• Sinyal jam yaiku Y_CLK_I, Cb_CLK_I, lan Cr_CLK_I.
Pandhuan pangguna
DS50003319C – 6
© 2024 Microchip Technology Inc lan anak perusahaan
Implementasi Hardware
• Saluran data kalebu DATA_Y_I, DATA_Cb_I, lan DATA_Cr_I.
• Sinyal input Data Auxiliary yaiku AUX_DATA_Y_I lan AUX_DATA_C_I.
Gambar 2-2. Diagram Blok IP HDMI TX (Format Warna YCbCr444)
Kanggo informasi luwih lengkap babagan sinyal I / O kanggo format werna YCbCr444, ndeleng Tabel 3-6. Mode Format Warna YCbCr422
Port HDMI TX IP kanggo siji piksel saben jam nalika mode audio diaktifake lan format Warna YCbCr422 ditampilake ing gambar ing ngisor iki. Perwakilan visual port inti HDMI Tx kaya ing ngisor iki:
• Sinyal kontrol yaiku LANE1_CLK_LOCK, LANE2_CLK_LOCK, lan LANE3_CLK_LOCK. • Sinyal jam yaiku LANE1_CLK_I, LANE2_CLK_I, lan LANE3_CLK_I.
• Saluran data kalebu DATA_Y_I lan DATA_C_I.
Pandhuan pangguna
DS50003319C – 7
© 2024 Microchip Technology Inc lan anak perusahaan
Implementasi Hardware
Gambar 2-3. Diagram Blok IP HDMI TX (Format Warna YCbCr422)
Kanggo informasi luwih lengkap babagan sinyal I / O kanggo format werna YCbCr422, ndeleng Tabel 3-7 Pandhuan pangguna
DS50003319C – 8
© 2024 Microchip Technology Inc lan anak perusahaan
Parameter HDMI TX lan Sinyal Antarmuka
3. Parameter HDMI TX lan Sinyal Antarmuka (Njaluk Pitakonan)
Bagean iki ngrembug paramèter ing HDMI TX GUI configurator lan sinyal I / O. 3.1 Parameter Konfigurasi (Njaluk Pitakonan)
Tabel ing ngisor iki nampilake paramèter konfigurasi ing IP HDMI TX.
Tabel 3-1. Parameter Konfigurasi
|
Jeneng Parameter |
Katrangan |
|
Format Warna |
Nemtokake ruang warna. Ndhukung format warna ing ngisor iki: • RGB • YCbCr422 • YCbCr444 |
|
Jumlah bit saben komponen |
Nemtokake jumlah bit saben komponen warna. Ndhukung 8, 10, 12, lan 16 bit saben komponen. |
|
Jumlah Piksel |
Nuduhake jumlah piksel saben input jam: • Piksel saben jam = 1 • Piksel saben jam = 4 |
|
Dhukungan 4Kp60 |
Dhukungan kanggo resolusi 4K ing 60 frame per detik: • Nalika 1, dhukungan 4Kp60 diaktifake • Nalika 0, 4Kp60 support dipatèni |
|
Mode Audio |
Ngatur mode transmisi audio. Data audio kanggo saluran R lan G: • Aktifake • Pateni |
|
Antarmuka |
Native lan AXI stream |
|
Testbench |
Ngidini pilihan lingkungan testbench. Ndhukung pilihan testbench ing ngisor iki: • Panganggo • Ora ana |
|
Lisensi |
Nemtokake jinis lisensi. Nyedhiyakake rong pilihan lisensi ing ngisor iki: • RTL • ndhelik |
3.2 Pelabuhan (Njaluk Pitakonan)
Tabel ing ngisor iki nampilake port input lan output saka HDMI TX IP kanggo antarmuka Native nalika mode Audio diaktifake lan format Warna RGB.
Tabel 3-2. Sinyal Input lan Output
|
Jeneng Sinyal |
arah |
Jembar |
Katrangan |
|
SYS_CLK_I |
Input |
1-dicokot |
Jam sistem, biasane jam sing padha karo pengontrol tampilan |
|
RESET_N_I |
Input |
1-dicokot |
Sinyal reset aktif-kurang asinkron |
|
VIDEO_DATA_VALID_I |
Input |
1-dicokot |
Data video input valid |
|
AUDIO_DATA_VALID_I |
Input |
1-dicokot |
Data paket audio input valid |
|
R_CLK_I |
Input |
1-dicokot |
Jam TX kanggo saluran "R" saka XCVR |
|
R_CLK_LOCK |
Input |
1-dicokot |
TX_CLK_STABLE kanggo saluran R saka XCVR |
|
G_CLK_I |
Input |
1-dicokot |
Jam TX kanggo saluran "G" saka XCVR |
|
G_CLK_LOCK |
Input |
1-dicokot |
TX_CLK_STABLE kanggo saluran G saka XCVR |
|
B_CLK_I |
Input |
1-dicokot |
Jam TX kanggo saluran "B" saka XCVR |
Pandhuan pangguna
DS50003319C – 9
© 2024 Microchip Technology Inc lan anak perusahaan
Parameter HDMI TX lan Sinyal Antarmuka
|
……….. lanjutane Jeneng Sinyal Arah Jembar Katrangan |
|||
|
B_CLK_LOCK |
Input |
1-dicokot |
TX_CLK_STABLE kanggo saluran B saka XCVR |
|
H_SYNC_I |
Input |
1-dicokot |
Pulsa sinkronisasi horisontal |
|
V_SYNC_I |
Input |
1-dicokot |
Pulsa sinkronisasi vertikal |
|
PAKET_HEADER_I |
Input |
PIXELS_PER_CLK*1 |
Header paket kanggo data paket audio |
|
DATA_R_I |
Input |
PIXELS_PER_CLK*8 |
Input data "R". |
|
DATA_G_I |
Input |
PIXELS_PER_CLK*8 |
Input data "G". |
|
DATA_B_I |
Input |
PIXELS_PER_CLK*8 |
Input data "B". |
|
AUX_DATA_R_I |
Input |
PIXELS_PER_CLK*4 |
Data saluran paket audio "R". |
|
AUX_DATA_G_I |
Input |
PIXELS_PER_CLK*4 |
Paket audio "G" saluran data |
|
TMDS_R_O |
Output |
PIXELS_PER_CLK*10 |
Data sing dikodekake "R". |
|
TMDS_G_O |
Output |
PIXELS_PER_CLK*10 |
Data sing dikodekake "G". |
|
TMDS_B_O |
Output |
PIXELS_PER_CLK*10 |
Data sing dikodekake "B". |
Tabel ing ngisor iki nampilake port kanggo antarmuka Stream AXI4 kanthi Audio Enable.
Tabel 3-3. Port Input lan Output kanggo Antarmuka Stream AXI4
|
Tipe Jeneng Port |
|
Jembar |
Katrangan |
|
TDATA_I |
Input |
3*g_BITS_PER_COMPONENT*g_PIXELS_PER_CLK Input data video |
|
|
TVALID_I |
Input |
1-dicokot |
Video input valid |
|
TREADY_O Output 1-bit |
|
|
Output slave sinyal siap |
|
TUSER_I |
Input |
PIXELS_PER_CLK*9 + 5 |
bit 0 = ora digunakake bit 1 = VSYNC bit 2 = HSYNC bit 3 = ora digunakake bit [3 + g_PIXELS_PER_CLK: 4] = Bit header paket [4 + g_PIXELS_PER_CLK] = Data audio valid bit [(5 * g_PIXELS_PER_CLK) + 4: (1*g_PIXELS_PER_CLK) + 5] = Audio G data bit [(9 * g_PIXELS_PER_CLK) + 4: (5*g_PIXELS_PER_CLK) + 5] = Audio R data |
Tabel ing ngisor iki nampilake port input lan output HDMI TX IP kanggo antarmuka Native nalika mode Audio dipateni.
Tabel 3-4. Sinyal Input lan Output
|
Jeneng Sinyal |
arah |
Jembar |
Katrangan |
|
SYS_CLK_I |
Input |
1-dicokot |
Jam sistem, biasane jam sing padha karo pengontrol tampilan |
|
RESET_N_I |
Input |
1-dicokot |
Asynchronous sinyal reset aktif-kurang |
|
VIDEO_DATA_VALID_I |
Input |
1-dicokot |
Data video input valid |
|
R_CLK_I |
Input |
1-dicokot |
Jam TX kanggo saluran "R" saka XCVR |
|
R_CLK_LOCK |
Input |
1-dicokot |
TX_CLK_STABLE kanggo saluran R saka XCVR |
|
G_CLK_I |
Input |
1-dicokot |
Jam TX kanggo saluran "G" saka XCVR |
|
G_CLK_LOCK |
Input |
1-dicokot |
TX_CLK_STABLE kanggo saluran G saka XCVR |
|
B_CLK_I |
Input |
1-dicokot |
Jam TX kanggo saluran "B" saka XCVR |
|
B_CLK_LOCK |
Input |
1-dicokot |
TX_CLK_STABLE kanggo saluran B saka XCVR |
|
H_SYNC_I |
Input |
1-dicokot |
Pulsa sinkronisasi horisontal |
|
V_SYNC_I |
Input |
1-dicokot |
Pulsa sinkronisasi vertikal |
|
DATA_R_I |
Input |
PIXELS_PER_CLK*8 |
Input data "R". |
Pandhuan pangguna
DS50003319C – 10
© 2024 Microchip Technology Inc lan anak perusahaan
Parameter HDMI TX lan Sinyal Antarmuka
|
……….. lanjutane Jeneng Sinyal Arah Jembar Katrangan |
|||
|
DATA_G_I |
Input |
PIXELS_PER_CLK*8 |
Input data "G". |
|
DATA_B_I |
Input |
PIXELS_PER_CLK*8 |
Input data "B". |
|
TMDS_R_O |
Output |
PIXELS_PER_CLK*10 |
Data sing dikodekake "R". |
|
TMDS_G_O |
Output |
PIXELS_PER_CLK*10 |
Data sing dikodekake "G". |
|
TMDS_B_O |
Output |
PIXELS_PER_CLK*10 |
Data sing dikodekake "B". |
Tabel ing ngisor iki nampilake port kanggo antarmuka AXI4 Stream.
Tabel 3-5. Port Input lan Output kanggo Antarmuka Stream AXI4
|
Jeneng Port |
Jinis |
Jembar |
Katrangan |
|
TDATA_I_VIDEO |
Input |
3*g_BITS_PER_KOMPONEN*g_PIXELS_PER_CLK |
Input data video |
|
TVALID_I_VIDEO |
Input |
1-dicokot |
Video input valid |
|
TREADY_O_VIDEO |
Output |
1-dicokot |
Output slave sinyal siap |
|
TUSER_I_VIDEO |
Input |
4 bit |
bit 0 = ora digunakake bit 1 = VSYNC bit 2 = HSYNC bit 3 = ora digunakake |
Tabel ing ngisor iki nampilake port kanggo mode YCbCr444 nalika mode audio diaktifake.
Tabel 3-6. Input lan Output kanggo Mode YCbCr444 lan Mode Audio Diaktifake
|
Jeneng Sinyal |
Jembar arah |
|
Katrangan |
|
SYS_CLK_I |
Input |
1-dicokot |
Jam sistem, biasane jam sing padha karo pengontrol tampilan |
|
RESET_N_I |
Input |
1-dicokot |
Sinyal reset aktif-kurang asinkron |
|
VIDEO_DATA_VALID_I Input |
|
1-dicokot |
Data video input valid |
|
AUDIO_DATA_VALID_I Input |
|
1-dicokot |
Data paket audio input valid |
|
Y_CLK_I |
Input |
1-dicokot |
Jam TX kanggo saluran "Y" saka XCVR |
|
Y_CLK_LOCK |
Input |
1-dicokot |
TX_CLK_STABLE kanggo saluran Y saka XCVR |
|
Cb_CLK_I |
Input |
1-dicokot |
Jam TX kanggo saluran "Cb" saka XCVR |
|
Cb_CLK_LOCK |
Input |
1-dicokot |
TX_CLK_STABLE kanggo saluran Cb saka XCVR |
|
Cr_CLK_I |
Input |
1-dicokot |
Jam TX kanggo saluran "Cr" saka XCVR |
|
Cr_CLK_LOCK |
Input |
1-dicokot |
TX_CLK_STABLE kanggo saluran Cr saka XCVR |
|
H_SYNC_I |
Input |
1-dicokot |
Pulsa sinkronisasi horisontal |
|
V_SYNC_I |
Input |
1-dicokot |
Pulsa sinkronisasi vertikal |
|
PAKET_HEADER_I |
Input |
PIXELS_PER_CLK*1 |
Header paket kanggo data paket audio |
|
DATA_Y_I |
Input |
PIXELS_PER_CLK*8 |
Ketik data "Y". |
|
DATA_Cb_I |
Input |
PIXELS_PER_CLK*DATA_WIDTH Input data “Cb”. |
|
|
DATA_Cr_I |
Input |
PIXELS_PER_CLK*DATA_WIDTH Input data "Cr". |
|
|
AUX_DATA_Y_I |
Input |
PIXELS_PER_CLK*4 |
Data saluran paket audio "Y". |
|
AUX_DATA_C_I |
Input |
PIXELS_PER_CLK*4 |
Data saluran paket audio "C". |
|
TMDS_R_O |
Output |
PIXELS_PER_CLK*10 |
Data "Cb" sing dikode |
|
TMDS_G_O |
Output |
PIXELS_PER_CLK*10 |
Data sing dikodekake "Y". |
|
TMDS_B_O |
Output |
PIXELS_PER_CLK*10 |
Data "Cr" dienkode |
Tabel ing ngisor iki nampilake port kanggo mode YCbCr422 nalika mode audio diaktifake.
Pandhuan pangguna
DS50003319C – 11
© 2024 Microchip Technology Inc lan anak perusahaan
Parameter HDMI TX lan Sinyal Antarmuka
Tabel 3-7. Input lan Output kanggo Mode YCbCr422 lan Mode Audio Diaktifake
|
Jeneng Sinyal |
Jembar arah |
|
Katrangan |
|
SYS_CLK_I |
Input |
1-dicokot |
Jam sistem, biasane jam sing padha karo pengontrol tampilan |
|
RESET_N_I |
Input |
1-dicokot |
Asynchronous Active -Sinyal reset Low |
|
VIDEO_DATA_VALID_I Input |
|
1-dicokot |
Data video input valid |
|
LANE1_CLK_I |
Input |
1-dicokot |
TX jam kanggo "lane saka XCVE lane 1" saluran saka XCVR |
|
LANE1_CLK_LOCK |
Input |
1-dicokot |
TX_CLK_STABLE kanggo jalur saka jalur XCVE 1 |
|
LANE2_CLK_I |
Input |
1-dicokot |
TX jam kanggo "lane saka XCVE lane 2" saluran saka XCVR |
|
LANE2_CLK_LOCK |
Input |
1-dicokot |
TX_CLK_STABLE kanggo jalur saka jalur XCVE 2 |
|
LANE3_CLK_I |
Input |
1-dicokot |
TX jam kanggo "lane saka XCVE lane 3" saluran saka XCVR |
|
LANE3_CLK_LOCK |
Input |
1-dicokot |
TX_CLK_STABLE kanggo jalur saka jalur XCVE 3 |
|
H_SYNC_I |
Input |
1-dicokot |
Pulsa sinkronisasi horisontal |
|
V_SYNC_I |
Input |
1-dicokot |
Pulsa sinkronisasi vertikal |
|
PAKET_HEADER_I |
Input |
PIXELS_PER_CLK*1 |
Header paket kanggo data paket audio |
|
DATA_Y_I |
Input |
PIXELS_PER_CLK*DATA_WIDTH Input data "Y". |
|
|
DATA_C_I |
Input |
PIXELS_PER_CLK*DATA_WIDTH Input data “C”. |
|
|
AUX_DATA_Y_I |
Input |
PIXELS_PER_CLK*4 |
Data saluran paket audio "Y". |
|
AUX_DATA_C_I |
Input |
PIXELS_PER_CLK*4 |
Data saluran paket audio "C". |
|
TMDS_R_O |
Output |
PIXELS_PER_CLK*10 |
Data sing dikodekake "C". |
|
TMDS_G_O |
Output |
PIXELS_PER_CLK*10 |
Data sing dikodekake "Y". |
|
TMDS_B_O |
Output |
PIXELS_PER_CLK*10 |
Data sing dienkode sing ana gandhengane karo informasi sinkronisasi |
Pandhuan pangguna
DS50003319C – 12
© 2024 Microchip Technology Inc lan anak perusahaan
Register Peta lan Katrangan
4. Register Peta lan Katrangan (Njaluk Pitakonan)
|
Offset |
jeneng |
Bit Pos. |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
0x00 |
SCRAMBLER_IP_EN |
7:0 |
|
|
|
|
|
|
|
MULAI |
|
15:8 |
|
|
|
|
|
|
|
|
||
|
23:16 |
|
|
|
|
|
|
|
|
||
|
31:24 |
|
|
|
|
|
|
|
|
||
|
0x04 |
XCVR_DATA_LANE_ 0_SEL |
7:0 |
|
|
|
|
|
|
Miwiti [1:0] |
|
|
15:8 |
|
|
|
|
|
|
|
|
||
|
23:16 |
|
|
|
|
|
|
|
|
||
|
31:24 |
|
|
|
|
|
|
|
|
||
Pandhuan pangguna
DS50003319C – 13
© 2024 Microchip Technology Inc lan anak perusahaan
Register Peta lan Katrangan
4.1 SCRAMBLER_IP_EN (Njaluk Pitakonan)
Jeneng: SCRAMBLER_IP_EN
Offset: 0x000
Reset: 0x0
Properti: Mung Tulis
Scrambler Aktifake Control Register. Register iki kudu ditulis kanggo entuk Dhukungan 4kp60 kanggo IP HDMI TX
Bit 31 30 29 28 27 26 25 24
Akses
Reset
Bit 23 22 21 20 19 18 17 16
Akses
Reset
Bit 15 14 13 12 11 10 9 8
Akses
Reset
Bit 7 6 5 4 3 2 1 0
|
|
|
|
|
|
|
|
MULAI |
Akses W Reset 0
Bit 0 - MULAI Nulis "1" menyang bit iki miwiti transfer data Scrambler diaktifake. HDMI 2.0 nggunakake wangun scrambling sing dikenal minangka enkoding 8b/10b. Skema enkoding iki digunakake kanggo ngirim data liwat antarmuka HDMI kanthi andal lan efisien.
Pandhuan pangguna
DS50003319C – 14
© 2024 Microchip Technology Inc lan anak perusahaan
Register Peta lan Katrangan
4.2 XCVR_DATA_LANE_0_SEL (Njaluk Pitakonan)
Jeneng: XCVR_DATA_LANE_0_SEL
Offset: 0x004
Reset: 0x1
Properti: Mung Tulis
Daftar XCVR_DATA_LANE_0_SEL milih data sing kudu ditransfer menyang XCVR saka HDMI TX IP kanggo entuk jam kanggo Full HD, 4kp30, 4kp60.
Bit 31 30 29 28 27 26 25 24
|
|
|
|
|
|
|
|
|
Akses
Reset
Bit 23 22 21 20 19 18 17 16
|
|
|
|
|
|
|
|
|
Akses
Reset
Bit 15 14 13 12 11 10 9 8
|
|
|
|
|
|
|
|
|
Akses
Reset
Bit 7 6 5 4 3 2 1 0
|
|
|
|
|
|
|
Miwiti [1:0] |
Akses WW Reset 0 1
Bit 1:0 – START [1:0] Nulis "10" kanggo bit iki miwiti 4KP60 diaktifake lan XCVR data-rate diwenehi minangka FFFFF_00000.
Pandhuan pangguna
DS50003319C – 15
© 2024 Microchip Technology Inc lan anak perusahaan
Simulasi Testbench
5. Simulasi Testbench (Njaluk Pitakonan)
Testbench diwenehake kanggo mriksa fungsi inti HDMI TX. Testbench mung dianggo ing antarmuka native karo 1 piksel saben jam lan mode audio aktif.
Tabel ing ngisor iki nampilake paramèter sing dikonfigurasi miturut aplikasi kasebut.
Tabel 5-1. Parameter Konfigurasi Testbench
|
jeneng |
Parameter Default |
|
Format Warna (g_COLOR_FORMAT) |
RGB |
|
Bit saben komponen (g_BITS_PER_COMPONENT) |
8 |
|
Jumlah Piksel (g_PIXELS_PER_CLK) |
1 |
|
Dhukungan 4Kp60 (g_4K60_DUKUNGAN) |
0 |
|
Mode Audio (g_AUX_CHANNEL_ENABLE) |
1 (Aktifake) |
|
Antarmuka (G_FORMAT) |
0 (Pateni) |
Kanggo simulasi inti nggunakake testbench, tindakake langkah ing ngisor iki:
1. Ing jendhela Design Flow, nggedhekake Nggawe Desain.
2. Klik-tengen Gawe SmartDesign Testbench, banjur klik Run, minangka ditampilake ing tokoh ing ngisor iki. Gambar 5-1. Nggawe SmartDesign Testbench
3. Ketik jeneng kanggo SmartDesign testbench, banjur klik OK.
Gambar 5-2. Jeneng SmartDesign Testbench
Testbench SmartDesign digawe, lan kanvas katon ing sisih tengen panel Design Flow.
Pandhuan pangguna
DS50003319C – 16
© 2024 Microchip Technology Inc lan anak perusahaan
Simulasi Testbench
4. Navigasi menyang Libero® Katalog SoC, pilih View > Windows > IP Catalog, banjur nggedhekake Solutions Video. Klik kaping pindho HDMI TX IP (v5.2.0), banjur klik OK.
5. Ing jendhela Parameter Configurator, pilih Nilai Jumlah piksel dibutuhake, minangka ditampilake ing tokoh ing ngisor iki.
Gambar 5-3. Konfigurasi Parameter
6. Pilih kabeh port, klik-tengen banjur pilih Promote to Top Level.
7. Ing toolbar SmartDesign, klik Generate Component.
8. Ing tab Stimulus Hierarchy, klik-tengen HDMI_TX_TB testbench file, banjur klik Simulate Pre-Synth Design > Open Interactively.
ModelSim® alat mbukak karo testbench, minangka ditampilake ing tokoh ing ngisor iki. Gambar 5-4. Alat ModelSim karo HDMI TX Testbench File
penting: Yen simulasi diselani amarga watesan wektu roto kasebut ing DO file, nggunakake mlayu-kabeh printah kanggo ngrampungake simulasi.
Pandhuan pangguna
DS50003319C – 17
© 2024 Microchip Technology Inc lan anak perusahaan
Simulasi Testbench
5.1 Diagram wektu (Njaluk Pitakonan)
Diagram wektu ing ngisor iki kanggo HDMI TX IP nuduhake data video lan wektu data kontrol kanggo 1 piksel saben jam.
Gambar 5-5. HDMI TX IP Wektu Diagram Data Video kanggo 1 Piksel Saben Jam
Diagram ing ngisor iki nuduhake papat kombinasi data kontrol.
Gambar 5-6. HDMI TX IP Wektu Diagram Data Kontrol kanggo 1 Piksel Saben Jam
Pandhuan pangguna
DS50003319C – 18
© 2024 Microchip Technology Inc lan anak perusahaan
Integrasi Sistem
6. Integrasi Sistem (Njaluk Pitakonan)
Bagean iki nuduhake minangkaampgambaran desain.
Tabel ing ngisor iki nampilake konfigurasi PF XCVR, PF TX PLL, lan PF CCC.
Tabel 6-1. PF XCVR, PF TX PLL, lan Konfigurasi PF CCC
|
Resolusi |
|
Bit Jembar PF XCVR Konfigurasi |
PF TX PLL Konfigurasi |
Konfigurasi PF CCC |
||||
|
Data TX Kab Rate |
Jam TX Kab Divisi Faktor |
TX PCS Kain Jembar |
Dipengini Output Bit Jam |
Referensi jam Frekuensi |
Input Frekuensi |
Output Frekuensi |
||
|
1PXL (1080p60) 8 |
|
1485 |
4 |
10 |
5940 |
148.5 |
NA |
NA |
|
1PXL (1080p30) 10 |
|
925 |
4 |
10 |
3700 |
148.5 |
92.5 |
74 |
|
12 |
1113.75 |
4 |
10 |
4455 |
148.5 |
111.375 |
74.25 |
|
|
16 |
1485 |
4 |
10 |
5940 |
148.5 |
148.5 |
74.25 |
|
|
4PXL (1080p60) 10 |
|
1860 |
4 |
40 |
7440 |
148.5 |
46.5 |
37.2 |
|
12 |
2229 |
4 |
40 |
8916 |
148.5 |
55.725 |
37.15 |
|
|
16 |
2970 |
2 |
40 |
5940 |
148.5 |
74.25 |
37.125 |
|
|
4PXL (4kp30) |
8 |
2970 |
2 |
40 |
5940 |
148.5 |
NA |
NA |
|
10 |
3712.5 |
2 |
40 |
7425 |
148.5 |
92.812 |
74.25 |
|
|
12 |
4455 |
1 |
40 |
4455 |
148.5 |
111.375 |
74.25 |
|
|
16 |
5940 |
1 |
40 |
5940 |
148.5 |
148.5 |
74.25 |
|
|
4PXL (4Kp60) |
8 |
5940 |
1 |
40 |
5940 |
148.5 |
NA |
NA |
HDMI TX S Kabample Design, nalika diatur ing g_BITS_PER_COMPONENT = 8-dicokot lan
g_PIXELS_PER_CLK = 1 mode PXL, ditampilake ing gambar ing ngisor iki.
Gambar 6-1. HDMI TX S Kabample Desain
HDMI_TX_C0_0
PF_INIT_MONITOR_C0_0
|
FABRIC_POR_N PCIE_INIT_DONE USRAM_INIT_DONE SRAM_INIT_DONE DEVICE_INIT_DONE XCVR_INIT_DONE USRAM_INIT_FROM_SNVM_DONE USRAM_INIT_FROM_UPROM_DONE USRAM_INIT_FROM_SPI_DONE SRAM_INIT_FROM_SNVM_DONE SRAM_INIT_FROM_UPROM_DONE SRAM_INIT_FROM_SPI_DONE AUTOCALIB_DONE |
PF_INIT_MONITOR_C0
CORERESET_PF_C0_0
|
CLK EXT_RST_N BANK_x_VDDI_STATUS BANK_y_VDDI_STATUS PLL_POWERDOWN_B PLL_LOCK FABRIC_RESET_N SS_SIBUK INIT_DONE FF_US_RESTORE FPGA_POR_N |
CORERESET_PF_C0
Display_Controller_C0_0
|
FRAME_END_O H_SYNC_O RESETN_I V_SYNC_O SYS_CLK_I V_AKTIF_O ENABLE_I DATA_TRIGGER_O H_RES_O[15:0] V_RES_O[15:0] |
Display_Controller_C0
pattern_generator_verilog_pattern_0
|
DATA_VALID_O SYS_CLK_I FRAME_END_O RESET_N_I LINE_END_O DATA_EN_I RED_O[7:0] FRAME_END_I Ijo_O[7:0] POLA_SEL_I[2:0] BIRU_O[7:0] BAYER_O[7:0] |
Test_Pola_Generator_C1
PF_XCVR_REF_CLK_C0_0
|
RESET_N_I SYS_CLK_I VIDEO_DATA_VALID_I R_CLK_I R_CLK_LOCK G_CLK_I G_CLK_LOCK TMDS_R_O[9:0] B_CLK_I TMDS_G_O[9:0] B_CLK_LOCK TMDS_B_O[9:0] V_SYNC_I XCVR_LANE_0_DATA_O[9:0] H_SYNC_I
DATA_R_I[7:0]
DATA_G_I[7:0]
DATA_B_I[7:0] |
HDMI_TX_C0
PF_TX_PLL_C0_0
PF_XCVR_ERM_C0_0
|
PADs_OUT LANE3_TXD_N CLKS_FROM_TXPLL_0 LANE3_TXD_P LANE0_IN LANE2_TXD_N LANE0_PCS_ARST_N LANE2_TXD_P LANE0_PMA_ARST_N LANE1_TXD_N LANE0_TX_DATA[9:0] LANE1_TXD_P LANE1_IN LANE0_TXD_N LANE1_PCS_ARST_N LANE0_TXD_P LANE1_PMA_ARST_N LANE0_OUT LANE1_TX_DATA[9:0] LANE0_TX_CLK_R LANE2_IN LANE0_TX_CLK_STABLE LANE2_PCS_ARST_N LANE1_OUT LANE2_PMA_ARST_N LANE1_TX_CLK_R LANE2_TX_DATA[9:0] LANE1_TX_CLK_STABLE LANE3_IN LANE2_OUT LANE3_PCS_ARST_N LANE2_TX_CLK_R LANE3_PMA_ARST_N LANE2_TX_CLK_STABLE LANE3_TX_DATA[9:0] LANE3_OUT LANE3_TX_CLK_STABLE |
PF_XCVR_ERM_C0
LANE3_TXD_N LANE3_TXD_P LANE2_TXD_N LANE2_TXD_P LANE1_TXD_N LANE1_TXD_P LANE0_TXD_N LANE0_TXD_P
POLA_SEL_I[2:0] REF_CLK_PAD_P REF_CLK_PAD_N
|
REF_CLK_PAD_P REF_CLK_PAD_NREF_CLK |
|
REF_CLKPLL_LOCKCLKS_TO_XCVR |
PF_XCVR_REF_CLK_C0
PF_TX_PLL_C0
Kanggo Example, ing konfigurasi 8-dicokot, komponen ing ngisor iki minangka bagéan saka desain: • PF_XCVR_ERM (PF_XCVR_ERM_C0_0) diatur kanggo tingkat data 1485 Mbps ing mode PMA kanggo TX mung, karo jembaré data diatur minangka 10 dicokot kanggo mode 1pxl lan Jam referensi 148.5 MHz, adhedhasar setelan tabel sadurunge
• Output LANE0_TX_CLK_R saka PF_XCVR_ERM_C0_0 digawe minangka jam 148.5 MHz, adhedhasar setelan tabel sadurunge
• SYS_CLK_I (HDMI_TX_C0, Display_Controller_C0, pattern_generator_C0, CORERESET_PF_C0, lan PF_INIT_MONITOR_C0) didhukung dening LANE0_TX_CLK_R, yaiku 148.5 MHz
• R_CLK_I, G_CLK_I, lan B_CLK_I didorong dening LANE3_TX_CLK_R, LANE2_TX_CLK_R, lan LANE1_TX_CLK_R, mungguh
Pandhuan pangguna
DS50003319C – 19
© 2024 Microchip Technology Inc lan anak perusahaan
Integrasi Sistem
Sampintegrasi kanggo, g_BITS_PER_COMPONENT = 8 lan g_PIXELS_PER_CLK = 4. Kanggo Example, ing konfigurasi 8-dicokot, komponen ing ngisor iki minangka bagéan saka desain: • PF_XCVR_ERM (PF_XCVR_ERM_C0_0) diatur kanggo tingkat data 2970 Mbps ing mode PMA kanggo
Mung TX, kanthi jembar data dikonfigurasi minangka 40-bit kanggo mode 1pxl lan jam referensi 148.5 MHz adhedhasar setelan tabel sadurunge.
• Output LANE0_TX_CLK_R saka PF_XCVR_ERM_C0_0 digawe minangka jam 74.25 MHz, adhedhasar setelan tabel sadurunge
• SYS_CLK_I (HDMI_TX_C0, Display_Controller_C0, pattern_generator_C0, CORERESET_PF_C0, lan PF_INIT_MONITOR_C0) didhukung dening LANE0_TX_CLK_R, yaiku 148.5 MHz
• R_CLK_I, G_CLK_I, lan B_CLK_I didorong dening LANE3_TX_CLK_R, LANE2_TX_CLK_R, lan LANE1_TX_CLK_R, mungguh
HDMI TX S Kabample Desain, nalika diatur ing g_BITS_PER_COMPONENT = 12 Bit lan g_PIXELS_PER_CLK = 1 mode PXL, ditampilake ing tokoh ing ngisor iki.
Gambar 6-2. HDMI TX S Kabample Desain
PF_XCVR_ERM_C0_0
POLA_SEL_I[2:0]
REF_CLK_PAD_P REF_CLK_PAD_N
PF_CCC_C1_0
|
REF_CLK_0 OUT0_FABCLK_0PLL_LOCK_0 |
PF_CCC_C1
PF_INIT_MONITOR_C0_0
CORERESET_PF_C0_0
|
CLK EXT_RST_N BANK_x_VDDI_STATUS BANK_y_VDDI_STATUS PLL_POWERDOWN_B PLL_LOCK FABRIC_RESET_N SS_SIBUK INIT_DONE FF_US_RESTORE FPGA_POR_N |
CORERESET_PF_C0
Display_Controller_C0_0
|
FRAME_END_O H_SYNC_O RESETN_I V_SYNC_O SYS_CLK_I V_AKTIF_O ENABLE_I DATA_TRIGGER_O H_RES_O[15:0] V_RES_O[15:0] |
Display_Controller_C0
pattern_generator_verilog_pattern_0
|
DATA_VALID_O SYS_CLK_I FRAME_END_O RESET_N_I LINE_END_O DATA_EN_I RED_O[7:0] FRAME_END_I Ijo_O[7:0] POLA_SEL_I[2:0] BIRU_O[7:0] BAYER_O[7:0] |
Test_Pola_Generator_C0
PF_XCVR_REF_CLK_C0_0
|
REF_CLK_PAD_P REF_CLK_PAD_NREF_CLK |
PF_XCVR_REF_CLK_C0
HDMI_TX_0
|
RESET_N_I SYS_CLK_I VIDEO_DATA_VALID_I R_CLK_I R_CLK_LOCK G_CLK_I G_CLK_LOCK TMDS_R_O[9:0] B_CLK_I TMDS_G_O[9:0] B_CLK_LOCK TMDS_B_O[9:0] V_SYNC_I XCVR_LANE_0_DATA_O[9:0] H_SYNC_I
DATA_R_I[11:4]
DATA_G_I[11:4]
DATA_B_I[11:4] |
HDMI_TX_C0
PF_TX_PLL_C0_0
|
PADs_OUT CLKS_FROM_TXPLL_0 LANE3_TXD_N LANE0_IN LANE3_TXD_P LANE0_PCS_ARST_N LANE2_TXD_N LANE0_PMA_ARST_N LANE2_TXD_P LANE0_TX_DATA[9:0] LANE1_TXD_N LANE1_IN LANE1_TXD_P LANE1_PCS_ARST_N LANE0_TXD_N LANE1_PMA_ARST_N LANE0_TXD_P LANE1_TX_DATA[9:0] LANE0_OUT LANE2_IN LANE1_OUT LANE2_PCS_ARST_N LANE1_TX_CLK_R LANE2_PMA_ARST_N LANE1_TX_CLK_STABLE LANE2_TX_DATA[9:0] LANE2_OUT LANE2_TX_CLK_R LANE3_PCS_ARST_N LANE2_TX_CLK_STABLE LANE3_PMA_ARST_N LANE3_OUT LANE3_TX_DATA[9:0] LANE3_TX_CLK_R LANE3_TX_CLK_STABLE |
PF_XCVR_ERM_C0
LANE3_TXD_N LANE3_TXD_P LANE2_TXD_N LANE2_TXD_P LANE1_TXD_N LANE1_TXD_P LANE0_TXD_N LANE0_TXD_P
|
FABRIC_POR_N PCIE_INIT_DONE USRAM_INIT_DONE SRAM_INIT_DONE DEVICE_INIT_DONE XCVR_INIT_DONE USRAM_INIT_FROM_SNVM_DONE USRAM_INIT_FROM_UPROM_DONE USRAM_INIT_FROM_SPI_DONE SRAM_INIT_FROM_SNVM_DONE SRAM_INIT_FROM_UPROM_DONE SRAM_INIT_FROM_SPI_DONE AUTOCALIB_DONE |
|
REF_CLKPLL_LOCKCLKS_TO_XCVR |
PF_INIT_MONITOR_C0
PF_TX_PLL_C0
Sampintegrasi kanggo, g_BITS_PER_COMPONENT > 8 lan g_PIXELS_PER_CLK = 1. Kanggo Example, ing konfigurasi 12-bit, komponen ing ngisor iki minangka bagéan saka desain:
• PF_XCVR_ERM (PF_XCVR_ERM_C0_0) dikonfigurasi kanggo tingkat data 111.375 Mbps ing mode PMA mung kanggo TX, kanthi jembar data dikonfigurasi minangka 10 bit kanggo mode 1pxl lan jam referensi 1113.75 Mbps, adhedhasar Tabel 6-1 setelan
• Output LANE1_TX_CLK_R saka PF_XCVR_ERM_C0_0 digawe minangka jam 111.375 MHz, adhedhasar Tabel 6-1 setelan
• R_CLK_I, G_CLK_I, lan B_CLK_I didorong dening LANE3_TX_CLK_R, LANE2_TX_CLK_R, lan LANE1_TX_CLK_R, mungguh
• PF_CCC_C0 ngasilake jam sing jenenge OUT0_FABCLK_0, kanthi frekuensi 74.25 MHz, nalika jam input 111.375 MHz, sing didorong dening LANE1_TX_CLK_R
• SYS_CLK_I (HDMI_TX_C0, Display_Controller_C0, pattern_generator_C0, CORERESET_PF_C0, lan PF_INIT_MONITOR_C0) didhukung dening OUT0_FABCLK_0, yaiku 74.25 MHz
Sampintegrasi kanggo, g_BITS_PER_COMPONENT > 8 lan g_PIXELS_PER_CLK = 4. Kanggo Example, ing konfigurasi 12-bit, komponen ing ngisor iki minangka bagéan saka desain:
• PF_XCVR_ERM (PF_XCVR_ERM_C0_0) dikonfigurasi kanggo tingkat data 4455 Mbps ing mode PMA mung kanggo TX, kanthi jembar data dikonfigurasi minangka 40 bit kanggo mode 4pxl lan jam referensi 111.375 MHz, adhedhasar Tabel 6-1 setelan
• Output LANE1_TX_CLK_R saka PF_XCVR_ERM_C0_0 digawe minangka jam 111.375 MHz, adhedhasar Tabel 6-1 setelan
Pandhuan pangguna
DS50003319C – 20
© 2024 Microchip Technology Inc lan anak perusahaan
Integrasi Sistem
• R_CLK_I, G_CLK_I, lan B_CLK_I didorong dening LANE3_TX_CLK_R, LANE2_TX_CLK_R, lan LANE1_TX_CLK_R, mungguh
• PF_CCC_C0 ngasilake jam sing jenenge OUT0_FABCLK_0, kanthi frekuensi 74.25 MHz, nalika jam input 111.375 MHz, sing didorong dening LANE1_TX_CLK_R
• SYS_CLK_I (HDMI_TX_C0, Display_Controller_C0, pattern_generator_C0, CORERESET_PF_C0, lan PF_INIT_MONITOR_C0) didhukung dening OUT0_FABCLK_0, yaiku 74.25 MHz
Pandhuan pangguna
DS50003319C – 21
© 2024 Microchip Technology Inc lan anak perusahaan
Riwayat Revisi
7. Riwayat Revisi (Njaluk Pitakonan)
Riwayat revisi nggambarake owah-owahan sing ditindakake ing dokumen kasebut. Owah-owahan kasebut didhaptar kanthi revisi, diwiwiti saka publikasi paling anyar.
Tabel 7-1. Riwayat Revisi
|
Revisi |
Tanggal |
Katrangan |
|
C |
05/2024 |
Ing ngisor iki dhaptar owah-owahan ing revisi C dokumen kasebut: • Dianyari Pambuka bagean • Dibusak tabel panggunaan sumber kanggo siji piksel lan papat piksel lan ditambahake Tabel 2 lan Tabel 3 in 1. Pemanfaatan Sumber Daya bagean • Dianyari Tabel 3-1 ing 3.1. Parameter Konfigurasi bagean • Ditambahake Tabel 3-6 lan Tabel 3-7 ing 3.2. Pelabuhan bagean • Ditambahake 6. Integrasi Sistem bagean |
|
B |
|
09/2022 Ing ngisor iki dhaptar owah-owahan ing revisi B dokumen kasebut: • Dianyari isi Fitur lan Pambuka • Ditambahake Gambar 2-2 kanggo Mode Audio dipatèni • Ditambahake Tabel 3-4 lan Tabel 3-5 • Dianyari ing Tabel 3-2 lan Tabel 3-3 • Dianyari Tabel 3-1 • Dianyari 1. Pemanfaatan Sumber Daya • Dianyari Gambar 1-1 • Dianyari Gambar 5-3 |
|
A |
|
04/2022 Ing ngisor iki dhaptar owah-owahan ing revisi A dokumen: • Dokumen kasebut dipindhah menyang cithakan Microchip • Nomer dokumen dianyari dadi DS50003319 saka 50200863 |
|
2.0 |
— |
Ing ngisor iki ringkesan owah-owahan sing ditindakake ing revisi iki. • Fitur Added lan kulawarga Didhukung bagean |
|
1.0 |
|
08/2021 Revisi awal |
Pandhuan pangguna
DS50003319C – 22
© 2024 Microchip Technology Inc lan anak perusahaan
Dhukungan FPGA Microchip
Klompok produk Microchip FPGA ndhukung produk karo macem-macem layanan dhukungan, kalebu Layanan Pelanggan, Pusat Dhukungan Teknis Pelanggan, a websitus, lan kantor sales donya. Pelanggan disaranake ngunjungi sumber online Microchip sadurunge ngubungi dhukungan amarga kemungkinan pitakone wis dijawab.
Hubungi Pusat Dhukungan Teknis liwat websitus ing www.microchip.com/support. Sebutake nomer Komponen Piranti FPGA, pilih kategori kasus sing cocog, lan upload desain files nalika nggawe cilik support technical.
Hubungi Layanan Pelanggan kanggo dhukungan produk non-teknis, kayata rega produk, upgrade produk, informasi nganyari, status pesenan, lan wewenang.
• Saka Amerika Utara, nelpon 800.262.1060
• Saka liyane saka donya, nelpon 650.318.4460
• Fax, saka ngendi wae ing donya, 650.318.8044
Informasi Microchip
Microchip kasebut Websitus
Microchip nyedhiyakake dhukungan online liwat kita websitus ing www.microchip.com/. Iki websitus digunakake kanggo nggawe files lan informasi gampang kasedhiya kanggo pelanggan. Sawetara konten sing kasedhiya kalebu:
• Dhukungan produk - Lembar data lan kesalahan, cathetan aplikasi lan sampprogram le, sumber desain, Panuntun pangguna lan dokumen support hardware, Rilis piranti lunak paling anyar lan piranti lunak arsip
• Dhukungan Teknis Umum - Pitakonan sing Sering Ditakoni (FAQ), panjalukan dhukungan teknis, grup diskusi online, daftar anggota program mitra desain Microchip
• Bisnis Microchip - Pandhuan pamilih lan pesenan produk, siaran pers Microchip paling anyar, dhaptar seminar lan acara, dhaptar kantor penjualan Microchip, distributor lan perwakilan pabrik
Layanan Notifikasi Ganti Produk
Layanan kabar pangowahan produk Microchip mbantu para pelanggan tetep saiki ing produk Microchip. Pelanggan bakal nampa kabar email yen ana owah-owahan, nganyari, revisi utawa kesalahan sing ana gandhengane karo kulawarga produk utawa alat pangembangan sing dikarepake.
Kanggo ndhaftar, pindhah menyang www.microchip.com/pcn lan tindakake pandhuan registrasi. Dhukungan Pelanggan
Pangguna produk Microchip bisa nampa pitulungan liwat sawetara saluran: • Distributor utawa Perwakilan
• Kantor Penjualan Lokal
• Embedded Solutions Engineer (ESE)
• Dhukungan Teknis
Pelanggan kudu hubungi distributor, wakil utawa ESE kanggo dhukungan. Kantor penjualan lokal uga kasedhiya kanggo mbantu para pelanggan. Dhaptar kantor penjualan lan lokasi kalebu ing dokumen iki.
Dhukungan teknis kasedhiya liwat websitus ing: www.microchip.com/support Fitur Proteksi Kode Piranti Microchip
Elinga rincian ing ngisor iki babagan fitur perlindungan kode ing produk Microchip:
Pandhuan pangguna
DS50003319C – 23
© 2024 Microchip Technology Inc lan anak perusahaan
• Produk Microchip nyukupi spesifikasi sing ana ing Lembar Data Microchip tartamtu.
• Microchip pitados bilih kulawarga produk aman nalika digunakake ing proses dimaksudaké, ing specifications operasi, lan ing kahanan normal.
• Nilai Microchip lan agresif nglindhungi hak properti intelektual sawijining. Usaha kanggo nglanggar fitur perlindungan kode produk Microchip dilarang banget lan bisa uga nglanggar Digital Millennium Copyright Act.
• Microchip utawa pabrikan semikonduktor liyane ora bisa njamin keamanan kode kasebut. Proteksi kode ora ateges manawa produk kasebut "ora bisa dipecah". Proteksi kode terus berkembang. Microchip nduweni komitmen kanggo terus ningkatake fitur perlindungan kode produk kita.
Kabar Legal
Publikasi iki lan informasi ing kene mung bisa digunakake karo produk Microchip, kalebu kanggo ngrancang, nguji, lan nggabungake produk Microchip karo aplikasi sampeyan. Panganggone informasi iki kanthi cara liya nglanggar syarat kasebut. Informasi babagan aplikasi piranti diwenehake mung kanggo penak sampeyan lan bisa uga diganti karo nganyari. Sampeyan tanggung jawab kanggo mesthekake yen aplikasi sampeyan cocog karo spesifikasi sampeyan. Hubungi kantor sales Microchip lokal kanggo dhukungan tambahan utawa, entuk dhukungan tambahan ing www.microchip.com/en-us/support/design-help/client-support-services.
INFORMASI IKI DISEDIAKAN BY MICROCHIP "AS IS". MICROCHIP TANPA REPRESENTASI UTAWA JAMINAN APA SAJA APA SAJA UTAWA TERSURAT, TERTULIS UTAWA LISAN, STATUTORY UTAWA LAIN, sing ana hubungane karo informasi kasebut kalebu nanging ora winates karo JAMINAN NON-INFLARITY, NON-INFRINGEMENT. TUJUAN, Utawa JAMINAN sing ana gandhengane karo KONDISI, KUALITAS, UTAWA KINERJA.
MICROCHIP ORA TANGGUH TANGGUNG JAWAB ANGGAP, KHUSUS, PUNITIF, INSIDENTAL, UTAWA KONSEQUENTIAL RUGI, RUSAK, BIAYA, UTAWA BAYARAN APA SAJA KANGGO ING INFORMASI UTAWA PENGGUNAAN, NANGUN SING DIBUAT, SANAYAN ANA KEMUNGKINAN UTAWA KERUSAKAN SING BISA DIPIKIR. TO THE FULLEST EXTENT diijini dening hukum, TANGGUNG JAWAB TOTAL MICROCHIP ING ALL CLAIMS ing sembarang cara sing ana hubungane karo informasi utawa panggunaan ora ngluwihi jumlah biaya, yen ana, sing sampeyan wis mbayar langsung menyang microchip kanggo informasi.
Panggunaan piranti Microchip ing support urip lan / utawa aplikasi safety tanggung ing resiko panuku, lan panuku setuju kanggo defend, indemnify lan terus Microchip mbebayani saka samubarang lan kabeh karusakan, claims, cocog, utawa expenses asil saka nggunakake kuwi. Ora ana lisensi sing diwenehake, kanthi implisit utawa liya, miturut hak properti intelektual Microchip kajaba kasebut.
merek dagang
Jeneng lan logo Microchip, logo Microchip, Adaptec, AVR, logo AVR, AVR Freaks, BesTime, BitCloud, CryptoMemory, CryptoRF, dsPIC, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXStylus, maXTouch MediaLB, megaAVR, Microsemi, logo Microsemi, MOST, MOST logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, PolarFire, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetricom , SyncServer, Tachyon, TimeSource, tinyAVR, UNI/O, Vectron, lan XMEGA minangka merek dagang kadhaptar saka Microchip Technology Incorporated ing AS lan negara liya.
AgileSwitch, ClockWorks, Perusahaan Solusi Kontrol Tertanam, EtherSynch, Flashtec, Kontrol Kacepetan Hiper, Beban HyperLight, Libero, motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus, logo ProASIC Plus, Quiet-Wire, SmartFusion, SyncWorld, TimeCesium, TimeHub, TimePictra, TimeProvider, lan ZL minangka merek dagang kadhaptar saka Microchip Technology Incorporated ing AS
Penindasan Tombol Adjacent, AKS, Analog-kanggo-Digital Age, Kapasitor Sembarang, AnyIn, AnyOut, Augmented Switching, BlueSky, BodyCom, Clockstudio, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic
Pandhuan pangguna
DS50003319C – 24
© 2024 Microchip Technology Inc lan anak perusahaan
Pencocokan Rata-rata, DAM, ECAN, Espresso T1S, EtherGREEN, EyeOpen, GridTime, IdealBridge, IGaT, In-Circuit Serial Programming, ICSP, INICnet, Intelligent Parallel, IntelliMOS, Inter-Chip Connectivity, JitterBlocker, Knob-on-Display, MarginLink, maxCrypto, maksView, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, mSiC, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, Power MOS IV, Power MOS 7, PowerSmart, PureSilicon , QMatrix, REAL ICE, Ripple Blocker, RTAX, RTG4, SAM-ICE, Serial Quad I/O, simpleMAP, SimpliPHY, SmartBuffer, SmartHLS, SMART-IS, storClad, SQI, SuperSwitcher, SuperSwitcher II, Switchtec, SynchroPHY, Total Endurance , Trusted Time, TSHARC, Turing, USBCheck, VariSense, VectorBlox, VeriPHY, ViewSpan, WiperLock, XpressConnect, lan ZENA minangka merek dagang Microchip Technology Incorporated ing AS lan negara liya.
SQTP minangka tandha layanan saka Microchip Technology Incorporated ing AS
Logo Adaptec, Frequency on Demand, Silicon Storage Technology, lan Symmcom minangka merek dagang kadhaptar saka Microchip Technology Inc. ing negara liya.
GestIC minangka merek dagang kadhaptar saka Microchip Technology Germany II GmbH & Co. KG, anak perusahaan saka Microchip Technology Inc., ing negara liya.
Kabeh merek dagang liyane sing kasebut ing kene minangka properti saka perusahaan kasebut. © 2024, Microchip Technology Incorporated lan anak perusahaan. Kabeh hak dilindhungi undhang-undhang. ISBN:
Sistem Manajemen Mutu
Kanggo informasi babagan Sistem Manajemen Kualitas Microchip, bukak www.microchip.com/quality.
Pandhuan pangguna
DS50003319C – 25
© 2024 Microchip Technology Inc lan anak perusahaan
Dodolan lan Layanan ing saindenging jagad
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DS50003319C – 26
© 2024 Microchip Technology Inc lan anak perusahaan
Dokumen / Sumber Daya
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MICROCHIP DS50003319C-13 Ethernet HDMI TX IP [pdf] Pandhuan pangguna DS50003319C - 13, DS50003319C - 2, DS50003319C - 3, DS50003319C-13 Ethernet HDMI TX IP, DS50003319C-13, Ethernet HDMI TX IP, HDMI TX IP, IP |
