DS50003319C-13 Ethernet HDMI TX IP
HDMI TX IP User Guide
Nhanganyaya (Bvunza mubvunzo)
Microchip's High-Definition Multimedia Interface (HDMI) transmitter IP inotsigira kufambisa vhidhiyo uye odhiyo packet data inotsanangurwa muHDMI yakatarwa.
HDMI inoshandisa Transition Minimized Differential Signaling (TMDS) kuti ifambise zvakakura mavhoriyamu edhijitari data pamakiromita akareba etambo, kuve nechokwadi chekufambisa-kumhanya, serial, uye yakavimbika dhijitari chiratidzo chekufambisa. A TMDS link ine imwechete wachi chiteshi uye matatu data chiteshi. Vhidhiyo pixel wachi inofambiswa pane TMDS wachi chiteshi, iyo inobatsira kuchengetedza masaini mukuyananisa. Vhidhiyo data inotakurwa se24-bit pixels pane matatu TMDS data chiteshi, apo yega yega data chiteshi chakarongerwa tsvuku, girinhi, uye yebhuruu ruvara chikamu. Audio data inotakurwa se8-bit mapaketi paTMDS yegirini uye tsvuku chiteshi.
TMDS encoder inobvumira kufambisa serial data nekumhanya kwakanyanya, uku ichideredza mukana weElectro-magnetic Interference (EMI) pamusoro petambo dzemhangura nekudzikisa huwandu hwekuchinja (kuderedza kupindira pakati pechaneti), uye kuwana Direct Current (DC) chiyero, pawaya. , nekuchengeta nhamba yeayo nemazero pamutsetse yakada kuenzana.
HDMI TX IP yakagadzirirwa kushandiswa pamwe chete nePolarFire® SoC uye PolarFire mudziyo transceivers. IP inoenderana neHDMI 1.4 uye HDMI 2.0, inotsigira kusvika kumafuremu makumi matanhatu pasekondi, ine bandwidth yakakura ye60 Gbps. Iyo IP inoshandisa TMDS encoder inoshandura iyo 18-bit vhidhiyo data pachiteshi uye odhiyo packet kuita gumi-bit DC-yakaenzana, uye shanduko yakaderedzwa kutevedzana. Inobva yatumirwa serially pachiyero chegumi-bits pa pixel, pachiteshi. Munguva yevhidhiyo isina nguva, tokeni dzekutonga dzinofambiswa. Aya ma tokeni anogadzirwa zvichienderana nehsync uye vsync masaini. Munguva yedata chitsuwa nguva, odhiyo pakiti inofambiswa segumi-bit mapaketi pane tsvuku uye girinhi chiteshi.
User Guide
DS50003319C - 1
© 2024 Microchip Technology Inc. uye masangano ayo
Summary
Tafura inotevera inopa pfupiso yeHDMI TX IP maitiro.
Tafura 1. HDMI TX IP Maitiro
|
Core Version |
Iri bhuku remushandisi rinotsigira HDMI TX IP v5.2.0 |
|
Inotsigirwa Mudziyo Mhuri |
• PolarFire® SoC • PolarFire |
|
Inotsigirwa Tool Flow |
Inoda Libero® SoC v11.4 kana gare gare inoburitswa |
|
Inotsigirwa Interfaces |
Mainterface anotsigirwa neHDMI TX IP ndeaya: • AXI4-Stream -Iyi musimboti inotsigira AXI4-Kuyerera kune ekuisa madoko. Kana yakagadziriswa mune iyi modhi, IP inotora AXI4 Stream yakajairwa zvichemo zvikwangwani semapupu. • AXI4-Lite Configuration Interface -Iyi Core inotsigira AXI4-Lite yekumisikidza interface ye4Kp60 inodiwa. Mune iyi modhi, IP yekupinda inopihwa kubva kuSoftConsole. • Native -Kana yakagadziridzwa mune iyi modhi, IP inotora yemuno vhidhiyo uye masaini masaini seyekupinza. |
|
Rezinesi |
HDMI TX IP inopihwa maviri anotevera marezinesi sarudzo: • Encrypted: Yakazara encrypted RTL kodhi inopihwa iyo yakakosha. Inowanikwa mahara nechero rezinesi reLibero, zvichiita kuti musimboti ugadzirwe neSmartDesign. Iwe unogona kuita Simulation, Synthesis, Layout, uye kuronga iyo FPGA silicon uchishandisa Libero dhizaini suite. • RTL: Yakazara RTL sosi kodhi rezinesi rakakiiwa, iro rinoda kutengwa zvakasiyana. |
Features
HDMI TX IP ine zvinotevera maficha:
• Inoenderana neHDMI 2.0 uye 1.4b
• Inotsigira imwe kana mana chiratidzo/pixel pawachi inopinza
• Inotsigira Sarudzo kusvika ku3840 x 2160 pa60 fps
• Inotsigira 8, 10, 12, uye 16-bit kudzika kwemavara
• Inotsigira mafomati emavara akadai seRGB, YUV 4:2:2, uye YUV 4:4:4
• Inotsigira odhiyo kusvika makumi matatu nemaviri chiteshi
• Inotsigira Encoding Scheme - TMDS
• Inotsigira Native uye AXI4 Stream Vhidhiyo uye Audio Data interface
• Inotsigira Native uye AXI4-Lite Configuration interface kuti parameter kugadziriswa
Installation Instructions
Iyo IP musimboti inofanirwa kuiswa kune IP Catalog yeLibero® SoC software otomatiki kuburikidza neiyo IP Catalog yekuvandudza basa muLibero SoC software, kana iyo inotorwa nemaoko kubva kukhathalogi. Kana iyo IP musimboti yaiswa muLibero SoC software IP Catalog, inogadziriswa, inogadzirwa, uye inomisikidzwa mukati meSmartDesign kuti ibatanidzwe muLibero purojekiti.
User Guide
DS50003319C - 2
© 2024 Microchip Technology Inc. uye masangano ayo
Resource Utilization (Bvunza mubvunzo)
HDMI TX IP inoshandiswa muPolarFire® FPGA (MPF300T – 1FCG1152I Package).
Tafura inotevera inoburitsa zviwanikwa zvinoshandiswa apo g_PIXELS_PER_CLK = 1PXL.
Tafura 2. Resource Utilization ye1PXL
|
|
g_COLOR_FORMAT g_BITS_PER_COMPONENT (Bits) |
g_AUX_CHANNEL_ENABLE g_4K60_SUPPORT Fabric |
|
4LUT |
Fabric DFF |
Interface 4LUT |
Interface DFF |
SRAM (64×12) |
|
RGB |
8 |
Enable |
Disable |
787 |
514 |
108 |
108 |
9 |
|
Disable |
Disable |
819 |
502 |
108 |
108 |
9 |
||
|
10 |
Disable |
Disable |
1070 |
849 |
156 |
156 |
13 |
|
|
12 |
Disable |
Disable |
1084 |
837 |
156 |
156 |
13 |
|
|
16 |
Disable |
Disable |
1058 |
846 |
156 |
156 |
13 |
|
|
YCbCr422 |
8 |
Disable |
Disable |
696 |
473 |
96 |
96 |
8 |
|
YCbCr444 |
8 |
Disable |
Disable |
819 |
513 |
108 |
108 |
9 |
|
10 |
Disable |
Disable |
1068 |
849 |
156 |
156 |
13 |
|
|
12 |
Disable |
Disable |
1017 |
837 |
156 |
156 |
13 |
|
|
16 |
Disable |
Disable |
1050 |
845 |
156 |
156 |
13 |
Tafura inotevera inoburitsa zviwanikwa zvinoshandiswa apo g_PIXELS_PER_CLK = 4PXL.
Tafura 3. Resource Utilization ye4PXL
|
|
g_COLOR_FORMAT g_BITS_PER_COMPONENT (Bits) |
g_AUX_CHANNEL_ENABLE g_4K60_SUPPORT Fabric |
|
4LUT |
Fabric DFF |
Interface 4LUT |
Interface DFF |
SRAM (64×12) |
|
RGB |
8 |
Disable |
Enable |
4078 |
2032 |
144 |
144 |
12 |
|
Enable |
Disable |
1475 |
2269 |
144 |
144 |
12 |
||
|
Disable |
Disable |
1393 |
1092 |
144 |
144 |
12 |
||
|
10 |
Disable |
Disable |
2151 |
1635 |
264 |
264 |
22 |
|
|
12 |
Disable |
Disable |
1909 |
1593 |
264 |
264 |
22 |
|
|
16 |
Disable |
Disable |
1645 |
1284 |
264 |
264 |
22 |
|
|
YCbCr422 |
8 |
Disable |
Disable |
1265 |
922 |
144 |
144 |
12 |
|
YCbCr444 |
8 |
Disable |
Disable |
1119 |
811 |
144 |
144 |
12 |
|
10 |
Disable |
Disable |
2000 |
1627 |
264 |
264 |
22 |
|
|
12 |
Disable |
Disable |
1909 |
1585 |
264 |
264 |
22 |
|
|
16 |
Disable |
Disable |
1604 |
1268 |
264 |
264 |
22 |
User Guide
DS50003319C - 3
© 2024 Microchip Technology Inc. uye masangano ayo
HDMI TX IP Configurator
1. HDMI TX IP Configurator (Bvunza mubvunzo)
Ichi chikamu chinopa pamusoroview yeHDMI TX Configurator interface uye zvikamu zvayo zvakasiyana.
Iyo HDMI TX Configurator inopa graphical interface yekumisikidza iyo HDMI TX musimboti kune chaiwo vhidhiyo kutapurirana zvinodiwa. Iyi configurator inobvumira mushandisi kusarudza maparameter akadai seBits Per Component, Color Format, Nhamba yePixels, Audio Mode, Interface, Testbench, uye Rezinesi. Izvo zvakakosha kugadzirisa aya marongero nemazvo kuti uve nechokwadi chekufambisa kwevhidhiyo data pamusoro peHDMI.
Iyo interface yeHDMI TX Configurator ine akasiyana mamenu ekudonha uye sarudzo dzinogonesa vashandisi kugadzirisa iyo HDMI kutapurirana marongero. Izvo zvakakosha zvigadziriso zvinotsanangurwa mukati Tafura 3-1.
Mufananidzo unotevera unopa zvakadzama view yeHDMI TX Configurator interface.
Mufananidzo 1-1. HDMI TX IP Configurator
Iyo interface inosanganisirawo OK uye Kanzura mabhatani ekusimbisa kana kurasa magadzirirwo akaitwa.
User Guide
DS50003319C - 5
© 2024 Microchip Technology Inc. uye masangano ayo
Hardware Implementation
2. Hardware Implementation (Bvunza mubvunzo)
HDMI Transmitter (TX) ine maviri stages:
• Kushanda kweXOR/XNOR, iyo inoderedza nhamba yekuchinja
• An INV/NONINV, iyo inoderedza kusawirirana (DC balance). Mamwe mabhiti maviri akawedzerwa pane inotage kushanda. Kudzora dhata (hsync uye vsync) yakavharirwa kune gumi mabhiti mune ina inogoneka musanganiswa kubatsira mugamuchiri kuyananidza wachi yayo newachi inotumira. Transceiver inofanira kushandiswa pamwe chete neHDMI TX IP kugadzirisa 10 bits (10 pixel mode) kana 1 bits (40 pixels mode).
Iyo configurator inoratidzawo inomiririra yeHDMI Tx musimboti, yakanyorwa HDMI_TX_0, ichiratidza zvakasiyana-siyana zvekupinza uye zvinobuda zvinosanganiswa nepakati. Kune matatu modhi yeHDMI TX interface uye inotsanangurwa seizvi:
RGB Ruvara Format Mode
Zviteshi zveHDMI TX IP zvepixel imwe pawachi kana odhiyo modhi yakagoneswa uye Rudzi fomati iRGB yePolarFire.® zvishandiso zvinoratidzwa mumufananidzo unotevera. Iyo inomiririra inomiririra yeHDMI Tx core's ports sezvinotevera:
• Masaini ewachi anoti R_CLK_LOCK, G_CLK_LOCK, uye B_CLK_LOCK. Chiratidzo chewachi anoti R_CLK_I, G_CLK_I, uye B_CLK_I.
• Nzira dzedata dzinosanganisira DATA_R_I, DATA_G_I, uye DATA_B_I.
• Maziviro eData Ebetsero anoti AUX_DATA_R_I uye AUX_DATA_G_I.
Mufananidzo 2-1. HDMI TX IP Block Digiramu (RGB Ruvara Format)
Kuti uwane rumwe ruzivo nezve I/O masaini eRGB fomati yemavara, ona Tafura 3-2.
YCbCr444 Ruvara Format Mode
Zviteshi zveHDMI TX IP zvepixel imwe pawachi kana odhiyo modhi yagoneswa uye Ruvara fomati iri YCbCr444 inoratidzwa mumufananidzo unotevera. Iyo inomiririra inomiririra yeHDMI Tx core's ports sezvinotevera:
• Kudzora zviratidzo zvinoti Y_CLK_LOCK, Cb_CLK_LOCK, uye Cr_CLK_LOCK.
• Masizioni ewachi anoti Y_CLK_I, Cb_CLK_I, uye Cr_CLK_I.
User Guide
DS50003319C - 6
© 2024 Microchip Technology Inc. uye masangano ayo
Hardware Implementation
• Nzvimbo dzedata dzinosanganisira DATA_Y_I, DATA_Cb_I, uye DATA_Cr_I.
• Masaini ekuwedzera eData anoti AUX_DATA_Y_I uye AUX_DATA_C_I.
Mufananidzo 2-2. HDMI TX IP Block Digiramu (YCbCr444 Ruvara Format)
Kuti uwane rumwe ruzivo nezve masaini eI/O eYCbCr444 fomati yemavara, ona Tafura 3-6. YCbCr422 Ruvara Format Mode
Zviteshi zveHDMI TX IP zvepixel imwe pawachi kana odhiyo modhi yagoneswa uye Ruvara fomati iri YCbCr422 inoratidzwa mumufananidzo unotevera. Iyo inomiririra inomiririra yeHDMI Tx core's ports sezvinotevera:
• Kudzora zviratidzo zvinoti LANE1_CLK_LOCK, LANE2_CLK_LOCK, neLANE3_CLK_LOCK. • Masizioni ewachi anoti LANE1_CLK_I, LANE2_CLK_I, neLANE3_CLK_I.
• Matanho edata anosanganisira DATA_Y_I uye DATA_C_I.
User Guide
DS50003319C - 7
© 2024 Microchip Technology Inc. uye masangano ayo
Hardware Implementation
Mufananidzo 2-3. HDMI TX IP Block Digiramu (YCbCr422 Ruvara Format)
Kuti uwane rumwe ruzivo nezve masaini eI/O eYCbCr422 fomati yemavara, ona Tafura 3-7 User Guide
DS50003319C - 8
© 2024 Microchip Technology Inc. uye masangano ayo
HDMI TX Parameters uye Interface Signals
3. HDMI TX Parameters uye Interface Signals (Bvunza mubvunzo)
Ichi chikamu chinokurukura maparameter muHDMI TX GUI configurator uye I / O zviratidzo. 3.1 Configuration Parameters (Bvunza mubvunzo)
Tafura inotevera inonyora zvigadziriso zvimiro muHDMI TX IP.
Tafura 3-1. Configuration Parameters
|
Parameter Zita |
Tsanangudzo |
|
Color Format |
Inotsanangura nzvimbo yemavara. Inotsigira anotevera mavara mafomati: • RGB • YCbCr422 • YCbCr444 |
|
Nhamba yebhiti pa chikamu |
Inotsanangura huwandu hwemabhiti pachikamu cheruvara. Inotsigira 8, 10, 12, uye 16 bits pachikamu. |
|
Nhamba yePixels |
Inotaridza huwandu hwemapixels pawachi yekupinda: • Pixel pawachi = 1 • Pixel pawachi = 4 |
|
4Kp60 Tsigiro |
Tsigiro ye4K resolution pamafuremu makumi matanhatu pasekondi: • Kana 1, 4Kp60 rutsigiro rwaitwa • Kana 0, 4Kp60 rutsigiro rwadzimwa |
|
Audio Mode |
Inogadzirisa maitiro ekutumira odhiyo. R uye G chiteshi data: • Vhura • Dzima |
|
Interface |
Native uye AXI rwizi |
|
Testbench |
Inobvumira kusarudzwa kwenzvimbo ye testbench. Inotsigira zvinotevera testbench sarudzo: • Mushandisi • Hakuna |
|
License |
Inotsanangura mhando yerezinesi. Inopa marezinesi maviri anotevera sarudzo: • RTL • Encrypted |
3.2 Ports (Bvunza mubvunzo)
Iri tafura rinotevera rinonyora ekuisa uye kubuda zviteshi zveHDMI TX IP yeNative interface kana Audio modhi inogoneswa uye Rudzi fomati iRGB.
Tafura 3-2. Kupinza uye Kubuda Zviratidzo
|
Zita rechiratidzo |
Direction |
Upamhi |
Tsanangudzo |
|
SYS_CLK_I |
Input |
1-bit |
Wachi yeSistimu, kazhinji wachi imwe chete neyemutongi wekuratidzira |
|
RESET_N_I |
Input |
1-bit |
Asynchronous active-low reset signal |
|
VIDEO_DATA_VALID_I |
Input |
1-bit |
Vhidhiyo data inoenderana |
|
AUDIO_DATA_VALID_I |
Input |
1-bit |
Odhiyo packet data inoshanda |
|
R_CLK_I |
Input |
1-bit |
TX wachi ye "R" chiteshi kubva kuXCVR |
|
R_CLK_LOCK |
Input |
1-bit |
TX_CLK_STABLE yeR chiteshi kubva kuXCVR |
|
G_CLK_I |
Input |
1-bit |
TX wachi ye "G" chiteshi kubva kuXCVR |
|
G_CLK_LOCK |
Input |
1-bit |
TX_CLK_STABLE yeG chiteshi kubva kuXCVR |
|
B_CLK_I |
Input |
1-bit |
TX wachi ye "B" chiteshi kubva kuXCVR |
User Guide
DS50003319C - 9
© 2024 Microchip Technology Inc. uye masangano ayo
HDMI TX Parameters uye Interface Signals
|
………..enderera mberi Signal Name Direction Width Description |
|||
|
B_CLK_LOCK |
Input |
1-bit |
TX_CLK_STABLE yeB chiteshi kubva kuXCVR |
|
H_SYNC_I |
Input |
1-bit |
Horizontal sync pulse |
|
V_SYNC_I |
Input |
1-bit |
Vertical sync pulse |
|
PACKET_HEADER_I |
Input |
PIXELS_PER_CLK*1 |
Packet header yeadhiyo packet data |
|
DATA_R_I |
Input |
PIXELS_PER_CLK*8 |
Isa "R" data |
|
DATA_G_I |
Input |
PIXELS_PER_CLK*8 |
Isa "G" data |
|
DATA_B_I |
Input |
PIXELS_PER_CLK*8 |
Isa "B" data |
|
AUX_DATA_R_I |
Input |
PIXELS_PER_CLK*4 |
Audio packet "R" chiteshi data |
|
AUX_DATA_G_I |
Input |
PIXELS_PER_CLK*4 |
Audio packet "G" chiteshi data |
|
TMDS_R_O |
Output |
PIXELS_PER_CLK*10 |
Encoded "R" data |
|
TMDS_G_O |
Output |
PIXELS_PER_CLK*10 |
Encoded "G" data |
|
TMDS_B_O |
Output |
PIXELS_PER_CLK*10 |
Encoded "B" data |
Tafura inotevera inonyora madoko eiyo AXI4 Stream interface ine Audio Gonesa.
Tafura 3-3. Input uye Output Ports yeAXI4 Stream Interface
|
Port Name Type |
|
Upamhi |
Tsanangudzo |
|
TDATA_I |
Input |
3*g_BITS_PER_COMPONENT*g_PIXELS_PER_CLK Isa data yevhidhiyo |
|
|
TVALID_I |
Input |
1-bit |
Nyora vhidhiyo inoshanda |
|
TREADY_O Kuburitsa 1-bit |
|
|
Chiratidzo chemuranda anobuda |
|
TUSER_I |
Input |
PIXELS_PER_CLK*9 + 5 |
bit 0 = isina kushandiswa zvishoma 1 = VSYNC zvishoma 2 = HSYNC bit 3 = isina kushandiswa bhiti [3 + g_PIXELS_PER_CLK: 4] = Packet header bit [4 + g_PIXELS_PER_CLK] = Audio data inoshanda zvishoma [(5 * g_PIXELS_PER_CLK) + 4: (1*g_PIXELS_PER_CLK) + 5] = Audio G data zvishoma [(9 * g_PIXELS_PER_CLK) + 4: (5*g_PIXELS_PER_CLK) + 5] = Audio R data |
Iri tafura rinotevera rinonyora ekuisa uye kubuda madoko eHDMI TX IP yeNative interface kana Audio mode yakadzimwa.
Tafura 3-4. Kupinza uye Kubuda Zviratidzo
|
Zita rechiratidzo |
Direction |
Upamhi |
Tsanangudzo |
|
SYS_CLK_I |
Input |
1-bit |
Wachi yeSistimu, kazhinji wachi imwe chete neyemutongi wekuratidzira |
|
RESET_N_I |
Input |
1-bit |
Asynchronous active -low reset chiratidzo |
|
VIDEO_DATA_VALID_I |
Input |
1-bit |
Vhidhiyo data inoenderana |
|
R_CLK_I |
Input |
1-bit |
TX wachi ye "R" chiteshi kubva kuXCVR |
|
R_CLK_LOCK |
Input |
1-bit |
TX_CLK_STABLE yeR chiteshi kubva kuXCVR |
|
G_CLK_I |
Input |
1-bit |
TX wachi ye "G" chiteshi kubva kuXCVR |
|
G_CLK_LOCK |
Input |
1-bit |
TX_CLK_STABLE yeG chiteshi kubva kuXCVR |
|
B_CLK_I |
Input |
1-bit |
TX wachi ye "B" chiteshi kubva kuXCVR |
|
B_CLK_LOCK |
Input |
1-bit |
TX_CLK_STABLE yeB chiteshi kubva kuXCVR |
|
H_SYNC_I |
Input |
1-bit |
Horizontal sync pulse |
|
V_SYNC_I |
Input |
1-bit |
Vertical sync pulse |
|
DATA_R_I |
Input |
PIXELS_PER_CLK*8 |
Isa "R" data |
User Guide
DS50003319C - 10
© 2024 Microchip Technology Inc. uye masangano ayo
HDMI TX Parameters uye Interface Signals
|
………..enderera mberi Signal Name Direction Width Description |
|||
|
DATA_G_I |
Input |
PIXELS_PER_CLK*8 |
Isa "G" data |
|
DATA_B_I |
Input |
PIXELS_PER_CLK*8 |
Isa "B" data |
|
TMDS_R_O |
Output |
PIXELS_PER_CLK*10 |
Encoded "R" data |
|
TMDS_G_O |
Output |
PIXELS_PER_CLK*10 |
Encoded "G" data |
|
TMDS_B_O |
Output |
PIXELS_PER_CLK*10 |
Encoded "B" data |
Tafura inotevera inonyora madoko eiyo AXI4 Stream interface.
Tafura 3-5. Input uye Output Ports yeAXI4 Stream Interface
|
Port Name |
Type |
Upamhi |
Tsanangudzo |
|
TDATA_I_VIDEO |
Input |
3*g_BITS_PER_COMPONENT*g_PIXELS_PER_CLK |
Isa data yevhidhiyo |
|
TVALID_I_VIDEO |
Input |
1-bit |
Nyora vhidhiyo inoshanda |
|
TREADY_O_VIDEO |
Output |
1-bit |
Chiratidzo chemuranda anobuda |
|
TUSER_I_VIDEO |
Input |
4 zvishoma |
bit 0 = isina kushandiswa zvishoma 1 = VSYNC zvishoma 2 = HSYNC bit 3 = isina kushandiswa |
Tafura inotevera inonyora madoko eiyo YCbCr444 modhi kana odhiyo modhi inogoneswa.
Tafura 3-6. Kupinza uye Kubuda kweYCbCr444 Modhi uye Audio Modhi Inogoneswa
|
Zita rechiratidzo |
Direction Width |
|
Tsanangudzo |
|
SYS_CLK_I |
Input |
1-bit |
Wachi yeSistimu, kazhinji wachi imwe chete neyemutongi wekuratidzira |
|
RESET_N_I |
Input |
1-bit |
Asynchronous active-low reset signal |
|
VIDEO_DATA_VALID_I Input |
|
1-bit |
Vhidhiyo data inoenderana |
|
AUDIO_DATA_VALID_I Input |
|
1-bit |
Odhiyo packet data inoshanda |
|
Y_CLK_I |
Input |
1-bit |
TX wachi ye "Y" chiteshi kubva kuXCVR |
|
Y_CLK_LOCK |
Input |
1-bit |
TX_CLK_STABLE ye Y chiteshi kubva kuXCVR |
|
Cb_CLK_I |
Input |
1-bit |
TX wachi ye "Cb" chiteshi kubva kuXCVR |
|
Cb_CLK_LOCK |
Input |
1-bit |
TX_CLK_STABLE yeCb chiteshi kubva kuXCVR |
|
Cr_CLK_I |
Input |
1-bit |
TX wachi ye "Cr" chiteshi kubva kuXCVR |
|
Cr_CLK_LOCK |
Input |
1-bit |
TX_CLK_STABLE yeCr chiteshi kubva kuXCVR |
|
H_SYNC_I |
Input |
1-bit |
Horizontal sync pulse |
|
V_SYNC_I |
Input |
1-bit |
Vertical sync pulse |
|
PACKET_HEADER_I |
Input |
PIXELS_PER_CLK*1 |
Packet header yeadhiyo packet data |
|
DATA_Y_I |
Input |
PIXELS_PER_CLK*8 |
Isa "Y" data |
|
DATA_Cb_I |
Input |
PIXELS_PER_CLK*DATA_WIDTH Isa "Cb" data |
|
|
DATA_Cr_I |
Input |
PIXELS_PER_CLK*DATA_WIDTH Isa "Cr" data |
|
|
AUX_DATA_Y_I |
Input |
PIXELS_PER_CLK*4 |
Audio packet "Y" chiteshi data |
|
AUX_DATA_C_I |
Input |
PIXELS_PER_CLK*4 |
Audio packet "C" chiteshi data |
|
TMDS_R_O |
Output |
PIXELS_PER_CLK*10 |
Encoded "Cb" data |
|
TMDS_G_O |
Output |
PIXELS_PER_CLK*10 |
Encoded "Y" data |
|
TMDS_B_O |
Output |
PIXELS_PER_CLK*10 |
Encoded "Cr" data |
Tafura inotevera inonyora madoko eiyo YCbCr422 modhi kana odhiyo modhi inogoneswa.
User Guide
DS50003319C - 11
© 2024 Microchip Technology Inc. uye masangano ayo
HDMI TX Parameters uye Interface Signals
Tafura 3-7. Kupinza uye Kubuda kweYCbCr422 Modhi uye Audio Modhi Inogoneswa
|
Zita rechiratidzo |
Direction Width |
|
Tsanangudzo |
|
SYS_CLK_I |
Input |
1-bit |
Wachi yeSistimu, kazhinji wachi imwe chete neyemutongi wekuratidzira |
|
RESET_N_I |
Input |
1-bit |
Asynchronous Active -Low reset chiratidzo |
|
VIDEO_DATA_VALID_I Input |
|
1-bit |
Vhidhiyo data inoenderana |
|
LANE1_CLK_I |
Input |
1-bit |
TX wachi ye "nzira kubva kuXCVE lane 1" chiteshi kubva kuXCVR |
|
LANE1_CLK_LOCK |
Input |
1-bit |
TX_CLK_STABLE yemugwagwa unobva kuXCVE mugwagwa wekutanga |
|
LANE2_CLK_I |
Input |
1-bit |
TX wachi ye "nzira kubva kuXCVE lane 2" chiteshi kubva kuXCVR |
|
LANE2_CLK_LOCK |
Input |
1-bit |
TX_CLK_STABLE yemugwagwa unobva kuXCVE mugwagwa wekutanga |
|
LANE3_CLK_I |
Input |
1-bit |
TX wachi ye "nzira kubva kuXCVE lane 3" chiteshi kubva kuXCVR |
|
LANE3_CLK_LOCK |
Input |
1-bit |
TX_CLK_STABLE yemugwagwa unobva kuXCVE mugwagwa wekutanga |
|
H_SYNC_I |
Input |
1-bit |
Horizontal sync pulse |
|
V_SYNC_I |
Input |
1-bit |
Vertical sync pulse |
|
PACKET_HEADER_I |
Input |
PIXELS_PER_CLK*1 |
Packet header yeadhiyo packet data |
|
DATA_Y_I |
Input |
PIXELS_PER_CLK*DATA_WIDTH Isa "Y" data |
|
|
DATA_C_I |
Input |
PIXELS_PER_CLK*DATA_WIDTH Isa "C" data |
|
|
AUX_DATA_Y_I |
Input |
PIXELS_PER_CLK*4 |
Audio packet "Y" chiteshi data |
|
AUX_DATA_C_I |
Input |
PIXELS_PER_CLK*4 |
Audio packet "C" chiteshi data |
|
TMDS_R_O |
Output |
PIXELS_PER_CLK*10 |
Encoded "C" data |
|
TMDS_G_O |
Output |
PIXELS_PER_CLK*10 |
Encoded "Y" data |
|
TMDS_B_O |
Output |
PIXELS_PER_CLK*10 |
Encoded data ine chekuita neruzivo rwekuwiriranisa |
User Guide
DS50003319C - 12
© 2024 Microchip Technology Inc. uye masangano ayo
Nyora Mepu uye Tsananguro
4. Nyora Mepu uye Tsananguro (Bvunza mubvunzo)
|
Offset |
Zita |
Bit Pos. |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
0x00 |
SCRAMBLER_IP_EN |
7:0 |
|
|
|
|
|
|
|
START |
|
15:8 |
|
|
|
|
|
|
|
|
||
|
23:16 |
|
|
|
|
|
|
|
|
||
|
31:24 |
|
|
|
|
|
|
|
|
||
|
0x04 |
XCVR_DATA_LANE_ 0_SEL |
7:0 |
|
|
|
|
|
|
START[1:0] |
|
|
15:8 |
|
|
|
|
|
|
|
|
||
|
23:16 |
|
|
|
|
|
|
|
|
||
|
31:24 |
|
|
|
|
|
|
|
|
||
User Guide
DS50003319C - 13
© 2024 Microchip Technology Inc. uye masangano ayo
Nyora Mepu uye Tsananguro
4.1 SCRAMBLER_IP_EN (Bvunza mubvunzo)
Zita: SCRAMBLER_IP_EN
Kuenzanisa: 0x000
Reset: 0x0
Property: Nyora-chete
Scrambler Inogonesa Kudzora Rejista. Iri rerejista rinofanira kunyorwa kuti uwane 4kp60 Tsigiro yeHDMI TX IP
Zvishoma 31 30 29 28 27 26 25 24
Access
Reset
Zvishoma 23 22 21 20 19 18 17 16
Access
Reset
Zvishoma 15 14 13 12 11 10 9 8
Access
Reset
Zvishoma 7 6 5 4 3 2 1 0
|
|
|
|
|
|
|
|
START |
Svika W Reset 0
Bit 0 - TANGA Kunyora "1" kune iyi bit inotanga Scrambler data transfer inogoneswa. HDMI 2.0 inoshandisa nzira yekukwenya inozivikanwa se8b/10b encoding. Iyi encoding scheme inoshandiswa kufambisa data pamusoro peHDMI interface nekuvimbika uye nemazvo.
User Guide
DS50003319C - 14
© 2024 Microchip Technology Inc. uye masangano ayo
Nyora Mepu uye Tsananguro
4.2 XCVR_DATA_LANE_0_SEL (Bvunza mubvunzo)
Zita: XCVR_DATA_LANE_0_SEL
Kuenzanisa: 0x004
Reset: 0x1
Property: Nyora-chete
XCVR_DATA_LANE_0_SEL rejista inosarudza data inoda kuendeswa kuXCVR kubva kuHDMI TX IP kuti iwane wachi yeFull HD, 4kp30, 4kp60.
Zvishoma 31 30 29 28 27 26 25 24
|
|
|
|
|
|
|
|
|
Access
Reset
Zvishoma 23 22 21 20 19 18 17 16
|
|
|
|
|
|
|
|
|
Access
Reset
Zvishoma 15 14 13 12 11 10 9 8
|
|
|
|
|
|
|
|
|
Access
Reset
Zvishoma 7 6 5 4 3 2 1 0
|
|
|
|
|
|
|
START[1:0] |
Svika WW Reset 0 1
Bits 1:0 - START[1:0] Kunyora "10" kune iyi bits kunotangisa 4KP60 inogoneswa uye iyo XCVR data-reti inopiwa seFFFFF_00000.
User Guide
DS50003319C - 15
© 2024 Microchip Technology Inc. uye masangano ayo
Testbench Simulation
5. Testbench Simulation (Bvunza mubvunzo)
Testbench inopiwa kutarisa kushanda kweHDMI TX musimboti. Testbench inoshanda chete mune yemuno interface ine 1 pixel pawachi uye odhiyo modhi inogoneswa.
Iro tafura rinotevera rinonyora ma parameter akagadziriswa maererano nekushandiswa.
Tafura 5-1. Testbench Configuration Parameter
|
Zita |
Default Parameters |
|
Mamiriro Emavara (g_COLOR_FORMAT) |
RGB |
|
Mabhiti pachikamu (g_BITS_PER_COMPONENT) |
8 |
|
Nhamba yePixels (g_PIXELS_PER_CLK) |
1 |
|
4Kp60 Rutsigiro (g_4K60_SUPPORT) |
0 |
|
Audio Mode (g_AUX_CHANNEL_ENABLE) |
1 (gonesa) |
|
Interface (G_FORMAT) |
0 (Dzima) |
Kutevedzera musimboti uchishandisa testbench, ita zvinotevera matanho:
1. MuDhizaini Flow hwindo, wedzera Gadzira Dhizaini.
2. Right-click Gadzira SmartDesign Testbench, uye wobva wadzvanya Run, sezvinoratidzwa mumufananidzo unotevera. Mufananidzo 5-1. Kugadzira SmartDesign Testbench
3. Isa zita reSmartDesign testbench, wobva wadzvanya OK.
Mufananidzo 5-2. Kutumidza SmartDesign Testbench
SmartDesign testbench inogadzirwa, uye canvas inoonekwa kurudyi kweiyo Dhizaini Flow pane.
User Guide
DS50003319C - 16
© 2024 Microchip Technology Inc. uye masangano ayo
Testbench Simulation
4. Enda kuLibero® SoC Catalog, sarudza View > Windows > IP Catalog, uye wobva wawedzera Solutions Vhidhiyo. Tinya kaviri HDMI TX IP (v5.2.0), wobva wadzvanya OK.
5. Muwindo reParameter Configurator, sarudza Nhamba inodiwa yePixels kukosha, sezvinoratidzwa mumufananidzo unotevera.
Mufananidzo 5-3. Parameter Configuration
6. Sarudza zviteshi zvose, penya-kurudyi uye sarudza Kurudzira Kumusoro Wepamusoro.
7. PaSmartDesign toolbar, baya Gadzira Chikamu.
8. Pa Stimulus Hierarchy tab, tinya-kurudyi HDMI_TX_TB testbench file, wobva wadzvanya Simulate Pre-Synth Design> Vhura Interactively.
The ModelSim® chishandiso chinovhura ne testbench, sezvinoratidzwa mumufananidzo unotevera. Mufananidzo 5-4. ModelSim Tool ine HDMI TX Testbench File
Zvakakosha: Kana iyo simulation ikakanganiswa nekuda kwekumhanya nguva yakatarwa inotsanangurwa mu DO file, shandisa kumhanya -zvose raira kuti upedze simulation.
User Guide
DS50003319C - 17
© 2024 Microchip Technology Inc. uye masangano ayo
Testbench Simulation
5.1 Madhiyamu enguva (Bvunza mubvunzo)
Inotevera dhayagiramu yenguva yeHDMI TX IP inoratidza vhidhiyo data uye kutonga nguva dzedhata kwe1 pixel pawachi.
Mufananidzo 5-5. HDMI TX IP Nguva Yenguva yeVhidhiyo Dhata ye1 Pixel Pawachi
Dhiagiramu inotevera inoratidza iwo mana masanganiswa ekudzora data.
Mufananidzo 5-6. HDMI TX IP Nguva Yenguva Dhiagiramu yeKudzora Dhata ye1 Pixel Pawachi
User Guide
DS50003319C - 18
© 2024 Microchip Technology Inc. uye masangano ayo
Kubatanidzwa kweSystem
6. Kubatanidzwa kweSystem (Bvunza mubvunzo)
Ichi chikamu chinoratidza seample design tsananguro.
Tafura inotevera inoronga masimirwo ePF XCVR, PF TX PLL, uye PF CCC.
Tafura 6-1. PF XCVR, PF TX PLL, uye PF CCC Configurations
|
Resolution |
|
Bit Width PF XCVR Configuration |
PF TX PLL Configuration |
PF CCC Kugadziriswa |
||||
|
TX Data Rate |
TX Clock Division Factor |
TX PCS Fabric Upamhi |
Desired Output Bit Clock |
Reference Clock Frequency |
Input Frequency |
Output Frequency |
||
|
1PXL (1080p60) 8 |
|
1485 |
4 |
10 |
5940 |
148.5 |
NA |
NA |
|
1PXL (1080p30) 10 |
|
925 |
4 |
10 |
3700 |
148.5 |
92.5 |
74 |
|
12 |
1113.75 |
4 |
10 |
4455 |
148.5 |
111.375 |
74.25 |
|
|
16 |
1485 |
4 |
10 |
5940 |
148.5 |
148.5 |
74.25 |
|
|
4PXL (1080p60) 10 |
|
1860 |
4 |
40 |
7440 |
148.5 |
46.5 |
37.2 |
|
12 |
2229 |
4 |
40 |
8916 |
148.5 |
55.725 |
37.15 |
|
|
16 |
2970 |
2 |
40 |
5940 |
148.5 |
74.25 |
37.125 |
|
|
4PXL (4kp30) |
8 |
2970 |
2 |
40 |
5940 |
148.5 |
NA |
NA |
|
10 |
3712.5 |
2 |
40 |
7425 |
148.5 |
92.812 |
74.25 |
|
|
12 |
4455 |
1 |
40 |
4455 |
148.5 |
111.375 |
74.25 |
|
|
16 |
5940 |
1 |
40 |
5940 |
148.5 |
148.5 |
74.25 |
|
|
4PXL (4Kp60) |
8 |
5940 |
1 |
40 |
5940 |
148.5 |
NA |
NA |
HDMI TX Sample Dhizaini, kana yakagadziriswa mu g_BITS_PER_COMPONENT = 8-bit uye
g_PIXELS_PER_CLK = 1 PXL modhi, inoratidzwa mumufananidzo unotevera.
Mufananidzo 6-1. HDMI TX Sample Dhizaini
HDMI_TX_C0_0
PF_INIT_MONITOR_C0_0
|
FABRIC_POR_N PCIE_INIT_DONE USRAM_INIT_DONE SRAM_INIT_DONE DEVICE_INIT_DONE XCVR_INIT_DONE USRAM_INIT_FROM_SNVM_DONE USRAM_INIT_FROM_UPROM_DONE USRAM_INIT_FROM_SPI_DONE SRAM_INIT_FROM_SNVM_DONE SRAM_INIT_FROM_UPROM_DONE SRAM_INIT_FROM_SPI_DONE AUTOCALIB_WAITA |
PF_INIT_MONITOR_C0
CORARESET_PF_C0_0
|
CLK EXT_RST_N BANK_x_VDDI_STATUS BANK_y_VDDI_STATUS PLL_POWERDOWN_B PLL_LOCK FABRIC_RESET_N SS_BUSY INIT_KUITA FF_US_RESTORE FPGA_POR_N |
CORARESET_PF_C0
Display_Controller_C0_0
|
FRAME_END_O H_SYNC_O RESETN_I V_SYNC_O SYS_CLK_I V_ACTIVE_O ITA_I DATA_TRIGGER_O H_RES_O[15:0] V_RES_O[15:0] |
Display_Controller_C0
pattern_generator_verilog_pattern_0
|
DATA_VALID_O SYS_CLK_I FRAME_END_O RESET_N_I LINE_END_O DATA_EN_I RED_O[7:0] FRAME_END_I GREEN_O[7:0] PATTERN_SEL_I[2:0] BLUE_O[7:0] BAYER_O[7:0] |
Test_Pattern_Jenareta_C1
PF_XCVR_REF_CLK_C0_0
|
RESET_N_I SYS_CLK_I VIDEO_DATA_VALID_I R_CLK_I R_CLK_LOCK G_CLK_I G_CLK_LOCK TMDS_R_O[9:0] B_CLK_I TMDS_G_O[9:0] B_CLK_LOCK TMDS_B_O[9:0] V_SYNC_I XCVR_LANE_0_DATA_O[9:0] H_SYNC_I
DATA_R_I[7:0]
DATA_G_I[7:0]
DATA_B_I[7:0] |
HDMI_TX_C0
PF_TX_PLL_C0_0
PF_XCVR_ERM_C0_0
|
PADs_OUT LANE3_TXD_N CLKS_FROM_TXPLL_0 LANE3_TXD_P LANE0_IN LANE2_TXD_N LANE0_PCS_ARST_N LANE2_TXD_P LANE0_PMA_ARST_N LANE1_TXD_N LANE0_TX_DATA[9:0] LANE1_TXD_P LANE1_IN LANE0_TXD_N LANE1_PCS_ARST_N LANE0_TXD_P LANE1_PMA_ARST_N LANE0_OUT LANE1_TX_DATA[9:0] LANE0_TX_CLK_R LANE2_IN LANE0_TX_CLK_STABLE LANE2_PCS_ARST_N LANE1_OUT LANE2_PMA_ARST_N LANE1_TX_CLK_R LANE2_TX_DATA[9:0] LANE1_TX_CLK_STABLE LANE3_IN LANE2_OUT LANE3_PCS_ARST_N LANE2_TX_CLK_R LANE3_PMA_ARST_N LANE2_TX_CLK_STABLE LANE3_TX_DATA[9:0] LANE3_OUT LANE3_TX_CLK_STABLE |
PF_XCVR_ERM_C0
LANE3_TXD_N LANE3_TXD_P LANE2_TXD_N LANE2_TXD_P LANE1_TXD_N LANE1_TXD_P LANE0_TXD_N LANE0_TXD_P
PATTERN_SEL_I[2:0] REF_CLK_PAD_P REF_CLK_PAD_N
|
REF_CLK_PAD_P REF_CLK_PAD_NREF_CLK |
|
REF_CLKPLL_LOCKCLKS_TO_XCVR |
PF_XCVR_REF_CLK_C0
PF_TX_PLL_C0
For Example, mune 8-bit zvigadziriso, zvinotevera zvinoumba chikamu chedhizaini: • PF_XCVR_ERM (PF_XCVR_ERM_C0_0) yakagadziridzwa kuitira data rate ye1485 Mbps muPMA modhi yeTX chete, nehupamhi hwedata hwakagadziriswa se10 bit ye1pxl modhi uye 148.5 MHz referensi wachi, zvichibva pane yakapfuura tafura marongero
• LANE0_TX_CLK_R yakabuda yePF_XCVR_ERM_C0_0 inogadzirwa se148.5 MHz wachi, zvichienderana nemasetin'i ematafura agara
• SYS_CLK_I (HDMI_TX_C0, Display_Controller_C0, pattern_generator_C0, CORERESET_PF_C0, nePF_INIT_MONITOR_C0) inofambiswa neLANE0_TX_CLK_R, inova 148.5 MHz
• R_CLK_I, G_CLK_I, neB_CLK_I inofambiswa neLANE3_TX_CLK_R, LANE2_TX_CLK_R, neLANE1_TX_CLK_R, zvichiteerana.
User Guide
DS50003319C - 19
© 2024 Microchip Technology Inc. uye masangano ayo
Kubatanidzwa kweSystem
Sample kubatanidzwa kwe, g_BITS_PER_COMPONENT = 8 uye g_PIXELS_PER_CLK = 4. For Example, mune 8-bit zvigadziriso, zvinotevera zvikamu chikamu chedhizaini: • PF_XCVR_ERM (PF_XCVR_ERM_C0_0) yakagadziridzwa kuitira data rero ye2970 Mbps muPMA modhi ye.
TX chete, iine hupamhi hwedata hwakarongedzerwa se40-bit ye1pxl modhi uye 148.5 MHz referensi wachi zvichienderana neapfuura marongero etafura.
• LANE0_TX_CLK_R yakabuda yePF_XCVR_ERM_C0_0 inogadzirwa se74.25 MHz wachi, zvichienderana nemasetin'i ematafura agara
• SYS_CLK_I (HDMI_TX_C0, Display_Controller_C0, pattern_generator_C0, CORERESET_PF_C0, nePF_INIT_MONITOR_C0) inofambiswa neLANE0_TX_CLK_R, inova 148.5 MHz
• R_CLK_I, G_CLK_I, neB_CLK_I inofambiswa neLANE3_TX_CLK_R, LANE2_TX_CLK_R, neLANE1_TX_CLK_R, zvichiteerana.
HDMI TX Sample Dhizaini, kana yakagadziriswa mu g_BITS_PER_COMPONENT = 12 Bit uye g_PIXELS_PER_CLK = 1 PXL modhi, inoratidzwa mumufananidzo unotevera.
Mufananidzo 6-2. HDMI TX Sample Dhizaini
PF_XCVR_ERM_C0_0
PATTERN_SEL_I[2:0]
REF_CLK_PAD_P REF_CLK_PAD_N
PF_CCC_C1_0
|
REF_CLK_0 OUT0_FABCLK_0PLL_LOCK_0 |
PF_CCC_C1
PF_INIT_MONITOR_C0_0
CORARESET_PF_C0_0
|
CLK EXT_RST_N BANK_x_VDDI_STATUS BANK_y_VDDI_STATUS PLL_POWERDOWN_B PLL_LOCK FABRIC_RESET_N SS_BUSY INIT_KUITA FF_US_RESTORE FPGA_POR_N |
CORARESET_PF_C0
Display_Controller_C0_0
|
FRAME_END_O H_SYNC_O RESETN_I V_SYNC_O SYS_CLK_I V_ACTIVE_O ITA_I DATA_TRIGGER_O H_RES_O[15:0] V_RES_O[15:0] |
Display_Controller_C0
pattern_generator_verilog_pattern_0
|
DATA_VALID_O SYS_CLK_I FRAME_END_O RESET_N_I LINE_END_O DATA_EN_I RED_O[7:0] FRAME_END_I GREEN_O[7:0] PATTERN_SEL_I[2:0] BLUE_O[7:0] BAYER_O[7:0] |
Test_Pattern_Jenareta_C0
PF_XCVR_REF_CLK_C0_0
|
REF_CLK_PAD_P REF_CLK_PAD_NREF_CLK |
PF_XCVR_REF_CLK_C0
HDMI_TX_0
|
RESET_N_I SYS_CLK_I VIDEO_DATA_VALID_I R_CLK_I R_CLK_LOCK G_CLK_I G_CLK_LOCK TMDS_R_O[9:0] B_CLK_I TMDS_G_O[9:0] B_CLK_LOCK TMDS_B_O[9:0] V_SYNC_I XCVR_LANE_0_DATA_O[9:0] H_SYNC_I
DATA_R_I[11:4]
DATA_G_I[11:4]
DATA_B_I[11:4] |
HDMI_TX_C0
PF_TX_PLL_C0_0
|
PADs_OUT CLKS_FROM_TXPLL_0 LANE3_TXD_N LANE0_IN LANE3_TXD_P LANE0_PCS_ARST_N LANE2_TXD_N LANE0_PMA_ARST_N LANE2_TXD_P LANE0_TX_DATA[9:0] LANE1_TXD_N LANE1_IN LANE1_TXD_P LANE1_PCS_ARST_N LANE0_TXD_N LANE1_PMA_ARST_N LANE0_TXD_P LANE1_TX_DATA[9:0] LANE0_OUT LANE2_IN LANE1_OUT LANE2_PCS_ARST_N LANE1_TX_CLK_R LANE2_PMA_ARST_N LANE1_TX_CLK_STABLE LANE2_TX_DATA[9:0] LANE2_OUT LANE2_TX_CLK_R LANE3_PCS_ARST_N LANE2_TX_CLK_STABLE LANE3_PMA_ARST_N LANE3_OUT LANE3_TX_DATA[9:0] LANE3_TX_CLK_R LANE3_TX_CLK_STABLE |
PF_XCVR_ERM_C0
LANE3_TXD_N LANE3_TXD_P LANE2_TXD_N LANE2_TXD_P LANE1_TXD_N LANE1_TXD_P LANE0_TXD_N LANE0_TXD_P
|
FABRIC_POR_N PCIE_INIT_DONE USRAM_INIT_DONE SRAM_INIT_DONE DEVICE_INIT_DONE XCVR_INIT_DONE USRAM_INIT_FROM_SNVM_DONE USRAM_INIT_FROM_UPROM_DONE USRAM_INIT_FROM_SPI_DONE SRAM_INIT_FROM_SNVM_DONE SRAM_INIT_FROM_UPROM_DONE SRAM_INIT_FROM_SPI_DONE AUTOCALIB_WAITA |
|
REF_CLKPLL_LOCKCLKS_TO_XCVR |
PF_INIT_MONITOR_C0
PF_TX_PLL_C0
Sampkusanganisa kwe, g_BITS_PER_COMPONENT > 8 uye g_PIXELS_PER_CLK = 1. For Example, mune 12-bit zvigadziriso, zvinotevera zvikamu chikamu chedhizaini:
• PF_XCVR_ERM (PF_XCVR_ERM_C0_0) yakagadziridzwa kuitira data rate ye111.375 Mbps muPMA mode yeTX chete, nehupamhi hwedata hwakarongwa se10 bit ye1pxl modhi uye 1113.75 Mbps referensi wachi, zvichibva pa Tafura 6-1 zvirongwa
• LANE1_TX_CLK_R yakabuda yePF_XCVR_ERM_C0_0 inogadzirwa se111.375 MHz wachi, zvichienderana ne Tafura 6-1 zvirongwa
• R_CLK_I, G_CLK_I, neB_CLK_I inofambiswa neLANE3_TX_CLK_R, LANE2_TX_CLK_R, neLANE1_TX_CLK_R, zvichiteerana.
• PF_CCC_C0 inogadzira wachi inonzi OUT0_FABCLK_0, ine frequency ye 74.25 MHz, kana wachi yekupinda iri 111.375 MHz, inofambiswa neLANE1_TX_CLK_R
• SYS_CLK_I (HDMI_TX_C0, Display_Controller_C0, pattern_generator_C0, CORERESET_PF_C0, uye PF_INIT_MONITOR_C0) inofambiswa neOUT0_FABCLK_0, inova 74.25 MHz
Sampkusanganisa kwe, g_BITS_PER_COMPONENT > 8 uye g_PIXELS_PER_CLK = 4. For Example, mune 12-bit zvigadziriso, zvinotevera zvikamu chikamu chedhizaini:
• PF_XCVR_ERM (PF_XCVR_ERM_C0_0) yakagadziridzwa kuitira data rate ye4455 Mbps muPMA mode yeTX chete, nehupamhi hwedata hwakarongwa se40 bit ye4pxl modhi uye 111.375 MHz referensi wachi, zvichibva pa Tafura 6-1 zvirongwa
• LANE1_TX_CLK_R yakabuda yePF_XCVR_ERM_C0_0 inogadzirwa se111.375 MHz wachi, zvichienderana ne Tafura 6-1 zvirongwa
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Kubatanidzwa kweSystem
• R_CLK_I, G_CLK_I, neB_CLK_I inofambiswa neLANE3_TX_CLK_R, LANE2_TX_CLK_R, neLANE1_TX_CLK_R, zvichiteerana.
• PF_CCC_C0 inogadzira wachi inonzi OUT0_FABCLK_0, ine frequency ye 74.25 MHz, kana wachi yekupinda iri 111.375 MHz, inofambiswa neLANE1_TX_CLK_R
• SYS_CLK_I (HDMI_TX_C0, Display_Controller_C0, pattern_generator_C0, CORERESET_PF_C0, uye PF_INIT_MONITOR_C0) inofambiswa neOUT0_FABCLK_0, inova 74.25 MHz
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Revision History
7. Revision History (Bvunza mubvunzo)
Nhoroondo yekudzokorora inotsanangura shanduko dzakaitwa mugwaro. Kuchinja kwacho kunorongwa nekudzokorora, kutanga nebhuku razvino uno.
Tafura 7-1. Revision History
|
Kudzokorora |
Date |
Tsanangudzo |
|
C |
05/2024 |
Inotevera rondedzero yeshanduko mukudzokorora C yegwaro: • Updated Nhanganyaya chikamu • Matafura ekushandisa zviwanikwa zvepikisi imwe chete nemapikisi mana uye akawedzera Tafura 2 uye Tafura 3 in 1. Resource Utilization chikamu • Updated Tafura 3-1 mu 3.1. Configuration Parameters chikamu • Yakawedzerwa Tafura 3-6 uye Tafura 3-7 mu 3.2. Ports chikamu • Yakawedzerwa 6. Kubatanidzwa kweSystem chikamu |
|
B |
|
09/2022 Iyi inotevera rondedzero yekuchinja mukudzokorora B kwegwaro: • Yakagadziridza zviri muZvinhu uye Nhanganyaya • Yakawedzerwa Mufananidzo 2-2 yeakaremara Audio Mode • Yakawedzerwa Tafura 3-4 uye Tafura 3-5 • Updated the Tafura 3-2 uye Tafura 3-3 • Updated Tafura 3-1 • Updated 1. Resource Utilization • Updated Mufananidzo 1-1 • Updated Mufananidzo 5-3 |
|
A |
|
04/2022 Iyi inotevera rondedzero yeshanduko mukudzokorora A yegwaro: • Gwaro rakatamirwa kuMicrochip template • Nhamba yegwaro yakagadziridzwa kuita DS50003319 kubva pa50200863 |
|
2.0 |
— |
Inotevera ipfupiso yeshanduko dzakaitwa mudzokororo iyi. • Zvikamu zvakawedzerwa uye zvikamu zveMhuri Dzinotsigirwa |
|
1.0 |
|
08/2021 Ongororo yekutanga |
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Microchip FPGA Tsigiro
Microchip FPGA zvigadzirwa boka rinodzosera zvigadzirwa zvaro neakasiyana masevhisi ekutsigira, anosanganisira Customer Service, Customer Technical Support Center, a webnzvimbo, uye mahofisi ekutengesa pasi rose. Vatengi vanokurudzirwa kushanyira Microchip online zviwanikwa vasati vabata rutsigiro sezvo paine mukana wekuti mibvunzo yavo yatopindurwa.
Bata Technical Support Center kuburikidza ne website pa www.microchip.com/support. Taura iyo FPGA Chidimbu Chikamu nhamba, sarudza yakakodzera nyaya chikamu, uye kurodha dhizaini files paunenge uchigadzira tekinoroji yekutsigira kesi.
Bata Mutengi Sevhisi kune isiri-tekinoroji yechigadzirwa rutsigiro, semitengo yechigadzirwa, kukwidziridzwa kwechigadzirwa, ruzivo rwekuvandudza, mamiriro eodha, uye mvumo.
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Microchip's product change notification service inobatsira kuchengetedza vatengi varipo paMicrochip zvigadzirwa. Vanyoreri vanogashira email chiziviso pese paine shanduko, zvigadziriso, zvidzokororo kana errata ine chekuita neyakatsanangurwa chigadzirwa mhuri kana chekuvandudza chishandiso chekufarira.
Kuti unyore, enda ku www.microchip.com/pcn uye tevera mirairo yekunyoresa. Mutengi Support
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Tsigiro yehunyanzvi inowanikwa kuburikidza ne websaiti pa: www.microchip.com/support Microchip Devices Code Dziviriro Feature
Ziva zvinotevera zvinongedzo zvechidziviriro chekodhi pane Microchip zvigadzirwa:
User Guide
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• Zvigadzirwa zveMicrochip zvinosangana nezvinodiwa zviri mune yavo Microchip Data Sheet.
• Microchip inotenda kuti mhuri yayo yezvigadzirwa yakachengeteka kana ichishandiswa nenzira yakarongwa, mukati memaitiro ekushanda, uye pasi pemamiriro ezvinhu.
• Microchip inokoshesa uye inodzivirira zvine hukasha kodzero dzayo dzepfuma. Kuedza kutyora kodhi yekudzivirira maficha eMicrochip chigadzirwa zvinorambidzwa zvachose uye zvinogona kutyora Digital Millennium Copyright Act.
• Hapana Microchip kana chero imwe semiconductor mugadziri anogona kuvimbisa kuchengetedzwa kwekodhi yayo. Kudzivirirwa kwekodhi hazvireve kuti tiri kuvimbisa kuti chigadzirwa "hachiputsike". Kudzivirirwa kwekodhi kunogara kuchishanduka. Microchip yakazvipira kuramba ichivandudza kodhi yekudzivirira maficha ezvigadzirwa zvedu.
Legal Notice
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RUZIVO IYI INOPIWA NE MICROCHIP "SESE ZVIRI". MICROCHIP HAIITA ZVINOmiririrwa KANA KUTI MWARATIDZO YERUPI RWERUDZI ZVINO ZVINOTAURA KANA ZVINOREVA, KUNYORA KANA KUTAURA, ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINO zvinosanganisira ASI ZVISI ZVINOGWADZIRWA KUTI ZVINO ZVINOREVA KUTI ZVINOTAURWA KUTI ZVINOTAURWA, ZVINOTAURWA, ZVINOTAURWA, ZVINOTAURWA. KUNE CHINANGWA CHAKATADZWA, KANA KUTI MAWARANTI ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVICHAITWA NEZVINHU ZVAKAITWA, HUNHU, KANA KUITA.
HAPANA CHIITIKO CHICHAITWA MICROCHIP KUNE MHOSVA DZEPI ZVIRI KUNHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU , ZVINHU , ZVINOITWA , ZVAKAITIKA , KANA ZVINOTEVERA KURASIKA , KUPARADZWA , MUTEMO , KANA KUTI KUTI MUTE CHESE ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINO KANA MASHANDISI AWO, ZVISINEI ZVAKAITWA MAZANO ZVINOGONA KANA KUKABADZA ZVINOFONEKWA. ZVINO ZVIKURU ZVINOBVUNZWA NEMUTEMO, MICROCHIP YAKATAURWA YOSE PAZVINOITWA ZVINHU ZVINHU ZVINHU ZVINOITWA NERUZIVO KANA KUSHANDISA KWAKO HAKUZOPIRI MUNHU WEMURIPO, KANA UCHIDA, WAWAKABHADHARA ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINOITWA NERUZIVO KANA KUSHANDISWA KWAKO HAKUZOPFUURA MUNHU WEMURIPO, KANA UCHIDA, WAWAKABHADHARA ZVINHU ZVINO KUNYANYA KUTI MICROCHIP.
Kushandiswa kweMicrochip zvishandiso mukutsigira hupenyu uye / kana kuchengetedza zvikumbiro zviri panjodzi yemutengi, uye mutengi anobvuma kudzivirira, kubhadharira uye kubata Microchip isingakuvadzi kubva kune chero uye zvese zvinokuvadza, zvirevo, masutu, kana mari inokonzerwa nekushandiswa kwakadaro. Hapana marezinesi anofambiswa, zviri pachena kana neimwe nzira, pasi peMicrochip intellectual property rights kunze kwekunge zvataurwa neimwe nzira.
Trademarks
Iyo Microchip zita uye logo, iyo Microchip logo, Adaptec, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, CryptoMemory, CryptoRF, dsPIC, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXTouchlus MediaLB, megaAVR, Microsemi, Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, PolarFire, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetri , SyncServer, Tachyon, TimeSource, tinyAVR, UNI/O, Vectron, uye XMEGA zviratidzo zvakanyoreswa zveMicrochip Technology Incorporated muUSA nedzimwe nyika.
AgileSwitch, ClockWorks, The Embedded Control Solutions Company, EtherSynch, Flashtec, Hyper Speed Control, HyperLight Load, Libero, motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire, SmartFusion, SyncWorld, TimeCesium, TimeHub, TimePictra, TimeProvider, uye ZL zviratidzo zvakanyoreswa zveMicrochip Technology Incorporated muUSA.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Chero Capacitor, AnyIn, AnyOut, Augmented Switching, BlueSky, BodyCom, Clockstudio, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, dsPICDEM.net,
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Avhareji Matching, DAM, ECAN, Espresso T1S, EtherGREEN, EyeOpen, GridTime, IdealBridge, IGaT, In-Circuit Serial Programming, ICSP, INICnet, Intelligent Paralleling, IntelliMOS, Inter-Chip Connectivity, JitterBlocker, Knob-onDinks, Margin-Dink maxCrypto, maxView, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, mSiC, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, Power MOS IV, Power MOS 7, PowerSmart, PowerSmart, , QMatrix, REAL ICE, Ripple Blocker, RTAX, RTG4, SAM-ICE, Serial Quad I/O, simpleMAP, SimpliPHY, SmartBuffer, SmartHLS, SMART-IS, storClad, SQI, SuperSwitcher, SuperSwitcher II, Switchtec, SynchroPHY, Total Endurance , Nguva Yakavimbika, TSHARC, Turing, USBCheck, VariSense, VectorBlox, VeriPHY, ViewSpan, WiperLock, XpressConnect, uye ZENA zviratidzo zveMicrochip Technology Incorporated muUSA nedzimwe nyika.
SQTP chiratidzo chesevhisi cheMicrochip Technology Incorporated muUSA
The Adaptec logo, Frequency on Demand, Silicon Storage Technology, neSymmcom zviratidzo zvekutengeserana zveMicrochip Technology Inc. kune dzimwe nyika.
GestIC ichiratidzo chekutengeserana chakanyoreswa cheMicrochip Technology Germany II GmbH & Co. KG, inotsigira Microchip Technology Inc., kune dzimwe nyika.
Mamwe matrademark ese ataurwa pano zvinhu zvemakambani avo. © 2024, Microchip Technology Incorporated uye masangano ayo. All Rights Reserved. ISBN:
Quality Management System
Kuti uwane ruzivo nezve Microchip's Quality Management Systems, ndapota shanya www.microchip.com/quality.
User Guide
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Munyika Yose Kutengesa uye Basa
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