DS50003319C-13 Ethernet HDMI TX IP
HDMI TX IP Jagorar Mai amfani
Gabatarwa (Tambaya Tambaya)
Microchip's High-Definition Multimedia Interface (HDMI) mai watsawa IP yana goyan bayan watsa fakitin fakitin bidiyo da mai jiwuwa da aka kwatanta a cikin ƙayyadaddun ma'auni na HDMI.
HDMI tana ɗaukar Siginar Rarraba Rarraban Canjawa (TMDS) don isar da ɗimbin ɗimbin bayanai na dijital cikin nagarta a cikin nisan kebul na kebul, yana tabbatar da babban saurin, serial, da amintaccen watsa siginar dijital. Hanyar haɗin TMDS ta ƙunshi tashar agogo ɗaya da tashoshi bayanai uku. Ana watsa agogon pixel na bidiyo akan tashar agogon TMDS, wanda ke taimakawa kiyaye sigina cikin aiki tare. Ana ɗaukar bayanan bidiyo azaman pixels 24-bit akan tashoshin bayanan TMDS guda uku, inda aka keɓance kowace tashar bayanai don ɓangaren launi ja, kore, da shuɗi. Ana ɗaukar bayanan odiyo azaman fakiti 8-bit akan tashar TMDS kore da ja.
TMDS encoder yana ba da damar watsa bayanan serial a cikin babban sauri, yayin da rage yuwuwar Tsangwama na Electro-magnetic Interference (EMI) akan igiyoyin jan ƙarfe ta hanyar rage yawan sauye-sauye (rage tsangwama tsakanin tashoshi), kuma ya cimma daidaiton Direct Current (DC), akan wayoyi. , ta hanyar kiyaye adadin ɗaya da sifili akan layi kusan daidai.
HDMI TX IP an tsara shi don amfani da shi tare da PolarFire® SoC da PolarFire transceivers. IP ɗin ya dace da HDMI 1.4 da HDMI 2.0, wanda ke tallafawa har zuwa firam ɗin 60 a sakan daya, tare da matsakaicin bandwidth na 18 Gbps. IP ɗin tana amfani da mai rikodin TMDS wanda ke canza bayanan bidiyo 8-bit kowane tashoshi da fakitin sauti zuwa ma'auni na 10-bit DC, da taƙaitaccen tsarin canji. Sa'an nan kuma ana watsa shi a jere a kan ƙimar 10-bits kowace pixel, kowane tashoshi. A lokacin faifan bidiyo, ana watsa alamun sarrafawa. Ana samar da waɗannan alamun bisa ga hsync da siginar vsync. A lokacin lokacin tsibirin bayanai, ana watsa fakitin sauti azaman fakiti 10-bit akan tashar ja da kore.
Jagorar Mai Amfani
DS50003319C 1
© 2024 Microchip Technology Inc. da rassansa
Takaitawa
Tebur mai zuwa yana ba da taƙaitaccen halayen HDMI TX IP.
Tebur 1. HDMI TX IP Halayen
|
Sigar Core |
Wannan jagorar mai amfani yana goyan bayan HDMI TX IP v5.2.0 |
|
Tallafawa Iyalan Na'ura |
• Wuta ta Polar® SoC • Wuta ta Polar |
|
Gudun Kayan Aikin Goyon baya |
Yana buƙatar Libero® SoC v11.4 ko daga baya sakewa |
|
Tallafawa Hanyoyin sadarwa |
Hanyoyi masu goyan bayan HDMI TX IP sune: • AXI4-Rafi - Wannan ainihin yana goyan bayan AXI4-Rafi zuwa tashoshin shigarwa. Lokacin da aka saita a wannan yanayin, IP yana ɗaukar daidaitattun siginar ƙararrakin AXI4 Stream azaman abubuwan shigarwa. • AXI4-Lite Interface Kanfigareshan - Wannan Core yana goyan bayan ƙirar ƙirar AXI4-Lite don buƙatun 4Kp60. A cikin wannan yanayin, ana ba da abubuwan shigar da IP daga SoftConsole. • Dan ƙasa - Lokacin da aka saita shi a cikin wannan yanayin, IP yana ɗaukar bidiyo na asali da siginar sauti azaman abubuwan shigarwa. |
|
Yin lasisi |
Ana ba da HDMI TX IP tare da zaɓuɓɓukan lasisi guda biyu masu zuwa: • Rufaffen: An ba da cikakken rufaffiyar lambar RTL don ainihin. Ana samun kyauta tare da kowane lasisin Libero, yana ba da damar ci gaba da kasancewa tare da SmartDesign. Kuna iya yin Simulation, Synthesis, Layout, da tsara silikon FPGA ta amfani da ɗakin ƙirar Libero. • RTL: Cikakken lambar tushen RTL tana kulle lasisi, wanda ke buƙatar siya daban. |
Siffofin
HDMI TX IP yana da fasali masu zuwa:
• Mai jituwa don HDMI 2.0 da 1.4b
• Yana goyan bayan alama ɗaya ko huɗu/pixel kowace shigarwar agogo
• Yana goyan bayan ƙuduri har zuwa 3840 x 2160 a 60fps
• Yana goyan bayan zurfin launi 8, 10, 12, da 16-bit
• Yana goyan bayan tsarin launi kamar RGB, YUV 4:2:2, da YUV 4:4:4
• Yana goyan bayan sauti har zuwa tashoshi 32
Yana goyan bayan Tsarin Rufewa – TMDS
• Yana goyan bayan ɗan ƙasa da AXI4 Stream Video da Audio Data interface
• Yana goyan bayan ɗan ƙasa da AXI4-Lite Kanfigareshan dubawa don gyara siga
Umarnin Shigarwa
Dole ne a shigar da ainihin IP zuwa kundin IP na Libero® Software na SoC ta atomatik ta hanyar aikin sabuntawar Catalog na IP a cikin software na Libero SoC, ko kuma ana zazzage shi da hannu daga kasida. Da zarar an shigar da ainihin IP a cikin software na Libero SoC IP Catalog, an saita shi, ƙirƙira, kuma a nan take a cikin SmartDesign don haɗawa cikin aikin Libero.
Jagorar Mai Amfani
DS50003319C 2
© 2024 Microchip Technology Inc. da rassansa
Amfani da Albarkatu (Tambaya Tambaya)
Ana aiwatar da HDMI TX IP a cikin PolarFire® FPGA (MPF300T - 1FCG1152I Kunshin).
Tebur mai zuwa yana lissafin albarkatun da aka yi amfani da su lokacin g_PIXELS_PER_CLK = 1PXL.
Tebur 2. Amfani da albarkatun don 1PXL
|
|
g_COLOR_FORMAT g_BITS_PER_COMPONENT (Bits) |
g_AUX_CHANNEL_ENABLE g_4K60_SUPPORT Fabric |
|
4 LUT |
Fabric DFF |
Farashin 4LUT |
Farashin DFF |
uSRAM (64×12) |
|
RGB |
8 |
Kunna |
A kashe |
787 |
514 |
108 |
108 |
9 |
|
A kashe |
A kashe |
819 |
502 |
108 |
108 |
9 |
||
|
10 |
A kashe |
A kashe |
1070 |
849 |
156 |
156 |
13 |
|
|
12 |
A kashe |
A kashe |
1084 |
837 |
156 |
156 |
13 |
|
|
16 |
A kashe |
A kashe |
1058 |
846 |
156 |
156 |
13 |
|
|
YCbCr422 |
8 |
A kashe |
A kashe |
696 |
473 |
96 |
96 |
8 |
|
YCbCr444 |
8 |
A kashe |
A kashe |
819 |
513 |
108 |
108 |
9 |
|
10 |
A kashe |
A kashe |
1068 |
849 |
156 |
156 |
13 |
|
|
12 |
A kashe |
A kashe |
1017 |
837 |
156 |
156 |
13 |
|
|
16 |
A kashe |
A kashe |
1050 |
845 |
156 |
156 |
13 |
Tebur mai zuwa yana lissafin albarkatun da aka yi amfani da su lokacin g_PIXELS_PER_CLK = 4PXL.
Tebur 3. Amfani da albarkatun don 4PXL
|
|
g_COLOR_FORMAT g_BITS_PER_COMPONENT (Bits) |
g_AUX_CHANNEL_ENABLE g_4K60_SUPPORT Fabric |
|
4 LUT |
Fabric DFF |
Farashin 4LUT |
Farashin DFF |
uSRAM (64×12) |
|
RGB |
8 |
A kashe |
Kunna |
4078 |
2032 |
144 |
144 |
12 |
|
Kunna |
A kashe |
1475 |
2269 |
144 |
144 |
12 |
||
|
A kashe |
A kashe |
1393 |
1092 |
144 |
144 |
12 |
||
|
10 |
A kashe |
A kashe |
2151 |
1635 |
264 |
264 |
22 |
|
|
12 |
A kashe |
A kashe |
1909 |
1593 |
264 |
264 |
22 |
|
|
16 |
A kashe |
A kashe |
1645 |
1284 |
264 |
264 |
22 |
|
|
YCbCr422 |
8 |
A kashe |
A kashe |
1265 |
922 |
144 |
144 |
12 |
|
YCbCr444 |
8 |
A kashe |
A kashe |
1119 |
811 |
144 |
144 |
12 |
|
10 |
A kashe |
A kashe |
2000 |
1627 |
264 |
264 |
22 |
|
|
12 |
A kashe |
A kashe |
1909 |
1585 |
264 |
264 |
22 |
|
|
16 |
A kashe |
A kashe |
1604 |
1268 |
264 |
264 |
22 |
Jagorar Mai Amfani
DS50003319C 3
© 2024 Microchip Technology Inc. da rassansa
HDMI TX IP Configurator
1. HDMI TX IP Configurator (Tambaya Tambaya)
Wannan sashe yana ba da ƙarewaview na HDMI TX Configurator interface da nau'ikansa daban-daban.
HDMI TX Configurator yana ba da ƙirar hoto don saita ainihin HDMI TX don takamaiman buƙatun watsa bidiyo. Wannan mai daidaitawa yana bawa mai amfani damar zaɓar sigogi kamar Bits Per Component, Tsarin launi, Yawan Pixels, Yanayin Sauti, Interface, Testbench, da Lasisi. Yana da mahimmanci don daidaita waɗannan saitunan daidai don tabbatar da ingantaccen watsa bayanan bidiyo akan HDMI.
Keɓancewar HDMI TX Configurator ya ƙunshi menus na zazzage daban-daban da zaɓuɓɓuka waɗanda ke ba masu amfani damar tsara saitunan watsawa na HDMI. An bayyana maɓallan maɓalli a ciki Table 3-1.
Hoto na gaba yana ba da daki-daki view na HDMI TX Configurator interface.
Hoto na 1-1. HDMI TX IP Configurator
Maballin ya haɗa da Ok da Maɓallin Soke don tabbatarwa ko zubar da saitunan da aka yi.
Jagorar Mai Amfani
DS50003319C 5
© 2024 Microchip Technology Inc. da rassansa
Aiwatar Hardware
2. Aiwatar Hardware (Tambaya Tambaya)
HDMI Transmitter (TX) ya ƙunshi s biyutage:
Aiki na XOR/XNOR, wanda ke rage yawan canjin canji
• INV/NONINV, wanda ke rage rarrabuwa (ma'aunin DC). Ana ƙara ƙarin ragi biyu a wannan stage aiki. Bayanan sarrafawa (hsync da vsync) an sanya su zuwa rago 10 a cikin haɗe-haɗe huɗu masu yuwuwa don taimakawa mai karɓa ya daidaita agogonsa tare da agogon watsawa. Dole ne a yi amfani da transceiver tare da HDMI TX IP don tsara rago 10 (yanayin pixel 1) ko 40 ragowa (yanayin pixels 4).
Mai daidaitawa kuma yana nuna wakilcin ainihin HDMI Tx, mai lakabin HDMI_TX_0, yana nuna hanyoyin shigarwa da fitarwa iri-iri waɗanda aka haɗa tare da ainihin. Akwai hanyoyi guda uku don haɗin HDMI TX kuma an bayyana su kamar haka:
Yanayin Tsarin Launi na RGB
Tashar jiragen ruwa na HDMI TX IP na pixel ɗaya a kowace agogo lokacin da aka kunna yanayin sauti kuma Tsarin launi shine RGB don PolarFire® Ana nuna na'urori a cikin adadi mai zuwa. Wakilin gani na tashar tashar HDMI Tx core kamar haka:
• Alamomin agogon sarrafawa sune R_CLK_LOCK, G_CLK_LOCK, da B_CLK_LOCK. Alamomin agogo sune R_CLK_I, G_CLK_I, da B_CLK_I.
• Tashoshin bayanai da suka hada da DATA_R_I, DATA_G_I, da DATA_B_I.
• Sigina na bayanai na taimako sune AUX_DATA_R_I da AUX_DATA_G_I.
Hoto na 2-1. HDMI TX IP Block zane (Tsarin Launi na RGB)
Don ƙarin bayani game da sigina na I/O don tsarin launi na RGB, duba Table 3-2.
YCbCr444 Yanayin Tsarin Launi
Tashoshin tashar jiragen ruwa na HDMI TX IP na pixel ɗaya a kowace agogo lokacin da yanayin sauti ke kunna kuma Tsarin launi shine YCbCr444 ana nuna shi a cikin adadi mai zuwa. Wakilin gani na tashar tashar HDMI Tx core kamar haka:
• Alamomin sarrafawa sune Y_CLK_LOCK, Cb_CLK_LOCK, da Cr_CLK_LOCK.
• Alamomin agogo sune Y_CLK_I, Cb_CLK_I, da Cr_CLK_I.
Jagorar Mai Amfani
DS50003319C 6
© 2024 Microchip Technology Inc. da rassansa
Aiwatar Hardware
• Tashoshin bayanai da suka hada da DATA_Y_I, DATA_Cb_I, da DATA_Cr_I.
• Sigina na shigar da bayanai na taimako sune AUX_DATA_Y_I da AUX_DATA_C_I.
Hoto na 2-2. HDMI TX IP Block zane (Tsarin Launi YCbCr444)
Don ƙarin bayani game da sigina na I/O don tsarin launi na YCbCr444, duba Table 3-6. YCbCr422 Yanayin Tsarin Launi
Tashoshin tashar jiragen ruwa na HDMI TX IP na pixel ɗaya a kowace agogo lokacin da yanayin sauti ke kunna kuma Tsarin launi shine YCbCr422 ana nuna shi a cikin adadi mai zuwa. Wakilin gani na tashar tashar HDMI Tx core kamar haka:
• Alamomin sarrafawa sune LANE1_CLK_LOCK, LANE2_CLK_LOCK, da LANE3_CLK_LOCK. • Alamomin agogo sune LANE1_CLK_I, LANE2_CLK_I, da LANE3_CLK_I.
• Tashoshin bayanai da suka hada da DATA_Y_I da DATA_C_I.
Jagorar Mai Amfani
DS50003319C 7
© 2024 Microchip Technology Inc. da rassansa
Aiwatar Hardware
Hoto na 2-3. HDMI TX IP Block zane (Tsarin Launi YCbCr422)
Don ƙarin bayani game da sigina na I/O don tsarin launi na YCbCr422, duba Table 3-7 Jagorar Mai Amfani
DS50003319C 8
© 2024 Microchip Technology Inc. da rassansa
HDMI TX Parameters da Interface Signals
3. HDMI TX Parameters da Interface Signals (Tambaya Tambaya)
Wannan sashe yana tattauna sigogi a cikin HDMI TX GUI mai daidaitawa da alamun I/O. 3.1 Ma'aunin Kanfigareshan (Tambaya Tambaya)
Tebur mai zuwa yana lissafin sigogin daidaitawa a cikin HDMI TX IP.
Tebur 3-1. Ma'aunin Kanfigareshan
|
Sunan Siga |
Bayani |
|
Tsarin launi |
Yana bayyana sararin launi. Yana goyan bayan tsarin launi masu zuwa: • RGB • YCbCr422 • YCbCr444 |
|
Adadin rago kowane bangaren |
Yana ƙayyade adadin ragowa a kowane ɓangaren launi. Yana goyan bayan 8, 10, 12, da 16 ragowa kowane bangare. |
|
Adadin Pixels |
Yana nuna adadin pixels a kowace shigarwar agogo: • Pixel kowace agogo = 1 • Pixel kowace agogo = 4 |
|
4Kp60 Taimako |
Taimako don ƙudurin 4K a firam 60 a sakan daya: • Lokacin da aka kunna tallafin 1, 4Kp60 • Lokacin da aka kashe tallafin 0, 4Kp60 |
|
Yanayin Sauti |
Yana saita yanayin watsa sauti. Bayanan odiyo don tashar R da G: • Kunna Kashe |
|
Interface |
Na asali da AXI rafi |
|
Testbench |
Yana ba da damar zaɓin muhallin testbench. Yana goyan bayan zaɓuɓɓukan gwajin benci masu zuwa: • Mai amfani • Babu |
|
Lasisi |
Yana ƙayyade nau'in lasisi. Yana ba da zaɓuɓɓukan lasisi guda biyu masu zuwa: • RTL • Rufewa |
3.2 Tashoshi (Tambaya Tambaya)
Tebur mai zuwa yana lissafin shigarwar da tashoshin fitarwa na HDMI TX IP don mahaɗin ɗan ƙasa lokacin da yanayin Audio ya kunna kuma Tsarin launi shine RGB.
Tebur 3-2. Sigina na shigarwa da fitarwa
|
Sunan siginar |
Hanyar |
Nisa |
Bayani |
|
SYS_CLK_I |
Shigarwa |
1-bit |
Agogon tsarin, yawanci agogo ɗaya da mai sarrafa nuni |
|
SAKETA_N_I |
Shigarwa |
1-bit |
Asynchronous mai aiki-ƙananan siginar sake saiti |
|
VIDEO_DATA_VALID_I |
Shigarwa |
1-bit |
Ingantattun bayanan bidiyo |
|
AUDIO_DATA_VALID_I |
Shigarwa |
1-bit |
Bayanan fakitin odiyo ingantaccen shigarwar |
|
R_CLK_I |
Shigarwa |
1-bit |
Agogon TX don tashar "R" daga XCVR |
|
R_CLK_LOCK |
Shigarwa |
1-bit |
TX_CLK_STABLE don tashar R daga XCVR |
|
G_CLK_I |
Shigarwa |
1-bit |
Agogon TX don tashar "G" daga XCVR |
|
G_CLK_LOCK |
Shigarwa |
1-bit |
TX_CLK_STABLE don tashar G daga XCVR |
|
B_CLK_I |
Shigarwa |
1-bit |
Agogon TX don tashar "B" daga XCVR |
Jagorar Mai Amfani
DS50003319C 9
© 2024 Microchip Technology Inc. da rassansa
HDMI TX Parameters da Interface Signals
|
………… ci gaba Bayanin Nisa Sunan Siginar |
|||
|
B_CLK_LOCK |
Shigarwa |
1-bit |
TX_CLK_STABLE don tashar B daga XCVR |
|
H_SYNC_I |
Shigarwa |
1-bit |
A tsaye bugun bugun jini |
|
V_SYNC_I |
Shigarwa |
1-bit |
bugun jini daidaitacce a tsaye |
|
PACKET_HEADER_I |
Shigarwa |
PIXELS_PER_CLK*1 |
Babban fakiti don bayanan fakitin odiyo |
|
DATA_R_I |
Shigarwa |
PIXELS_PER_CLK*8 |
Shigar da bayanan "R". |
|
DATA_G_I |
Shigarwa |
PIXELS_PER_CLK*8 |
Shigar da bayanan "G". |
|
DATA_B_I |
Shigarwa |
PIXELS_PER_CLK*8 |
Shigar da bayanan "B". |
|
AUX_DATA_R_I |
Shigarwa |
PIXELS_PER_CLK*4 |
Fakitin audio "R" bayanan tashar |
|
AUX_DATA_G_I |
Shigarwa |
PIXELS_PER_CLK*4 |
Fakitin audio "G" bayanan tashar |
|
TMDS_R_O |
Fitowa |
PIXELS_PER_CLK*10 |
An shigar da bayanan "R". |
|
TMDS_G_O |
Fitowa |
PIXELS_PER_CLK*10 |
An shigar da bayanan "G". |
|
TMDS_B_O |
Fitowa |
PIXELS_PER_CLK*10 |
An shigar da bayanan "B". |
Tebur mai zuwa yana lissafin tashoshin jiragen ruwa na AXI4 Stream interface tare da Mai kunna Audio.
Tebur 3-3. Shigarwa da Tashoshin fitarwa don AXI4 Stream Interface
|
Nau'in Sunan Port |
|
Nisa |
Bayani |
|
TDATA_I |
Shigarwa |
3*g_BITS_PER_COMPONENT*g_PIXELS_PER_CLK shigar da bayanan bidiyo |
|
|
TVALID_I |
Shigarwa |
1-bit |
Shigar da bidiyon yana aiki |
|
TREADY_O Fitowa 1-bit |
|
|
Sigina shirye-shiryen bawa |
|
TUSER_I |
Shigarwa |
PIXELS_PER_CLK*9 + 5 |
bit 0 = rashin amfani bit 1 = VSYNC bit 2 = HSYNC bit 3 = rashin amfani bit [3 + g_PIXELS_PER_CLK: 4] = Babban fakitin bitar [4 + g_PIXELS_PER_CLK] = Ingantaccen bayanan sauti bit [(5 * g_PIXELS_PER_CLK) + 4: (1*g_PIXELS_PER_CLK) + 5] = Audio G bayanai bit [(9 * g_PIXELS_PER_CLK) + 4: (5*g_PIXELS_PER_CLK) + 5] = Bayanan R Audio |
Tebur mai zuwa yana lissafin shigarwar da tashoshin fitarwa na HDMI TX IP don ƙirar ƙasa lokacin da yanayin Audio ya ƙare.
Tebur 3-4. Sigina na shigarwa da fitarwa
|
Sunan siginar |
Hanyar |
Nisa |
Bayani |
|
SYS_CLK_I |
Shigarwa |
1-bit |
Agogon tsarin, yawanci agogo ɗaya da mai sarrafa nuni |
|
SAKETA_N_I |
Shigarwa |
1-bit |
Asynchronous aiki-ƙananan siginar sake saiti |
|
VIDEO_DATA_VALID_I |
Shigarwa |
1-bit |
Ingantattun bayanan bidiyo |
|
R_CLK_I |
Shigarwa |
1-bit |
Agogon TX don tashar "R" daga XCVR |
|
R_CLK_LOCK |
Shigarwa |
1-bit |
TX_CLK_STABLE don tashar R daga XCVR |
|
G_CLK_I |
Shigarwa |
1-bit |
Agogon TX don tashar "G" daga XCVR |
|
G_CLK_LOCK |
Shigarwa |
1-bit |
TX_CLK_STABLE don tashar G daga XCVR |
|
B_CLK_I |
Shigarwa |
1-bit |
Agogon TX don tashar "B" daga XCVR |
|
B_CLK_LOCK |
Shigarwa |
1-bit |
TX_CLK_STABLE don tashar B daga XCVR |
|
H_SYNC_I |
Shigarwa |
1-bit |
A tsaye bugun bugun jini |
|
V_SYNC_I |
Shigarwa |
1-bit |
bugun jini daidaitacce a tsaye |
|
DATA_R_I |
Shigarwa |
PIXELS_PER_CLK*8 |
Shigar da bayanan "R". |
Jagorar Mai Amfani
DS50003319C 10
© 2024 Microchip Technology Inc. da rassansa
HDMI TX Parameters da Interface Signals
|
………… ci gaba Bayanin Nisa Sunan Siginar |
|||
|
DATA_G_I |
Shigarwa |
PIXELS_PER_CLK*8 |
Shigar da bayanan "G". |
|
DATA_B_I |
Shigarwa |
PIXELS_PER_CLK*8 |
Shigar da bayanan "B". |
|
TMDS_R_O |
Fitowa |
PIXELS_PER_CLK*10 |
An shigar da bayanan "R". |
|
TMDS_G_O |
Fitowa |
PIXELS_PER_CLK*10 |
An shigar da bayanan "G". |
|
TMDS_B_O |
Fitowa |
PIXELS_PER_CLK*10 |
An shigar da bayanan "B". |
Tebur mai zuwa yana lissafin tashoshin jiragen ruwa na AXI4 Stream interface.
Tebur 3-5. Shigarwa da Tashoshin fitarwa don AXI4 Stream Interface
|
Sunan tashar jiragen ruwa |
Nau'in |
Nisa |
Bayani |
|
TDATA_I_VIDEO |
Shigarwa |
3*g_BITS_PER_COMPONENT*g_PIXELS_PER_CLK |
Shigar da bayanan bidiyo |
|
TVALID_I_VIDEO |
Shigarwa |
1-bit |
Shigar da bidiyon yana aiki |
|
TAFIYA_O_VIDEO |
Fitowa |
1-bit |
Sigina shirye-shiryen bawa |
|
TUSER_I_VIDEO |
Shigarwa |
4 bits |
bit 0 = rashin amfani bit 1 = VSYNC bit 2 = HSYNC bit 3 = rashin amfani |
Tebur mai zuwa yana lissafin tashoshin jiragen ruwa don yanayin YCbCr444 lokacin da yanayin sauti ya kunna.
Tebur 3-6. Shigarwa da Fitarwa don Yanayin YCbCr444 da Yanayin Sauti
|
Sunan siginar |
Nisa Hanyar |
|
Bayani |
|
SYS_CLK_I |
Shigarwa |
1-bit |
Agogon tsarin, yawanci agogo ɗaya da mai sarrafa nuni |
|
SAKETA_N_I |
Shigarwa |
1-bit |
Asynchronous mai aiki-ƙananan siginar sake saiti |
|
VIDEO_DATA_VALID_I Shigarwa |
|
1-bit |
Ingantattun bayanan bidiyo |
|
Shigar AUDIO_DATA_VALID_I |
|
1-bit |
Bayanan fakitin odiyo ingantaccen shigarwar |
|
Y_CLK_I |
Shigarwa |
1-bit |
Agogon TX don tashar "Y" daga XCVR |
|
Y_CLK_LOCK |
Shigarwa |
1-bit |
TX_CLK_STABLE don tashar Y daga XCVR |
|
Cb_CLK_I |
Shigarwa |
1-bit |
Agogon TX don tashar "Cb" daga XCVR |
|
Cb_CLK_LOCK |
Shigarwa |
1-bit |
TX_CLK_STABLE don tashar Cb daga XCVR |
|
Cr_CLK_I |
Shigarwa |
1-bit |
Agogon TX don tashar "Cr" daga XCVR |
|
Cr_CLK_LOCK |
Shigarwa |
1-bit |
TX_CLK_STABLE don tashar Cr daga XCVR |
|
H_SYNC_I |
Shigarwa |
1-bit |
A tsaye bugun bugun jini |
|
V_SYNC_I |
Shigarwa |
1-bit |
bugun jini daidaitacce a tsaye |
|
PACKET_HEADER_I |
Shigarwa |
PIXELS_PER_CLK*1 |
Babban fakiti don bayanan fakitin odiyo |
|
DATA_Y_I |
Shigarwa |
PIXELS_PER_CLK*8 |
Shigar da bayanan "Y". |
|
DATA_Cb_I |
Shigarwa |
PIXELS_PER_CLK*DATA_WIDTH Shigar da bayanan "Cb". |
|
|
DATA_Cr_I |
Shigarwa |
PIXELS_PER_CLK*DATA_WIDTH Shigar da bayanan "Cr". |
|
|
AUX_DATA_Y_I |
Shigarwa |
PIXELS_PER_CLK*4 |
Fakitin audio "Y" bayanan tashar |
|
AUX_DATA_C_I |
Shigarwa |
PIXELS_PER_CLK*4 |
Fakitin audio "C" bayanan tashar |
|
TMDS_R_O |
Fitowa |
PIXELS_PER_CLK*10 |
An shigar da bayanan "Cb". |
|
TMDS_G_O |
Fitowa |
PIXELS_PER_CLK*10 |
An shigar da bayanan "Y". |
|
TMDS_B_O |
Fitowa |
PIXELS_PER_CLK*10 |
An shigar da bayanan "Cr". |
Tebur mai zuwa yana lissafin tashoshin jiragen ruwa don yanayin YCbCr422 lokacin da yanayin sauti ya kunna.
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HDMI TX Parameters da Interface Signals
Tebur 3-7. Shigarwa da Fitarwa don Yanayin YCbCr422 da Yanayin Sauti
|
Sunan siginar |
Nisa Hanyar |
|
Bayani |
|
SYS_CLK_I |
Shigarwa |
1-bit |
Agogon tsarin, yawanci agogo ɗaya da mai sarrafa nuni |
|
SAKETA_N_I |
Shigarwa |
1-bit |
Asynchronous Active - siginar sake saiti mara ƙarancin ƙima |
|
VIDEO_DATA_VALID_I Shigarwa |
|
1-bit |
Ingantattun bayanan bidiyo |
|
LANE1_CLK_I |
Shigarwa |
1-bit |
Agogon TX don "layin daga layin XCVE 1" tashar daga XCVR |
|
LANE1_CLK_LOCK |
Shigarwa |
1-bit |
TX_CLK_STABLE don layi daga layin XCVE 1 |
|
LANE2_CLK_I |
Shigarwa |
1-bit |
Agogon TX don "layin daga layin XCVE 2" tashar daga XCVR |
|
LANE2_CLK_LOCK |
Shigarwa |
1-bit |
TX_CLK_STABLE don layi daga layin XCVE 2 |
|
LANE3_CLK_I |
Shigarwa |
1-bit |
Agogon TX don "layin daga layin XCVE 3" tashar daga XCVR |
|
LANE3_CLK_LOCK |
Shigarwa |
1-bit |
TX_CLK_STABLE don layi daga layin XCVE 3 |
|
H_SYNC_I |
Shigarwa |
1-bit |
A tsaye bugun bugun jini |
|
V_SYNC_I |
Shigarwa |
1-bit |
bugun jini daidaitacce a tsaye |
|
PACKET_HEADER_I |
Shigarwa |
PIXELS_PER_CLK*1 |
Babban fakiti don bayanan fakitin odiyo |
|
DATA_Y_I |
Shigarwa |
PIXELS_PER_CLK*DATA_WIDTH Shigar da bayanan "Y". |
|
|
DATA_C_I |
Shigarwa |
PIXELS_PER_CLK*DATA_WIDTH Shigar da bayanan "C". |
|
|
AUX_DATA_Y_I |
Shigarwa |
PIXELS_PER_CLK*4 |
Fakitin audio "Y" bayanan tashar |
|
AUX_DATA_C_I |
Shigarwa |
PIXELS_PER_CLK*4 |
Fakitin audio "C" bayanan tashar |
|
TMDS_R_O |
Fitowa |
PIXELS_PER_CLK*10 |
An shigar da bayanan "C". |
|
TMDS_G_O |
Fitowa |
PIXELS_PER_CLK*10 |
An shigar da bayanan "Y". |
|
TMDS_B_O |
Fitowa |
PIXELS_PER_CLK*10 |
Rufaffen bayanai masu alaƙa da bayanin daidaitawa |
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Yi rijista taswira da Bayani
4. Yi rijista taswira da Bayani (Tambaya Tambaya)
|
Kashewa |
Suna |
Bit Pos. |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
0 x00 |
SCRAMBLER_IP_EN |
7:0 |
|
|
|
|
|
|
|
FARA |
|
15:8 |
|
|
|
|
|
|
|
|
||
|
23:16 |
|
|
|
|
|
|
|
|
||
|
31:24 |
|
|
|
|
|
|
|
|
||
|
0 x04 |
XCVR_DATA_LANE_ 0_SEL |
7:0 |
|
|
|
|
|
|
FARA[1:0] |
|
|
15:8 |
|
|
|
|
|
|
|
|
||
|
23:16 |
|
|
|
|
|
|
|
|
||
|
31:24 |
|
|
|
|
|
|
|
|
||
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Yi rijista taswira da Bayani
4.1 SCRAMBLER_IP_EN (Tambaya Tambaya)
Suna: SCRAMBLER_IP_EN
Saukewa: 0x000
Sake saita: 0x0
Dukiya: Rubutu-kawai
Scrambler Kunna Rijistar Sarrafa. Dole ne a rubuta wannan rajista don samun Tallafin 4kp60 don HDMI TX IP
Bit 31 30 29 28 27 26 25 24
Shiga
Sake saiti
Bit 23 22 21 20 19 18 17 16
Shiga
Sake saiti
Bit 15 14 13 12 11 10 9 8
Shiga
Sake saiti
Bit 7 6 5 4 3 2 1 0
|
|
|
|
|
|
|
|
FARA |
Shiga W Sake saitin 0
Bit 0 - Fara Rubutun "1" zuwa wannan bit yana farawa Scrambler canja wurin bayanai an kunna. HDMI 2.0 yana amfani da wani nau'i na scrambling da aka sani da 8b/10b encoding. Ana amfani da wannan makircin rufaffiyar don isar da bayanai akan hanyar sadarwa ta HDMI dogaro da inganci.
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Yi rijista taswira da Bayani
4.2 XCVR_DATA_LANE_0_SEL (Tambaya Tambaya)
Suna: XCVR_DATA_LANE_0_SEL
Saukewa: 0x004
Sake saita: 0x1
Dukiya: Rubutu-kawai
Rijistar XCVR_DATA_LANE_0_SEL yana zaɓar buƙatun bayanan don canjawa wuri zuwa XCVR daga HDMI TX IP don samun agogo don Cikakken HD, 4kp30, 4kp60.
Bit 31 30 29 28 27 26 25 24
|
|
|
|
|
|
|
|
|
Shiga
Sake saiti
Bit 23 22 21 20 19 18 17 16
|
|
|
|
|
|
|
|
|
Shiga
Sake saiti
Bit 15 14 13 12 11 10 9 8
|
|
|
|
|
|
|
|
|
Shiga
Sake saiti
Bit 7 6 5 4 3 2 1 0
|
|
|
|
|
|
|
FARA[1:0] |
Shiga WW Sake saitin 0 1
Bits 1:0 - START[1:0] Rubutun "10" ga wannan rago yana farawa 4KP60 kuma an ba da ƙimar bayanan XCVR a matsayin FFFFF_00000.
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Testbench Simulation
5. Testbench Simulation (Tambaya Tambaya)
Ana ba da Testbench don duba ayyukan HDMI TX core. Testbench yana aiki ne kawai a cikin mahalli na asali tare da 1 pixel kowace agogo da kunna yanayin sauti.
Tebu mai zuwa yana lissafin sigogi waɗanda aka saita bisa ga aikace-aikacen.
Tebur 5-1. Sigar Kanfigareshan Testbench
|
Suna |
Tsoffin Ma'auni |
|
Tsarin launi (g_COLOR_FORMAT) |
RGB |
|
Bits a kowane bangare (g_BITS_PER_COMPONENT) |
8 |
|
Adadin Pixels (g_PIXELS_PER_CLK) |
1 |
|
Tallafin 4Kp60 (g_4K60_SUPPORT) |
0 |
|
Yanayin Sauti (g_AUX_CHANNEL_ENABLE) |
1 (A kunna) |
|
Manhaja (G_FORMAT) |
0 (A kashe) |
Don kwaikwayi ainihin abin da ke amfani da testbench, yi matakai masu zuwa:
1. A cikin Zane Flow taga, fadada Create Design.
2. Danna-dama Create SmartDesign Testbench, sa'an nan kuma danna Run, kamar yadda aka nuna a cikin wannan adadi. Hoto na 5-1. Ƙirƙirar SmartDesign Testbench
3. Shigar da suna don SmartDesign testbench, sa'an nan kuma danna Ok.
Hoto na 5-2. Sunan SmartDesign Testbench
SmartDesign testbench an ƙirƙira, kuma zane ya bayyana a hannun dama na Fane Flow Design.
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Testbench Simulation
4. Kewaya zuwa Libero® SoC Catalog, zaɓi View > Windows > IP Catalog, sannan kuma fadada Bidiyon Magani. Danna HDMI TX IP sau biyu (v5.2.0), sannan danna Ok.
5. A cikin taga mai daidaitawa, zaɓi adadin da ake buƙata na ƙimar Pixels, kamar yadda aka nuna a cikin adadi mai zuwa.
Hoto na 5-3. Kanfigareshi
6. Zaɓi duk tashoshin jiragen ruwa, danna-dama kuma zaɓi Ƙara zuwa Babban Matsayi.
7. A kan SmartDesign Toolbar, danna Ƙirƙirar Bangaren.
8. A shafin Stimulus Hierarchy, danna-dama HDMI_TX_TB testbench file, sannan danna Simulate Pre-Synth Design> Buɗe Interactively.
ModelSim® kayan aiki yana buɗewa tare da testbench, kamar yadda aka nuna a cikin adadi mai zuwa. Hoto na 5-4. ModelSim Tool tare da HDMI TX Testbench File
Muhimmi: Idan an katse simulation saboda iyakar lokacin gudu da aka ƙayyade a cikin DO file, amfani da gudu - duk umarni don kammala simintin.
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Testbench Simulation
5.1 Jadawalin lokaci (Tambaya Tambaya)
Zane mai zuwa na lokaci don HDMI TX IP yana nuna bayanan bidiyo da lokutan sarrafa bayanai don 1 pixel kowace agogo.
Hoto na 5-5. Tsarin lokaci na HDMI TX IP na Bayanan Bidiyo don 1 Pixel kowace agogo
Zane mai zuwa yana nuna haɗe-haɗe huɗu na bayanan sarrafawa.
Hoto na 5-6. HDMI TX IP Tsare-tsare Tsare-tsare na Bayanan Gudanarwa don 1 Pixel kowace agogo
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Haɗin tsarin
6. Haɗin tsarin (Tambaya Tambaya)
Wannan sashe yana nuna kamarample zane bayanin.
Tebur mai zuwa yana lissafin jeri na PF XCVR, PF TX PLL, da PF CCC.
Tebur 6-1. PF XCVR, PF TX PLL, da PF CCC Kanfigareshan
|
Ƙaddamarwa |
|
Saitin Nisa PF XCVR Bit |
PF TX PLL Kanfigareshan |
PF CCC Kanfigareshan |
||||
|
Bayanan Bayani na TX Rate |
TX agogo Rarraba Factor |
Farashin TX PCS Fabric Nisa |
Ana so Agogon fitarwa |
Magana Agogo Yawanci |
Shigarwa Yawanci |
Fitowa Yawanci |
||
|
1PXL (1080p60) 8 |
|
1485 |
4 |
10 |
5940 |
148.5 |
NA |
NA |
|
1PXL (1080p30) 10 |
|
925 |
4 |
10 |
3700 |
148.5 |
92.5 |
74 |
|
12 |
1113.75 |
4 |
10 |
4455 |
148.5 |
111.375 |
74.25 |
|
|
16 |
1485 |
4 |
10 |
5940 |
148.5 |
148.5 |
74.25 |
|
|
4PXL (1080p60) 10 |
|
1860 |
4 |
40 |
7440 |
148.5 |
46.5 |
37.2 |
|
12 |
2229 |
4 |
40 |
8916 |
148.5 |
55.725 |
37.15 |
|
|
16 |
2970 |
2 |
40 |
5940 |
148.5 |
74.25 |
37.125 |
|
|
4PXL (4kp30) |
8 |
2970 |
2 |
40 |
5940 |
148.5 |
NA |
NA |
|
10 |
3712.5 |
2 |
40 |
7425 |
148.5 |
92.812 |
74.25 |
|
|
12 |
4455 |
1 |
40 |
4455 |
148.5 |
111.375 |
74.25 |
|
|
16 |
5940 |
1 |
40 |
5940 |
148.5 |
148.5 |
74.25 |
|
|
4PXL (4Kp60) |
8 |
5940 |
1 |
40 |
5940 |
148.5 |
NA |
NA |
HDMI TX Sample Design, lokacin da aka saita a g_BITS_PER_COMPONENT = 8-bit da
g_PIXELS_PER_CLK = Yanayin PXL 1, ana nuna shi a cikin adadi mai zuwa.
Hoto na 6-1. HDMI TX Sampda Design
HDMI_TX_C0_0
PF_INIT_MONITOR_C0_0
|
FABRIC_POR_N PCIE_INIT_DONE USRAM_INIT_DONE SRAM_INIT_DONE DEVICE_INIT_DONE XCVR_INIT_DONE USRAM_INIT_FROM_SNVM_DONE USRAM_INIT_FROM_UPROM_DONE USRAM_INIT_FROM_SPI_DONE SRAM_INIT_FROM_SNVM_DONE SRAM_INIT_FROM_UPROM_DONE SRAM_INIT_FROM_SPI_DONE AUTOCALIB_DONE |
PF_INIT_MONITOR_C0
CORESET_PF_C0_0
|
CLK EXT_RST_N BANK_x_VDDI_MATSAYI BANK_y_VDDI_MATSAYI PLL_POWERDOWN_B PLL_LOCK FABRIC_RESET_N SS_BUSY INIT_DONE FF_US_RESTORE FPGA_POR_N |
CORESET_PF_C0
Nuni_Mai sarrafa_C0_0
|
FRAME_END_O H_SYNC_O SAKETA_I V_SYNC_O SYS_CLK_I V_ACTIVE_O ANABLE_I DATA_TRIGGER_O H_RES_O[15:0] V_RES_O[15:0] |
Nuni_Controller_C0
tsarin_generator_verilog_pattern_0
|
DATA_VALID_O SYS_CLK_I FRAME_END_O SAKETA_N_I LINE_END_O DATA_EN_I RED_O[7:0] FRAME_END_I GREEN_O[7:0] PATTERN_SEL_I[2:0] BLUE_O[7:0] BAYER_O[7:0] |
Gwaji_Tsarin_Generator_C1
PF_XCVR_REF_CLK_C0_0
|
SAKETA_N_I SYS_CLK_I VIDEO_DATA_VALID_I R_CLK_I R_CLK_LOCK G_CLK_I G_CLK_LOCK TMDS_R_O[9:0] B_CLK_I TMDS_G_O[9:0] B_CLK_LOCK TMDS_B_O[9:0] V_SYNC_I XCVR_LANE_0_DATA_O[9:0] H_SYNC_I
DATA_R_I[7:0]
DATA_G_I[7:0]
DATA_B_I[7:0] |
HDMI_TX_C0
PF_TX_PLL_C0_0
PF_XCVR_ERM_C0_0
|
PADs_OUT LANE3_TXD_N CLKS_FROM_TXPLL_0 LANE3_TXD_P LANE0_IN LANE2_TXD_N LANE0_PCS_ARST_N LANE2_TXD_P LANE0_PMA_ARST_N LANE1_TXD_N LANE0_TX_DATA[9:0] LANE1_TXD_P LANE1_IN LANE0_TXD_N LANE1_PCS_ARST_N LANE0_TXD_P LANE1_PMA_ARST_N LANE0_OUT LANE1_TX_DATA[9:0] LANE0_TX_CLK_R LANE2_IN LANE0_TX_CLK_STABLE LANE2_PCS_ARST_N LANE1_OUT LANE2_PMA_ARST_N LANE1_TX_CLK_R LANE2_TX_DATA[9:0] LANE1_TX_CLK_STABLE LANE3_IN LANE2_OUT LANE3_PCS_ARST_N LANE2_TX_CLK_R LANE3_PMA_ARST_N LANE2_TX_CLK_STABLE LANE3_TX_DATA[9:0] LANE3_OUT LANE3_TX_CLK_STABLE |
PF_XCVR_ERM_C0
LANE3_TXD_N LANE3_TXD_P LANE2_TXD_N LANE2_TXD_P LANE1_TXD_N LANE1_TXD_P LANE0_TXD_N LANE0_TXD_P
PATTERN_SEL_I[2:0] REF_CLK_PAD_P REF_CLK_PAD_N
|
REF_CLK_PAD_P REF_CLK_PAD_NREF_CLK |
|
REF_CLKPLL_LOCKCLKS_TO_XCVR |
PF_XCVR_REF_CLK_C0
PF_TX_PLL_C0
Don Example, a cikin saitunan 8-bit, waɗannan abubuwan haɗin sune ɓangaren ƙira: • PF_XCVR_ERM (PF_XCVR_ERM_C0_0) an saita don ƙimar bayanai na 1485 Mbps a yanayin PMA don TX kawai, tare da saita faɗin bayanan azaman 10 bit don yanayin 1pxl kuma Agogon tunani 148.5 MHz, dangane da saitunan tebur da suka gabata
• Ana samar da fitowar LANE0_TX_CLK_R na PF_XCVR_ERM_C0_0 azaman agogon 148.5 MHz, dangane da saitunan tebur da suka gabata.
• SYS_CLK_I (HDMI_TX_C0, Display_Controller_C0, pattern_generator_C0, CORERESET_PF_C0, da PF_INIT_MONITOR_C0) LANE0_TX_CLK_R ne ke tafiyar da shi, wanda shine 148.5 MHz
R_CLK_I, G_CLK_I, da B_CLK_I LANE3_TX_CLK_R, LANE2_TX_CLK_R, da LANE1_TX_CLK_R, bi da bi.
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Haɗin tsarin
Sample haɗin kai don, g_BITS_PER_COMPONENT = 8 da g_PIXELS_PER_CLK = 4. Ga Example, a cikin saitunan 8-bit, abubuwan da ke biyo baya sune ɓangaren ƙira: • PF_XCVR_ERM (PF_XCVR_ERM_C0_0) an saita don ƙimar bayanai na 2970 Mbps a yanayin PMA don
TX kawai, tare da faɗin bayanan da aka saita azaman 40-bit don yanayin 1pxl da agogon tunani 148.5 MHz dangane da saitunan tebur da suka gabata.
• Ana samar da fitowar LANE0_TX_CLK_R na PF_XCVR_ERM_C0_0 azaman agogon 74.25 MHz, dangane da saitunan tebur da suka gabata.
• SYS_CLK_I (HDMI_TX_C0, Display_Controller_C0, pattern_generator_C0, CORERESET_PF_C0, da PF_INIT_MONITOR_C0) LANE0_TX_CLK_R ne ke tafiyar da shi, wanda shine 148.5 MHz
R_CLK_I, G_CLK_I, da B_CLK_I LANE3_TX_CLK_R, LANE2_TX_CLK_R, da LANE1_TX_CLK_R, bi da bi.
HDMI TX Sample Design, lokacin da aka saita a g_BITS_PER_COMPONENT = 12 Bit da g_PIXELS_PER_CLK = yanayin PXL 1, wanda aka nuna a cikin adadi mai zuwa.
Hoto na 6-2. HDMI TX Sampda Design
PF_XCVR_ERM_C0_0
PATTERN_SEL_I[2:0]
REF_CLK_PAD_P REF_CLK_PAD_N
PF_CCC_C1_0
|
REF_CLK_0 OUT0_FABCLK_0PLL_LOCK_0 |
PF_CCC_C1
PF_INIT_MONITOR_C0_0
CORESET_PF_C0_0
|
CLK EXT_RST_N BANK_x_VDDI_MATSAYI BANK_y_VDDI_MATSAYI PLL_POWERDOWN_B PLL_LOCK FABRIC_RESET_N SS_BUSY INIT_DONE FF_US_RESTORE FPGA_POR_N |
CORESET_PF_C0
Nuni_Mai sarrafa_C0_0
|
FRAME_END_O H_SYNC_O SAKETA_I V_SYNC_O SYS_CLK_I V_ACTIVE_O ANABLE_I DATA_TRIGGER_O H_RES_O[15:0] V_RES_O[15:0] |
Nuni_Controller_C0
tsarin_generator_verilog_pattern_0
|
DATA_VALID_O SYS_CLK_I FRAME_END_O SAKETA_N_I LINE_END_O DATA_EN_I RED_O[7:0] FRAME_END_I GREEN_O[7:0] PATTERN_SEL_I[2:0] BLUE_O[7:0] BAYER_O[7:0] |
Gwaji_Tsarin_Generator_C0
PF_XCVR_REF_CLK_C0_0
|
REF_CLK_PAD_P REF_CLK_PAD_NREF_CLK |
PF_XCVR_REF_CLK_C0
HDMI_TX_0
|
SAKETA_N_I SYS_CLK_I VIDEO_DATA_VALID_I R_CLK_I R_CLK_LOCK G_CLK_I G_CLK_LOCK TMDS_R_O[9:0] B_CLK_I TMDS_G_O[9:0] B_CLK_LOCK TMDS_B_O[9:0] V_SYNC_I XCVR_LANE_0_DATA_O[9:0] H_SYNC_I
DATA_R_I[11:4]
DATA_G_I[11:4]
DATA_B_I[11:4] |
HDMI_TX_C0
PF_TX_PLL_C0_0
|
PADs_OUT CLKS_FROM_TXPLL_0 LANE3_TXD_N LANE0_IN LANE3_TXD_P LANE0_PCS_ARST_N LANE2_TXD_N LANE0_PMA_ARST_N LANE2_TXD_P LANE0_TX_DATA[9:0] LANE1_TXD_N LANE1_IN LANE1_TXD_P LANE1_PCS_ARST_N LANE0_TXD_N LANE1_PMA_ARST_N LANE0_TXD_P LANE1_TX_DATA[9:0] LANE0_OUT LANE2_IN LANE1_OUT LANE2_PCS_ARST_N LANE1_TX_CLK_R LANE2_PMA_ARST_N LANE1_TX_CLK_STABLE LANE2_TX_DATA[9:0] LANE2_OUT LANE2_TX_CLK_R LANE3_PCS_ARST_N LANE2_TX_CLK_STABLE LANE3_PMA_ARST_N LANE3_OUT LANE3_TX_DATA[9:0] LANE3_TX_CLK_R LANE3_TX_CLK_STABLE |
PF_XCVR_ERM_C0
LANE3_TXD_N LANE3_TXD_P LANE2_TXD_N LANE2_TXD_P LANE1_TXD_N LANE1_TXD_P LANE0_TXD_N LANE0_TXD_P
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FABRIC_POR_N PCIE_INIT_DONE USRAM_INIT_DONE SRAM_INIT_DONE DEVICE_INIT_DONE XCVR_INIT_DONE USRAM_INIT_FROM_SNVM_DONE USRAM_INIT_FROM_UPROM_DONE USRAM_INIT_FROM_SPI_DONE SRAM_INIT_FROM_SNVM_DONE SRAM_INIT_FROM_UPROM_DONE SRAM_INIT_FROM_SPI_DONE AUTOCALIB_DONE |
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REF_CLKPLL_LOCKCLKS_TO_XCVR |
PF_INIT_MONITOR_C0
PF_TX_PLL_C0
Sample haɗin kai don, g_BITS_PER_COMPONENT> 8 da g_PIXELS_PER_CLK = 1. Ga Example, a cikin saitunan 12-bit, abubuwan da ke biyowa sune ɓangaren ƙira:
• An saita PF_XCVR_ERM (PF_XCVR_ERM_C0_0) don ƙimar bayanai na 111.375 Mbps a cikin yanayin PMA don TX kawai, tare da faɗin bayanan da aka saita azaman 10 bit don yanayin 1pxl da 1113.75 Mbps nuni agogo, dangane da agogon tunani. Table 6-1 saituna
• Ana samar da fitowar LANE1_TX_CLK_R na PF_XCVR_ERM_C0_0 azaman agogon 111.375 MHz, dangane da Table 6-1 saituna
R_CLK_I, G_CLK_I, da B_CLK_I LANE3_TX_CLK_R, LANE2_TX_CLK_R, da LANE1_TX_CLK_R, bi da bi.
• PF_CCC_C0 yana samar da agogo mai suna OUT0_FABCLK_0, mai mitar 74.25 MHz, lokacin shigar da agogon 111.375 MHz, wanda LANE1_TX_CLK_R ke tafiyar da shi.
• SYS_CLK_I (HDMI_TX_C0, Display_Controller_C0, pattern_generator_C0, CORERESET_PF_C0, da PF_INIT_MONITOR_C0) OUT0_FABCLK_0 ne ke tafiyar da shi, wanda shine 74.25 MHz
Sample haɗin kai don, g_BITS_PER_COMPONENT> 8 da g_PIXELS_PER_CLK = 4. Ga Example, a cikin saitunan 12-bit, abubuwan da ke biyowa sune ɓangaren ƙira:
• PF_XCVR_ERM (PF_XCVR_ERM_C0_0) an saita don ƙimar bayanai na 4455 Mbps a cikin yanayin PMA don TX kawai, tare da faɗin bayanan da aka saita azaman 40 bit don yanayin 4pxl da agogon tunani 111.375 MHz, dangane da agogon tunani. Table 6-1 saituna
• Ana samar da fitowar LANE1_TX_CLK_R na PF_XCVR_ERM_C0_0 azaman agogon 111.375 MHz, dangane da Table 6-1 saituna
Jagorar Mai Amfani
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Haɗin tsarin
R_CLK_I, G_CLK_I, da B_CLK_I LANE3_TX_CLK_R, LANE2_TX_CLK_R, da LANE1_TX_CLK_R, bi da bi.
• PF_CCC_C0 yana samar da agogo mai suna OUT0_FABCLK_0, mai mitar 74.25 MHz, lokacin shigar da agogon 111.375 MHz, wanda LANE1_TX_CLK_R ke tafiyar da shi.
• SYS_CLK_I (HDMI_TX_C0, Display_Controller_C0, pattern_generator_C0, CORERESET_PF_C0, da PF_INIT_MONITOR_C0) OUT0_FABCLK_0 ne ke tafiyar da shi, wanda shine 74.25 MHz
Jagorar Mai Amfani
DS50003319C 21
© 2024 Microchip Technology Inc. da rassansa
Tarihin Bita
7. Tarihin Bita (Tambaya Tambaya)
Tarihin bita ya bayyana canje-canjen da aka aiwatar a cikin takaddar. Canje-canjen an jera su ta bita, farawa da mafi kyawun ɗaba'ar.
Tebur 7-1. Tarihin Bita
|
Bita |
Kwanan wata |
Bayani |
|
C |
05/2024 |
Mai zuwa shine jerin canje-canje a cikin bita C na daftarin aiki: • An sabunta Gabatarwa sashe • Cire teburin amfani da albarkatu don pixel ɗaya da pixels huɗu kuma an ƙara Tebur 2 kuma Tebur 3 in 1. Amfani da Albarkatu sashe • An sabunta Table 3-1 a cikin 3.1. Ma'aunin Kanfigareshan sashe • Ƙara Table 3-6 kuma Table 3-7 a cikin 3.2. Tashoshi sashe • Ƙara 6. Tsarin Haɗin Kai sashe |
|
B |
|
09/2022 Mai zuwa shine jerin canje-canje a cikin bita na B na takaddar: • An sabunta abun ciki na Features da Gabatarwa • Ƙara Hoto na 2-2 don naƙasasshen Yanayin Sauti • Ƙara Table 3-4 kuma Table 3-5 • An sabunta ta Table 3-2 kuma Table 3-3 • An sabunta Table 3-1 • An sabunta 1. Amfani da Albarkatu • An sabunta Hoto na 1-1 • An sabunta Hoto na 5-3 |
|
A |
|
04/2022 Mai zuwa shine jerin canje-canje a cikin bita A na takaddar: • An ƙaura da takarda zuwa samfurin Microchip • An sabunta lambar takardar zuwa DS50003319 daga 50200863 |
|
2.0 |
— |
Mai zuwa shine taƙaitaccen canje-canjen da aka yi a cikin wannan bita. • Haɓaka fasali da sassan Iyalai masu Goyan baya |
|
1.0 |
|
08/2021 Bita na farko |
Jagorar Mai Amfani
DS50003319C 22
© 2024 Microchip Technology Inc. da rassansa
Tallafin FPGA Microchip
Ƙungiyar samfuran Microchip FPGA tana goyan bayan samfuran ta tare da sabis na tallafi daban-daban, gami da Sabis na Abokin Ciniki, Cibiyar Tallafin Fasaha ta Abokin Ciniki, a website, da ofisoshin tallace-tallace na duniya. Ana ba abokan ciniki shawarar ziyartar albarkatun kan layi na Microchip kafin tuntuɓar tallafi saboda da yuwuwar an riga an amsa tambayoyinsu.
Tuntuɓi Cibiyar Tallafawa Fasaha ta hanyar websaiti a www.microchip.com/support. Ambaci lambar Sashe na Na'urar FPGA, zaɓi nau'in shari'ar da ta dace, da ƙaddamar da ƙira files yayin ƙirƙirar shari'ar tallafin fasaha.
Tuntuɓi Sabis na Abokin Ciniki don tallafin samfur mara fasaha, kamar farashin samfur, haɓaka samfur, sabunta bayanai, matsayin tsari, da izini.
• Daga Arewacin Amurka, kira 800.262.1060
• Daga sauran duniya, kira 650.318.4460
• Fax, daga ko'ina cikin duniya, 650.318.8044
Bayanin Microchip
Microchip Website
Microchip yana ba da tallafin kan layi ta hanyar mu websaiti a www.microchip.com/. Wannan webana amfani da site don yin files da bayanai cikin sauƙin samuwa ga abokan ciniki. Wasu daga cikin abubuwan da ake samu sun haɗa da:
• Tallafin samfur - Takaddun bayanai da errata, bayanin kula da aikace-aikacen sampshirye-shirye, albarkatun ƙira, jagororin mai amfani da takaddun tallafi na hardware, sabbin fitattun software da software da aka adana
• Babban Tallafin Fasaha - Tambayoyi akai-akai (FAQs), buƙatun tallafin fasaha, ƙungiyoyin tattaunawa akan layi, jerin membobin shirin abokan hulɗa na Microchip
• Kasuwancin Microchip - Mai zaɓin samfura da jagororin oda, sabbin sabbin labarai na Microchip, jerin tarurrukan karawa juna sani da abubuwan da suka faru, jerin ofisoshin tallace-tallace na Microchip, masu rarrabawa da wakilan masana'anta
Sabis ɗin Sanarwa Canjin samfur
Sabis ɗin sanarwar canjin samfur na Microchip yana taimakawa abokan ciniki su kasance a halin yanzu akan samfuran Microchip. Masu biyan kuɗi za su karɓi sanarwar imel a duk lokacin da aka sami canje-canje, sabuntawa, bita ko ƙirƙira masu alaƙa da ƙayyadadden dangin samfur ko kayan aikin haɓaka na ban sha'awa.
Don yin rajista, je zuwa www.microchip.com/pcn kuma bi umarnin rajista. Tallafin Abokin Ciniki
Masu amfani da samfuran Microchip na iya karɓar taimako ta tashoshi da yawa: • Mai Rarraba ko Wakili
• Ofishin Talla na Gida
• Injiniya Magani (ESE)
• Goyon bayan sana'a
Abokan ciniki yakamata su tuntuɓi mai rarraba su, wakilin ko ESE don tallafi. Hakanan akwai ofisoshin tallace-tallace na gida don taimakawa abokan ciniki. An haɗa lissafin ofisoshin tallace-tallace da wurare a cikin wannan takarda.
Ana samun tallafin fasaha ta hanyar websaiti a: www.microchip.com/support Siffar Kariyar Lambar Na'urorin Microchip
Kula da cikakkun bayanai masu zuwa na fasalin kariyar lambar akan samfuran Microchip:
Jagorar Mai Amfani
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© 2024 Microchip Technology Inc. da rassansa
• Samfuran Microchip sun hadu da ƙayyadaddun bayanai da ke ƙunshe a cikin takamaiman takaddar bayanan Microchip ɗin su.
• Microchip ya yi imanin cewa dangin samfuran sa suna da tsaro lokacin da aka yi amfani da su ta hanyar da aka yi niyya, cikin ƙayyadaddun aiki, da kuma ƙarƙashin yanayi na yau da kullun.
• Ma'auni na Microchip kuma yana kare haƙƙin mallaka na fasaha da ƙarfi. Ƙoƙarin keta fasalin kariyar lambar samfurin Microchip an haramta shi sosai kuma yana iya keta Dokar Haƙƙin mallaka ta Millennium Digital.
• Babu Microchip ko wani masana'anta na semiconductor ba zai iya tabbatar da amincin lambar sa ba. Kariyar lambar ba ta nufin cewa muna ba da garantin samfurin "ba zai karye ba". Kariyar lambar tana ci gaba da haɓakawa. Microchip ya himmatu don ci gaba da haɓaka fasalin kariyar lambar samfuranmu.
Sanarwa na Shari'a
Ana iya amfani da wannan ɗaba'ar da bayanin nan tare da samfuran Microchip kawai, gami da ƙira, gwadawa, da haɗa samfuran Microchip tare da aikace-aikacenku. Amfani da wannan bayanin ta kowace hanya ya saba wa waɗannan sharuɗɗan. Bayani game da aikace-aikacen na'ura an bayar da shi ne kawai don jin daɗin ku kuma ana iya maye gurbinsu da sabuntawa. Alhakin ku ne don tabbatar da cewa aikace-aikacenku ya dace da ƙayyadaddun bayananku. Tuntuɓi ofishin tallace-tallace na Microchip na gida don ƙarin tallafi ko, sami ƙarin tallafi a www.microchip.com/en-us/support/design-help/ abokin ciniki-support-services.
WANNAN BAYANI AN BAYAR DA MICROCHIP "KAMAR YADDA". MICROCHIP BA YA YI WAKILI KO GARANTIN KOWANE IRIN BAYANI KO BAYANI, RUBUTU KO BAKI, DOKA KO SAURAN BA, GAME DA BAYANIN GAME DA BAYANI AMMA BAI IYA IYAKA GA WANI GARGADI BA, DA KYAUTATA DON MUSAMMAN MANUFAR, KO GARANTIN DA KE DANGANTA DA SHARADINSA, INGANCI, KO AIKINSA.
BABU WANI FARKO MICROCHIP BA ZAI IYA HANNU GA DUK WATA BAYANI NA MUSAMMAN, HUKUNCI, MASU FARU, KO SAKAMAKON RASHI, LALATA, KUDI, KO KUDI NA KOWANE IRIN ABINDA YA DANGANE BAYANI KO SAMUN HANYAR AMFANINSA, ANA SHAWARAR DA YIWU KO LALACEWAR DA AKE SANYA. ZUWA CIKAKKIYAR DOKA, JAMA'AR DOKAR MICROCHIP A KAN DUK DA'AWA A KOWANE HANYA DAKE DANGANTA BAYANI KO AMFANINSA BA ZAI WUCE YAWAN KUDADE BA, IDAN WATA, CEWA KA BIYA GASKIYA GA GADON.
Amfani da na'urorin Microchip a cikin tallafin rayuwa da/ko aikace-aikacen aminci gabaɗaya yana cikin haɗarin mai siye, kuma mai siye ya yarda ya kare, ramuwa da riƙe Microchip mara lahani daga kowane lalacewa, iƙirari, dacewa, ko kashe kuɗi sakamakon irin wannan amfani. Ba a isar da lasisi, a fakaice ko akasin haka, ƙarƙashin kowane haƙƙin mallaka na Microchip sai dai in an faɗi haka.
Alamomin kasuwanci
Sunan Microchip da tambari, tambarin Microchip, Adaptec, AVR, tambarin AVR, AVR Freaks, BestTime, BitCloud, CryptoMemory, CryptoRF, dsPIC, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXStylus MediaLB, megaAVR, Microsemi, tambarin Microsemi, MAFI YAWAN tambari, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, tambarin PIC32, PolarFire, Prochip Designer, QTouch, SAM-BA, Sengenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetric , SyncServer, Tachyon, TimeSource, tinyAVR, UNI/O, Vectron, da XMEGA alamun kasuwanci ne masu rijista na Microchip Technology Incorporated a cikin Amurka da sauran ƙasashe.
AgileSwitch, ClockWorks, Kamfanin Haɓaka Sarrafa Sarrafa, EtherSynch, Flashtec, Sarrafa Saurin Saurin, HyperLight Load, Libero, motorBench, mTouch, Powermite 3, Daidaitaccen Edge, ProASIC, ProASIC Plus, Tambarin ProASIC Plus, Shuru-Wire, SmartFusion, SyncWorld, TimeCesium, TimeHub, TimePictra, TimeProvider, da ZL alamun kasuwanci ne masu rijista na Microchip Technology Incorporated a cikin Amurka
Maɓallin Maɓalli na kusa, AKS, Analog-for-da-Digital Age, Duk wani Capacitor, AnyIn, AnyOut, Ƙarfafa Canjawa, BlueSky, BodyCom, Clockstudio, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPImicdemnet, dsPICDEM.
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© 2024 Microchip Technology Inc. da rassansa
Matsakaicin Matching, DAM, ECAN, Espresso T1S, EtherGREEN, EyeOpen, GridTime, IdealBridge, IGAT, Shirye-shiryen Serial In-Circuit, ICSP, INICnet, Daidaitawar Hankali, IntelliMOS, Haɗin Chip Inter-Chip, JitterBlocker, Knob-on-Display, Mar. maxCrypto, maxView, memBrain, Mindi, MiWi, MPASM, MPF, Tambarin Tambarin MPLAB, MPLIB, MPLINK, mSiC, MultiTRAK, NetDetach, Ƙwararren Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, MOS IV, Powerarfin MOS 7, PowerSmart, PureSilicon , QMatrix, REAL ICE, Ripple Blocker, RTAX, RTG4, SAM-ICE, Serial Quad I/O, simpleMAP, SimpliPHY, SmartBuffer, SmartHLS, SMART-IS, storClad, SQI, SuperSwitcher, SuperSwitcher II, Switchtec, SynchroPHY, Jimlar Jimiri , Amintaccen Lokaci, TSHARC, Turing, USBCheck, VariSense, VectorBlox, VeriPHY, ViewSpan, WiperLock, XpressConnect, da ZENA alamun kasuwanci ne na Microchip Technology Incorporated a cikin Amurka da sauran ƙasashe.
SQTP alamar sabis ce ta Microchip Technology Incorporated a cikin Amurka
Alamar Adaptec, Mitar Buƙatu, Fasahar Adana Silicon, da Symmcom alamun kasuwanci ne masu rijista na Microchip Technology Inc. a wasu ƙasashe.
GestIC alamar kasuwanci ce mai rijista ta Microchip Technology Germany II GmbH & Co. KG, reshen Microchip Technology Inc., a wasu ƙasashe.
Duk sauran alamun kasuwanci da aka ambata a nan mallakin kamfanoninsu ne. © 2024, Microchip Technology Incorporated da rassanta. Duka Hakkoki. ISBN:
Tsarin Gudanar da inganci
Don bayani game da Tsarin Gudanar da Ingancin Microchip, da fatan za a ziyarci www.microchip.com/quality.
Jagorar Mai Amfani
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Kasuwanci da Sabis na Duniya
AMURKA ASIYA/PACIFIC ASIA/PACIFIC EUROPE
Ofishin Kamfanin
2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200
Fax: 480-792-7277
Goyon bayan sana'a:
www.microchip.com/support Web Adireshi:
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Takardu / Albarkatu
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MICROCHIP DS50003319C-13 Ethernet HDMI TX IP [pdf] Jagorar mai amfani DS50003319C - 13, DS50003319C - 2, DS50003319C - 3, DS50003319C-13 Ethernet HDMI TX IP, DS50003319C-13, Ethernet HDMI TX IP, HDMI TX IP, IP |
